Rev. 2.2
February 2000 1/135
This ispreliminary information on a new product in development or undergoing evaluation. Details aresubject to change without notice.
ST72104G, ST72215G,
ST72216G, ST72254G
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
ADC, 16-BIT TIMERS, SPI, I2C INTERFACES
PRELIMINARY DATA
■Memories
– 4K or 8K bytes Program memory (ROM and
single voltage FLASH) with read-out protec-
tion and in-situ programming (remote ISP)
– 256 bytes RAM
■Clock, Reset and Supply Management
– Enhanced reset system
– Enhanced low voltage supply supervisor with
3 programmable levels
– Clock sources: crystal/ceramic resonator os-
cillators or RC oscillators, external clock,
backup Clock Security System
– Clock-out capability
– 3 Power Saving Modes: Halt, Wait and Slow
■Interrupt Management
– 7 interrupt vectors plus TRAP and RESET
– 22 external interrupt lines (on 2 vectors)
■22 I/O Ports
– 22 multifunctional bidirectional I/O lines
– 14 alternate function lines
– 8 high sink outputs
■3 Timers
– Configurable watchdog timer
– Two 16-bittimers with: 2 input captures,2 out-
put compares,external clock input on one tim-
er, PWM and Pulse generator modes
(one only on ST72104Gx and ST72216G1)
■2 Communications Interfaces
– SPI synchronous serial interface
– I2C multimaster interface
(only on ST72254Gx)
■1 Analog peripheral
– 8-bit ADC with 6 input channels
(except on ST72104Gx)
■Instruction Set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
■Development Tools
– Fullhardware/softwaredevelopment package
Device Summary
SDIP32
SO28
Features ST72104G1 ST72104G2 ST72216G1 ST72215G2 ST72254G1 ST72254G2
Program memory -bytes 4K 8K 4K 8K 4K 8K
RAM (stack) - bytes 256 (128)
Peripherals Watchdog timer,
One 16-bit timer,
SPI
Watchdog timer,
One 16-bit timer,
SPI, ADC
Watchdog timer,
Two 16-bit timers,
SPI, ADC
Watchdog timer,
Two 16-bit timers,
SPI, I C, ADC
Operating Supply 3.0V to 5.5V
CPU Frequency Up to 8 MHz (with oscillator up to 16 MHz)
Operating Temperature -40°C to +85°C (-40°C to +105/125°C optional)
Packages SO28 / SDIP32
1
Table of Contents
135
2/135
2
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . ......................................... 6
2 PIN DESCRIPTION . . . . . . . . . . . . ................................................ 7
3 REGISTER & MEMORY MAP . . . ................................................ 10
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . ................................. 13
4.1 INTRODUCTION . ...................................................... 13
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... 13
4.3 STRUCTURAL ORGANISATION . . . . .. . . . . . . . . . ........................... 13
4.4 IN-SITU PROGRAMMING (ISP) MODE . .................................... 13
4.5 MEMORY READ-OUT PROTECTION . . . . . ................................. 13
5 CENTRAL PROCESSING UNIT . . ............................................... 14
5.1 INTRODUCTION . ...................................................... 14
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... 14
5.3 CPU REGISTERS . . .. . . . . . . . . . . . . . . . . . ................................. 14
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . ................................ 17
6.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . ................................ 18
6.2 RESET SEQUENCE MANAGER (RSM) . . . . . ................................ 19
6.2.1 Introduction . . . .................................................... 19
6.2.2 Asynchronous External RESET pin . . . . . . . . . . . .. . . . . . . . . . . . . . . . . ........ 20
6.2.3 Internal Low Voltage Detection RESET . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 20
6.2.4 Internal Watchdog RESET . . . . . . . . . . .................................. 20
6.3 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . ................................ 21
6.4 CLOCK SECURITY SYSTEM (CSS) . . . . . . . . ................................ 22
6.4.1 Clock Filter Control . . ...............................................22
6.4.2 Safe Oscillator Control . . . . ........................................... 22
6.4.3 Low Power Modes . . ............................................... 22
6.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 22
6.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR) . . . . . . . ........ 23
6.6 MAIN CLOCK CONTROLLER (MCC) . . . . . . . . . . . . ........................... 24
7 INTERRUPTS . . ............................................................. 25
7.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . ........................... 25
7.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . .................................. 25
7.3 PERIPHERAL INTERRUPTS . . ........................................... 25
8 POWER SAVING MODES . . . . . . . . . . ........................................... 27
8.1 INTRODUCTION . ...................................................... 27
8.2 SLOW MODE . . . . . . . . . . . . . . ........................................... 27
8.3 WAIT MODE . . . . . . . . . . . ............................................... 28
8.4 HALT MODE . . . . . . . . . . . ............................................... 29
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . ........................................ 30
9.1 INTRODUCTION . ...................................................... 30
9.2 FUNCTIONAL DESCRIPTION . . . . ........................................ 30
9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . ................................. 30
9.2.2 Output Modes . . . . . . ............................................... 30
9.2.3 Alternate Functions . . ...............................................30
9.3 I/O PORT IMPLEMENTATION . . . . ........................................ 33
Table of Contents
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3
9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . ................................. 34
9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . ................................. 34
9.6 REGISTER DESCRIPTION . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . ........ 34
10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . ................................ 36
10.2 I/O PORT ALTERNATE FUNCTIONS . . . . . .................................. 36
10.3 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11 ON-CHIP PERIPHERALS . . . . . . ............................................... 39
11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . ........................... 39
11.1.1Introduction . . . . ................................................... 39
11.1.2Main Features . . . . . . . . . . . . . . . . . . . . ................................. 39
11.1.3Functional Description . . . . . . . ........................................ 39
11.1.4Hardware Watchdog Option . . . . . . . . . . . ................................ 40
11.1.5Low Power Modes . . . ............................................... 40
11.1.6Interrupts . . . . . . . . . . . . . .. . . . . . . . . . ................................. 40
11.1.7Register Description . . . . . . . . . ........................................ 40
11.2 16-BIT TIMER . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 42
11.2.1Introduction . . . . ................................................... 42
11.2.2Main Features . . . . . . . . . . . . . . . . . . . . ................................. 42
11.2.3Functional Description . . . . . . . ........................................ 42
11.2.4Low Power Modes . . ............................................... 54
11.2.5Interrupts . . . . . . ................................................... 54
11.2.6Summary of Timer modes . . . . . . . . . . . . . . . . . ........................... 54
11.2.7Register Description . . . . . . . . . ........................................ 55
11.3 SERIAL PERIPHERAL INTERFACE (SPI) . .................................. 60
11.3.1Introduction . . . . ................................................... 60
11.3.2Main Features . . . . . . . . . . . . . . . . . . . . ................................. 60
11.3.3General description . . . . . ............................................ 60
11.3.4Functional Description . . . . . . . ........................................ 62
11.3.5Low Power Modes . . . ............................................... 69
11.3.6Interrupts . . . . . . ................................................... 69
11.3.7Register Description . . . . . . . . . ........................................ 70
11.4 I2C BUS INTERFACE (I2C) . . . . . . . . . . ....................................73
11.4.1Introduction . . . . ................................................... 73
11.4.2Main Features . . . . . . . . . . . . . . . . . . . . ................................. 73
11.4.3General Description . . . . . . . . . ........................................ 73
11.4.4Functional Description . . . . . . . ........................................ 75
11.4.5Low Power Modes . . . ............................................... 79
11.4.6Interrupts . . . . . . . . . . . . . .. . . . . . . . . . ................................. 79
11.4.7Register Description . . . . . . . . . ........................................ 80
11.5 8-BIT A/D CONVERTER (ADC) ........................................... 86
11.5.1Introduction . . . . ................................................... 86
11.5.2Main Features . . . . . . . . . . . . . . . . . . . . ................................. 86
11.5.3Functional Description . . . . . . . ........................................ 86
11.5.4Low Power Modes . . ............................................... 87
11.5.5Interrupts . . . . . . . . . . . . . .. . . . . . . . . . ................................. 87
11.5.6Register Description . . . . . . . . . ........................................ 88
ST72104G, ST72215G, ST72216G, ST72254G
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12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . ................................. 90
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 90
12.1.1Inherent . . . . . . . . . . . . . . . . . . . . . . . . . ................................. 91
12.1.2Immediate . . ...................................................... 91
12.1.3Direct . ........................................................... 91
12.1.4Indexed (No Offset, Short, Long) . . . . . .................................. 91
12.1.5Indirect (Short, Long) . . . . ............................................ 91
12.1.6Indirect Indexed (Short, Long) . ........................................ 92
12.1.7Relative mode (Direct, Indirect) . . . . ....................................92
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . .............................. 93
13 ELECTRICAL CHARACTERISTICS . . . . ......................................... 96
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . ............................... 96
13.1.1Minimum and Maximum values ........................................ 96
13.1.2Typical values . . . . . . . . . ............................................ 96
13.1.3Typical curves . . . . . . . . . . . . . ........................................ 96
13.1.4Loading capacitor . . . . . . . . . . . . . . . . . .................................. 96
13.1.5Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 97
13.2.1Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
13.2.2Current Characteristics . . . . . . . . . . . . . . . . .............................. 97
13.2.3Thermal Characteristics . . . . . . . . . .................................... 97
13.3 OPERATING CONDITIONS . . . . . . . . . . .................................... 98
13.3.1General Operating Conditions . . . . .................................... 98
13.3.2Operating Conditions with Low Voltage Detector (LVD) . .................... 99
13.4 SUPPLY CURRENT CHARACTERISTICS . . . ...............................101
13.4.1RUN and SLOW Modes . . . . . ....................................... 101
13.4.2WAIT and SLOW WAIT Modes . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . ....... 102
13.4.3HALT Mode . . . . . . . . .............................................. 103
13.4.4Supply and Clock Managers . ........................................ 103
13.4.5On-Chip Peripherals . . . . . .......................................... 103
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . ........... 104
13.5.1General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.5.2External Clock Source . . . . . . ....................................... 104
13.5.3Crystal and Ceramic Resonator Oscillators . . . . .......................... 105
13.5.4RC Oscillators . . . . . . . . . . .......................................... 106
13.5.5Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
13.6 MEMORY CHARACTERISTICS . . . ....................................... 108
13.6.1RAM and Hardware Registers . . . .. . . . . . . . . . . . . . . . . . . . . .............. 108
13.6.2FLASH Program Memory . . . . ....................................... 108
13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
13.7.1Functional EMS . . . . . .............................................. 109
13.7.2Absolute Electrical Sensitivity . . . .. . . . . . . . . . .......................... 110
13.7.3ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 112
13.8 I/O PORT PIN CHARACTERISTICS .......................................114
13.8.1General Characteristics . . . . . . . . . . . . ................................. 114
13.8.2Output Driving Current . . . . .......................................... 115
13.9 CONTROL PIN CHARACTERISTICS . . . . . ................................. 117
ST72104G, ST72215G, ST72216G, ST72254G
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13.9.1Asynchronous RESET Pin . . . . . . . . . . . . . . . . . .......................... 117
13.9.2ISPSEL Pin ...................................................... 119
13.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . .. . . . . . . . . . ....... 120
13.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 120
13.10.216-Bit Timer . . . . . . . . . . . . . . . . . . . . . ................................ 120
13.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . ................... 121
13.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . .......................... 121
13.11.2I2C - Inter IC ControlInterface . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .......... 123
13.12 8-BIT ADC CHARACTERISTICS . . . . . . . . ................................. 124
14 PACKAGE CHARACTERISTICS . . . . . . ........................................ 126
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . ............................. 126
14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . ................... 127
14.3 SOLDERING AND GLUEABILITY INFORMATION . . . .. . . . . . . . . . . . . . . . . ....... 128
14.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . .. . ................... 128
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 129
15.1 OPTION BYTES . . . ................................................... 129
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 130
15.3 DEVELOPMENT TOOLS . . . .. . . . . . . . . . . . . . . . . .......................... 132
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . ................................. 133
15.5 TO GETMORE INFORMATION . . . ....................................... 133
16 SUMMARY OF CHANGES . .................................................. 134
ST72104G, ST72215G, ST72216G, ST72254G
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1 INTRODUCTION
The ST72104G, ST72215G, ST72216G and
ST72254G devices are members of the ST7 mi-
crocontroller family. They can be grouped as fol-
lows:
– ST72254G devices are designed for mid-range
applications with ADC and I C interface capabili-
ties.
– ST72215/6G devices target the same range of
applications but without I C interface.
– ST72104G devices are for applications that do
not need ADC and I C peripherals.
All devices are based on a common industry-
standard 8-bitcore, featuringan enhancedinstruc-
tion set.
The ST72C104G, ST72C215G, ST72C216G and
ST72C254G versions feature single-voltage
FLASH memory with byte-by-byte In-Situ Pro-
gramming (ISP) capability.
Under software control, all devices can be placed
in WAIT, SLOW, or HALT mode, reducing power
consumption when the application is in idle or
standby state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
For easy reference, all parametric data are located
in Section 13 on page 96.
Figure 1. General Block Diagram
8-BIT CORE
ALU
ADDRESS AND DATA BUS
OSC1
OSC2
RESET
PORT B
16-BIT TIMER A
PORT A
SPI
PORT C
8-BIT ADC
WATCHDOG
PB7:0
(8 bits)
PC5:0
(6 bits)
MULTI OSC
Internal
CLOCK
CONTROL
RAM
(256 Bytes)
PA7:0
(8 bits)
VSS
VDD POWER
SUPPLY
16-BIT TIMER B
PROGRAM
(4 or 8K Bytes)
LVD
+
CLOCK FILTER I2C
MEMORY
4
ST72104G, ST72215G, ST72216G, ST72254G
7/135
2 PIN DESCRIPTION
Figure 2. 28-Pin SO Package Pinout
Figure 3. 32-Pin SDIP Package Pinout
15
16
17
18
19
20
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RESET
OSC1
AIN3/ICAP2_B/PC3
AIN4/OCMP2_B/PC4
AIN5/EXTCLK_A/PC5
ICAP1_A/PB0
OCMP1_A/PB1
ICAP2_A/PB2
OCMP2_A/PB3
MOSI/PB4
ISPDATA/MISO/PB5
ISPCLK/SCK/PB6
SS/PB7
OSC2
VDD
VSS
PC2/MCO/AIN2
PC1/OCMP1_B/AIN1
PC0/ICAP1_B/AIN0
PA7 (HS)
PA6 (HS)/SDAI
PA5 (HS)
PA4 (HS)/SCLI
PA3 (HS)
PA2 (HS)
PA1 (HS)
PA0 (HS)
ISPSEL
ei1 ei0
ei0 or ei1
(HS) 20mA high sink capability
eiX associated external interrupt vector
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
29
30
31
32
RESET
OSC1
AIN3/ICAP2_B/PC3
AIN4/OCMP2_B/PC4
AIN5/EXTCLK_A/PC5
ICAP1_A/PB0
OCMP1_A/PB1
ICAP2_A/PB2
OCMP2_A/PB3
MOSI/PB4
ISPDATA/MISO/PB5
ISPCLK/SCK/PB6
SS/PB7
OSC2
NC
NC
VDD
VSS
PC2/MCO/AIN2
PC1/OCMP1_B/AIN1
PC0/ICAP1_B/AIN0
PA7 (HS)
PA6 (HS)/SDAI
PA5 (HS)
PA4 (HS)/SCLI
PA3 (HS)
PA2 (HS)
PA1 (HS)
PA0 (HS)
ISPSEL
NC
NC
ei1
ei0
ei0
ei1
ei0orei1
(HS) 20mA high sink capability
eiX associated external interrupt vector
5
ST72104G, ST72215G, ST72216G, ST72254G
8/135
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to Section 13 ”ELECTRICAL CHARACTERISTICS” on page
96.
Legend / Abbreviations for Table 1:
Type: I = input, O = output, S = supply
Input level: A = Dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7VDD,
CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog
– Output: OD = open drain 2), PP = push-pull
Refer toSection 9 ”I/O PORTS” onpage 30 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Device Pin Description
Pin n°
Pin Name
Type
Level Port / Control Main
Function
(after reset) Alternate Function
SDIP32
SO28
Input
Output
Input Output
float
wpu
int
ana
OD
PP
1 1 RESET I/O CTX X Top priority non maskable interrupt (active low)
2 2 OSC1 3) IExternal clock input or Resonator oscillator in-
verter input or resistor input for RC oscillator
3 3 OSC2 3) OResonator oscillator inverter output or capaci-
tor input for RC oscillator
4 4 PB7/SS I/O CTXei1 X X Port B7 SPI Slave Select (active low)
5 5 PB6/SCK/ISPCLK I/O CTXei1 X X Port B6 SPI Serial Clock or ISP Clock
6 6 PB5/MISO/ISPDATA I/O CTXei1 X X Port B5 SPI Master In/ Slave Out Data
or ISP Data
7 7 PB4/MOSI I/O CTXei1 X X Port B4 SPI Master Out / Slave In Data
8NC Not Connected
9NC
10 8 PB3/OCMP2_A I/O CTXei1 X X Port B3 Timer A Output Compare 2
11 9 PB2/ICAP2_A I/O CTXei1 X X Port B2 Timer A Input Capture 2
12 10 PB1 /OCMP1_A I/O CTXei1 X X Port B1 Timer A Output Compare 1
13 11 PB0 /ICAP1_A I/O CTXei1 X X Port B0 Timer A Input Capture 1
14 12 PC5/EXTCLK_A/AIN5 I/O CTXei0/ei1 X X Port C5 Timer A Input Clock or ADC
Analog Input 5
15 13 PC4/OCMP2_B/AIN4 I/O CTXei0/ei1 X X Port C4 Timer B Output Compare 2 or
ADC Analog Input 4
16 14 PC3/ ICAP2_B/AIN3 I/O CTXei0/ei1 X X X Port C3 Timer B Input Capture 2 or
ADC Analog Input 3
17 15 PC2/MCO/AIN2 I/O CTXei0/ei1 X X X Port C2 Main clock output (fCPU)or
ADC Analog Input 2
6
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Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu)is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD
are not implemented). See Section 9 ”I/O PORTS” on page 30 and Section 13.8 ”I/O PORT PIN CHAR-
ACTERISTICS” on page 114 for more details.
3. OSC1 andOSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to
the on-chip oscillator see Section 2 ”PIN DESCRIPTION” onpage 7 and Section 13.5 ”CLOCK AND TIM-
ING CHARACTERISTICS” on page 104 for more details.
18 16 PC1/OCMP1_B/AIN1 I/O CTXei0/ei1 X X X Port C1 Timer B Output Compare 1 or
ADC Analog Input 1
19 17 PC0/ICAP1_B/AIN0 I/O CTXei0/ei1 X X X Port C0 Timer B Input Capture 1 or
ADC Analog Input 0
20 18 PA7 I/O CTHS Xei0 X X Port A7
21 19 PA6 /SDAI I/O CTHS Xei0 T Port A6 I2C Data
22 20 PA5 I/O CTHS Xei0 X X Port A5
23 21 PA4 /SCLI I/O CTHS Xei0 T Port A4 I2C Clock
24 NC Not Connected
25 NC
26 22 PA3 I/O CTHS Xei0 X X Port A3
27 23 PA2 I/O CTHS Xei0 X X Port A2
28 24 PA1 I/O CTHS Xei0 X X Port A1
29 25 PA0 I/O CTHS Xei0 X X Port A0
30 26 ISPSEL I C XIn situ programming selection (Should be tied
low in standard user mode).
31 27 VSS S Ground
32 28 VDD S Main power supply
Pin n°
Pin Name
Type
Level Port / Control Main
Function
(after reset) Alternate Function
SDIP32
SO28
Input
Output
Input Output
float
wpu
int
ana
OD
PP
ST72104G, ST72215G, ST72216G, ST72254G
10/135
3 REGISTER & MEMORY MAP
As shown in the Figure 4, the MCU is capable of
addressing 64K bytes of memories and I/O regis-
ters.
The available memory locations consist of 128
bytes of register location, 256 bytes of RAM and
up to 8Kbytes of user program memory. The RAM
space includes up to 128 bytes for the stack from
0100h to 017Fh.
The highest address bytes contain the user reset
and interrupt vectors.
IMPORTANT: Memory locations marked as “Re-
served” must never be accessed. Accessing a re-
seved area can have unpredicable effects on the
device.
Figure 4. Memory Map
0000h
Program Memory
(4K, 8 KBytes)
Interrupt & Reset Vectors
HW Registers
DFFFh
0080h
007Fh (see Table 2)
E000h
FFDFh
FFE0h
FFFFh (see Table 5 on page 26)
0180h Reserved
017Fh
Short Addressing RAM
0100h
017Fh
0080h
00FFh
256 Bytes RAM
4 KBytes
F000h
E000h 8 KBytes
FFFFh
Zero page
(128 Bytes)
Stack or
16-bit Addressing RAM
(128 Bytes)
ST72104G, ST72215G, ST72216G, ST72254G
11/135
Table 2. Hardware Register Map
Address Block Register
Label Register Name Reset
Status Remarks
0000h
0001h
0002h Port C PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
00h 1)
00h
00h
R/W 2)
R/W 2)
R/W 2)
0003h Reserved (1 Byte)
0004h
0005h
0006h Port B PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h 1)
00h
00h
R/W
R/W
R/W.
0007h Reserved (1 Byte)
0008h
0009h
000Ah Port A PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h 1)
00h
00h
R/W
R/W
R/W
000Bh
to
001Fh Reserved (21 Bytes)
0020h MISCR1 Miscellaneous Register 1 00h R/W
0021h
0022h
0023h SPI SPIDR
SPICR
SPISR
SPI Data I/O Register
SPI Control Register
SPI Status Register
xxh
0xh
00h
R/W
R/W
Read Only
0024h WATCHDOG WDGCR Watchdog Control Register 7Fh R/W
0025h CRSR Clock, Reset, Supply Control /Status Register 000x 000x R/W
0026h
0027h Reserved (2 bytes)
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
I2C
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
Control Register
Status Register 1
Status Register 2
Clock Control Register
Own Address Register 1
Own Address Register 2
Data Register
00h
00h
00h
00h
00h
00h
00h
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
002Fh
to
0030h Reserved (4 Bytes)
ST72104G, ST72215G, ST72216G, ST72254G
12/135
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated withunavailable pins must always keep their reset value.
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
TIMER A
TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer A Control Register 2
Timer A Control Register 1
Timer A Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
0040h MISCR2 Miscellaneous Register 2 00h R/W
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
TIMER B
TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B Control Register 2
Timer B Control Register 1
Timer B Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
0050h
to
006Fh Reserved (32 Bytes)
0070h
0071h ADC ADCDR
ADCCSR Data Register
Control/Status Register 00h
00h Read Only
R/W
0072h
to
007Fh Reserved (14 Bytes)
Address Block Register
Label Register Name Reset
Status Remarks
ST72104G, ST72215G, ST72216G, ST72254G
13/135
4 FLASH PROGRAM MEMORY
4.1 INTRODUCTION
FLASH devices have a single voltage non-volatile
FLASH memory that may be programmed in-situ
(or plugged in a programming tool) on a byte-by-
byte basis.
4.2 MAIN FEATURES
■Remote In-Situ Programming (ISP) mode
■Up to 16 bytes programmed in the same cycle
■MTP memory (Multiple Time Programmable)
■Read-out memory protection against piracy
4.3 STRUCTURAL ORGANISATION
The FLASH program memory is organised in a
single 8-bit wide memory block which can be used
for storing both code and data constants.
The FLASH program memory is mapped in the up-
per part of the ST7 addressing space and includes
the reset and interrupt user vector area .
4.4 IN-SITU PROGRAMMING (ISP) MODE
The FLASH program memory can be programmed
using Remote ISP mode. This ISP mode allows
the contents ofthe ST7program memory to be up-
dated usinga standard ST7 programming tools af-
ter the device is mounted on the application board.
This feature can be implemented with a minimum
number of added components and board area im-
pact.
An exampleRemote ISP hardware interface to the
standard ST7 programming tool is described be-
low. For more detailson ISP programming, refer to
the ST7 Programming Specification.
Remote ISP Overview
The Remote ISP modeis initiated by a specific se-
quence on the dedicated ISPSEL pin.
The Remote ISP is performedin three steps:
– Selection of the RAM execution mode
– Download of Remote ISP code in RAM
– Execution of Remote ISP code in RAM to pro-
gram the user program into the FLASH
Remote ISP hardware configuration
In Remote ISP mode, the ST7 has to be supplied
with power (VDD and VSS) and a clock signal (os-
cillator and application crystal circuit for example).
This mode needs five signals (plus the VDD signal
if necessary) to be connected to the programming
tool. This signals are:
– RESET: device reset
–V
SS: device ground power supply
– ISPCLK: ISP outputserial clock pin
– ISPDATA: ISP input serial data pin
– ISPSEL: RemoteISP mode selection. This pin
must be connected to VSS on the application
board through a pull-down resistor.
If any of thesepins are used for other purposes on
the application, a serial resistor has to be imple-
mented to avoid a conflict if the other device forces
the signal level.
Figure 5 shows a typical hardware interface to a
standard ST7 programming tool. For more details
on the pin locations, refer to the device pinout de-
scription.
Figure 5. Typical Remote ISP Interface
4.5 MEMORY READ-OUT PROTECTION
The read-out protection is enabled through an op-
tion bit.
For FLASH devices, when this option is selected,
the program and data stored in the FLASH memo-
ry are protected against read-out piracy (including
a re-write protection). When this protection option
is removed the entire FLASH program memory is
first automatically erased. However, the E2PROM
data memory (when available) can be protected
only with ROM devices.
ISPSEL
VSS
RESET
ISPCLK
ISPDATA
OSC1
OSC2
VDD
ST7
HE10 CONNECTOR TYPE
TO PROGRAMMING TOOL
10KΩ
CL0 CL1
APPLICATION
47KΩ
1
XTAL
ST72104G, ST72215G, ST72216G, ST72254G
14/135
5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
5.2 MAIN FEATURES
■63 basic instructions
■Fast 8-bit by 8-bit multiply
■17 main addressing modes
■Two 8-bit index registers
■16-bit stack pointer
■Low power modes
■Maskable hardware interrupts
■Non-maskable software interrupt
5.3 CPU REGISTERS
The 6 CPU registers shown in Figure 6 are not
present in thememory mapping and are accessed
by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations andto manipulate
data.
Index Registers (X and Y)
In indexed addressing modes, these 8-bitregisters
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede in-
struction (PRE) to indicate that the following in-
struction refers to the Y register.)
The Y registeris not affected by the interrupt auto-
matic procedures (notpushed to and popped from
the stack).
Program Counter (PC)
The program counter is a16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program CounterLow which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 6. CPU Registers
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
STACK POINTER
CONDITION CODE REGISTER
PROGRAM COUNTER
70
1C11HI NZ
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
70
70
70
0
7
15 8
PCH PCL
15 87 0
RESET VALUE = STACK HIGHER ADDRESS
RESET VALUE = 1X11X1XX
RESET VALUE = XXh
RESET VALUE = XXh
RESET VALUE = XXh
X = Undefined Value
ST72104G, ST72215G, ST72216G, ST72254G
15/135
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
The 8-bit Condition Code register contains the in-
terrupt mask and four flags representative of the
result ofthe instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
These bits can be individually tested and/or con-
trolled by specific instructions.
Bit 4 = H
Half carry
.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
Bit 3 = I
Interrupt mask
.
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM andIRET in-
structions and is tested by the JRM and JRNM in-
structions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware when you en-
ter it and reset bythe IRET instruction at the end of
the interrupt routine. If the I bit is cleared by soft-
ware in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.
Bit 2 = N
Negative
.
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7th
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit isaccessed by the JRMIandJRPL instruc-
tions.
Bit 1 = Z
Zero
.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C
Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
70
111HINZC
ST72104G, ST72215G, ST72216G, ST72254G
16/135
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 01 7Fh
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It isthen decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 7).
Since the stack is 128 bytes deep, the 9th most
significant bits are forced by hardware. Following
an MCU Reset, or after a Reset Stack Pointer in-
struction (RSP), the Stack Pointer contains its re-
set value (the SP6 to SP0 bits are set) which is the
stack higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost.The stackalso wrapsin case of anunder-
flow.
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCLis stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 7.
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context ispopped from the stack.
A subroutine call occupies twolocations and an in-
terrupt five locations in the stack area.
Figure 7. Stack Manipulation Example
15 8
00000001
70
0 SP6 SP5 SP4 SP3 SP2 SP1 SP0
PCH
PCL
SP
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
SP
Y
CALL
Subroutine Interrupt
Event PUSH Y POP Y IRET RET
or RSP
@ 017Fh
@ 0100h
Stack Higher Address = 017Fh
Stack Lower Address = 0100h
ST72104G, ST72215G, ST72216G, ST72254G
17/135
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The ST72104G, ST72215G, ST72216G and
ST72254G microcontrollers include a range of util-
ity features for securing the application in critical
situations (for example in case of a power brown-
out), and reducing the number of external compo-
nents. An overview is shown in Figure 8.
See Section 13 ”ELECTRICAL CHARACTERIS-
TICS” on page 96 for more details.
Main Features
■Supply Manager with main supply low voltage
detection (LVD)
■Reset Sequence Manager (RSM)
■Multi-Oscillator (MO)
– 4 Crystal/Ceramic resonator oscillators
– 1 External RC oscillator
– 1 Internal RC oscillator
■Clock Security System (CSS)
– Clock Filter
– Backup Safe Oscillator
Figure 8. Clock, Reset and Supply Block Diagram
IE D00 0 0 RF RF
CRSR
CSS WDG
fOSC
CSS INTERRUPT
LVD
LOW VOLTAGE
DETECTOR
(LVD)
MULTI-
OSCILLATOR
(MO)
FROM
WATCHDOG
PERIPHERAL
OSC1
RESET
VDD
VSS
RESET SEQUENCE
MANAGER
(RSM)
CLOCK
FILTER
SAFE
OSC
CLOCK SECURITYSYSTEM
(CSS)
MAIN CLOCK
CONTROLLER
(MCC)
MCO
fCPU
OSC2
ST72104G, ST72215G, ST72216G, ST72254G
18/135
6.1 LOW VOLTAGE DETECTOR (LVD)
To allow the integration of power management
features in the application, the Low Voltage Detec-
tor function (LVD) generates a static reset when
the VDD supply voltage is below a VIT- reference
value. This means that it secures the power-up as
well as the power-down keeping the ST7 in reset.
The VIT- reference value for a voltage drop is lower
than theVIT+ referencevalue forpower-on in order
to avoida parasiticreset when theMCU starts run-
ning and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
VDD is below:
–V
IT+ when VDD is rising
–V
IT- when VDD is falling
The LVD function is illustrated in the Figure 9.
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is below VIT-, the MCU
can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
1. The LVD allows the device to be used without
any external RESET circuitry.
2. Three different reference levels are selectable
through the option byte according to the applica-
tion requirement.
LVD application note
Application software can detect a reset caused by
the LVD by reading the LVDRF bit in the CRSR
register.
This bit is set by hardware when a LVD reset is
generated and cleared by software (writing zero).
Figure 9. Low Voltage Detector vs Reset
VDD
VIT+
RESET
VIT-
Vhyst
ST72104G, ST72215G, ST72216G, ST72254G
19/135
6.2 RESET SEQUENCE MANAGER (RSM)
6.2.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in Figure 11:
■External RESET source pulse
■Internal LVD RESET (Low Voltage Detection)
■Internal WATCHDOG RESET
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 10:
■Delay depending on the RESET source
■4096 CPU clock cycle delay
■RESET vector fetch
The 4096 CPU clock cycle delay allows the oscil-
lator to stabilise and ensures that recovery has
taken place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 10. RESET Sequence Phases
Figure 11. Reset Block Diagram
RESET
DELAY INTERNAL RESET
4096 CLOCK CYCLES FETCH
VECTOR
fCPU
COUNTER
RESET
RON
VDD
WATCHDOG RESET
LVD RESET
INTERNAL
RESET
ST72104G, ST72215G, ST72216G, ST72254G
20/135
RESET SEQUENCE MANAGER (Cont’d)
6.2.2 Asynchronous External RESET pin
The RESET pin is bothan input and an open-drain
output with integrated RON weak pull-up resistor.
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
A RESET signal originating from an external
source must have aduration of at least th(RSTL)in in
order to be recognized. This detection is asynchro-
nous and therefore the MCU can enter reset state
even in HALT mode.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
Two RESET sequences can be associated with
this RESET source: short or long external reset
pulse (see Figure 12).
Starting from the external RESET pulse recogni-
tion, the device RESET pin acts as an output that
is pulled low during at least tw(RSTL)out.
6.2.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■Power-On RESET
■Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when VDD<VIT+ (rising edge) or
VDD<VIT- (falling edge) as shown in Figure 12.
The LVD filters spikes on VDDlarger than tg(VDD) to
avoid parasitic resets.
6.2.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 12.
Starting from the Watchdog counterunderflow, the
device RESET pin acts as an output that is pulled
low during at least tw(RSTL)out.
Figure 12. RESET Sequences
VDD
RUN
RESET PIN
EXTERNAL
WATCHDOG
DELAY
VIT+
VIT-
th(RSTL)in
tw(RSTL)out
RUN DELAY
th(RSTL)in
DELAY
WATCHDOG UNDERFLOW
tw(RSTL)out
RUN RUN DELAY RUN
RESET
RESET
SOURCE
SHORT EXT.
RESET
LVD
RESET LONG EXT.
RESET WATCHDOG
RESET
INTERNAL RESET (4096 TCPU)
FETCH VECTOR
ST72104G, ST72215G, ST72216G, ST72254G
21/135
6.3 MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by
four different source types coming from the multi-
oscillator block:
■an external source
■4 crystal or ceramic resonator oscillators
■an external RC oscillator
■an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configuration are shown in Table 3. Refer to the
electrical characteristics section for more details.
External Clock Source
In this external clock mode, a clock signal (square,
sinus ortriangle) with ~50% duty cycle has todrive
the OSC1 pinwhile the OSC2 pin is tiedto ground.
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption. In this
mode of the multi-oscillator, the resonator and the
load capacitors have to be placed as close as pos-
sible to the oscillator pins in order to minimize out-
put distortion and start-up stabilization time. The
loading capacitance values must be adjusted ac-
cording to the selected oscillator.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
External RC Oscillator
This oscillator allows a low cost solution for the
main clock of the ST7 using only an external resis-
tor and an external capacitor. The frequencyof the
external RC oscillator (in the range of some MHz.)
is fixed by the resistor and the capacitor values.
Consequently in this MO mode, the accuracy of
the clock is directly linked to the accuracy of the
discrete components.
Internal RC Oscillator
The internal RC oscillator mode is based on the
same principle as the external RC oscillator includ-
ing the resistance and the capacitance of the de-
vice. This mode is the most cost effective one with
the drawback of a lower frequency accuracy. Its
frequency is in the range of several MHz.
In this mode, the two oscillator pins have to be tied
to ground.
Table 3. ST7 Clock Sources
Hardware Configuration
External ClockCrystal/Ceramic ResonatorsExternal RC OscillatorInternal RC Oscillator
OSC1 OSC2
EXTERNAL
ST7
SOURCE
OSC1 OSC2
LOAD
CAPACITORS
ST7
CL2
CL1
OSC1 OSC2
ST7
CEX
REX
OSC1 OSC2
ST7
ST72104G, ST72215G, ST72216G, ST72254G
22/135
6.4 CLOCK SECURITY SYSTEM (CSS)
The Clock Security System (CSS) protects the
ST7 against main clock problems. To allow the in-
tegration of the security features in the applica-
tions, it is based on a clock filter control and an In-
ternal safe oscillator. The CSS can be enabled or
disabled by option byte.
6.4.1 Clock Filter Control
The clock filter is based on a clock frequency limi-
tation function.
This filter function is able to detect and filter high
frequency spikes on the ST7 main clock.
If the oscillator is not working properly (e.g. work-
ing at a harmonic frequency of the resonator), the
current active oscillator clock can be totally fil-
tered, and then no clock signal is available for the
ST7 from this oscillator anymore. If the original
clock source recovers, the filtering is stopped au-
tomatically and the oscillator supplies the ST7
clock.
6.4.2 Safe Oscillator Control
The safe oscillator of the CSS block is a low fre-
quency back-up clock source (see Figure 13).
If the clock signal disappears (due to a broken or
disconnected resonator...) during a safe oscillator
period, the safe oscillator deliversa low frequency
clock signalwhich allows the ST7to perform some
rescue operations.
Automatically, the ST7 clock sourceswitches back
from the safe oscillator if the original clock source
recovers.
Limitation detection
The automatic safe oscillator selection is notified
by hardware setting the CSSD bit of the CRSR
register. An interrupt can be generated if the CS-
SIE bit has been previously set.
These two bits are described in the CRSR register
description.
6.4.3 Low Power Modes
6.4.4 Interrupts
The CSS interrupt event generates an interrupt if
the corresponding Enable Control Bit (CSSIE) is
set and the interrupt mask in the CC register is re-
set (RIM instruction).
Figure 13. Clock Filter Function and Safe Oscillator Function
Mode Description
WAIT No effect on CSS. CSS interrupt cause the
device to exit from Wait mode.
HALT
The CRSR register is frozen. The CSS (in-
cluding the safe oscillator) is disabled until
HALT mode is exited. The previous CSS
configuration resumes when the MCU is
woken up by an interrupt with “exit from
HALT mode” capability or from the counter
reset value when the MCU is woken up by a
RESET.
Interrupt Event Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
CSS event detection
(safe oscillator acti-
vated as main clock) CSSD CSSIE Yes No
fOSC/2
fCPU
fOSC/2
fCPU
fSFOSC
SAFE OSCILLATOR
FUNCTION CLOCK FILTER
FUNCTION
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6.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR)
Read/Write
Reset Value: 000x 000x (XXh)
Bit 7:5 = Reserved, always read as 0.
Bit 4 = LVDRF
LVD reset flag
This bit indicates that the last RESET was gener-
ated by the LVD block. It is set by hardware (LVD
reset) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by option byte, the LVDRF bit
value is undefined.
Bit 3 = Reserved, always read as 0.
Bit 2 = CSSIE
Clock security syst
.
interrupt enable
This bit enables the interrupt when a disturbance
is detected bythe clock security system(CSSD bit
set). It is set and cleared by software.
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
Refer to Table 5, “Interrupt Mapping,” on page 26
for more details on the CSS interrupt vector. When
the CSS is disabled by option byte, the CSSIE bit
has no effect.
Bit 1 = CSSD
Clock security system detection
This bit indicates that the safe oscillator of the
clock security system block has been selected by
hardware due to a disturbance on the main clock
signal (fOSC). It is set by hardware and cleared by
reading the CRSR registerwhen the original oscil-
lator recovers.
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the CSS is disabled by option byte, the
CSSD bit value is forced to 0.
Bit 0 = WDGRF
Watchdog reset flag
This bit indicates that the last RESET was gener-
ated by the watchdog peripheral. It is set by hard-
ware (Watchdog RESET) and cleared by software
(writing zero) or an LVD RESET (to ensure a sta-
ble cleared state of the WDGRF flag when the
CPU starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
Table 4. Clock, Reset and Supply Register Map and Reset Values
70
000
LVD
RF 0CSS
IE CSS
DWDG
RF
RESET Sources LVDRF WDGRF
External RESET pin 0 0
Watchdog 0 1
LVD 1 X
Address
(Hex.) Register
Label 76543210
0025h CRSR
Reset Value 0 0 0 LVDRF
x0
CSSIE
0CSSD
0WDGRF
x
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6.6 MAIN CLOCK CONTROLLER (MCC)
The Main Clock Controller (MCC) supplies the
clock for the ST7 CPU and its internal peripherals.
It allows SLOW power saving mode to be man-
aged by the application.
All functions are managed by the Miscellaneous
register 1 (MISCR1).
The MCC block consists of:
■A programmable CPU clock prescaler
■A clock-out signal to supply external devices
The prescaler allows the selection of the main
clock frequency and is controlled by three bits of
the MISCR1: CP1, CP0 and SMS.
The clock-out capability consists of a dedicated
I/O port pinconfigurable as an fCPU clockoutput to
drive external devices. It is controlled by the MCO
bit in the MISCR1 register.
See Section 10 ”MISCELLANEOUS REGIS-
TERS” on page 36 for more details.
Figure 14. Main Clock Controller (MCC) Block Diagram
DIV2,4,8,16DIV 2
SMSCP1 CP0
CPU CLOCK
MISCR1
CLOCK TO CAN
TO CPU AND
PERIPHERALS
fOSC
fCPU
MCO
PORT
FUNCTION
ALTERNATE
MCO ----
fOSC/2
PERIPHERAL
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7 INTERRUPTS
The ST7 coremay be interruptedby one of two dif-
ferent methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a non-
maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 15.
The maskable interrupts must be enabled clearing
the I bit in order to be serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsec-
tion).
When an interrupt has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registersare saved onto
the stack.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
– ThePC is thenloaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector address-
es).
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.
Priority management
By default, a servicing interrupt cannot be inter-
rupted because the I bit is set by hardware enter-
ing in interrupt routine.
In the case when severalinterrupts are simultane-
ously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Map-
ping Table).
Interrupts and Low power mode
All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifi-
cally mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the “Exit
from HALT“ column in the Interrupt Mapping Ta-
ble).
7.1 NON MASKABLE SOFTWARE INTERRUPT
This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit.
It will be serviced according to the flowchart on
Figure 15.
7.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred andif theI bit is cleared. Theseinterrupts
allow the processor to leave the Halt low power
mode.
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
If several input pins, connected to the same inter-
rupt vector, are configured as interrupts, their sig-
nals are logically ANDed before entering the edge/
level detection block.
Caution:The type of sensitivity defined in the Mis-
cellaneous or Interrupt register (if available) ap-
plies to the ei source. Incase of an ANDedsource
(as described on the I/O ports section), a low level
on an I/O pin configured as input with interrupt,
masks the interrupt request even in case of rising-
edge sensitivity.
7.3 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
– The I bit of the CC register is cleared.
– The correspondingenable bit is setin the control
register.
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
– Writing “0” to the corresponding bit in the status
register or
– Access to the status register while the flag is set
followed by a read or write of an associated reg-
ister.
Note: the clearing sequence resets the internal
latch. Apending interrupt (i.e. waiting for being en-
abled) will therefore be lost if the clear sequence is
executed.
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INTERRUPTS (Cont’d)
Figure 15. Interrupt Processing Flowchart
Table 5. Interrupt Mapping
Note
1. Configurable by option byte.
N°Source
Block Description Register
Label Priority
Order
Exit
from
HALT
Address
Vector
RESET Reset
N/A
Highest
Priority
Lowest
Priority
yes FFFEh-FFFFh
TRAP Software Interrupt no FFFCh-FFFDh
0 ei0 External Interrupt Port A7..0 (C5..01)yes FFFAh-FFFBh
1 ei1 External Interrupt Port B7..0 (C5..01) FFF8h-FFF9h
2 CSS Clock Filter Interrupt CRSR no FFF6h-FFF7h
3 SPI SPI Peripheral Interrupts SPISR FFF4h-FFF5h
4 TIMER A TIMER A Peripheral Interrupts TASR FFF2h-FFF3h
5 Not used FFF0h-FFF1h
6 TIMER B TIMER B Peripheral Interrupts TBSR no FFEEh-FFEFh
7 Not used FFECh-FFEDh
8 Not used FFEAh-FFEBh
9 Not used FFE8h-FFE9h
10 Not used FFE6h-FFE7h
11 I C I C P eripheral I nterrupt I2CSRx no FFE4h-FFE 5h
12 Not Used FFE2h-FFE3h
13 Not Used FFE0h-FFE1h
I BIT SET?
Y
N
IRET?
Y
N
FROM RESET
LOAD PC FROM INTERRUPT VECTOR
STACK PC, X, A, CC
SET I BIT
FETCH NEXT INSTRUCTION
EXECUTE INSTRUCTION
THIS CLEARS I BIT BY DEFAULT
RESTORE PC, X, A, CC FROM STACK
INTERRUPT
Y
NPENDING?
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8 POWER SAVING MODES
8.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, three main
power saving modes are implemented in the ST7
(see Figure 16).
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 2 (fCPU).
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specificST7 software
instruction whose action depends on the the oscil-
lator status.
Figure 16. Power Saving Mode Transitions
8.2 SLOW MODE
This mode has two targets:
– Toreduce powerconsumption bydecreasingthe
internal clock in the device,
– To adapt the internal clock frequency (fCPU)to
the available supply voltage.
SLOW mode is controlled by three bits in the
MISCR1 register: the SMS bit which enables or
disables Slow modeand two CPx bits whichselect
the internal slow frequency (fCPU).
In this mode, theoscillator frequency can be divid-
ed by 4, 8, 16 or 32 instead of 2 in normal operat-
ing mode. The CPUand peripherals are clocked at
this lower frequency.
Note: SLOW-WAIT mode is activated when enter-
ring the WAIT mode while the device is already in
SLOW mode.
Figure 17. SLOW Mode Clock Transitions
POWER CONSUMPTION
WAIT
SLOW
RUN
HALT
High
Low
SLOW WAIT
00 01
SMS
CP1:0
fCPU
NEW SLOW NORMAL RUN MODE
MISCR1
FREQUENCY
REQUEST
REQUEST
fOSC/2
fOSC/4 fOSC/8 fOSC/2
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POWER SAVING MODES (Cont’d)
8.3 WAIT MODE
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
“WFI” ST7 software instruction.
All peripherals remain active. During WAIT mode,
the I bit of the CC register is forced to 0, to enable
all interrupts. All other registers and memory re-
main unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occurs, whereup-
on the Program Counter branches to the starting
address of the interrupt or Reset service routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Refer to Figure 18.
Figure 18. WAIT Mode Flow-chart
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
WFI INSTRUCTION
RESET
INTERRUPT Y
N
N
Y
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
ON
0
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
OFF
1
ON
CPU
OSCILLATOR
PERIPHERALS
I BIT
ON
ON
X1)
ON
4096 CPU CLOCK CYCLE
DELAY
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POWER SAVING MODES (Cont’d)
8.4 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
ST7 HALT instruction (see Figure 20).
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 5, “Interrupt
Mapping,” on page 26) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 19).
When entering HALT mode, the Ibit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immedi-
ately.
In the HALT mode the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 15.1 ”OPTION BYTES” on page 129 for
more details).
Figure 19. HALT Mode Timing Overview
Figure 20. HALT Mode Flow-chart
Notes:
1.WDGHALT is anoption bit. See option byte sec-
tion for more details.
2. Peripheral clocked with anexternal clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 5, “Interrupt Mapping,” on page 26 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
HALTRUN RUN
4096 CPU CYCLE
DELAY
RESET
OR
INTERRUPT
HALT
INSTRUCTION
FETCH
VECTOR
HALT INSTRUCTION
RESET
INTERRUPT 3) Y
N
N
Y
CPU
OSCILLATOR
PERIPHERALS 2)
IBIT
OFF
OFF
0
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
OFF
1
ON
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
ON
X4)
ON
4096 CPU CLOCK CYCLE
DELAY
WATCHDOG
ENABLE
DISABLE
WDGHALT 1) 0
WATCHDOG
RESET
1
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9 I/O PORTS
9.1 INTRODUCTION
The I/O ports offer different functional modes:
– transferof datathrough digitalinputs and outputs
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input(with or
without interrupt generation)or digital output.
9.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis-
ters: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
The following description takes into account the
OR register, (for specific ports which do not pro-
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is
shown in Figure 21
9.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the OR register.
Notes:
1. Writing the DR register modifies the latch value
but does not affect the pin status.
2. When switching from input to output mode, the
DR register has to be written first to drive the cor-
rect level on the pin as soon as the port is config-
ured as an output.
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O cangenerate anexternal inter-
rupt request to the CPU.
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the Mis-
cellaneous register.
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se-
lected simultaneously as interrupt source, these
are logically ANDed. For this reason if one of the
interrupt pins is tied low, it masks the other ones.
In case of a floating input with interrupt configura-
tion, special care must be taken when changing
the configuration (see Figure 22).
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application)is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the Miscellane-
ous register must be modified.
9.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing the DR register applies this digital value to the
I/O pin through the latch.Then reading the DR reg-
ister returns the previously stored value.
Two different output modes can be selected by
software through theOR register: Output push-pull
and open-drain.
DR register value and output pin status:
9.2.3 Alternate Functions
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
standard I/O programming.
When the signal is coming from an on-chip periph-
eral, the I/O pin is automatically configured in out-
put mode (push-pull or open drain according to the
peripheral).
When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
Note: Input pull-up configuration can cause unex-
pected value attheinput of the alternateperipheral
input. When an on-chip peripheral use a pin as in-
put and output, this pin has to be configured in in-
put floating mode.
DR Push-pull Open-drain
0V
SS Vss
1V
DD Floating
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I/O PORTS (Cont’d)
Figure 21. I/O Port General Block Diagram
Table 6. I/O Port Mode Options
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
Note: The diode to VDD is not implemented in the
true open drain pads. A local protection between
the pad andVSS is implemented to protect the de-
vice against positive stress.
Configuration Mode Pull-Up P-Buffer Diodes
to VDD to VSS
Input Floating with/without Interrupt Off Off On On
Pull-up with/without Interrupt On
Output Push-pull Off On
Open Drain (logic level) Off
True Open Drain NI NI NI (see note)
DR
DDR
OR
DATA BUS
PAD
VDD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT 1
0
OR SEL
DDR SEL
DR SEL
PULL-UP
CONDITION
P-BUFFER
(see table below)
N-BUFFER
PULL-UP
(see table below)
1
0
ANALOG
INPUT
If implemented
ALTERNATE
INPUT
VDD
DIODES
(see table below)
FROM
OTHER
BITS
EXTERNAL
SOURCE (eix)
INTERRUPT
POLARITY
SELECTION
CMOS
SCHMITT
TRIGGER
REGISTER
ACCESS
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I/O PORTS (Cont’d)
Table 7. I/O Port Configurations
Notes:
1. WhentheI/O port is in input configuration and theassociated alternatefunction isenabled as an output,
reading the DR register will read the alternate function output status.
2. WhentheI/O port is in output configuration andthe associated alternate function is enabledas an input,
the alternate function reads the pin status given by the DR register content.
Hardware Configuration
INPUT 1)
OPEN-DRAIN OUTPUT 2)
PUSH-PULL OUTPUT 2)
CONDITION
PAD
VDD
RPU
EXTERNAL INTERRUPT
POLARITY
DATABUS
PULL-UP
INTERRUPT
DR REGISTER ACCESS
W
R
FROM
OTHER
PINS SOURCE (eix)
SELECTION
DR
REGISTER
CONDITION
ALTERNATE INPUT
NOT IMPLEMENTED IN
TRUEOPEN DRAIN
I/O PORTS
ANALOG INPUT
PAD
RPU
DATABUS
DR
DR REGISTER ACCESS
R/W
VDD
ALTERNATEALTERNATE
ENABLE OUTPUT
REGISTER
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
PAD
RPU
DATABUS
DR
DR REGISTER ACCESS
R/W
VDD
ALTERNATEALTERNATE
ENABLE OUTPUT
REGISTER
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
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I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt,in orderto avoid generating spurious
interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
9.3 I/O PORT IMPLEMENTATION
The hardware implementation oneach I/O port de-
pends onthe settings in the DDR and ORregisters
and specificfeature ofthe I/Oport such as ADC In-
put or true open drain.
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 22 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
Figure 22. Interrupt I/O Port State Transitions
The I/O port register configurations are summa-
rized as follows.
Interrupt Ports
PA7, PA5, PA3:0, PB7:0, PC5:0 (with pull-up)
True Open Drain Interrupt Ports
PA6, PA4 (without pull-up)
Table 8. Port Configuration
MODE DDR OR
floating input 0 0
pull-up interrupt input 0 1
open drain output 1 0
push-pull output 1 1
MODE DDR OR
floating input 0 0
floating interrupt input 0 1
open drain (high sink ports) 1 X
01
floating/pull-up
interrupt
INPUT
00
floating
(reset state)
INPUT
10
open-drain
OUTPUT
11
push-pull
OUTPUT
XX = DDR, OR
Port Pin name Input (DDR = 0) Output (DDR = 1)
OR = 0 OR = 1 OR = 0 OR = 1 High-Sink
Port A
PA7 floating pull-up interrupt open drain push-pull
Yes
PA6 floating floating interrupt true open-drain
PA5 floating pull-up interrupt open drain push-pull
PA4 floating floating interrupt true open-drain
PA3:0 floating pull-up interrupt open drain push-pull
Port B PB7:0 floating pull-up interrupt open drain push-pull No
Port C PC7:0 floating pull-up interrupt open drain push-pull
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I/O PORTS (Cont’d)
9.4 LOW POWER MODES
9.5 INTERRUPTS
The external interrupt event generates aninterrupt
if the corresponding configuration is selected with
DDR and OR registers and the I-bit in the CC reg-
ister is reset (RIM instruction).
9.6 REGISTER DESCRIPTION
DATA REGISTER (DR)
Port x Data Register
PxDR with x = A, B or C.
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[7:0]
Data register 8 bits.
The DR register has a specific behaviour accord-
ing to the selectedinput/output configuration. Writ-
ing the DR register is always taken into account
even if the pin is configured as an input; this allows
always having the expected level on the pin when
toggling to output mode. Reading the DR register
returns either the DR register latch content (pin
configured as output) or the digital value applied to
the I/O pin (pin configured as input).
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
PxDDR with x = A, B or C.
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = DD[7:0]
Data direction register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
OPTION REGISTER (OR)
Port x Option Register
PxOR with x = A, B or C.
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = O[7:0]
Option register 8 bits.
For specific I/O pins, this register is not implement-
ed. In this case the DDR register is enough to se-
lect the I/O pin configuration.
The OR register allows to distinguish: in input
mode if the pull-up with interrupt capability or the
basic pull-up configuration is selected, in output
mode if the push-pull or open drain configurationis
selected.
Each bit is set and cleared by software.
Input mode:
0: Floating input
1: Pull-up input with or without interrupt
Output mode:
0: Output open drain (with P-Buffer unactivated)
1: Output push-pull (when available)
Mode Description
WAIT No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
HALT No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
Interrupt Event Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
External interrupt on
selected external
event -DDRx
ORx Yes Yes
70
D7 D6 D5 D4 D3 D2 D1 D0
70
DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
70
O7 O6 O5 O4 O3 O2 O1 O0
ST72104G, ST72215G, ST72216G, ST72254G
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I/O PORTS (Cont’d)
Table 9. I/O Port Register Map and Reset Values
Address
(Hex.) Register
Label 76543210
Reset Value
of all I/O port registers 00000000
0000h PCDR
MSB LSB0001h PCDDR
0002h PCOR
0004h PBDR
MSB LSB0005h PBDDR
0006h PBOR
0008h PADR
MSB LSB0009h PADDR
000Ah PAOR
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10 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over
several different features such as the external in-
terrupts or the I/O alternate functions.
10.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by
the ISxx bits of the Miscellaneous register and the
OPTION BYTE. This control allows having two ful-
ly independent external interrupt source sensitivi-
ties with configurable sources (using EXTIT option
bit) as shown in Figure 23 and Figure 24.
Each external interrupt source can be generated
on four different events on the pin:
■Falling edge
■Rising edge
■Falling and rising edge
■Falling edge and low level
To guarantee correct functionality, the sensitivity
bits in the MISCR1 register must be modified only
when the I bit of the CC register is set to 1 (inter-
rupt masked). See I/O port register and Miscella-
neous register descriptions for more details on the
programming.
10.2 I/O PORT ALTERNATE FUNCTIONS
The MISCR registers manage four I/O port miscel-
laneous alternate functions:
■Main clock signal (fCPU) output on PC2
■SPI pin configuration:
– SS pin internal control to use the PB7 I/O port
function while the SPI is active.
– Master output capability on MOSI pin (PB4)
deactivated while the SPI is active.
– Slave output capability onMISO pin (PB5) de-
activated while the SPI is active.
These functions are described in detail in the Sec-
tion 10.3 ”MISCELLANEOUS REGISTER DE-
SCRIPTION” on page 37.
Figure 23. Ext. Interrupt Sensitivity (EXTIT=0)
Figure 24. Ext. Interrupt Sensitivity (EXTIT=1)
ei0
INTERRUPT
SOURCE
IS00 IS01
MISCR1
SENSITIVITY
CONTROL
PA7
PA0
PC5
PC0
PB7
PB0
IS10 IS11
MISCR1
SENSITIVITY
CONTROL
ei1
INTERRUPT
SOURCE
PA7
PA0
IS00 IS01
MISCR1
SENSITIVITY
CONTROL
ei0
INTERRUPT
SOURCE
ei1
INTERRUPT
SOURCE
IS10 IS11
MISCR1
SENSITIVITY
CONTROL
PB7
PB0
PC5
PC0
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MISCELLANEOUS REGISTERS (Cont’d)
10.3 MISCELLANEOUS REGISTER DESCRIPTION
MISCELLANEOUS REGISTER 1 (MISCR1)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = IS1[1:0]
ei1 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the ei1 external interrupts. These
two bitscan be written only when theI bit ofthe CC
register is set to 1 (interrupt masked).
ei1: Port B (C optional)
Bit 5 = MCO
Main clock out selection
This bit enables the MCO alternate function on the
PC2 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pinfree for
general-purpose I/O)
1: MCO alternate function enabled (fCPU on I/O
port)
Bit 4:3 = IS0[1:0]
ei0 sensitivity
The interrupt sensitivity, defined using the IS0[1:0]
bits, is applied to the ei0 external interrupts. These
two bitscan be written only when theI bit ofthe CC
register is set to 1 (interrupt masked).
ei0: Port A (C optional)
Bit 2:1 = CP[1:0]
CPU clock prescaler
These bitsselect the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
Bit 0 = SMS
Slow mode select
This bit is set and cleared by software.
0: Normal mode. fCPU =fOSC /2
1: Slow mode. fCPU is given by CP1, CP0
See low power consumption mode and MCC
chapters for more details.
70
IS11 IS10 MCO IS01 IS00 CP1 CP0 SMS
External Interrupt Sensitivity IS11 IS10
Falling edge & low level 0 0
Rising edge only 0 1
Falling edge only 1 0
Rising and falling edge 1 1
External Interrupt Sensitivity IS01 IS00
Falling edge & low level 0 0
Rising edge only 0 1
Falling edge only 1 0
Rising and falling edge 1 1
fCPU in SLOW mode CP1 CP0
fOSC /4 0 0
f
OSC /8 1 0
f
OSC /16 0 1
f
OSC /32 1 1
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MISCELLANEOUS REGISTERS (Cont’d)
MISCELLANEOUS REGISTER 2 (MISCR2)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:4 = Reserved
always read as 0
Bit 5 = MOD
SPI Master Output Disable
This bit is set and cleared by software. When set, it
disables the SPI Master (MOSI) output signal.
0: SPI Master Output enabled.
1: SPI Master Output disabled.
Bit 4 = SOD
SPI Slave Output Disable
This bit is set and cleared by software. When set it
disable the SPI Slave (MISO) output signal.
0: SPI Slave Output enabled.
1: SPI Slave Output disabled.
Bit 1 = SSM
SS mode selection
This bit is set and cleared by software.
0: Normal mode- the level of the SPI SS signal is
input from the external SS pin.
1: I/O mode, the level of the SPI SS signal is read
from the SSI bit.
Bit 0 = SSI
SS internal mode
This bit replaces the SS pin of the SPI when the
SSM bit is set to 1. (see SPI description). It is set
and cleared by software.
Table 10. Miscellaneous Register Map and Reset Values
70
0 0 0 0 MOD SOD SSM SSI
Address
(Hex.) Register
Label 76543210
0020h MISCR1
Reset Value IS11
0IS10
0MCO
0IS01
0IS00
0CP1
0CP0
0SMS
0
0040h MISCR2
Reset Value 0 0 0 0 MOD
0SOD
0SSM
0SSI
0
ST72104G, ST72215G, ST72216G, ST72254G
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11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG)
11.1.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usuallygenerated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
11.1.2 Main Features
■Programmable timer (64 increments of 12288
CPU cycles)
■Programmable reset
■Reset (if watchdog activated) when the T6 bit
reaches zero
■Optional reset on HALT instruction
(configurable by option byte)
■Hardware Watchdog selectable by option byte.
11.1.3 Functional Description
The counter value stored in the CR register (bits
T6:T0), is decremented every 12,288 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The application program must write in the CR reg-
ister atregular intervals during normaloperation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table 11 . Watchdog Timing (fCPU = 8
MHz)):
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
diate reset
– TheT5:T0bits contain thenumber ofincrements
which represents the time delay before the
watchdog produces a reset.
Figure 25. Watchdog Block Diagram
RESET
WDGA
7-BIT DOWNCOUNTER
fCPU
T6 T0
CLOCK DIVIDER
WATCHDOG CONTROL REGISTER (CR)
÷12288
T1
T2
T3
T4
T5
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WATCHDOG TIMER (Cont’d)
Table 11. Watchdog Timing (fCPU = 8 MHz)
Notes: Following a reset, the watchdog is disa-
bled. Once activated it cannotbe disabled, except
by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
11.1.4 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdogis always activeand the WDGAbit in
the CR is not used.
Refer to the device-specific Option Byte descrip-
tion.
11.1.5 Low Power Modes
WAIT Instruction
No effect on Watchdog.
HALT Instruction
If the Watchdog reset on HALT option is selected
by option byte, a HALT instruction causes an im-
mediate reset generation if the Watchdog is acti-
vated (WDGA bit is set).
11.1.5.1 UsingHalt Modewith the WDG (option)
If the Watchdog reset on HALT option is not se-
lected by option byte, the Halt mode can be used
when the watchdog is enabled.
In this case, the HALT instruction stops the oscilla-
tor. When the oscillator is stopped, the WDG stops
counting and is no longer able to generate a reset
until the microcontroller receives an external inter-
rupt or a reset.
If an external interrupt is received, the WDG re-
starts counting after 4096 CPU clocks. If a reset is
generated, the WDG is disabled (reset state).
Recommendations
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– Before executing the HALT instruction, refresh
the WDG counter, to avoidan unexpected WDG
reset immediately after waking up the microcon-
troller.
– When using an external interrupt to wake up the
microcontroller, reinitialize thecorrespondingI/O
as “InputPull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that theI/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
condition.
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
– Asthe HALT instruction clears the I bit inthe CC
register to allow interrupts, the user may choose
to clear all pending interrupt bits before execut-
ing the HALT instruction. This avoids entering
other peripheral interruptroutines afterexecuting
the external interrupt routine corresponding to
the wake-up event (reset or external interrupt).
11.1.6 Interrupts
None.
11.1.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
Bit 7 = WDGA
Activation bit
.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Bit 6:0 = T[6:0]
7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
CR Register
initial value WDG timeout period
(ms)
Max FFh 98.304
Min C0h 1.536
70
WDGA T6 T5 T4 T3 T2 T1 T0
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WATCHDOG TIMER (Cond’t)
Table 12. Watchdog Timer Register Map and Reset Values
Address
(Hex.) Register
Label 76543210
0024h WDGCR
Reset Value WDGA
0T6
1T5
1T4
1T3
1T2
1T1
1T0
1
ST72104G, ST72215G, ST72216G, ST72254G
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11.2 16-BIT TIMER
11.2.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (
input capture
) or generation of up to two out-
put waveforms (
output compare
and
PWM
).
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
Some ST7 devices have two on-chip 16-bittimers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequen-
cies are not modified.
This description covers oneor two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
11.2.2 Main Features
■Programmableprescaler:fCPU dividedby2,4or8.
■Overflow status flag and maskable interrupt
■External clock input (must be at least 4 times
slower thantheCPUclockspeed)withthechoice
of active edge
■Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■Pulse width modulation mode (PWM)
■One pulse mode
■5 alternatefunctionson I/Oports (ICAP1,ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 26.
*Note: Some timer pins may not available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
11.2.3 Functional Description
11.2.3.1 Counter
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Counter Register (CR):
– Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
– Counter Low Register (CLR) is the least sig-
nificant byte (LS Byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte(MS Byte).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 13 Clock
Control Bits. The value in the counter register re-
peats every 131.072, 262.144 or 524.288 CPU
clock cycles depending on the CC[1:0]bits.
The timer frequency can be fCPU/2, fCPU/4, fCPU/8
or an external frequency.
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16-BIT TIMER (Cont’d)
Figure 26. Timer Block Diagram
MCU-PERIPHERAL INTERFACE
COUNTER
ALTERNATE
OUTPUT
COMPARE
REGISTER
OUTPUT COMPARE EDGE DETECT
OVERFLOW
DETECT
CIRCUIT
1/2
1/4
1/8
8-bit
buffer
ST7 INTERNAL BUS
LATCH1 OCMP1
ICAP1
EXTCLK
fCPU
TIMER INTERRUPT
ICF2ICF1 000OCF2OCF1 TOF
PWMOC1E EXEDGIEDG2CC0CC1
OC2E OPMFOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIETOIE
ICAP2
LATCH2 OCMP2
88
8 low
16
8high
16 16
16 16
(Control Register 1) CR1 (Control Register 2) CR2
(Status Register) SR
6
16
888
888
high
low
high
high
high
low
low
low
EXEDG
TIMER INTERNAL BUS
CIRCUIT1
EDGE DETECT
CIRCUIT2
CIRCUIT
1
OUTPUT
COMPARE
REGISTER
2
INPUT
CAPTURE
REGISTER
1
INPUT
CAPTURE
REGISTER
2
CC[1:0]
COUNTER
pin
pin
pin
pin
pin
REGISTER
REGISTER
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
(See note)
ST72104G, ST72215G, ST72216G, ST72254G
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16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS Byte of the count value at the time of
the read.
Whatever the timer mode used (input capture, out-
put compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
Clearing the overflow interrupt request is done in
two steps:
1.Reading the SRregister while the TOF bit is set.
2.An access (read or write) to the CLR register.
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (forexample, to measureelapsed time)with-
out the risk of clearing the TOF bit erroneously.
The timer is not affected by WAIT mode.
In HALT mode, the counter stops countinguntil the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
11.2.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.
The status of the EXEDG bit in the CR2 register
determines the type of leveltransition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.
The counter is synchronised with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur betweentwo consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.
is buffered
Read
At t0
Read Returns the buffered
LS Byte value at t0
At t0 +∆t
Other
instructions
Beginning of the sequence
Sequence completed
LS Byte
LS Byte
MS Byte
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16-BIT TIMER (Cont’d)
Figure 27. Counter Timing Diagram, internal clock divided by 2
Figure 28. Counter Timing Diagram, internal clock divided by 4
Figure 29. Counter Timing Diagram, internal clock divided by 8
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
CPU CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFC FFFD 0000 0001
CPU CLOCK
INTERNAL RESET
TIMERCLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFC FFFD 0000
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16-BIT TIMER (Cont’d)
11.2.3.3 Input Capture
In this section, the index,
i
, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAP
i
pin (see figure 5).
IC
i
R register is a read-only register.
The active transition is software programmable
through the IEDG
i
bit of Control Registers (CR
i
).
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]).
Procedure:
To use the input capturefunction select the follow-
ing in the CR2 register:
– Select the timer clock (CC[1:0]) (see Table 13
Clock Control Bits).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input).
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
– Select the edge of the active transition on the
ICAP1 pin with theIEDG1 bit(the ICAP1pin must
be configured as floating input).
When an input capture occurs:
– ICF
i
bit is set.
– The IC
i
R register contains the value of the free
running counter on the active transition on the
ICAP
i
pin (see Figure 31).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request (i.e.
clearing the ICF
i
bit) is done in two steps:
1. Reading the SR register while the ICF
i
bitis set.
2.An access (read or write) to the IC
i
LR register.
Notes:
1.After reading the IC
i
HR register, transfer of
input capture data is inhibited and ICF
i
will
never be set until the IC
i
LR register is also
read.
2.The IC
i
R register contains the free running
counter value which corresponds to the most
recent input capture.
3.The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
4.In One pulse Mode and PWM mode only the
input capture 2 can be used.
5.The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activate the input cap-
ture function.
Moreover if one of the ICAP
i
pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggle
the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion
i
is disabled by reading the IC
i
HR (see note
1).
6.The TOF bit can be used with interrupt in order
to measure event that go beyond the timer
range (FFFFh).
MS Byte LS Byte
ICiR IC
i
HR IC
i
LR
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16-BIT TIMER (Cont’d)
Figure 30. Input Capture Block Diagram
Figure 31. Input Capture Timing Diagram
ICIE
CC0
CC1
16-BIT FREE RUNNING
COUNTER
IEDG1
(Control Register 1) CR1
(Control Register 2) CR2
ICF2ICF1 000
(Status Register) SR
IEDG2
ICAP1
ICAP2 EDGE DETECT
CIRCUIT2
16-BIT
IC1R RegisterIC2R Register
EDGE DETECT
CIRCUIT1
pin
pin
FF01 FF02 FF03
FF03
TIMER CLOCK
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
Note: Active edge is rising edge.
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16-BIT TIMER (Cont’d)
11.2.3.4 Output Compare
In this section, the index,
i
, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
When a match is found between the Output Com-
pare register andthe freerunning counter, the out-
put compare function:
– Assigns pins with a programmable value if the
OCIE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OC
i
R value to 8000h.
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]).
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
– Set the OC
i
E bit if an output is needed then the
OCMP
i
pin is dedicated to the output compare
i
signal.
– Select the timer clock (CC[1:0]) (see Table 13
Clock Control Bits).
And select the following in the CR1 register:
– Select theOLVL
i
bitto applied to theOCMP
i
pins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When a match is found between OCRi register
and CR register:
– OCF
i
bit is set.
– The OCMP
i
pin takes OLVL
i
bit value (OCMP
i
pin latch is forced low during reset).
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
The OC
i
R registervalue required for aspecific tim-
ing application can be calculated using the follow-
ing formula:
Where:
∆t = Output compare period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see Table 13
Clock Control Bits)
If the timer clock is an external clock, the formula
is:
Where:
∆t = Output compare period (in seconds)
fEXT = External timerclock frequency (in hertz)
Clearing the output compare interrupt request (i.e.
clearing the OCF
i
bit) is done by:
1.Reading the SR register while the OCF
i
bit is
set.
2. An access (read or write) to the OC
i
LR register.
The following procedure is recommended to pre-
vent the OCF
i
bit from being set between the time
it is read and the write to the OC
i
R register:
– Write to the OC
i
HR register (further compares
are inhibited).
– Readthe SR register (first step of theclearance
of the OCF
i
bit, which may be already set).
– Write to the OC
i
LR register (enables the output
compare function and clears the OCF
i
bit).
MS Byte LS Byte
OC
i
ROC
i
HR OC
i
LR
∆OC
i
R= ∆t*f
CPU
PRESC
∆OC
i
R=∆t*f
EXT
ST72104G, ST72215G, ST72216G, ST72254G
49/135
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to theOC
i
HR reg-
ister, the output compare function is inhibited
until the OC
i
LR register is also written.
2. If the OC
i
E bit is not set, the OCMP
i
pin is a
general I/O port and the OLVL
i
bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is fCPU/2, OCF
i
and
OCMP
i
are set while the counter value equals
theOC
i
R register value (see Figure 33 on page
49). This behaviour is the same in OPM or
PWM mode.
When the timer clock is fCPU/4, fCPU/8 or in
external clock mode, OCF
i
and OCMP
i
are set
while the counter value equals the OC
i
R regis-
ter value plus 1 (see Figure 34 on page 49).
4. The output compare functions can be used both
for generating external events on the OCMP
i
pins even if the input capture mode is also
used.
5. The value in the 16-bit OC
i
R register and the
OLV
i
bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Forced Compare Output capability
When the FOLV
i
bit is set by software, the OLVL
i
bit is copied to the OCMP
i
pin. The OLV
i
bit has to
be toggled in order to toggle the OCMP
i
pin when
it is enabled (OC
i
E bit=1).The OCF
i
bit is thennot
set by hardware, and thus no interrupt request is
generated.
FOLVL
i
bits have no effect in both one pulse mode
and PWM mode.
Figure 32. Output Compare Block Diagram
OUTPUT COMPARE
16-bit
CIRCUIT
OC1R Register
16 BIT FREE RUNNING
COUNTER OC1E CC0CC1
OC2E
OLVL1OLVL2OCIE
(Control Register 1) CR1
(Control Register 2) CR2
000OCF2OCF1
(Status Register) SR
16-bit
16-bit
OCMP1
OCMP2
Latch
1
Latch
2
OC2R Register
Pin
Pin
FOLV2 FOLV1
ST72104G, ST72215G, ST72216G, ST72254G
50/135
16-BIT TIMER (Cont’d)
Figure 33. Output Compare Timing Diagram, fTIMER =fCPU/2
Figure 34. Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
OUTPUT COMPARE REGISTER
i
(OCR
i
)
OUTPUT COMPARE FLAG
i
(OCF
i
)
OCMP
i
PIN (OLVL
i
=1)
2ED3
2ED0 2ED1 2ED2 2ED3 2ED42ECF
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
OUTPUT COMPARE REGISTER
i
(OCR
i
)
COMPARE REGISTER
i
LATCH
2ED3
2ED0 2ED1 2ED2 2ED3 2ED42ECF
OCMP
i
PIN (OLVL
i
=1)
OUTPUT COMPARE FLAG
i
(OCF
i
)
ST72104G, ST72215G, ST72216G, ST72254G
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16-BIT TIMER (Cont’d)
11.2.3.5 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure:
To use one pulse mode:
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
mula in the opposite column).
2. Select the following in the CR1 register:
– Using the OLVL1bit, selectthe level to be ap-
plied to the OCMP1 pin after the pulse.
– Using the OLVL2bit, selectthe level to be ap-
plied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
3. Select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 13
Clock Control Bits).
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the val-
ue FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
Clearing the Input Capture interrupt request (i.e.
clearing the ICF
i
bit) is done in two steps:
1. Reading the SR register while the ICF
i
bitis set.
2.An access (read or write) to the IC
i
LR register.
The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:
Where:
t = Pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8depend-
ing on the CC[1:0] bits, see Table 13
Clock Control Bits)
If the timerclock isan external clock theformula is:
Where:
t = Pulse period (in seconds)
fEXT = External timerclock frequency (in hertz)
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 35).
Notes:
1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
2.When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
3.If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture(ICF2 canbe set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
5.When one pulse mode is used OC1R is dedi-
cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the one pulse mode.
event occurs
Counter
= OC1R OCMP1 = OLVL1
When
When
on ICAP1
One pulse mode cycle
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
OC
i
R Value = t*fCPU
PRESC -5
OC
i
R=t*f
EXT -5
ST72104G, ST72215G, ST72216G, ST72254G
52/135
16-BIT TIMER (Cont’d)
Figure 35. One Pulse Mode Timing Example
Figure 36. Pulse Width Modulation Mode Timing Example
COUNTER FFFC FFFD FFFE 2ED0 2ED1 2ED2
2ED3
FFFC FFFD
OLVL2 OLVL2OLVL1
ICAP1
OCMP1 compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
COUNTER 34E2 34E2 FFFC
OLVL2 OLVL2OLVL1
OCMP1
compare2 compare1 compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
FFFC FFFD FFFE 2ED0 2ED1 2ED2
ST72104G, ST72215G, ST72216G, ST72254G
53/135
16-BIT TIMER (Cont’d)
11.2.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
The pulse width modulation mode uses the com-
plete Output Compare 1 function plus the OC2R
register, and so these functionality can not be
used when the PWM mode is activated.
Procedure
To use pulse width modulation mode:
1. Load the OC2R register with the value corre-
sponding to the period of the signal using the
formula in the opposite column.
2. Load the OC1R register with the value corre-
sponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the oppo-
site column.
3. Select the following in the CR1 register:
– Using the OLVL1bit, selectthe level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC1R register.
– Using the OLVL2bit, selectthe level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC2R register.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC[1:0])(see Table 13
Clock Control Bits).
If OLVL1=1 and OLVL2=0 the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
The OC
i
R registervalue required for aspecific tim-
ing application can be calculated using the follow-
ing formula:
Where:
t = Signal or pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8depend-
ing on CC[1:0] bits, see Table 13 Clock
Control Bits)
If the timerclock isan external clock theformula is:
Where:
t = Signal or pulse period (in seconds)
fEXT = External timerclock frequency (in hertz)
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 36)
Notes:
1.After a write instruction to the OC
i
HR register,
the output compare function is inhibited until the
OC
i
LR register is also written.
2.The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
3. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
4.In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
5.When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
Counter
OCMP1 = OLVL2
Counter
= OC2R
OCMP1 = OLVL1
When
When
= OC1R
Pulse Width Modulation cycle
Counter is reset
to FFFCh
ICF1 bit is set
OC
i
R Value = t*fCPU
PRESC -5
OC
i
R=t*f
EXT -5
ST72104G, ST72215G, ST72216G, ST72254G
54/135
16-BIT TIMER (Cont’d)
11.2.4 Low Power Modes
11.2.5 Interrupts
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
11.2.6 Summary of Timer modes
1) See note 4 in Section 11.2.3.5 ”One Pulse Mode” on page 50
2) See note 5 in Section 11.2.3.5 ”One Pulse Mode” on page 50
3) See note 4 in Section 11.2.3.6 ”Pulse Width Modulation Mode” on page 52
Mode Description
WAIT No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
HALT
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAP
i
pin, the input capture detection circuitry isarmed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICF
i
bit is set, and
the counter value present when exiting from HALT mode is captured into the IC
i
R register.
Interrupt Event Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Input Capture 1 event/Counter reset in PWM mode ICF1 ICIE Yes No
Input Capture 2 event ICF2 Yes No
Output Compare 1 event (not available in PWM mode) OCF1 OCIE Yes No
Output Compare 2 event (not available in PWM mode) OCF2 Yes No
Timer Overflow event TOF TOIE Yes No
MODES AVAILABLE RESOURCES
Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2
Input Capture (1 and/or 2) Yes Yes Yes Yes
Output Compare (1 and/or 2) Yes Yes Yes Yes
One Pulse Mode No Not Recommended1) No Partially 2)
PWM Mode No Not Recommended3) No No
ST72104G, ST72215G, ST72216G, ST72254G
55/135
16-BIT TIMER (Cont’d)
11.2.7 Register Description
Each Timer is associated with three control and
status registers, andwith six pairs ofdata registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
CONTROL REGISTER 1 (CR1)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = ICIE
Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE
Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 5 = TOIE
Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 4 = FOLV2
Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Bit 3 = FOLV1
Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to becopied to theOCMP1 pin,if
the OC1E bit is set and even if there is no suc-
cessful comparison.
Bit 2 = OLVL2
Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 1 = IEDG1
Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = OLVL1
Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
70
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
ST72104G, ST72215G, ST72216G, ST72254G
56/135
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = OC1E
Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode).Whatever the value of theOC1E
bit, the Output Compare 1 function of the timer re-
mains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
Bit 6 = OC2E
Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
mains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Bit 5 = OPM
One Pulse Mode.
0: One Pulse Mode is not active.
1: One PulseMode is active, the ICAP1 pin can be
used totrigger one pulse on the OCMP1 pin;the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
Bit 4 = PWM
Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Bit 3, 2 = CC[1:0]
Clock Control.
The timer clock mode depends on these bits:
Table 13. Clock Control Bits
Note: If the external clock pin is not available, pro-
gramming the external clock configuration stops
the counter.
Bit 1 = IEDG2
Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = EXEDG
External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
70
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Timer Clock CC1 CC0
fCPU /4 0 0
f
CPU /2 0 1
f
CPU /8 1 0
External Clock (where
available) 11
ST72104G, ST72215G, ST72216G, ST72254G
57/135
16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
Bit 7 = ICF1
Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on theICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 6 = OCF1
Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear thisbit, firstread the SRregister, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
Bit 5 = TOF
Timer OverflowFlag.
0: No timer overflow (reset value).
1: The freerunning counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
Note: Reading or writing the ACLR register does
not clear TOF.
Bit 4 = ICF2
Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
Bit 3 = OCF2
Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear thisbit, firstread the SRregister, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
Bit 2-0 = Reserved, forced by hardware to 0.
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
OUTPUT COMPARE 1 HIGH REGISTER
(OC1HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
OUTPUT COMPARE 1 LOW REGISTER
(OC1LR)
Read/Write
Reset Value: 0000 0000 (00h)
This isan 8-bitregister that contains the low part of
the value to be compared to the CLR register.
70
ICF1 OCF1 TOF ICF2 OCF2 0 0 0 70
MSB LSB
70
MSB LSB
70
MSB LSB
70
MSB LSB
ST72104G, ST72215G, ST72216G, ST72254G
58/135
16-BIT TIMER (Cont’d)
OUTPUT COMPARE 2 HIGH REGISTER
(OC2HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
OUTPUT COMPARE 2 LOW REGISTER
(OC2LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
COUNTER HIGH REGISTER (CHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the countervalue. A write to this registerresets the
counter. An access to this register after accessing
the SR register clears the TOF bit.
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read Only
Reset Value: 1111 1100 (FCh)
This isan 8-bitregister that contains the low part of
the counter value. Awrite to this register resetsthe
counter. An access to this register after anaccess
to SR register does not clear the TOF bit in SR
register.
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of thecounter value (transferred by the In-
put Capture 2 event).
70
MSB LSB
70
MSB LSB
70
MSB LSB
70
MSB LSB
70
MSB LSB
70
MSB LSB
70
MSB LSB
70
MSB LSB
ST72104G, ST72215G, ST72216G, ST72254G
59/135
16-BIT TIMER (Cont’d)
Table 14. 16-Bit Timer Register Map and Reset Values
Address
(Hex.) Register
Label 76543210
Timer A: 32
Timer B: 42 CR1
Reset Value ICIE
0OCIE
0TOIE
0FOLV2
0FOLV1
0OLVL2
0IEDG1
0OLVL1
0
Timer A: 31
Timer B: 41 CR2
Reset Value OC1E
0OC2E
0OPM
0PWM
0CC1
0CC0
0IEDG2
0EXEDG
0
Timer A: 33
Timer B: 43 SR
Reset Value ICF1
0OCF1
0TOF
0ICF2
0OCF2
0-
0-
0-
0
Timer A: 34
Timer B: 44 ICHR1
Reset Value MSB
-------
LSB
-
Timer A: 35
Timer B: 45 ICLR1
Reset Value MSB
-------
LSB
-
Timer A: 36
Timer B: 46 OCHR1
Reset Value MSB
-------
LSB
-
Timer A: 37
Timer B: 47 OCLR1
Reset Value MSB
-------
LSB
-
Timer A: 3E
Timer B: 4E OCHR2
Reset Value MSB
-------
LSB
-
Timer A: 3F
Timer B: 4F OCLR2
Reset Value MSB
-------
LSB
-
Timer A: 38
Timer B: 48 CHR
Reset Value MSB
1111111
LSB
1
Timer A: 39
Timer B: 49 CLR
Reset Value MSB
1111110
LSB
0
Timer A: 3A
Timer B: 4A ACHR
Reset Value MSB
1111111
LSB
1
Timer A: 3B
Timer B: 4B ACLR
Reset Value MSB
1111110
LSB
0
Timer A: 3C
Timer B: 4C ICHR2
Reset Value MSB
-------
LSB
-
Timer A: 3D
Timer B: 4D ICLR2
Reset Value MSB
-------
LSB
-
ST72104G, ST72215G, ST72216G, ST72254G
60/135
11.3 SERIAL PERIPHERAL INTERFACE (SPI)
11.3.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
The SPI is normally used for communication be-
tween themicrocontroller and external peripherals
or another microcontroller.
Refer to the Pin Description chapter for the device-
specific pin-out.
11.3.2 Main Features
■Full duplex, three-wire synchronous transfers
■Master or slave operation
■Four master mode frequencies
■Maximum slave mode frequency = fCPU/2.
■Four programmable master bit rates
■Programmable clock polarity and phase
■End of transfer interrupt flag
■Write collision flag protection
■Master mode fault protection capability.
11.3.3 General description
The SPI is connected to external devices through
4 alternate pins:
– MISO: Master In Slave Out pin
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
– SS: Slave select pin
A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 37.
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave (most significant bit
first).
When the master device transmits data to a slave
device via MOSI pin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master de-
vice via the SCK pin).
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is com-
plete.
Four possible data/clock timing relationships may
be chosen (see Figure 40) but master and slave
must be programmed with the same timing mode.
Figure 37. Serial Peripheral Interface Master/Slave
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
8-BIT SHIFT REGISTER
MISO
MOSI MOSI
MISO
SCK SCK
SLAVE
MASTER
SS SS
+5V
MSBit LSBit MSBit LSBit
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SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 38. Serial Peripheral Interface Block Diagram
DR
Read Buffer
8-Bit Shift Register
Write
Read
Internal Bus
SPI
SPIE SPE SPR2 MSTR CPHA SPR0SPR1CPOL
SPIF WCOL MODF
SERIAL
CLOCK
GENERATOR
MOSI
MISO
SS
SCK CONTROL
STATE
CR
SR
-----
IT
request
MASTER
CONTROL
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4 Functional Description
Figure 37 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 3 dedicated registers:
– A Control Register (CR)
– A Status Register (SR)
– A Data Register (DR)
Refer to the CR, SR and DR registers in Section
11.3.7for the bit definitions.
11.3.4.1 Master Configuration
In a master configuration, the serial clock is gener-
ated on the SCK pin.
Procedure
– Select theSPR0 & SPR1 bits to define these-
rial clock baud rate (see CR register).
– Select the CPOL and CPHA bits todefine one
of the four relationships between the data
transfer and the serial clock (see Figure 40).
– The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence.
– The MSTR and SPE bits must be set (they re-
main set only if the SS pin is connected to a
high level signal).
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Transmit sequence
The transmit sequence begins when a byte is writ-
ten the DR register.
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if the SPIE bit is set
and the I bit in the CCR register is cleared.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following
software sequence:
1.An access to the SR register while the SPIF bit
is set
2. A write or a read of the DR register.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited until the SR register is read.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4.2 Slave Configuration
In slave configuration, the serial clock is received
on the SCK pin from the master device.
The value of the SPR0 & SPR1 bits is not used for
the data transfer.
Procedure
– For correct data transfer, the slave device
must be in the same timing mode as the mas-
ter device (CPOL and CPHA bits). See Figure
40.
– The SS pin must be connected to a low level
signal during the complete byte transmit se-
quence.
– Clear the MSTR bit and set the SPE bit to as-
sign the pins to alternate function.
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if SPIE bit is set and
I bit in CCR register iscleared.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following
software sequence:
1.An access to the SR register while the SPIF bit
is set.
2. A write or a read of the DR register.
Notes: While the SPIF bit is set, all writes to the
DR register are inhibited until the SR register is
read.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 11.3.4.6).
Depending on the CPHA bit, the SS pin has to be
set to write to the DR register between each data
byte transfer to avoid a write collision (see Section
11.3.4.4).
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4.3 Data Transfer Format
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to syn-
chronize the data transfer during a sequence of
eight clock pulses.
The SS pin allows individual selection of a slave
device; theother slave devices that are not select-
ed do not interfere with the SPI transfer.
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.
Figure 40, shows an SPI transfer with the four
combinations of the CPHA and CPOLbits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and theslave device.
The SS pin is the slave device select input and can
be driven by the master device.
The master device applies data to its MOSI pin-
clock edge before the capture clock edge.
CPHA bit is set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the second clock transition.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 39).
CPHA bit is reset
The firstedge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the oc-
currence of the first clock transition.
The SS pin must be toggled high and low between
each byte transmitted (see Figure 39).
To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its DR register and does not allow it to
be altered. Therefore the SS pin must be high to
write a new data byte in the DR without producing
a write collision.
Figure 39. CPHA / SS Timing Diagram
MOSI/MISO
Master SS
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
Byte 1 Byte 2 Byte 3
VR02131A
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SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 40. Data Clock Timing Diagram
CPOL = 1)
CPOL =0)
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =1
CPOL = 1
CPOL = 0
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
MISO
(from master)
MOSI
SS
(to slave)
CAPTURE STROBE
CPHA =0
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
(from slave)
VR02131B
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
SCLK (with
SCLK (with
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4.4 Write Collision Error
A write collision occurs when the software tries to
write to the DR register while a data transfer is tak-
ing place with an external device. When this hap-
pens, the transfer continues uninterrupted; and
the software write will be unsuccessful.
Write collisions can occur both in master and slave
mode.
Note: a ”read collision” will never occur since the
received data byte is placed in a buffer in which
access is alwayssynchronous with the MCU oper-
ation.
In Slave mode
When the CPHA bit is set:
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
DR register and output the MSBit on to the exter-
nal MISO pin of the slave device.
The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.
When the CPHA bit is reset:
Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the DR register after its
SS pin has been pulled low.
For this reason, the SS pin mustbe high, between
each data byte transfer, to allow the CPU to write
in the DR register without generating a write colli-
sion.
In Master mode
Collision in the master device is defined as a write
of the DR register while the internal serial clock
(SCK) is in the process of transfer.
The SS pin signal must be always high on the
master device.
WCOL bit
The WCOL bit in the SR register is set if a write
collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 41).
Figure 41. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st Step Read SR
Read DR Write DR
2nd Step SPIF =0
WCOL=0
SPIF =0
WCOL=0 if no transfer has started
WCOL=1 if a transfer has started
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
2nd Step WCOL=0
before the 2nd step
Read SR
Read DR Note: Writing in DR register in-
stead of reading in it do not reset
WCOL bit
Read SR
OR THEN
THEN
THEN
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4.5 Master Mode Fault
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit isset.
Master mode fault affects the SPI peripheral in the
following ways:
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
– The MSTR bit is reset, thus forcing the device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
1. A read or write access to the SR register while
the MODF bit is set.
2. A write to the CR register.
Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing se-
quence of the MODF bit. The SPE and MSTR bits
may be restored to their original state during or af-
ter this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
In a slave device the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with this MODF bit set.
The MODF bit indicates that there might have
been amulti-master conflict for system control and
allows a proper exit from systemoperation to a re-
set or default system state using an interrupt rou-
tine.
11.3.4.6 Overrun Condition
An overrun condition occurs when the master de-
vice has sent several data bytes and the slave de-
vice has not cleared the SPIF bit issuing from the
previous data byte transmitted.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the DR register returns this byte. All other bytes
are lost.
This condition is not detected by the SPI peripher-
al.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4.7 Single Master and Multimaster Configurations
There are two types of SPI systems:
– Single Master System
– Multimaster System
Single Master System
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 42).
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
For more security, the slave device may respond
to the masterwith the received data byte. Then the
master will receive the previous byte backfrom the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written its DR regis-
ter.
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Multi-master System
A multi-master system may also be configured by
the user. Transfer of master control could be im-
plemented using ahandshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The multi-master system is principally handled by
the MSTR bit in the CR register and the MODF bit
in the SR register.
Figure 42. Single Master Configuration
MISO
MOSI
MOSI
MOSI MOSI MOSIMISO MISO MISOMISO
SS
SS SS SS SS
SCK SCK
SCK
SCK
SCK
5V
Ports
Slave
MCU
Slave
MCU
Slave
MCU
Slave
MCU
Master
MCU
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.5 Low Power Modes
11.3.6 Interrupts
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
Mode Description
WAIT No effect on SPI.
SPI interrupt events cause the device to exit from WAIT mode.
HALT SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with
“exit from HALT mode” capability.
Interrupt Event Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
SPI End of Transfer Event SPIF SPIE Yes No
Master Mode Fault Event MODF Yes No
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0000xxxx (0xh)
Bit 7 = SPIE
Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: AnSPI interrupt is generated whenever SPIF=1
or MODF=1 in the SR register
Bit 6 = SPE
Serial peripheral output enable.
This bit is set and cleared by software. It is also
cleared by hardware when, inmaster mode, SS=0
(see Section 11.3.4.5 ”Master Mode Fault” on
page 66).
0: I/O port connected to pins
1: SPI alternate functions connected to pins
The SPE bit is cleared by reset, so the SPIperiph-
eral is not initially connected to the external pins.
Bit 5 = SPR2
Divider Enable
.
this bit is set and cleared by software and it is
cleared by reset. It is usedwith the SPR[1:0] bits to
set the baud rate. Refer to Table 15.
0: Divider by 2 enabled
1: Divider by 2 disabled
Bit 4 = MSTR
Master.
This bit is set and cleared by software. It is also
cleared by hardware when, inmaster mode, SS=0
(see Section 11.3.4.5 ”Master Mode Fault” on
page 66).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changesfrom an input to an output and
the functions of the MISO and MOSI pinsare re-
versed.
Bit 3 = CPOL
Clock polarity.
This bit is set and cleared by software. This bit de-
termines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady stateis a high value at the SCK pin.
Bit 2 = CPHA
Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 1:0 = SPR[1:0]
Serial peripheral rate.
These bits are set and cleared by software.Used
with the SPR2 bit, they select one of six baud rates
to be used as the serial clock when the device is a
master.
These 2 bits have no effect in slave mode.
Table 15. Serial Peripheral Baud Rate
70
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Serial Clock SPR2 SPR1 SPR0
fCPU/2 1 0 0
fCPU/8 0 0 0
fCPU/16 0 0 1
fCPU/32 1 1 0
fCPU/64 0 1 0
fCPU/128 0 1 1
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SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7 = SPIF
Serial Peripheral data transfer flag.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a soft-
ware sequence (an access to the SR register fol-
lowed by a read or write to the DR register).
0: Data transfer is in progress or has been ap-
proved by a clearing sequence.
1: Data transfer between the device and an exter-
nal device has been completed.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited.
Bit 6 = WCOL
Write Collision status.
This bit is set by hardware when a write to the DR
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 41).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = Unused.
Bit 4 = MODF
Mode Fault flag.
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 11.3.4.5
”Master ModeFault” on page 66). An SPIinterrupt
can be generated if SPIE=1 in the CR register.
This bit is cleared by a software sequence (An ac-
cess to the SR register while MODF=1 followed by
a write to the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bits 3-0 = Unused.
DATA I/O REGISTER (DR)
Read/Write
Reset Value: Undefined
The DR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/re-
ception of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved toa buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
Warning:
A write to the DR register places data directly into
the shift register fortransmission.
A write to the the DR register returns the value lo-
cated inthe bufferand notthe contents of the shift
register (See Figure 38 ).
70
SPIF WCOL - MODF - - - -
70
D7 D6 D5 D4 D3 D2 D1 D0
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SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 16. SPI Register Map and Reset Values
Address
(Hex.) Register
Label 76543210
0021h SPIDR
Reset Value MSB
xxxxxxx
LSB
x
0022h SPICR
Reset Value SPIE
0SPE
0SPR2
0MSTR
0CPOL
xCPHA
xSPR1
xSPR0
x
0023h SPISR
Reset Value SPIF
0WCOL
00
MODF
00000
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11.4 I2C BUS INTERFACE (I2C)
11.4.1 Introduction
The I2C Bus Interface serves as an interface be-
tween the microcontroller and the serial I2C bus. It
provides both multimaster and slave functions,
and controls all I2C bus-specific sequencing, pro-
tocol, arbitration and timing. It supports fast I2C
mode (400kHz).
11.4.2 Main Features
■Parallel-bus/I2C protocol converter
■Multi-master capability
■7-bit/10-bit Addressing
■Transmitter/Receiver flag
■End-of-byte transmission flag
■Transfer problem detection
I2C Master Features:
■Clock generation
■I2C bus busy flag
■Arbitration Lost Flag
■End of byte transmission flag
■Transmitter/Receiver Flag
■Start bit detection flag
■Start and Stop generation
I2C Slave Features:
■Stop bit detection
■I2C bus busy flag
■Detection of misplaced start or stop condition
■Programmable I2C Address detection
■Transfer problem detection
■End-of-byte transmission flag
■Transmitter/Receiver flag
11.4.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
handshake. The interrupts areenabled or disabled
by software. The interface is connectedto the I2C
bus by a data pin (SDAI) and bya clock pin(SCLI).
It can be connected both with a standard I2C bus
and a Fast I2C bus.This selection is madeby soft-
ware.
Mode Selection
The interface can operate in the four following
modes:
– Slave transmitter/receiver
– Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitrationloss or a
STOP generation, allowing then Multi-Master ca-
pability.
Communication Flow
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
In Slave mode, the interface is capable of recog-
nising its own address (7 or 10-bit), and the Gen-
eral Call address. The General Call address de-
tection may be enabled or disabled by software.
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte(s) following the start con-
dition contain the address (one in 7-bit mode, two
in 10-bit mode). The address is always transmitted
in Master mode.
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledgebit to the transmitter. Referto Fig-
ure 43.
Figure 43. I2C BUS Protocol
SCL
SDA
12 89
MSB ACK
STOP
START CONDITION
CONDITION VR02119B
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I2C BUS INTERFACE (Cont’d)
Acknowledge may be enabled and disabled by
software.
The I2C interface address and/or general call ad-
dress can be selected by software.
The speed of the I2C interface may be selected
between Standard (0-100KHz) and Fast I2C (100-
400KHz).
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
The SCL frequency (Fscl) is controlled by a pro-
grammable clock divider which depends on the
I2C bus mode.
When the I2C cell is enabled, the SDA and SCL
ports must be configured as floating inputs. In this
case, the value of the external pull-up resistor
used depends on the application.
When the I2C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
Figure 44. I2C Interface Block Diagram
DATA REGISTER(DR)
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER1 (OAR1)
CLOCK CONTROL REGISTER (CCR)
STATUS REGISTER 1 (SR1)
CONTROL REGISTER (CR)
CONTROL LOGIC
STATUS REGISTER 2 (SR2)
INTERRUPT
CLOCK CONTROL
DATA CONTROL
SCL or SCLI
SDA or SDAI
OWN ADDRESS REGISTER 2 (OAR2)
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I2C BUS INTERFACE (Cont’d)
11.4.4 Functional Description
Refer tothe CR, SR1 and SR2 registers in Section
11.4.7. for the bit definitions.
By default the I2C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
First the interface frequency must be configured
using the FRi bits in the OAR2 register.
11.4.4.1 Slave Mode
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
Note: In 10-bit addressing mode, the comparision
includes the header sequence (11110xx0) and the
two most significant bits of the address.
Header matched (10-bit mode only): the interface
generates an acknowledge pulse if the ACK bit is
set.
Address not matched: the interface ignores it
and waits for another Start condition.
Address matched: the interface generates in se-
quence:
– Acknowledge pulse if the ACK bit is set.
– EVFand ADSL bits areset with an interrupt if the
ITE bit is set.
Then theinterface waits for a read of the SR1 reg-
ister, holding the SCL line low (see Figure 45
Transfer sequencing EV1).
Next, in 7-bit mode read the DR register to deter-
mine from the least significant bit (Data Direction
Bit) if the slave must enter Receiver or Transmitter
mode.
In 10-bit mode, after receiving the address se-
quence the slave is always in receive mode. It will
enter transmit mode on receiving a repeated Start
condition followed by the header sequence with
matching address bits and the least significant bit
set (11110xx1) .
Slave Receiver
Following the address reception and after SR1
register has been read, the slave receives bytes
from the SDA line into the DR register via the inter-
nal shiftregister. After each byte the interface gen-
erates in sequence:
– Acknowledge pulse if the ACK bit is set
– EVF and BTFbits are set with an interrupt if the
ITE bit is set.
Then the interfacewaits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see Figure 45 Transfer se-
quencing EV2).
Slave Transmitter
Following the address reception and after SR1
register has been read, the slave sends bytes from
the DR register tothe SDA line via the internal shift
register.
The slave waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 45 Transfer sequencing
EV3).
When the acknowledge pulse is received:
– The EVF and BTF bits are set by hardware with
an interrupt if the ITE bit is set.
Closing slave communication
After the last data byte is transferred a Stop Con-
dition is generated by the master. The interface
detects this condition and sets:
– EVF and STOPF bits with an interrupt if the ITE
bit is set.
Then the interfacewaits for a read of the SR2 reg-
ister (see Figure 45 Transfer sequencing EV4).
Error Cases
–BERR: Detection of a Stop or a Start condition
during a byte transfer.In this case, the EVF and
the BERR bits are set with an interrupt ifthe ITE
bit is set.
If it is a Stop then the interface discards thedata,
released the lines and waits for another Start
condition.
If it is a Start then the interface discards the data
and waits for the next slave address on the bus.
–AF: Detection of anon-acknowledge bit. In this
case, the EVF and AF bits are set with an inter-
rupt if the ITE bit is set.
Note: In both cases, SCL line is not held low; how-
ever, SDA line can remain low due to possible «0»
bits transmitted last. It is then necessary to release
both lines by software.
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I2C BUS INTERFACE (Cont’d)
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while
BTF is set. The SDA/SCL lines are released after
the transfer of the current byte.
11.4.4.2 Master Mode
To switch from default Slave mode to Master
mode a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is
cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condi-
tion.
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register with the
Slave address, holding the SCL line low (see
Figure 45 Transfer sequencing EV5).
Slave address transmission
Then the slave address is sent to the SDA line via
the internal shift register.
In 7-bit addressing mode, one address byte is
sent.
In 10-bit addressing mode, sending the first byte
including the header sequence causes the follow-
ing event:
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register, holding
the SCL line low (see Figure 45 Transfer se-
quencing EV9).
Then the second address byte is sent by the inter-
face.
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed bya write in the CR register(for exam-
ple set PE bit), holding the SCL line low (see Fig-
ure 45 Transfer sequencing EV6).
Next the master must enter Receiver or Transmit-
ter mode.
Note: In 10-bit addressing mode, to switch the
master to Receiver mode, software must generate
a repeated Start condition and resend the header
sequence with the least significant bit set
(11110xx1).
Master Receiver
Following the address transmission and after SR1
and CR registers have been accessed, the master
receives bytes from the SDA line into the DR reg-
ister via the internal shift register. After each byte
the interface generates in sequence:
– Acknowledge pulse if if the ACK bit is set
– EVFand BTF bits are setby hardware withan in-
terrupt if the ITE bit is set.
Then the interfacewaits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see Figure 45 Transfer se-
quencing EV7).
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to slave mode (M/SL bit
cleared).
Note: In order to generate the non-acknowledge
pulse after the last received data byte, the ACK bit
must be cleared just before reading the second
last data byte.
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I2C BUS INTERFACE (Cont’d)
Master Transmitter
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the inter-
nal shift register.
The master waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 45 Transfer sequencing
EV8).
When the acknowledge bit is received, the
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit
is set.
To close the communication: after writing the last
byte to the DR register, set theSTOP bit to gener-
ate the Stop condition. The interface goes auto-
matically back to slave mode (M/SL bit cleared).
Error Cases
–BERR: Detection of a Stop or a Start condition
during a bytetransfer. In this case, the EVF and
BERR bits are set by hardware with an interrupt
if ITE is set.
–AF: Detection of anon-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
–ARLO: Detection of an arbitration lost condition.
In this case theARLO bitis setby hardware (with
an interrupt if the ITE bit is set and the interface
goes automaticallybacktoslavemode(theM/SL
bit is cleared).
Note: In all these cases, the SCL line is not held
low; however, the SDA line can remain low due to
possible «0» bits transmittedlast. It is then neces-
sary to release both lines by software.
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I2C BUS INTERFACE (Cont’d)
Figure 45. Transfer Sequencing
Legend: S=Start, Sr= Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1;AF is cleared by readingSR1 register. BTFis cleared by releasing the
lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by
STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, clearedby reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
7-bit Slave receiver:
7-bit Slave transmitter:
7-bit Master receiver:
7-bit Master transmitter:
10-bit Slave receiver:
10-bit Slave transmitter:
10-bit Master transmitter
10-bit Master receiver:
S Address A Data1 A Data2 A ..... DataN A P
EV1 EV2 EV2 EV2 EV4
S Address A Data1 A Data2 A ..... DataN NA P
EV1 EV3 EV3 EV3 EV3-1 EV4
S Address A Data1 A Data2 A ..... DataN NA P
EV5 EV6 EV7 EV7 EV7
S Address A Data1 A Data2 A ..... DataN A P
EV5 EV6 EV8 EV8 EV8 EV8
S Header A Address A Data1 A ..... DataN A P
EV1 EV2 EV2 EV4
SrHeader A Data1 A ....
.DataN A P
EV1 EV3 EV3 EV3-1 EV4
S Header A Address A Data1 A ..... DataN A P
EV5 EV9 EV6 EV8 EV8 EV8
SrHeader A Data1 A ..... DataN A P
EV5 EV6 EV7 EV7
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I2C BUS INTERFACE (Cont’d)
11.4.5 Low Power Modes
11.4.6 Interrupts
Figure 46. Event Flags and Interrupt Generation
Note: The I2C interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bitis set and theI-bit inthe CCreg-
ister is reset (RIM instruction).
Mode Description
WAIT No effect on I2C interface.
I2C interrupts cause the device to exit from WAIT mode.
HALT I2C registers are frozen.
In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
Interrupt Event Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
10-bit Address Sent Event (Master mode) ADD10
ITE
Yes No
End of Byte Transfer Event BTF Yes No
Address Matched Event (Slave mode) ADSEL Yes No
Start Bit Generation Event (Master mode) SB Yes No
Acknowledge Failure Event AF Yes No
Stop Detection Event (Slave mode) STOPF Yes No
Arbitration Lost Event (Multimaster configuration) ARLO Yes No
Bus Error Event BERR Yes No
BTF
ADSL
SB
AF
STOPF
ARLO
BERR EVF
INTERRUPT
ITE
*
*
EVF can also be set by EV6 or an error from the SR2 register.
ADD10
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I2C BUS INTERFACE (Cont’d)
11.4.7 Register Description
I2C CONTROL REGISTER (CR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE
Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Notes:
– When PE=0, all the bits of the CR register and
the SR register except the Stop bit are reset. All
outputs are released while PE=0
– When PE=1, the corresponding I/O pins are se-
lected by hardware as alternate functions.
– ToenabletheI2C interface, writethe CR register
TWICEwith PE=1asthe first write onlyactivates
the interface (only PE is set).
Bit 4 = ENGC
Enable General Call.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0). The 00h General Call address is ac-
knowledged (01h ignored).
0: General Call disabled
1: General Call enabled
Bit 3 = START
Generation of a Start condition
.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation
– In slave mode:
0: No start generation
1: Start generation when the bus is free
Bit 2 = ACK
Acknowledge enable.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or
a data byte is received
Bit 1 = STOP
Generation of a Stop condition
.
This bit is set and cleared by software. It is also
cleared by hardware in master mode. Note: This
bit is not cleared when the interface is disabled
(PE=0).
– In master mode:
0: No stop generation
1: Stopgeneration after thecurrent byte transfer
or after the current Start condition is sent. The
STOP bit is cleared by hardware when the Stop
condition is sent.
– In slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the cur-
rent byte transfer (BTF=1). In this mode the
STOP bit has to be cleared by software.
Bit 0 = ITE
Interrupt enable.
This bit is set and cleared bysoftware and cleared
by hardware when the interface is disabled
(PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer toFigure 46 for the relationship between the
events and the interrupt.
SCL is held low when the ADD10, SB, BTF or
ADSL flagsor an EV6 event (See Figure 45) is de-
tected.
70
0 0 PE ENGC START ACK STOP ITE
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I2C BUS INTERFACE (Cont’d)
I2C STATUS REGISTER 1 (SR1)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7 = EVF
Event flag.
This bit is set by hardware as soon asan event oc-
curs. It is cleared by software reading SR2 register
in case of error eventor asdescribed in Figure 45.
It isalso cleared by hardware when theinterface is
disabled (PE=0).
0: No event
1: One of the following events has occurred:
– BTF=1 (Byte received or transmitted)
– ADSL=1 (Address matched in Slave mode
while ACK=1)
– SB=1 (Start condition generated in Master
mode)
– AF=1 (No acknowledge received after byte
transmission)
– STOPF=1 (Stop condition detected in Slave
mode)
– ARLO=1 (Arbitration lost in Master mode)
– BERR=1 (Bus error, misplaced Start or Stop
condition detected)
– ADD10=1 (Master has sent header byte)
– Address byte successfully transmitted in Mas-
ter mode.
Bit 6 = ADD10
10-bit addressing in Master mode
.
This bit is set by hardware when the master has
sent the first byte in 10-bit address mode. It is
cleared by software reading SR2 register followed
by awrite inthe DR register of the second address
byte. It is also cleared by hardware when the pe-
ripheral is disabled (PE=0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
Bit 5 = TRA
Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware after de-
tection of Stop condition (STOPF=1), loss of bus
arbitration (ARLO=1) or when the interface is disa-
bled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 4 = BUSY
Bus busy
.
This bit is set by hardware on detection of a Start
condition and cleared by hardware on detection of
a Stop condition. It indicates a communication in
progress on the bus.This information is still updat-
ed when the interface is disabled (PE=0).
0: No communication on the bus
1: Communication ongoing on the bus
Bit 3 = BTF
Byte transfer finished.
This bit isset by hardware as soon as a byte is cor-
rectly received or transmitted with interrupt gener-
ation if ITE=1. It is cleared by software reading
SR1 register followed by a read or write ofDR reg-
ister. It is also cleared by hardware when the inter-
face is disabled (PE=0).
– Followinga byte transmission, this bit is set after
reception of the acknowledge clock pulse. In
case an address byte is sent, this bit is set only
after the EV6 event (See Figure 45). BTF is
cleared by reading SR1 register followed by writ-
ing the next byte in DR register.
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
Bit 2 = ADSL
Address matched (Slave mode).
This bit is set by hardware assoon as the received
slave address matched with the OAR register con-
tent or a general call is recognized. An interrupt is
generated if ITE=1. It is cleared by software read-
ing SR1 register or by hardware when the inter-
face is disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
70
EVF ADD10 TRA BUSY BTF ADSL M/SL SB
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I2C BUS INTERFACE (Cont’d)
Bit 1 = M/SL
Master/Slave.
This bit is set byhardware as soon asthe interface
is in Master mode (writing START=1). It is cleared
by hardware after detecting a Stop condition on
the bus or a loss of arbitration (ARLO=1). It is also
cleared when the interface is disabled (PE=0).
0: Slave mode
1: Master mode
Bit 0 = SB
Start bit (Master mode).
This bit is set by hardware as soon as the Start
condition is generated (following a write
START=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register followed
by writing the address byte in DRregister. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No Start condition
1: Start condition generated
I2C STATUS REGISTER 2 (SR2)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:5 = Reserved. Forced to 0 by hardware.
Bit 4 = AF
Acknowledge failure
.
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
0: No acknowledge failure
1: Acknowledge failure
Bit 3 = STOPF
Stop detection (Slave mode).
This bit is set by hardware when a Stop condition
is detected on the bus after an acknowledge (if
ACK=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
Bit 2 = ARLO
Arbitration lost
.
This bit is set by hardware when the interface los-
es the arbitration of the bus to another master. An
interrupt is generated if ITE=1. It is cleared by soft-
ware reading SR2 register or by hardware when
the interface is disabled (PE=0).
After an ARLO event the interface switches back
automatically to Slave mode (M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
Bit 1 = BERR
Bus error.
This bit is set by hardware when the interface de-
tects a misplaced Start or Stop condition. An inter-
rupt is generated if ITE=1. Itis cleared by software
reading SR2 register or by hardware when the in-
terface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Bit 0 = GCAL
General Call (Slave mode).
This bit is set by hardware when a general callad-
dress is detected on the bus while ENGC=1. It is
cleared by hardware detecting a Stop condition
(STOPF=1) or when the interface is disabled
(PE=0).
0: No general call address detected on bus
1: general call address detected on bus
70
0 0 0 AF STOPF ARLO BERR GCAL
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I2C BUS INTERFACE (Cont’d)
I2C CLOCK CONTROL REGISTER (CCR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7 = FM/SM
Fast/Standard I
2
C mode.
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
0: Standard I2C mode
1: Fast I2C mode
Bit 6:0 = CC6-CC0
7-bit clock divider.
These bits select the speed of the bus (FSCL) de-
pending on the I2C mode. They are not cleared
when the interface is disabled (PE=0).
– Standard mode (FM/SM=0): FSCL <= 100kHz
FSCL =F
CPU/(2x([CC6..CC0]+2))
– Fast mode (FM/SM=1): FSCL > 100kHz
FSCL =F
CPU/(3x([CC6..CC0]+2))
Note: The programmed FSCL assumes no load on
SCL and SDA lines.
I2C DATA REGISTER (DR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = D7-D0
8-bit Data Register.
These bits contain the byte tobe received or trans-
mitted on the bus.
– Transmitter mode: Byte transmission startauto-
matically when the software writes in the DR reg-
ister.
– Receiver mode: the first data byte is received au-
tomatically in the DR register using the least sig-
nificant bit of the address.
Then, the following data bytes are received one
by one after reading the DR register.
70
FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0 70
D7 D6 D5 D4 D3 D2 D1 D0
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I2C BUS INTERFACE (Cont’d)
I2C OWN ADDRESS REGISTER (OAR1)
Read / Write
Reset Value: 0000 0000 (00h)
7-bit Addressing Mode
Bit 7:1 = ADD7-ADD1
Interface address
.
These bits define the I2C bus address of the inter-
face. They are not cleared when the interface is
disabled (PE=0).
Bit 0 = ADD0
Address direction bit.
This bit is don’t care, the interface acknowledges
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
Note: Address 01h is always ignored.
10-bit Addressing Mode
Bit 7:0 = ADD7-ADD0
Interface address
.
These are the least significant bits of the I2C bus
address of the interface. They are not cleared
when the interface is disabled (PE=0).
I2C OWN ADDRESS REGISTER (OAR2)
Read / Write
Reset Value: 0100 0000 (40h)
Bit 7:6 = FR1-FR0
Frequency bits.
These bitsare set by software only when the inter-
face is disabled(PE=0). To configure the interface
to I2C specifed delays select the value corre-
sponding to the microcontroller frequency FCPU.
Bit 5:3 = Reserved
Bit 2:1 = ADD9-ADD8
Interface address
.
These are the most significant bits of the I2C bus
address of the interface (10-bit mode only). They
are not cleared when the interface is disabled
(PE=0).
Bit 0 = Reserved.
70
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
70
FR1 FR0 0 0 0 ADD9 ADD8 0
FCPU Range (MHz) FR1 FR0
2.5 - 6 0 0
6 -10 0 1
10 - 14 1 0
14 - 24 1 1
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I C BUS INTERFACE (Cont’d)
Table 17. I2C Register Map and Reset Values
Address
(Hex.) Register
Label 76543210
0028h I2CCR
Reset Value 0 0 PE
0ENGC
0START
0ACK
0STOP
0ITE
0
0029h I2CSR1
Reset Value EVF
0ADD10
0TRA
0BUSY
0BTF
0ADSL
0M/SL
0SB
0
002Ah I2CSR2
Reset Value 0 0 0 AF
0STOPF
0ARLO
0BERR
0GCAL
0
02Bh I2CCCR
Reset Value FM/SM
0CC6
0CC5
0CC4
0CC3
0CC2
0CC1
0CC0
0
02Ch I2COAR1
Reset Value ADD7
0ADD6
0ADD5
0ADD4
0ADD3
0ADD2
0ADD1
0ADD0
0
002Dh I2COAR2
Reset Value FR1
0FR0
1000
ADD9
0ADD8
00
002Eh I2CDR
Reset Value MSB
0000000
LSB
0
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11.5 8-BIT A/D CONVERTER (ADC)
11.5.1 Introduction
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 8-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
11.5.2 Main Features
■8-bit conversion
■Up to 16 channels with multiplexed input
■Linear successive approximation
■Data register (DR) which contains the results
■Conversion complete status flag
■On/off bit (to reduce consumption)
The block diagram is shown in Figure 47.
11.5.3 Functional Description
11.5.3.1 Analog Power Supply
VDDA and VSSA are the high and low level refer-
ence voltage pins. In some devices (refer to device
pin out description) they are internally connected
to the VDD and VSS pins.
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
See electrical characteristics section for more de-
tails.
Figure 47. ADC Block Diagram
CH2 CH1CH3COCO 0 ADON 0 CH0 ADCCSR
AIN0
AIN1 ANALOG TO DIGITAL
CONVERTER
AINx
ANALOG
MUX
RADC
CADC
D2 D1D3D7 D6 D5 D4 D0
ADCDR
4
DIV 2 fADC
fCPU
HOLD CONTROL
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8-BIT A/D CONVERTER (ADC) (Cont’d)
11.5.3.2 Digital A/D Conversion Result
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (VAIN) is greater than or equal
to VDDA (high-level voltage reference) then the
conversion result in the DR register is FFh (full
scale) without overflow indication.
If input voltage (VAIN) is lower than or equal to
VSSA (low-level voltage reference) then the con-
version result in the DR register is 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.
RAIN is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
11.5.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion
phases as shown in Figure 48:
■Sample capacitor loading [duration: tLOAD]
During this phase, the VAIN input voltage to be
measured is loaded into the CADC sample
capacitor.
■A/D conversion [duration: tCONV]
During this phase, the A/D conversion is
computed (8 successive approximations cycles)
and the CADC sample capacitor is disconnected
from the analog input pin to get the optimum
analog to digital conversion accuracy.
While the ADC is on, these two phases are contin-
uously repeated.
At the end of each conversion, the sample capaci-
tor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.
11.5.3.4 Software Procedure
Refer tothe control/status register(CSR) and data
register (DR) in Section 11.5.6 for the bit defini-
tions and to Figure 48 for the timings.
ADC Configuration
The total duration of the A/D conversion is 12 ADC
clock periods (1/fADC=2/fCPU).
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the CSR register:
– Select the CH[3:0] bits to assign the analog
channel to be converted.
ADC Conversion
In the CSR register:
– Set the ADON bit to enable the A/D converter
and tostart the first conversion. From this time
on, the ADC performs a continuous conver-
sion of the selected channel.
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
valid until the next conversion has ended.
A write to the CSR register (with ADON set) aborts
the current conversion, resets the COCO bit and
starts a new conversion.
Figure 48. ADC Conversion Timings
11.5.4 Low Power Modes
Note: TheA/D converter maybe disabled by reset-
ting the ADON bit. This feature allows reduced
power consumption when no conversion is needed
and between single shot conversions.
11.5.5 Interrupts
None
Mode Description
WAIT No effect on A/D Converter
HALT
A/D Converter disabled.
After wakeup from Halt mode, the A/D Con-
verter requires a stabilisation time before ac-
curate conversions can be performed.
ADCCSR WRITE
ADON
COCO BIT SET
tLOAD
tCONV OPERATION
HOLD
CONTROL
ST72104G, ST72215G, ST72216G, ST72254G
88/135
8-BIT A/D CONVERTER (ADC) (Cont’d)
11.5.6 Register Description
CONTROL/STATUSREGISTER (CSR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = COCO
Conversion Complete
This bit is set by hardware. It is cleared by soft-
ware readingthe resultin the DRregister or writing
to the CSR register.
0: Conversion is not complete
1: Conversion can be read from the DR register
Bit 6 = Reserved.
must always be cleared.
Bit 5 = ADON
A/D Converter On
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 4 = Reserved.
must always be cleared.
Bit 3:0 = CH[3:0]
Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*Note: The number of pins AND the channel selec-
tion varies accordingto the device. Refer to the de-
vice pinout.
DATA REGISTER (DR)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[7:0]
Analog Converted Value
This register contains the converted analog value
in the range 00h to FFh.
Note: Reading this register reset the COCO flag.
70
COCO 0 ADON 0 CH3 CH2 CH1 CH0
Channel Pin* CH3 CH2 CH1 CH0
AIN0 0 0 0 0
AIN1 0 0 0 1
AIN2 0 0 1 0
AIN3 0 0 1 1
AIN4 0 1 0 0
AIN5 0 1 0 1
AIN6 0 1 1 0
AIN7 0 1 1 1
AIN8 1 0 0 0
AIN9 1 0 0 1
AIN10 1 0 1 0
AIN11 1 0 1 1
AIN12 1 1 0 0
AIN13 1 1 0 1
AIN14 1 1 1 0
AIN15 1 1 1 1
70
D7 D6 D5 D4 D3 D2 D1 D0
ST72104G, ST72215G, ST72216G, ST72254G
89/135
8-BIT A/D CONVERTER (ADC) (Cont’d)
Table 18. ADC Register Map and Reset Values
Address
(Hex.) Register
Label 76543210
0070h ADCDR
Reset Value D7
0D6
0D5
0D4
0D3
0D2
0D1
0D0
0
0071h ADCCSR
Reset Value COCO
00
ADON
00
CH3
0CH2
0CH1
0CH0
0
ST72104G, ST72215G, ST72216G, ST72254G
90/135
12 INSTRUCTION SET
12.1 ST7 ADDRESSING MODES
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
The ST7 Instruction set is designed to minimize
the number ofbytes required per instruction: To do
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
– Long addressing mode is more powerful be-
cause itcan use the full 64Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
– Short addressing mode isless powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and
short addressing modes.
Table 19. ST7 Addressing Mode Overview
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-
ing JRxx.
Addressing Mode Example
Inherent nop
Immediate ld A,#$55
Direct ld A,$55
Indexed ld A,($55,X)
Indirect ld A,([$55],X)
Relative jrne loop
Bit operation bset byte,#5
Mode Syntax Destination/
Source
Pointer
Address
(Hex.)
Pointer
Size
(Hex.)
Length
(Bytes)
Inherent nop + 0
Immediate ld A,#$55 + 1
Short Direct ld A,$10 00..FF + 1
Long Direct ld A,$1000 0000..FFFF + 2
No Offset Direct Indexed ld A,(X) 00..FF + 0 (with X register)
+ 1 (with Y register)
Short Direct Indexed ld A,($10,X) 00..1FE + 1
Long Direct Indexed ld A,($1000,X) 0000..FFFF + 2
Short Indirect ld A,[$10] 00..FF 00..FF byte + 2
Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word + 2
Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte + 2
Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word + 2
Relative Direct jrne loop PC-128/PC+1271) +1
Relative Indirect jrne [$10] PC-128/PC+1271) 00..FF byte + 2
Bit Direct bset $10,#7 00..FF + 1
Bit Indirect bset [$10],#7 00..FF 00..FF byte + 2
Bit Direct Relative btjt $10,#7,skip 00..FF + 2
Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte + 3
ST72104G, ST72215G, ST72216G, ST72254G
91/135
ST7 ADDRESSING MODES (Cont’d)
12.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for theCPU to process the operation.
12.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.
12.1.3 Direct
In Direct instructions, theoperands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Direct (short)
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
12.1.4 Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three
sub-modes:
Indexed (No Offset)
There is no offset, (no extra byteafter the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
12.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
Indirect (short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
Inherent Instruction Function
NOP No operation
TRAP S/W Interrupt
WFI Wait For Interrupt (Low Power
Mode)
HALT Halt Oscillator (Lowest Power
Mode)
RET Sub-routine Return
IRET Interrupt Sub-routine Return
SIM Set Interrupt Mask
RIM Reset Interrupt Mask
SCF Set Carry Flag
RCF Reset Carry Flag
RSP Reset Stack Pointer
LD Load
CLR Clear
PUSH/POP Push/Pop to/from the stack
INC/DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 Complement
MUL Byte Multiplication
SLL, SRL, SRA, RLC,
RRC Shift and Rotate Operations
SWAP Swap Nibbles
Immediate Instruction Function
LD Load
CP Compare
BCP Bit Compare
AND, OR, XOR Logical Operations
ADC, ADD, SUB, SBC Arithmetic Operations
ST72104G, ST72215G, ST72216G, ST72254G
92/135
ST7 ADDRESSING MODES (Cont’d)
12.1.6 Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address followsthe opcode.
The indirect indexed addressing mode consists of
two sub-modes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
Table 20. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
12.1.7 Relative mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
The relative addressing mode consists of two sub-
modes:
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the ad-
dress follows the opcode.
Long and Short
Instructions Function
LD Load
CP Compare
AND, OR, XOR Logical Operations
ADC, ADD, SUB, SBC Arithmetic Addition/subtrac-
tion operations
BCP Bit Compare
Short Instructions Only Function
CLR Clear
INC, DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 Complement
BSET, BRES Bit Operations
BTJT, BTJF Bit Test and Jump Opera-
tions
SLL, SRL, SRA, RLC,
RRC Shift and Rotate Operations
SWAP Swap Nibbles
CALL, JP Call or Jump subroutine
Available Relative Direct/
Indirect Instructions Function
JRxx Conditional Jump
CALLR Call Relative
ST72104G, ST72215G, ST72216G, ST72254G
93/135
12.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in
the following table:
Using a pre-byte
The instructions are described with one to four
bytes.
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PC opcode
PC+1 Additional word (0 to 2) according
to the number of bytes required to compute the ef-
fective address
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
PDY 90 Replace an X based instruction
using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
PIX 92 Replace an instruction using di-
rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.
PIY 91 Replace an instruction using X in-
direct indexed addressing mode by a Y one.
Load and Transfer LD CLR
Stack operation PUSH POP RSP
Increment/Decrement INC DEC
Compare and Tests CP TNZ BCP
Logical operations AND OR XOR CPL NEG
Bit Operation BSET BRES
Conditional Bit Test and Branch BTJT BTJF
Arithmetic operations ADC ADD SUB SBC MUL
Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA
Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET
Conditional Branch JRxx
Interruption management TRAP WFI HALT IRET
Code Condition Flag modification SIM RIM SCF RCF
ST72104G, ST72215G, ST72216G, ST72254G
94/135
INSTRUCTION GROUPS (Cont’d)
Mnemo Description Function/Example Dst Src H I N Z C
ADC Add with Carry A = A + M + C A M H N Z C
ADD Addition A = A + M A M H N Z C
AND Logical And A = A . M A M N Z
BCP Bit compare A, Memory tst (A . M) A M N Z
BRES Bit Reset bres Byte, #3 M
BSET Bit Set bset Byte, #3 M
BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C
BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C
CALL Call subroutine
CALLR Call subroutine relative
CLR Clear reg, M 0 1
CP Arithmetic Compare tst(Reg - M) reg M N Z C
CPL One Complement A = FFH-A reg, M N Z 1
DEC Decrement dec Y reg, M N Z
HALT Halt 0
IRET Interrupt routine return Pop CC, A, X, PC H I N Z C
INC Increment inc X reg, M N Z
JP Absolute Jump jp [TBL.w]
JRA Jump relative always
JRT Jump relative
JRF Never jump jrf *
JRIH Jump if ext. interrupt = 1
JRIL Jump if ext. interrupt = 0
JRH Jump if H = 1 H = 1 ?
JRNH Jump if H = 0 H = 0 ?
JRM Jump if I = 1 I = 1 ?
JRNM Jump if I = 0 I = 0 ?
JRMI Jump if N = 1 (minus) N = 1 ?
JRPL Jump if N = 0 (plus) N = 0 ?
JREQ Jump if Z = 1 (equal) Z = 1 ?
JRNE Jump if Z = 0 (not equal) Z = 0 ?
JRC Jump if C = 1 C = 1 ?
JRNC Jump if C = 0 C = 0 ?
JRULT Jump if C = 1 Unsigned <
JRUGE Jump if C = 0 Jmp if unsigned >=
JRUGT Jump if (C + Z = 0) Unsigned >
ST72104G, ST72215G, ST72216G, ST72254G
95/135
INSTRUCTION GROUPS (Cont’d)
Mnemo Description Function/Example Dst Src H I N Z C
JRULE Jump if (C + Z = 1) Unsigned <=
LD Load dst <= src reg, M M, reg N Z
MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0
NEG Negate (2’s compl) neg $10 reg, M N Z C
NOP No Operation
OR OR operation A = A + M A M N Z
POP Pop from the Stack pop reg reg M
pop CC CC M H I N Z C
PUSH Push onto the Stack push Y M reg, CC
RCF Reset carry flag C = 0 0
RET Subroutine Return
RIM Enable Interrupts I = 0 0
RLC Rotate left true C C <= Dst <= C reg, M N Z C
RRC Rotate right true C C => Dst => C reg, M N Z C
RSP Reset Stack Pointer S = Max allowed
SBC Subtract with Carry A = A - M - C A M N Z C
SCF Set carry flag C = 1 1
SIM Disable Interrupts I = 1 1
SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C
SLL Shift left Logic C <= Dst <= 0 reg, M N Z C
SRL Shift right Logic 0 => Dst => C reg, M 0 Z C
SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C
SUB Subtraction A = A - M A M N Z C
SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z
TNZ Test for Neg & Zero tnz lbl1 N Z
TRAP S/W trap S/W interrupt 1
WFI Wait for Interrupt 0
XOR Exclusive OR A = A XOR M A M N Z
ST72104G, ST72215G, ST72216G, ST72254G
96/135
13 ELECTRICAL CHARACTERISTICS
13.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
ferred to VSS.
13.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
devices with an ambient temperature at TA=25°C
and TA=TAmax (given bythe selected temperature
range).
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
13.1.2 Typical values
Unless otherwise specified, typical data are based
on TA=25°C, VDD=5V (for the 4.5V≤VDD≤5.5V
voltage range)and VDD=3.3V (for the3V≤VDD≤4V
voltage range). They are given only as design
guidelines and are not tested.
13.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
13.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 49.
Figure 49. Pin loading conditions
13.1.5 Pin input voltage
The input voltage measurement on a pin of the de-
vice is described in Figure 50.
Figure 50. Pin input voltage
CL
ST7 PIN
VIN
ST7 PIN
ST72104G, ST72215G, ST72216G, ST72254G
97/135
13.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
13.2.1 Voltage Characteristics
13.2.2 Current Characteristics
13.2.3 Thermal Characteristics
Notes:
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩfor
RESET, 10kΩfor I/Os). Unused I/O pins must betied in the same way to VDD orVSS according totheir reset configuration.
2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to
IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.
3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive
and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maxi-
mum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.
Symbol Ratings Maximum value Unit
VDD -V
SS Supply voltage 6.5 V
VIN Input voltage on any pin 1) &2) VSS-0.3 to VDD+0.3
VESD(HBM) Electro-static discharge voltage (Human Body Model) see Section 13.7.2 ”Absolute Elec-
trical Sensitivity” on page 110
VESD(MM) Electro-static discharge voltage (Machine Model)
Symbol Ratings Maximum value Unit
IVDD Total current into VDD power lines (source) 3) 80
mA
IVSS Total current out of VSS ground lines (sink) 3) 80
IIO
Output current sunk by any standard I/O and control pin 25
Output current sunk by any high sink I/O pin 50
Output current source by any I/Os and control pin - 25
IINJ(PIN) 2) & 4)
Injected current on ISPSEL pin ±5
Injected current on RESET pin ±5
Injected current on OSC1 and OSC2 pins ±5
Injected current on any other pin 5) & 6) ±5
ΣIINJ(PIN) 2) Total injected current (sum of all I/O and control pins) 5) ±20
Symbol Ratings Value Unit
TSTG Storage temperature range -65 to +150 °C
TJMaximum junction temperature
(see Section 14.2 ”THERMAL CHARACTERISTICS” on page 127 )
ST72104G, ST72215G, ST72216G, ST72254G
98/135
13.3 OPERATING CONDITIONS
13.3.1 General Operating Conditions
Figure 51. fOSC Maximum Operating Frequency Versus VDD Supply Voltage for ROM devices 2)
Figure 52. fOSC Maximum Operating Frequency Versus VDD Supply Voltage for FLASH devices 2)
Notes:
1. Guaranteed by construction. A/D operation and resonator oscillator start-up are not guaranteed below 1MHz.
2. Operating conditions with TA=-40 to +125°C.
3. FLASH programming tested in production at maximum TAwith two different conditions: VDD=5.5V, fCPU=8MHz and
VDD=3V, fCPU=4MHz.
Symbol Parameter Conditions Min Max Unit
VDD Supply voltage see Figure 51 and Figure 52 3.0 5.5 V
fOSC External clock frequency VDD≥3.5V for ROM devices
VDD≥4.5V for FLASH devices 01) 16 MHz
VDD≥3.0V 0 1) 8
TAAmbient temperature range
1 Suffix Version 0 70
°C
6 Suffix Version -40 85
7 Suffix Version -40 105
3 Suffix Version -40 125
fOSC [MHz]
SUPPLYVOLTAGE [V]
16
8
4
1
02.5 3 3.5 4 4.5 5 5.5
FUNCTIONALITY
FUNCTIONALITY
FUNCTIONALITY
GUARANTEED
IN THIS AREA
NOT GUARANTEED
IN THIS AREA NOT GUARANTEED
IN THIS AREA
WITH RESONATOR1)
fOSC [MHz]
SUPPLYVOLTAGE [V]
16
8
4
1
02.5 3 3.5 4 4.5 5 5.5
FUNCTIONALITY
FUNCTIONALITY
FUNCTIONALITY
GUARANTEED
IN THIS AREA 3)
NOT GUARANTEED
IN THIS AREA NOT GUARANTEED
IN THIS AREA
WITH RESONATOR1)
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
FOR TEMPERATURE HIGHER THAN 85°C3)
3.85
ST72104G, ST72215G, ST72216G, ST72254G
99/135
OPERATING CONDITIONS (Cont’d)
13.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject togeneral operating conditions for VDD,f
OSC, and TA.
Figure 53. High LVD Threshold Versus VDD and fOSC for FLASH devices 3)
Figure 54. Medium LVD Threshold Versus VDD and fOSC for FLASH devices 3)
Figure 55. Low LVD Threshold Versus VDD and fOSC for FLASH devices 2)
Notes:
1. LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested.
2. Data based on characterization results, not tested in production.
3. The VDD rise time rate condition isneeded to insure a correct device power-on and LVD reset. Not tested in production.
Symbol Parameter Conditions Min Typ 1) Max Unit
VIT+ Reset release threshold
(VDD rise)
High Threshold
Med. Threshold
Low Threshold
4.10 2)
3.75 2)
3.25 2)
4.30
3.90
3.35
4.50
4.05
3.45 V
VIT- Reset generation threshold
(VDD fall)
High Threshold
Med. Threshold
Low Threshold
3.85
3.50
3.00
4.05
3.65
3.10
4.25
3.80
3.20
Vhyst LVD voltage threshold hysteresis VIT+-VIT- 200 250 300 mV
VtPOR VDD rise time rate 3) 0.2 50 V/ms
tg(VDD) Filtered glitch delay on VDD 2) Not detected by the LVD 40 ns
fOSC [MHz]
SUPPLYVOLTAGE [V]
16
8
02.5 3 3.5 4 4.5 5 5.5
FUNCTIONAL AREA
DEVICE UNDER
FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA
FOR TEMPERATURES HIGHER THAN 85°C
RESET
IN THIS AREA
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
VIT-≥3.85
fOSC [MHz]
SUPPLYVOLTAGE [V]
16
8
02.5 3 VIT-≥3.5V 4 4.5 5 5.5
FUNCTIONAL AREA
DEVICE UNDER
FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA
FOR TEMPERATURES HIGHER THAN 85°C
RESET
IN THIS AREA
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
fOSC [MHz]
SUPPLYVOLTAGE [V]
16
8
02.5 VIT-≥3V 3.5 4 4.5 5 5.5
FUNCTIONAL AREA
DEVICE UNDER
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
FOR TEMPERATURES HIGHER THAN 85°C
RESET
IN THIS AREA
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
ST72104G, ST72215G, ST72216G, ST72254G
100/135
FUNCTIONAL OPERATING CONDITIONS (Cont’d)
Figure 56. High LVD Threshold Versus VDD and fOSC for ROM devices 2)
Figure 57. Medium LVD Threshold Versus VDD and fOSC for ROM devices 2)
Figure 58. Low LVD Threshold Versus VDD and fOSC for ROM devices 2)
Notes:
1. LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested.
2. The minimum VDD rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.
fOSC [MHz]
SUPPLYVOLTAGE [V]
16
8
02.5 3 3.5 4 4.5 5 5.5
FUNCTIONAL AREA
DEVICE UNDER
RESET
IN THIS AREA
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
VIT-≥3.85
fOSC [MHz]
SUPPLYVOLTAGE [V]
16
8
02.5 3 VIT-≥3.5V 4 4.5 5 5.5
FUNCTIONAL AREA
DEVICE UNDER
RESET
IN THIS AREA
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
fOSC [MHz]
SUPPLYVOLTAGE [V]
16
8
02.5 VIT-≥3.00V 3.5 4 4.5 5 5.5
FUNCTIONAL AREA
DEVICE UNDER
RESET
IN THIS AREA
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
ST72104G, ST72215G, ST72216G, ST72254G
101/135
13.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
13.4.1 RUN and SLOW Modes
Figure 59. Typical IDD in RUN vs. fCPU Figure 60. Typical IDD in SLOW vs. fCPU
Notes:
1. Typical data are based on TA=25°C, VDD=5V (4.5V≤VDD≤5.5V range) and VDD=3.3V (3V≤VDD≤3.6V range).
2. Data based on characterization results, tested in production at VDD max. and fCPU max.
3. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals
in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
4. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or
VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
Symbol Parameter Conditions Max Unit
∆IDD(∆Ta) Supply current variation vs. temperature Constant VDD and fCPU 10 %
Symbol Parameter Conditions Typ 1) Max 2) Unit
IDD
Supply current in RUN mode 3)
(see Figure 59)
4.5V≤VDD≤5.5V
fOSC=1MHz, fCPU=500kHz
fOSC=4MHz, fCPU=2MHz
fOSC=16MHz, fCPU=8MHz
500
1500
5600
900
2500
9000
µA
Supply current in SLOW mode 4)
(see Figure 60) fOSC=1MHz, fCPU=31.25kHz
fOSC=4MHz, fCPU=125kHz
fOSC=16MHz, fCPU=500kHz
150
250
670
450
550
1250
Supply current in RUN mode 3)
(see Figure 59)
3V≤VDD≤3.6V
fOSC=1MHz, fCPU=500kHz
fOSC=4MHz, fCPU=2MHz
fOSC=16MHz, fCPU=8MHz
300
970
3600
550
1350
4500
Supply current in SLOW mode 4)
(see Figure 60) fOSC=1MHz, fCPU=31.25kHz
fOSC=4MHz, fCPU=125kHz
fOSC=16MHz, fCPU=500kHz
100
170
420
250
300
700
3 3.5 4 4.5 5 5.5
VDD [V]
0
1
2
3
4
5
6
7
IDD [mA]
8MHz
4MHz 2MHz
500kHz
3 3.5 4 4.5 5 5.5
VDD [V]
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
IDD [mA] 500kHz
250kHz 125kHz
31.25kHz
ST72104G, ST72215G, ST72216G, ST72254G
102/135
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
13.4.2 WAIT and SLOW WAIT Modes
Figure 61. Typical IDD in WAIT vs. fCPU Figure 62. Typical IDD in SLOW-WAIT vs. fCPU
Notes:
1. Typical data are based on TA=25°C, VDD=5V (4.5V≤VDD≤5.5V range) and VDD=3.3V (3V≤VDD≤3.6V range).
2. Data based on characterization results, tested in production at VDD max. and fCPU max.
3. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1)
driven by external square wave, CSS and LVD disabled.
4. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at
VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD
disabled.
Symbol Parameter Conditions Typ 1) Max 2) Unit
IDD
Supply current in WAIT mode 3)
(see Figure 61)
4.5V≤VDD≤5.5V
fOSC=1MHz, fCPU=500kHz
fOSC=4MHz, fCPU=2MHz
fOSC=16MHz, fCPU=8MHz
150
560
2200
280
900
3000
µA
Supply current in SLOW WAIT mode 4)
(see Figure 62)
fOSC=1MHz, fCPU=31.25kHz
fOSC=4MHz, fCPU=125kHz
fOSC=16MHz, fCPU=500kHz
20
90
340
70
190
850
Supply current in WAIT mode 3)
(see Figure 61)
3V≤VDD≤3.6V
fOSC=1MHz, fCPU=500kHz
fOSC=4MHz, fCPU=2MHz
fOSC=16MHz, fCPU=8MHz
90
350
1370
200
550
1900
Supply current in SLOW WAIT mode 4)
(see Figure 62)
fOSC=1MHz, fCPU=31.25kHz
fOSC=4MHz, fCPU=125kHz
fOSC=16MHz, fCPU=500kHz
10
50
200
20
80
350
3 3.5 4 4.5 5 5.5
VDD [V]
0
0.5
1
1.5
2
2.5
3
IDD [mA]
8MHz
4MHz 2MHz
500kHz
3 3.5 4 4.5 5 5.5
VDD [V]
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
IDD [mA]
500kHz
250kHz 125kHz
31.25kHz
ST72104G, ST72215G, ST72216G, ST72254G
103/135
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
13.4.3 HALT Mode
13.4.4 Supply and Clock Managers
The previous current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode).
13.4.5 On-Chip Peripherals
Notes:
1. Typical data are based on TA=25°C.
2. All I/O pins in input mode with a static value at VDD or VSS (no load), CSS and LVD disabled. Data based on charac-
terization results, tested in production at VDD max. and fCPU max.
3. Data based on characterization results, not tested in production.
4. Data based on characterization results done with the external components specified in Section 13.5.3 and Section
13.5.4, not tested in production.
5. As the oscillator is based on a current source, the consumption does not depend on the voltage.
6. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/4) and timer
counter stopped (selecting external clock capability). Data valid for one timer.
7. Data based on a differential IDD measurement between reset configuration and a permanent SPI master communica-
tion (data sent equal to 55h).
8. Data based on a differential IDD measurement between reset configuration and I2C peripheral enabled (PE bit set).
9. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.
Symbol Parameter Conditions Typ 1) Max Unit
IDD Supply current in HALT mode 2) VDD=5.5V -40°C≤TA≤+85°C
0
10
µA
-40°C≤TA≤+125°C50
V
DD=3.6V -40°C≤TA≤+85°C6
-40°C≤TA≤+125°C50
Symbol Parameter Conditions Typ 1) Max 3) Unit
IDD(CK)
Supply current of internal RC oscillator 500 750
µA
Supply current of external RC oscillator 4) 525 750
Supply current of resonator oscillator 4) & 5) LP: Low power oscillator
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator
200
300
450
700
400
550
750
1000
Clock security system supply current 150 350
IDD(LVD) LVD supply current HALT mode 100 150
Symbol Parameter Conditions Typ Unit
IDD(TIM) 16-bit Timer supply current 6) fCPU=8MHz VDD=3.3V 50
µA
VDD=5.0V 150
IDD(SPI) SPI supply current 7) fCPU=8MHz VDD=3.3V 250
VDD=5.0V 350
IDD(I2C) I2C supply current 8) fCPU=8MHz VDD=3.3V 250
VDD=5.0V 350
IDD(ADC) ADC supply current when converting 9) fADC=4MHz VDD=3.3V 800
VDD=5.0V 1100
ST72104G, ST72215G, ST72216G, ST72254G
104/135
13.5 CLOCK AND TIMING CHARACTERISTICS
Subject togeneral operating conditions for VDD,f
OSC, and TA.
13.5.1 General Timings
13.5.2 External Clock Source
Figure 63. Typical Application with an External Clock Source
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) isthe number of tCPU cycles needed tofinish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
Symbol Parameter Conditions Min Typ 1) Max Unit
tc(INST) Instruction cycle time 2 3 12 tCPU
fCPU=8MHz 250 375 1500 ns
tv(IT) Interrupt reaction time 2)
tv(IT) =∆tc(INST) +10 10 22 tCPU
fCPU=8MHz 1.25 2.75 µs
Symbol Parameter Conditions Min Typ Max Unit
VOSC1H OSC1 input pin high level voltage
see Figure 63
0.7xVDD VDD V
VOSC1L OSC1 input pin low level voltage VSS 0.3xVDD
tw(OSC1H)
tw(OSC1L) OSC1 high or low time 3) 15 ns
tr(OSC1)
tf(OSC1) OSC1 rise or fall time 3) 15
ILOSCx Input leakage current VSS≤VIN≤VDD ±1µA
OSC1
OSC2
fOSC
EXTERNAL
ST72XXX
CLOCK SOURCE
Not connected internally
VOSC1L
VOSC1H
tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L)
IL
90%
10%
ST72104G, ST72215G, ST72216G, ST72254G
105/135
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
13.5.3 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four
different Crystal/Ceramic resonator oscillators. All
the information given in this paragraph are based
on characterization results with specified typical
external componants. In the application, the reso-
nator andthe load capacitors have to beplaced as
close as possible to the oscillator pins in order to
minimize output distortion and start-up stabiliza-
tion time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, pack-
age, accuracy...).
Figure 64. Typical Application with a Crystal or Ceramic Resonator
Notes:
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. tSU(OSC) is the typical oscillator start-up time measured between VDD=2.8V and the fetch of the first instruction (with a
quick VDD ramp-up from 0 to 5V (<50µs).
3. The oscillator selection canbe optimized in terms of supply current using anhigh quality resonator with small RSvalue.
Refer to crystal/ceramic resonator manufacturer for more details.
Symbol Parameter Conditions Min Max Unit
fOSC Oscillator Frequency 3) LP: Low power oscillator
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator
1
>2
>4
>8
2
4
8
16
MHz
RFFeedback resistor 20 40 kΩ
CL1
CL2
Recommanded load capacitances ver-
sus equivalent serial resistance of the
crystal or ceramic resonator (RS)
RS=200ΩLP oscillator
RS=200ΩMP oscillator
RS=200ΩMS oscillator
RS=100ΩHS oscillator
38
32
18
15
56
46
26
21
pF
i2OSC2 driving current
VDD=5V LP oscillator
VIN=VSS MP oscillator
MS oscillator
HS oscillator
40
110
180
400
100
190
360
700
µA
Oscil. Typical Crystal or Ceramic Resonators CL1
[pF] CL2
[pF] tSU(osc)
[ms] 2)
Reference Freq. Characteristic 1)
Crystal
LP
JAUCH
S-200-30-30/50 2MHz ∆fOSC=[±30ppm25°C,±30ppm∆Ta], Typ. RS=200Ω33 34 10~15
MP SS3-400-30-30/30 4MHz ∆fOSC=[±30ppm25°C,±30ppm∆Ta], Typ. RS=60Ω33 34 7~10
MS SS3-800-30-30/30 8MHz ∆fOSC=[±30ppm25°C,±30ppm∆Ta], Typ. RS=25Ω33 34 2.5~3
HS SS3-1600-30-30/30 16MHz ∆fOSC=[±30ppm25°C,±30ppm∆Ta], Typ. RS=15Ω33 34 1~1.5
Ceramic
LP
MURATA
CSA2.00MG 2MHz ∆fOSC=[±0.5%tolerance,±0.3%∆Ta,±0.3%aging,±x.x%correl] 33 30 4.2
MP CSA4.00MG 4MHz ∆fOSC=[±0.5%tolerance,±0.3%∆Ta,±0.3%aging,±x.x%correl] 33 30 2.1
MS CSA8.00MTZ 8MHz ∆fOSC=[±0.5%tolerance,±0.5%∆Ta,±0.3%aging,±x.x%correl] 33 30 1.1
HS CSA16.00MXZ040 16MHz ∆fOSC=[±0.5%tolerance,±0.3%∆Ta,±0.3%aging,±x.x%correl] 33 30 0.7
OSC2
OSC1 fOSC
CL1
CL2
i2
RF
ST72XXX
RESONATOR
WHEN RESONATOR WITH
INTEGRATEDCAPACITORS
ST72104G, ST72215G, ST72216G, ST72254G
106/135
CLOCK CHARACTERISTICS (Cont’d)
13.5.4 RC Oscillators
The ST7 internal clock can be supplied with an RC
oscillator. This oscillator can be used with internal or external components (selectable by option
byte).
Figure 65. Typical Application with RC oscillator
Figure 66. Typical Internal RC Oscillator Figure 67. Typical External RC Oscillator
Notes:
1. Data based on characterization results.
2. Guaranteed frequency range with the specified CEX and REX ranges taking into account the device process variation.
Data based on design simulation.
3. Data based on characterization results done with VDD nominal at 5V, not tested in production.
4. REX must have a positive temperature coefficient (ppm/°C), carbon resistors should therefore not be used.
5. Important:when noexternal CEX is applied, the capacitance tobe considered is theglobal parasitic capacitance which
is subject to high variation (package, application...). In this case, the RC oscillator frequency tuning has to be done by
trying out several resistor values.
Symbol Parameter Conditions Min Typ Max Unit
fOSC Internal RC oscillator frequency 1) see Figure 66 3.60 5.10 MHz
External RC oscillator frequency 2) 114
t
SU(OSC)
Internal RC Oscillator Start-up Time 3) 2.0
ms
External RC Oscillator Start-up Time 3) REX=47K
Ω,
CEX=”0”pF
REX=47K
Ω,
CEX=100pF
REX=10K
Ω,
CEX=6.8pF
REX=10K
Ω,
CEX=470pF
1.0
6.5
0.7
3.0
REX Oscillator external resistor 4) see Figure 67 10 47 KΩ
CEX Oscillator external capacitor 0 5) 470 pF
OSC1
OSC2
fOSC
CEX
REX
EXTERNAL RC
INTERNAL RC
VREF +
-
VDD
Current copy
Voltage generator CEX discharge
ST72XXX
3 5.5
VDD [V]
3.8
3.9
4
4.1
4.2
4.3
fosc [MHz] -40°C
+25°C+85°C
+125°C
0 6.8 22 47 100 270 470
Cex [pF]
0
5
10
15
20
fosc [MHz] Rex=10KOhm
Rex=15KOhm
Rex=22KOhm
Rex=33KOhm
Rex=39KOhm
Rex=47KOhm
ST72104G, ST72215G, ST72216G, ST72254G
107/135
CLOCK CHARACTERISTICS (Cont’d)
13.5.5 Clock Security System (CSS)
Figure 68. Typical Safe Oscillator Frequencies
Note:
1. Data based on characterization results, tested in production between 90KHz and 500KHz.
2. Filtered glitch on the fOSC signal. See functional description in Section 6.5 on page 23 for more details.
Symbol Parameter Conditions Min Typ Max Unit
fSFOSC Safe Oscillator Frequency 1) TA=25°C, VDD=5.0V 250 340 430 kHz
TA=25°C, VDD=3.3V 190 260 330
fGFOSC Glitch Filtered Frequency 2) 30 MHz
3 5.5
VDD [V]
200
250
300
350
400
fosc [kHz] -40°C
+25°C+85°C
+125°C
ST72104G, ST72215G, ST72216G, ST72254G
108/135
13.6 MEMORY CHARACTERISTICS
Subject togeneral operating conditions for VDD,f
OSC, and TAunless otherwise specified.
13.6.1 RAM and Hardware Registers
13.6.2 FLASH Program Memory
Notes:
1. Minimum VDD supply voltage without losing data stored in RAM (in in HALT mode or under RESET) or in hardware
registers (only in HALT mode). Guaranteed by construction, not tested in production.
2. Data based on characterization results, tested inproduction at TA=25°C.
3. Up to 16 bytes can be programmed at a time for a 4kBytes FLASH block (then up to 32 bytes at a time for an 8k device)
4. The data retention time increases when the TAdecreases.
5. Data based on reliability test results and monitored in production.
Symbol Parameter Conditions Min Typ Max Unit
VRM Data retention mode 1) HALT mode (or RESET) 1.6 V
Symbol Parameter Conditions Min Typ Max Unit
TA(prog) Programming temperature range 2) 02570°C
t
prog Programming time for 1~16 bytes 3) TA=+25°C825
ms
Programming time for 4 or 8kBytes TA=+25°C 2.1 6.4 sec
tret Data retention 5) TA=+55°C4) 20 years
NRW Write erase cycles5) TA=+25°C 100 cycles
ST72104G, ST72215G, ST72216G, ST72254G
109/135
13.7 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample ba-
sis during product characterization.
13.7.1 Functional EMS
(Electro Magnetic Susceptibility)
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
■ESD: Electro-Static Discharge (positive and
negative) is applied on all pinsof the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
■FTB: A Burst of Fast Transient voltage (positive
and negative)is appliedtoVDD and VSS through
a 100pF capacitor, until afunctional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
A device reset allows normal operations to be re-
sumed.
Figure 69. EMC Recommended star network power supply connection 2)
Notes:
1. Data based on characterization results, not tested in production.
2. The suggested 10nFand 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs.EMC
performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC recommen-
dations are given in other sections (I/Os, RESET, OSCx pin characteristics).
Symbol Parameter Conditions Neg 1) Pos 1) Unit
VFESD Voltage limits to be applied on any I/O pin
to induce a functional disturbance VDD=5V, TA=+25°C, fOSC=8MHz
conforms to IEC 1000-4-2 -1 1
kV
VFFTB Fast transient voltage burst limits to be ap-
plied through 100pF on VDD and VDD pins
to induce a functional disturbance
VDD=5V, TA=+25°C, fOSC=8MHz
conforms to IEC 1000-4-4 -4 4
VDD
VSS
0.1µF10nF
VDD
ST72XXX
VSSA
VDDA
0.1µF
POWER
SUPPLY
SOURCE
ST7
DIGITAL NOISE
FILTERING
EXTERNAL
NOISE
FILTERING
ST72104G, ST72215G, ST72216G, ST72254G
110/135
EMC CHARACTERISTICS (Cont’d)
13.7.2 Absolute Electrical Sensitivity
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressedin order to determine itsperformance in
terms of electrical sensitivity. For more details, re-
fer to the AN1181 ST7 application note.
13.7.2.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (3 positive then 3 nega-
tive pulses separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends of the
number of supply pins of the device(3 parts*(n+1)
supply pin). Two models are usually simulated:
Human Body Model and Machine Model. This test
conforms to the JESD22-A114A/A115A standard.
See Figure 70 and the following test sequences.
Human Body Model Test Sequence
–C
Lis loaded through S1 by the HV pulse gener-
ator.
– S1 switches position from generator to R.
– Adischarge fromCLthroughR(body resistance)
to the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
Machine Model Test Sequence
–C
Lis loaded through S1 by the HV pulse gener-
ator.
– S1 switches position from generator to ST7.
– A discharge from CLto the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
– R (machine resistance), in series with S2, en-
sures a slow discharge of the ST7.
Absolute Maximum Ratings
Figure 70. Typical Equivalent ESD Circuits
Notes:
1. Data based on characterization results, not tested in production.
Symbol Ratings Conditions Maximum value 1) Unit
VESD(HBM) Electro-static discharge voltage
(Human Body Model) TA=+25°C2000 V
VESD(MM) Electro-static discharge voltage
(Machine Model) TA=+25°C 200
ST7 S2
R=1500ΩS1
HIGH VOLTAGE CL=100pF
PULSE
GENERATOR ST7
S2
HIGH VOLTAGE
CL=200pF
PULSE
GENERATOR
R=10k~10MΩ
S1
HUMAN BODY MODEL MACHINE MODEL
ST72104G, ST72215G, ST72216G, ST72254G
111/135
EMC CHARACTERISTICS (Cont’d)
13.7.2.2 Static and Dynamic Latch-Up
■LU: 3 complementary static tests are required
on 10parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin), a current injection (applied to each
input, output and configurable I/O pin) and a
power supply switch sequence are performed
on each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard. For more details,
refer to the AN1181 ST7 application note.
■DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 71. For
more details, refer to the AN1181 ST7
application note.
Electrical Sensitivities
Figure 71. Simplified Diagram of the ESD Generator for DLU
Notes:
1. Class description: A Class is anSTMicroelectronics internal specification. Allits limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
Symbol Parameter Conditions Class 1)
LU Static latch-up class TA=+25°C
TA=+85°CA
A
DLU Dynamic latch-up class VDD=5.5V, fOSC=4MHz, TA=+25°CA
RCH=50MΩRD=330Ω
CS=150pF
ESD
HV RELAY
DISCHARGE TIP
DISCHARGE
RETURN CONNECTION
GENERATOR 2)
ST7
VDD
VSS
ST72104G, ST72215G, ST72216G, ST72254G
112/135
EMC CHARACTERISTICS (Cont’d)
13.7.3 ESD Pin Protection Strategy
To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit el-
ements. The stress generally affects the circuit el-
ements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
tected must not receive excessive current, voltage
or heating within their structure.
An ESD network combines the different input and
output ESD protections. Thisnetwork works, byal-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in Figure 72 and Figure 73 for standard
pins and in Figure 74 and Figure 75 for true open
drain pins.
Standard Pin Protection
To protect the output structure the following ele-
ments are added:
– A diode to VDD (3a) and a diode from VSS (3b)
– A protection device between VDD and VSS (4)
To protect the input structure the following ele-
ments are added:
– A resistor in series with the pad (1)
– A diode to VDD (2a) and a diode from VSS (2b)
– A protection device between VDD and VSS (4)
Figure 72. Positive Stress on a Standard Pad vs. VSS
Figure 73. Negative Stress on a Standard Pad vs. VDD
IN
VDD
VSS
(1)
(2a)
(2b)
(4)
OUT
VDD
VSS
(3a)
(3b)
Main path
Path to avoid
IN
VDD
VSS
(1)
(2a)
(2b)
(4)
OUT
VDD
VSS
(3a)
(3b)
Main path
ST72104G, ST72215G, ST72216G, ST72254G
113/135
EMC CHARACTERISTICS (Cont’d)
True Open Drain Pin Protection
The centralized protection (4) is not involvedin the
discharge of the ESD stresses applied to true
open drain pads due to the fact that a P-Buffer and
diode to VDD are not implemented. An additional
local protection between the pad and VSS (5a &
5b) is implemented to completly absorb the posi-
tive ESD discharge.
Multisupply Configuration
When several types of ground (VSS,V
SSA, ...) and
power supply (VDD,VDDA, ...)are available for any
reason (better noise immunity...), the structure
shown in Figure 76 is implemented to protect the
device against ESD.
Figure 74. Positive Stress on a True Open Drain Pad vs. VSS
Figure 75. Negative Stress on a True Open Drain Pad vs. VDD
Figure 76. Multisupply Configuration
IN
VDD
VSS
(1)
(2b)
(4)OUT
VDD
VSS
(3b)
Main path
Path to avoid
(5a) (5b)
IN
VDD
VSS
(1)
(2b)
(4)OUT
VDD
VSS
(3b)
Main path
(3b) (3b)
VDDA
VSSA
VDDA
VDD
VSS
BACK TO BACK DIODE
BETWEEN GROUNDS
VSSA
ST72104G, ST72215G, ST72216G, ST72254G
114/135
13.8 I/O PORT PIN CHARACTERISTICS
13.8.1 General Characteristics
Subject togeneral operating conditions for VDD,f
OSC, and TAunless otherwise specified.
Figure 77. Two typical Applications with unused I/O Pin
Figure 78. Typical IPU vs. VDD with VIN=VSS
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 77). Data based on design simulation and/or technology
characteristics, not tested in production.
5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-
scribed in Figure 78). This data is based on characterization results, tested in production at VDD max.
6. Data based on characterization results, not tested in production.
7. To generate an external interrupt, a minimum pulse width has tobe applied on anI/O portpin configured asan external
interrupt source.
Symbol Parameter Conditions Min Typ 1) Max Unit
VIL Input low level voltage 2) 0.3xVDD V
VIH Input high level voltage 2) 0.7xVDD
Vhys Schmitt trigger voltage hysteresis 3) 400 mV
ILInput leakage current VSS≤VIN≤VDD ±1µA
ISStatic current consumption 4) Floating input mode 200
RPU Weak pull-up equivalent resistor 5) VIN=VSS VDD=5V 80 120 250 kΩ
VDD=3.3V 170 200 230
CIO I/O pin capacitance 5 pF
tf(IO)out Output high to low level fall time 6) CL=50pF
Between 10% and 90% 25 ns
tr(IO)out Output low to high level rise time 6) 25
tw(IT)in External interrupt pulse time 7) 1t
CPU
10kΩUNUSED I/OPORT
ST72XXX
10kΩUNUSED I/OPORT
ST72XXX
VDD
3 3.5 4 4.5 5 5.5
Vdd [V]
0
10
20
30
40
50
60
70
Ipu [µA]
Ta=-40°C
Ta=25°CTa=85°C
Ta=125°C
ST72104G, ST72215G, ST72216G, ST72254G
115/135
I/O PORT PIN CHARACTERISTICS (Cont’d)
13.8.2 Output Driving Current
Subject togeneral operating conditions for VDD,f
OSC, and TAunless otherwise specified.
Figure 79. Typical VOL at VDD=5V (standard)
Figure 80. Typical VOL at VDD=5V (high-sink)
Figure 81. Typical VDD-VOH at VDD=5V
Notes:
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of
IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH.
Symbol Parameter Conditions Min Max Unit
VOL 1)
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 79 and Figure 82)
VDD=5V
IIO=+5mA 1.2
V
IIO=+2mA 0.5
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 80 and Figure 83)
IIO=+20mA,TA≤85°C
TA≥85°C1.3
1.5
IIO=+8mA 0.6
VOH 2) Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 81 and Figure 84)
IIO=-5mA, TA≤85°C
TA≥85°CVDD-1.4
VDD-1.6
IIO=-2mA VDD-0.7
0246810
Iio [mA]
0
0.5
1
1.5
2
2.5
Vol [V] at Vdd=5V
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
0 5 10 15 20 25 30
Iio [mA]
0
0.5
1
1.5
2
Vol [V] at Vdd=5V
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
-8 -6 -4 -2 0
Iio [mA]
1
2
3
4
5
6
Vdd-Voh [V] at Vdd=5V
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
ST72104G, ST72215G, ST72216G, ST72254G
116/135
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 82. Typical VOL vs. VDD (standard I/Os)
Figure 83. Typical VOL vs. VDD (high-sink I/Os)
Figure 84. Typical VDD-VOH vs. VDD
3 3.5 4 4.5 5 5.5
Vdd [V]
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Vol [V] at Iio=2mA Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
3 3.5 4 4.5 5 5.5
Vdd [V]
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
Vol [V] at Iio=5mA Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
3 3.5 4 4.5 5 5.5
Vdd [V]
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
Vol [V] at Iio=8mA Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
3 3.5 4 4.5 5 5.5
Vdd [V]
0.5
0.7
0.9
1.1
1.3
1.5
Vol [V] at Iio=20mA Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
3 3.5 4 4.5 5 5.5
Vdd [V]
2
2.5
3
3.5
4
4.5
5
5.5
Vdd-Voh [V] at Iio=-2mA
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
3.5 4 4.5 5 5.5
Vdd [V]
0
1
2
3
4
5
Vdd-Voh [V] at Iio=-5mA
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
ST72104G, ST72215G, ST72216G, ST72254G
117/135
13.9 CONTROL PIN CHARACTERISTICS
13.9.1 Asynchronous RESET Pin
Subject togeneral operating conditions for VDD,f
OSC, and TAunless otherwise specified.
Figure 85. Typical Application with RESET pin 8)
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
5. The RON pull-up equivalent resistor is based on a resistive transistor (corresponding ION current characteristics de-
scribed in Figure 86). This data is based on characterization results, not tested in production.
5. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin.
6. All short pulse applied on RESET pin with a duration below th(RSTL)in can be ignored.
7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy
environment.
8. The output ofthe external reset circuit must have an open-drain output to drive theST7 reset pad.Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
Symbol Parameter Conditions Min Typ 1) Max Unit
VIL Input low level voltage 2) 0.3xVDD V
VIH Input high level voltage 2) 0.7xVDD
Vhys Schmitt trigger voltage hysteresis 3) 400 mV
VOL Output low level voltage 4)
(see Figure 87, Figure 88) VDD=5V IIO=+5mA 0.68 0.95 V
IIO=+2mA 0.28 0.45
RON Weak pull-up equivalent resistor 5) VIN=VSS VDD=5V 20 40 60 kΩ
VDD=3.3V 80 100 120
tw(RSTL)out Generated reset pulse duration External pin or
internal reset sources 6
30 1/fSFOSC
µs
th(RSTL)in External reset pulse hold time 6) 20 µs
tg(RSTL)in Filtered glitch duration 7) 100 ns
RESET
VDD
WATCHDOG RESET
ST72XXX
LVD RESET
INTERNAL
RON
0.1µF
VDD
0.1µF
VDD
4.7kΩ
EXTERNAL
RESET
CIRCUIT 8)
RESET CONTROL
OPTIONAL
USER
ST72104G, ST72215G, ST72216G, ST72254G
118/135
CONTROL PIN CHARACTERISTICS (Cont’d)
Figure 86. Typical ION vs. VDD with VIN=VSS Figure 87. Typical VOL at VDD=5V (RESET)
Figure 88. Typical VOL vs. VDD (RESET)
3 3.5 4 4.5 5 5.5
Vdd [V]
0
50
100
150
200
Ion [µA]
Ta=-40°C
Ta=25°CTa=85°C
Ta=125°C
012345678
Iio [mA]
0
0.5
1
1.5
2
Vol [V] at Vdd=5V Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
3 3.5 4 4.5 5 5.5
Vdd [V]
0.4
0.6
0.8
1
1.2
Vol [V] at Iio=5mA Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
3 3.5 4 4.5 5 5.5
Vdd [V]
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
Vol [V] at Iio=2mA Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
ST72104G, ST72215G, ST72216G, ST72254G
119/135
CONTROL PIN CHARACTERISTICS (Cont’d)
13.9.2 ISPSEL Pin
Subject togeneral operating conditions for VDD,f
OSC, and TAunless otherwise specified.
Figure 89. Two typical Applications with ISPSEL Pin 2)
Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When the ISP Remote mode is not required by the application ISPSEL pin must be tied to VSS.
Symbol Parameter Conditions Min Max Unit
VIL Input low level voltage 1) VSS 0.2 V
VIH Input high level voltage 1) VDD-0.1 12.6
ILInput leakage current VIN=VSS ±1µA
ISPSEL
ST72XXX 10kΩ
PROGRAMMING
TOOL
ISPSEL
ST72XXX
ST72104G, ST72215G, ST72216G, ST72254G
120/135
13.10 TIMER PERIPHERAL CHARACTERISTICS
Subject to general operating conditions for VDD,
fOSC, and TAunless otherwise specified. Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(output compare, input capture, external clock,
PWM output...).
13.10.1 Watchdog Timer
13.10.2 16-Bit Timer
Symbol Parameter Conditions Min Typ Max Unit
tw(WDG) Watchdog time-out duration 12,288 786,432 tCPU
fCPU=8MHz 1.54 98.3 ms
Symbol Parameter Conditions Min Typ Max Unit
tw(ICAP)in Input capture pulse time 1 tCPU
tres(PWM) PWM resolution time 2t
CPU
fCPU=8MHz 250 ns
fEXT Timer external clock frequency 0 fCPU/4 MHz
fPWM PWM repetition rate 0 fCPU/4 MHz
ResPWM PWM resolution 16 bit
ST72104G, ST72215G, ST72216G, ST72254G
121/135
13.11 COMMUNICATION INTERFACE CHARACTERISTICS
13.11.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for VDD,
fOSC, and TAunless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Figure 90. SPI Slave Timing Diagram with CPHA=0 3)
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
Symbol Parameter Conditions Min Max Unit
fSCK
1/tc(SCK) SPI clock frequency
Master fCPU=8MHz fCPU/128
0.0625 fCPU/4
2MHz
Slave fCPU=8MHz 0fCPU/2
4
tr(SCK)
tf(SCK) SPI clock rise and fall time see I/O port pin description
tsu(SS) SS setup time Slave 120
ns
th(SS) SS hold time Slave 120
tw(SCKH)
tw(SCKL) SCK high and low time Master
Slave 100
90
tsu(MI)
tsu(SI) Data input setup time Master
Slave 100
100
th(MI)
th(SI) Data input hold time Master
Slave 100
100
ta(SO) Data output access time Slave 0 120
tdis(SO) Data output disable time Slave 240
tv(SO) Data output valid time Slave (after enable edge) 120
th(SO) Data output hold time 0
tv(MO) Data output valid time Master (before capture edge) 0.25 tCPU
th(MO) Data output hold time 0.25
SS INPUT
SCK INPUT
CPHA=0
MOSI INPUT
MISO OUTPUT
CPHA=0
tc(SCK)
tw(SCKH)
tw(SCKL) tr(SCK)
tf(SCK)
tv(SO)
ta(SO)
tsu(SI) th(SI)
MSB OUT
MSB IN
BIT6 OUT
LSB IN
LSB OUTsee note 2
CPOL=0
CPOL=1
tsu(SS) th(SS)
tdis(SO)
th(SO)
see
note 2
BIT1 IN
ST72104G, ST72215G, ST72216G, ST72254G
122/135
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 91. SPI Slave Timing Diagram with CPHA=11)
Figure 92. SPI Master Timing Diagram 1)
Notes:
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
SS INPUT
SCK INPUT
CPHA=0
MOSI INPUT
MISO OUTPUT
CPHA=0
tw(SCKH)
tw(SCKL) tr(SCK)
tf(SCK)
ta(SO)
tsu(SI) th(SI)
MSB OUT BIT6OUT LSB OUT
see
CPOL=0
CPOL=1
tsu(SS) th(SS)
tdis(SO)
th(SO)
see
note 2note 2
tc(SCK)
HZ
tv(SO)
MSB IN LSB IN
BIT1 IN
SS INPUT
SCK INPUT
CPHA=0
MOSI OUTPUT
MISO INPUT
CPHA=0
CPHA=1
CPHA=1
tc(SCK)
tw(SCKH)
tw(SCKL)
th(MI)
tsu(MI)
tv(MO) th(MO)
MSB IN
MSB OUT
BIT6IN
BIT6 OUT LSB OUT
LSB IN
see note 2 see note 2
CPOL=0
CPOL=1
CPOL=0
CPOL=1
tr(SCK)
tf(SCK)
ST72104G, ST72215G, ST72216G, ST72254G
123/135
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
13.11.2 I2C - Inter IC Control Interface
Subject to general operating conditions for VDD,
fOSC, and TAunless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SDAI and SCLI).The ST7 I2C interfacemeets the
requirements of the Standard I2C communication
protocol described in the following table.
Figure 93. Typical Application with I2C Bus and Timing Diagram4)
Notes:
1. Data based on standard I2C protocol requirement, not tested in production.
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
Symbol Parameter Standard modeI2C Fast mode I2CUnit
Min 1) Max 1) Min 1) Max1)
tw(SCLL) SCL clock low time 4.7 1.3 µs
tw(SCLH) SCL clock high time 4.0 0.6
tsu(SDA) SDA setup time 250 100
ns
th(SDA) SDA data hold time 0 3) 02) 900 3)
tr(SDA)
tr(SCL) SDA and SCL rise time 1000 20+0.1Cb300
tf(SDA)
tf(SCL) SDA and SCL fall time 300 20+0.1Cb300
th(STA) START condition hold time 4.0 0.6 µs
tsu(STA) Repeated START condition setup time 4.7 0.6
tsu(STO) STOP condition setup time 4.0 0.6 ns
tw(STO:STA) STOP to START condition time (bus free) 4.7 1.3 ms
CbCapacitive load for each bus line 400 400 pF
REPEATED START
START
STOP
START
tf(SDA) tr(SDA) tsu(SDA) th(SDA)
tf(SCK)
tr(SCK)
tw(SCKL)
tw(SCKH)
th(STA) tsu(STO)
tsu(STA) tw(STO:STA)
SDA
SCK
4.7kΩSDAI
ST72XXX
SCLI
VDD
100Ω
100Ω
VDD
4.7kΩ
I2CBUS
ST72104G, ST72215G, ST72216G, ST72254G
124/135
13.12 8-BIT ADC CHARACTERISTICS
Subject togeneral operating conditions for VDD,f
OSC, and TAunless otherwise specified.
Figure 94. Typical Application with ADC
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
lines and are not tested.
2. When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS .
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then
always valid.
Symbol Parameter Conditions Min Typ 1) Max Unit
fADC ADC clock frequency 4 MHz
VAIN Conversion range voltage 2) VSSA VDDA V
RAIN External input resistor 10 3) kΩ
CADC Internal sample and hold capacitor 6 pF
tSTAB Stabilization time after ADC enable
fCPU=8MHz, fADC=4MHz
04) µs
tADC
Conversion time (Sample+Hold) 3
- Sample capacitor loading time
- Hold conversion time 4
81/fADC
AINx
ST72XXX
CIO
~2pF
VDD
IL
±1µA
VT
0.6V
VT
0.6V
VAIN
RAIN
VDDA
VSSA
0.1µF
VDD
ADC
ST72104G, ST72215G, ST72216G, ST72254G
125/135
8-BIT ADC CHARACTERISTICS (Cont’d)
ADC Accuracy
Figure 95. ADC Accuracy Characteristics
Notes:
1. ADC Accuracy vs. Negative Injection Current:
For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB
for each 10KΩincrease of the external analog source impedance. This effect on the ADC accuracy has been observed
under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
-at5VV
DD supply, and worst case temperature.
3. Data based on characterization results over the whole temperature range, monitored in production.
Symbol Parameter Conditions Min Max Unit
|ET| Total unadjusted error 1)
VDD=5.0V, 3)
fCPU=8MHz
1
LSB
EOOffset error 1) -0.5 0.5
EGGain Error 1) -0.5 0.5
|ED| Differential linearity error 1) 0.5
|EL| Integral linearity error 1) 0.5
EO
EG
1 LSBIDEAL
1LSBIDEAL VDDA VSSA
–
256
-----------------------------------------=
Vin (LSBIDEAL)
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
Digital Result ADCDR
255
254
253
5
4
3
2
1
0
7
6
1 2 3 4 5 6 7 253 254 255 256
(1)
(2)
ET
ED
EL
(3)
VDDA
VSSA
ST72104G, ST72215G, ST72216G, ST72254G
126/135
14 PACKAGE CHARACTERISTICS
14.1 PACKAGE MECHANICAL DATA
Figure 96. 32-Pin Shrink Plastic Dual In Line Package
Figure 97. 28-Pin Plastic Small Outline Package, 300-mil Width
Dim. mm inches
Min Typ Max Min Typ Max
A3.56 3.76 5.08 0.140 0.148 0.200
A1 0.51 0.020
A2 3.05 3.56 4.57 0.120 0.140 0.180
b0.36 0.46 0.58 0.014 0.018 0.023
b1 0.76 1.02 1.40 0.030 0.040 0.055
C0.20 0.25 0.36 0.008 0.010 0.014
D27.43 27.94 28.45 1.080 1.100 1.120
E9.91 10.41 11.05 0.390 0.410 0.435
E1 7.62 8.89 9.40 0.300 0.350 0.370
e1.78 0.070
eA 10.16 0.400
eB 12.70 0.500
L2.54 3.05 3.81 0.100 0.120 0.150
Number of Pins
N32
1
N
b
D
VR01725J
N/2
b1
e
A
L
See Lead Detail
E1
e3
A2
A1
E
C
eB
eA
Dim. mm inches
Min Typ Max Min Typ Max
A2.35 2.65 0.0926 0.1043
A1 0.10 0.30 0.0040 0.0118
B0.33 0.51 0.013 0.020
C0.23 0.32 0.0091 0.0125
D17.70 18.10 0.6969 0.7125
E7.40 7.60 0.2914 0.2992
e1.27 0.0500
H10.01 10.64 0.394 0.419
h0.25 0.74 0.010 0.029
K0°8°
L0.41 1.27 0.016 0.050
G0.10 0.004
Number of Pins
N28
SO28
ST72104G, ST72215G, ST72216G, ST72254G
127/135
14.2 THERMAL CHARACTERISTICS
Notes:
1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD)
and PPORT is the port power dissipation determined by the user.
2. The average chip-junction temperature can be obtained from the formula TJ=TA+P
Dx RthJA.
Symbol Ratings Value Unit
RthJA
Package thermal resistance (junction to ambient)
SDIP32
SO28 60
75 °C/W
PDPower dissipation 1) 500 mW
TJmax Maximum junction temperature 2) 150 °C
ST72104G, ST72215G, ST72216G, ST72254G
128/135
14.3 SOLDERING AND GLUEABILITYINFORMATION
Recommended soldering information given only
as design guidelines in Figure 98 and Figure 99. Recommended glue for SMD plastic packages
dedicated to molding compound with silicone:
■Heraeus: PD945, PD955
■Loctite: 3615, 3298
Figure 98. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
Figure 99. Recommended Reflow Soldering Oven Profile (MID JEDEC)
14.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL
Table 21. Suggested List of SDIP32 Socket Types
Table 22. Suggested List of SO28 Socket Types
Package / Probe Adaptor / Socket Reference Same
Footprint Socket Type
SDIP32
EMU PROBE TEXTOOL 232-1291-00 X Textool
Package / Probe Adaptor / Socket Reference Same
Footprint Socket Type
SO28 ENPLAS OTS-28-1.27-04 Open Top
YAMAICHI IC51-0282-334-1 Clamshell
EMU PROBE Adapter from SO28 to SDIP32 footprint (delivered with emulator) X SMD to SDIP
250
200
150
100
50
040 80 120 160Time [sec]
Temp. [°C]
20 60 100 140
5 sec COOLING PHASE
(ROOM TEMPERATURE)
PREHEATING
80°C
PHASE
SOLDERING
PHASE
250
200
150
100
50
0100 200 300 400 Time [sec]
Temp. [°C]
ramp up
2°C/sec for 50sec
90 sec at 125°C150 sec above 183°C
ramp down natural
2°C/sec max
Tmax=220+/-5°C
for 25 sec
ST72104G, ST72215G, ST72216G, ST72254G
129/135
15 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each deviceis available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (ROM). FLASH devices are
shipped to customers with a default content (FFh),
while ROM factory coded parts contain the code
supplied by the customer. This implies that FLASH
devices have to be configured by the customer us-
ing the Option Bytes while the ROM devices are
factory-configured.
15.1 OPTION BYTES
The two option bytes allow the hardware configu-
ration of the microcontroller to be selected.
The option bytes have no address in the memory
map and can be accessed only in programming
mode (for example using a standard ST7 program-
ming tool). The default content of the FLASH is
fixed to FFh.
In masked ROM devices, the option bytes are
fixed in hardware by the ROM code (see option
list).
USER OPTION BYTE 0
Bit 7:2 = Reserved, must always be 1.
Bit 1 = EXTIT
External Interrupt Configuration
.
This option bit allows the external interrupt map-
ping to be configured as shown in Table 23.
Table 23. External Interrupt Configuration
Bit 0 = FMP
Full memory protection.
This option bit enables ordisables external access
to the internal program memory (read-out protec-
tion). Clearing this bit causes the erasing (to 00h)
of the whole memory (including the option byte).
0: Program memory not read-out protected
1: Program memory read-out protected
USER OPTION BYTE 1
Bit 7 = CFC
Clock filter control on/off
This option bit enables or disables the clock filter
(CF) features.
0: Clock filter enabled
1: Clock filter disabled
Bit 6:4 = OSC[2:0]
Oscillator selection
These three option bits can be used to select the
main oscillator as shown in Table 24.
Bit 3:2 = LVD[1:0]
Low voltage detection selection
These option bits enable the LVD block with a se-
lected threshold as shown in Table 25.
Bit 1 = WDG HALT
Watchdog and halt mode
This option bit determines ifa RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Bit 0 = WDG SW
Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Table 24. Main Oscillator Configuration
Table 25. LVD Threshold Configuration
External IT0 External IT1 EXTIT
Ports PA7-PA0 Ports PB7-PB0
Ports PC5-PC0 1
Ports PA7-PA0
Ports PC5-PC0 Ports PB7-PB0 0
Selected Oscillator OSC2 OSC1 OSC0
External Clock (Stand-by) 111
~4 MHz Internal RC 110
1~14 MHz External RC 10X
Low Power Resonator (LP) 011
Medium Power Resonator (MP) 010
Medium Speed Resonator (MS) 001
High Speed Resonator (HS) 000
Configuration LVD1 LVD0
LVD Off 11
Highest Voltage Threshold (∼4.50V) 10
Medium Voltage Threshold (∼4.05V) 01
Lowest Voltage Threshold (∼3.45V) 00
USER OPTIONBYTE 0
70
USER OPTION BYTE 1
70
Reserved EXTIT FMP CFC OSC
2OSC
1OSC
0LVD1 LVD0 WDG
HALT WDG
SW
Default
Value 1111111011101111
ST72104G, ST72215G, ST72216G, ST72254G
130/135
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the S19 hexadecimal file
generated by the development tool. All unused
bytes must be set to FFh.
The selected options are communicated to
STMicroelectronics using the correctly completed
OPTION LIST appended.
The STMicroelectronicsSales Organizationwill be
pleased to provide detailed information on con-
tractual points.
Figure 100. ROM Factory Coded Device Types
Figure 101. FLASH User Programmable Device Types
DEVICE PACKAGE TEMP.
RANGE XXX
/
Code name (defined by STMicroelectronics)
1= standard 0 to +70 °C
6= industrial -40 to +85 °C
7= automotive -40 to +105°C
3 = automotive -40 to +125 °C
B= Plastic DIP
M= Plastic SOIC
ST72104G1, ST72104G2,
ST72215G2, ST72216G1,
ST72254G1, ST72254G2
DEVICE PACKAGE TEMP.
RANGE
1= standard 0 to +70 °C
6= industrial -40 to +85 °C
7= automotive -40 to +105°C
3 = automotive -40 to +125 °C
B= Plastic DIP
M= Plastic SOIC
ST72C104G1, ST72C104G2,
ST72C215G2, ST72C216G1,
ST72C254G1, ST72C254G2
ST72104G, ST72215G, ST72216G, ST72254G
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TRANSFER OF CUSTOMER CODE (Cont’d)
MICROCONTROLLEROPTION LIST
Customer . . . . ..............................................................
Address . . . . ..............................................................
..................................................................
Contact . . . . ..............................................................
Phone No . . . . ..............................................................
Reference . . . . ..............................................................
STMicroelectronics references
Device: [] ST72104G1 [ ] ST72215G2 [ ] ST72254G1
[ ] ST72104G2 [ ] ST72216G1 [ ] ST72254G2
Package: [ ] SDIP32 [ ] SO28 with Standard conditionning (tube)
[ ] SO28 with Tape & Reel conditionning
External Interrupt: [ ] IT0 interrupt vector Port A, IT1 interrupt vector Port B & C
[ ] IT0 interrupt vector Port A & C, IT1 interruptvector Port B
Temperature Range: [ ] 0°Cto+70°C[]-40°C to + 105°C
[]-40°Cto+85°C[]-40°C to + 125°C
ClockSource Selection: [ ] Resonator: [ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP:Medium power resonator(2 to 4 MHz)
[ ] MS:Medium speed resonator (4 to 8 MHz)
[ ] HS:High speed resonator (8 to 16 MHz)
[ ] RC Network: [ ] Internal
[ ] External
[ ] External Clock
ClockSecurity System: [ ] Disabled [ ] Enabled
Watchdog Selection: [ ] SoftwareActivation [ ] Hardware Activation
Halt when Watchdog on: [ ] Reset [ ] No reset
Readout Protection: [ ] Disabled [ ] Enabled
LVD Reset [ ] Disabled []Enabled: [ ] Highest threshold (4.05V/4.30V)
[ ] Medium threshold (3.65V/3.90V)
[ ] Lowest threshold(3.10V/3.35V)
Comments : . . . . . . . . . . . . . . . . . . ...............................................
Supply Operating Range in the application: . . . . . . . . . . . .. . . . . . .......................
Notes . . . . ..............................................................
Signature . . . . ..............................................................
Date . . . . ..............................................................
ST72104G, ST72215G, ST72216G, ST72254G
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15.3 DEVELOPMENT TOOLS
STmicroelectronics offers a range of hardware
and software development tools for the ST7 micro-
controller family. Full details of tools available for
the ST7 from third party manufacturers can be ob-
tain from the STMicroelectronics Internet site:
➟http//mcu.st.com.
Third Party Tools
■ACTUM
■BP
■COSMIC
■CMX
■DATA I/O
■HITEX
■HIWARE
■ISYSTEM
■KANDA
■LEAP
Tools from these manufacturers include C compli-
ers, emulators and gang programmers.
STMicroelectronics Tools
Three types of development tool are offered by
ST, all of them connect to a PC via a parallel (LPT)
port: see Table 26 and Table 27 for more details.
Table 26. STMicroelectronic Tool Features
Table 27. Dedicated STMicroelectronics Development Tools
Note:
1. In-Situ Programming (ISP) interface for FLASH devices.
In-Circuit Emulation Programming Capability1) Software Included
ST7 Development Kit Yes. (Same features as
HDS2 emulator but without
logic analyzer) Yes (DIP packages only) ST7 CD ROM with:
– ST7 Assembly toolchain
– STVD7 and WGDB7 powerful
Source Level Debugger for Win
3.1, Win 95 and NT
– C compiler demo versions
– ST Realizer forWin 3.1 andWin
95.
– Windows Programming Tools
for Win 3.1, Win 95 and NT
ST7 HDS2 Emulator Yes, powerful emulation
features including trace/
logic analyzer No
ST7 Programming Board No Yes (All packages)
Supported Products ST7 Development Kit ST7 HDS2 Emulator ST7 Programming Board
ST72254G1, ST72C254G1
ST72254G2, ST72C254G2
ST72215G2, ST72C215G2
ST72216G1, ST72C216G1
ST72104G1, ST72C104G1,
ST72104G2, ST72C104G2
ST7MDT1-DVP2 ST7MDT1-EMU2B ST7MDT1-EPB2/EU
ST7MDT1-EPB2/US
ST7MDT1-EPB2/UK
ST72104G, ST72215G, ST72216G, ST72254G
133/135
15.4 ST7 APPLICATION NOTES
15.5 TO GET MORE INFORMATION
To get the latest information on this product please use the ST web server.➟http://mcu.st.com/
Identification Description
PROGRAMMING AND TOOLS
AN985 Executing code in ST7 RAM
AN986 Using the ST7 indirect addressing mode
AN987 ST7 in-circuit programming
AN988 Starting with ST7 assembly tool chain
AN989 Starting with ST7 Hiware C
AN1039 ST7 math utility routines
AN1064 Writing optimized hiware C language for ST7
AN1179 Programming ST7 Flash Microcontrollers in Remote ISP Mode (In-Situ Programming)
EXAMPLE DRIVERS
AN969 ST7 SCI communication between the ST7 and a PC
AN970 ST7 SPI communication between the ST7 and E PROM
AN971 ST7 I C c ommunication between the ST7 and E PROM
AN972 ST7 software SPI master communication
AN973 SCI software communication with a PC using ST72251 16-bit timer
AN974 Real time clock with the ST7 timer output compare
AN976 Driving a buzzer using the ST7 PWM function
AN979 Driving an analog keyboard with the ST7 ADC
AN980 ST7 keypad decoding techniques, implementing wake-up on keystroke
AN1017 Using the ST7 USB microcontroller
AN1041 Using ST7 PWM signal to generate analog output (sinusoid)
AN1042 ST7 routine for I C slave mode management
AN1044 Multiple interrupt sources management for ST7 MCUs
AN1045 ST7 software implementation o f I C b us master
AN1047 Managing reception errors with the ST7 SCI peripheral
AN1048 ST7 software LCD driver
AN1048 ST7 timer PWM duty cycle switch for true 0% or 100% duty cycle
PRODUCT OPTIMIZATION
AN982 Using ceramic resonators with the ST7
AN1014 How to minimize the ST7 power consumption
AN1070 ST7 checksum selfchecking capability
PRODUCT EVALUATION
AN910 ST7 and ST9 performance benchmarking
AN990 ST7 benefits versus industry standard
AN1181 Electrostatic discharge sensitivity measurement
APPLICATION EXAMPLES
AN1086 ST7 / ST10U435 CAN-Do solutions for car multiplexing
ST72104G, ST72215G, ST72216G, ST72254G
134/135
16 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Rev. Main changes Date
2.2 Power saving mode corrected in Figure 18 on page 28 and Figure 20 on page 29. Feb-00
ST72104G, ST72215G, ST72216G, ST72254G
135/135
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useof such information nor forany infringement of patents or other rights of third parties which may result from itsuse. No license isgranted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2000 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
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