Revised February 1999 DM74LS193 Synchronous 4-Bit Binary Counters with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation is provided by having all flip-flops clocked simultaneously, so that the outputs change together when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (rippleclock) counters. The outputs of the four master-slave flip-flops are triggered by a LOW-to-HIGH level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is held HIGH. The counter is fully programmable; that is, each output may be preset to either level by entering the desired data at the inputs while the load input is LOW. The output will change independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A clear input has been provided which, when taken to a high level, forces all outputs to the low level; independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements of clock drivers, etc., required for long words. These counters were designed to be cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up and down counting functions. The borrow output produces a pulse equal in width to the count down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the count down input when an overflow condition exists. The counters can then be easily cascaded by feeding the borrow and carry outputs to the count down and count up inputs respectively of the succeeding counter. Features * Fully independent clear input * Synchronous operation * Cascading circuitry provided internally * Individual preset each flip-flop Ordering Code: Order Number Package Number Package Description DM74LS193N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide DM74LS193M M16A 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body Connection Diagram (c) 1999 Fairchild Semiconductor Corporation DS006406.prf www.fairchildsemi.com DM74LS193 Synchronous 4-Bit Binary Counters with Dual Clock September 1986 DM74LS193 Logic Diagram www.fairchildsemi.com 2 DM74LS193 Timing Diagram Note A: Clear overrides load, data, and count inputs Note B: When counting up, count-down input must be HIGH; when counting down, count-up input must be HIGH. 3 www.fairchildsemi.com DM74LS193 Absolute Maximum Ratings(Note 1) Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the abbsolute maximum ratings. The "Reccommended Operating Conditions" table will define the conditions for actual device operation. Operating Free Air Temperature Range -0C to +70C Supply Voltage 7V Input Voltage 7V Storage Temperature Range -65C to +125C Recommended Operating Conditions Symbol Parameter Min Nom Max Units 4.75 5 5.25 V VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current -0.4 mA IOL LOW Level Output Current 8 mA fCLK Clock Frequency (Note 2) 2 V 0 25 MHz Clock Frequency (Note 3) tW Pulse Width of any Input (Note 4) 20 ns tSU Data Setup Time (Note 4) 20 ns tH Data Hold Time (Note 4) 0 ns tEN Enable Time to Clock (Note 4) 40 TA Free Air Operating Temperature 0 ns C 70 Note 2: CL = 15 pF, R L = 2 k, IA = 25C and V CC = 5V. Note 3: CL = 50 pF, R L = 2 k, IA = 25C and V CC = 5V. Note 4: TA = 25C and V CC = 5V. DC Electrical Characteristics Symbol Parameter Conditions Min Typ VI Input Clamp Voltage VCC = Min, II = -18 mA VOH HIGH Level Output VCC = Min, IOH = Max 2.5 3.4 Voltage VIL = Max, VIH = Min 2.7 3.4 VOL Max (Note 5) -1.5 Units V V LOW Level Output VCC = Min, IOL = Max 0.25 0.4 Voltage VIL = Max, VIH = Min 0.35 0.5 IOL = 4 mA, VCC = Min 0.25 0.4 V II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 A IIL LOW Level Input Current VCC = Max, VI = 0.4V -0.4 mA IOS ICC Short Circuit VCC = Max -20 -100 Output Current (Note 6) -20 -100 Supply Current VCC = Max (Note 7) Note 5: All typicals are at VCC = 5V, TA = 25C. Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 7: ICC is measured with all outputs open, CLEAR and LOAD inputs grounded, and all other inputs at 4.5V. www.fairchildsemi.com 4 19 34 mA mA mA RL = 2 k From (Input) Symbol Parameter To (Output) CL = 15 pF Min fMAX Maximum Clock Frequency tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL tPLH Propagation Delay Time tPHL tPHL 25 Count Up Count Up Count Down 20 MHz 26 30 ns 24 36 ns 24 29 ns 24 32 ns 38 45 ns 47 54 ns 40 41 ns 40 47 ns 35 44 ns to Borrow Count Down to Borrow Either Count to Any Q Either Count Propagation Delay Time Load to Any Q Propagation Delay Time Load to HIGH-to-LOW Level Output Any Q HIGH-to-LOW Level Output Units Max to Carry to Any Q Propagation Delay Time CL = 50 pF Min to Carry HIGH-to-LOW Level Output LOW-to-HIGH Level Output Max Clear to Any Q 5 www.fairchildsemi.com DM74LS193 AC Electrical Characteristics DM74LS193 Synchronous 4-Bit Binary Counters with Dual Clock Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit(SOIC), JEDEC MS-012, 0150" Narrow Body Package Number M16A 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.