September 1986
Revised February 1999
DM74LS193 Synchronous 4-Bit Binary Counters with Dual Clock
© 1999 Fairchild Semicond uctor Corpor ation DS006406.prf www.fairchildsemi.com
DM74LS193
Synchronous 4-Bit Binary Counters with Dual Clock
General Descript ion
The DM74LS193 circuit is a synchronous up/down 4-bit
binar y c ounter. Synchr onous operatio n i s provided by hav-
ing all flip -flops clo cked simultaneou sly, so that the outp uts
change together when so instructed by the steering lo gic.
This mode of operation eliminates the output counting
spikes normally associated with asynchronous (ripple-
clock) counters.
The outpu ts of th e four mast er- sl ave flip-flop s are tr igg er ed
by a LOW-to-HIGH level transition of either count (clock)
input. The direction of counting is determined by which
count input is pulsed while the other count input is held
HIGH.
The counter is fully programmable; that is, each output ma y
be prese t to either level by enteri ng t he de sired data at the
inputs while the load inpu t is LOW. The output will change
independently of the count pulses. This feature allows the
counters to be used as modul o-N dividers by sim ply modi-
fying the count length with the preset inputs.
A clear input has been provided which, when taken to a
high level, fo rces all outputs to the low level; independent of
the count and load inputs. The clear , count, and load inputs
are buffered to lower the drive re quirements of clock driv-
ers, etc., required for long words.
These coun ters were de signe d to be casca ded witho ut the
need for external circuitry. Both borrow and carry outputs
are available to cascade both the up and down counting
functions. The borrow output produces a pulse equal in
width to the count down input when the counter underflows.
Simila rly, the carry o utput produces a pu lse equal in width
to the count down input wh en a n overflow con dition exists.
The counters can the n be easily cascaded by feeding the
borrow and carry outputs to the count d own a nd count up
inputs respectively of the succeeding counter.
Features
• Fully independent clear input
• Synchronous operation
• Cascading circuitry provided internally
• Individual preset each flip-flop
Ordering Code:
Connection Diagram
Order Number Package Number Package Description
DM74LS193N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
DM74LS193M M16A 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
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DM74LS193
Logic Diagra m
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DM74LS193
Timing Diagram
Note A: Clear overrides lo ad, data, and coun t in puts
Note B: When countin g up, c ount-down inp ut mu st be HIGH; when co unting down, co unt-up input must be HIGH.
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DM74LS193
Absolute Maximum Ratings(Note 1) Note 1: The “A bsolute Ma ximum Ratin gs” are thos e values beyond whic h
the safety of the device cannot be guaranteed. The device sh ould not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the abbsolute maximum rat-
ings. The “Re cco mme nde d Opera ting C ondi tions ” table will define the co n-
ditions for actual device operation.
Recommended Operating Conditions
Note 2: CL = 15 pF, RL = 2 kΩ, IA = 25°C and VCC = 5V.
Note 3: CL = 50 pF, RL = 2 kΩ, IA = 25°C and VCC = 5V.
Note 4: TA = 25°C and VCC = 5V.
DC Electrical Character istics
Note 5: All typicals are at VCC = 5V, TA = 25°C.
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 7: ICC is measured with all outpu t s o pen, CLEAR and LOAD inputs gro unded, and all other input s a t 4.5V.
Operating Free Air Temper ature Ra nge −0°C to +70°C
Supply Voltage 7V
Input Voltage 7V
Storage Temperature Range −65°C to +125°C
Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Lev el Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current −0.4 mA
IOL LOW Level Output Current 8 mA
fCLK Clock Frequency (Note 2) 0 25 MHz
Clock Frequency (Note 3)
tWPul se Width of any Input (Note 4) 20 ns
tSU Data Setup Time (Note 4) 20 ns
tHData Hold Time (Note 4) 0 ns
tEN Enable Time to Clock (Note 4) 40 ns
TAFree Air Operatin g Temperature 0 70 °C
Symbol Parameter Conditions Min Typ Max Units
(Note 5)
VIInput Clamp Voltage VCC = Min, I I = −18 mA −1.5 V
VOH HIGH Level Output VCC =Min, IOH =Max 2.5 3.4 V
Voltage VIL = Max, VIH = Min 2.7 3.4
VOL LOW Level Output VCC =Min, IOL =Max 0.25 0.4
Voltage VIL = Max, VIH = Min 0.35 0.5 V
IOL =4mA,V
CC =Min 0.25 0.4
IIInput Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA
IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA
IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA
IOS Short Circuit VCC = Max −20 −100 mA
Output Current (Note 6) −20 −100
ICC Supply Current VCC = Max (Note 7) 19 34 mA
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DM74LS193
AC Electrical Characteristics
From (Input) RL = 2 kΩ
Symbol Parameter To (Output) CL = 15 pF CL = 50 pF Units
Min Max Min Max
fMAX Maximum Clock Frequency 25 20 MHz
tPLH Propagation Delay Time Count Up 26 30 ns
LOW-to-HIGH Level Output to Carry
tPHL Propagation Delay Time Count Up 24 36 ns
HIGH-to-LOW Level Output to Carry
tPLH Propagation Delay Time Count Down 24 29 ns
LOW-to-HIGH Level Output to Borrow
tPHL Propagation Delay Time Count Down 24 32 ns
HIGH-to-LOW Level Output to Borrow
tPLH Propagation Delay Time Either Count 38 45 ns
LOW-to-HIGH Level Output to Any Q
tPHL Propagation Delay Time Either Count 47 54 ns
HIGH-to-LOW Level Output to Any Q
tPLH Propagation Delay Time Load to 40 41 ns
LOW-to-HIGH Level Output Any Q
tPHL Propagation Delay Time Load to 40 47 ns
HIGH-to-LOW Level Output Any Q
tPHL Propagation Delay Time Clear to 35 44 ns
HIGH-to-LOW Level Output Any Q
F airchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and F airchild reserves the right at any tim e without notice to change said circuitry and specifications.
DM74LS193 Synchronous 4-Bit Binary Counters with Dual Cloc k
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used h erein:
1. Life support devices or system s ar e devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A criti cal comp onent in any comp onent of a l ife suppor t
device or system whose failure to perform can be rea-
sonably expected to cau se the failure of the li fe support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit(SOIC), JEDEC MS-012, 0150” Narrow Body
Package Number M16A
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
