30 V, Low Noise, Rail-to-Rail Input/Output,
Low Power Operational Amplifiers
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
Rev. I Document Feedback
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FEATURES
Rail-to-rail input/output
Low power: 0.625 mA typical per amplifier at ±15 V
Gain bandwidth product: 15.9 MHz at AV = 100 typical
Unity-gain crossover: 9.9 MHz typical
−3 dB closed-loop bandwidth: 13.9 MHz typical at ±15 V
Low offset voltage: 100 µV maximum (SOIC)
Unity-gain stable
High slew rate: 4.6 V/µs typical
Low noise: 3.9 nV/√Hz typical at 1 kHz
Long-term offset voltage drift (10,000 hours): 3 µV typical
Temperature hysteresis: 4 µV typical
APPLICATIONS
Battery-powered instrumentation
High-side and low-side sensing
Power supply control and protection
Telecommunications
Digital-to-analog converter (DAC) output amplifiers
Analog-to-digital converter (ADC) input buffers
PIN CONNECTION DIAGRAM
08237-001
NOTES
1. F OR T HE LF CS P P ACKAGE,
THE EXPOSED PAD MUST BE
CONNECTED TO V –.
3+IN A
4V–
1OUT A
2–I N A
6–IN B
5+IN B
8 V+
7OUT B
ADA4084-2
Figure 1. ADA4084-2, 8-Lead LFCSP (CP); for Additional Packages and
Models, See the Pin Configurations and Function Descriptions Section
GENERAL DESCRIPTION
The ADA4084-1 (single), ADA4084-2 (dual), and ADA4084-4
(quad) are single-supply, 10 MHz bandwidth amplifiers featuring
rail-to-rail inputs and outputs. They are guaranteed to operate
from +3 V to +30 V (or ±1.5 V to ±15 V).
These amplifiers are well suited for single-supply applications
requiring both ac and precision dc performance. The combination
of wide bandwidth, low noise, and precision makes the
ADA4084-1/ADA4084-2/ADA4084-4 useful in a wide variety of
applications, including filters and instrumentation.
Other applications for these amplifiers include portable telecom-
munications equipment, power supply control and protection, and
use as amplifiers or buffers for transducers with wide output
ranges. Sensors requiring a rail-to-rail input amplifier include
Hall effect, piezoelectric, and resistive transducers.
The ability to swing rail to rail at both the input and output
enables designers to build multistage filters in single-supply
systems and to maintain high signal-to-noise ratios.
The ADA4084-1/ADA4084-2/ADA4084-4 are specified over
the industrial temperature range of −40°C to +125°C.
The single ADA4084-1 is available in the 5-lead SOT-23 and
8-lead SOIC; the dual ADA4084-2 is available in the 8-lead
SOIC, 8-lead MSOP, and 8-lead LFCSP surface-mount
packages; and the ADA4084-4 is offered in the 14-lead TSSOP
and 16-lead LFCSP.
The ADA4084-1/ADA4084-2/ADA4084-4 are members of a
growing series of high voltage, low noise op amps offered by
Analog Devices, Inc. (see Table 1).
Table 1. Low Noise Op Amps
Single
Dual
Quad
Voltage Noise
AD8597 AD8599 1.1 nV/Hz
ADA4004-1 ADA4004-2 ADA4004-4 1.8 nV/Hz
AD8675 AD8676 2.8 nV/Hz rail-to-rail output
AD8671 AD8672 AD8674 2.8 nV/Hz
OP27, OP37 3.2 nV/Hz
ADA4084-1 ADA4084-2 ADA4084-4 3.9 nV/Hz rail-to-rail
input/output
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Connection Diagram ................................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 4
Electrical Characteristics ............................................................. 4
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 11
±1.5 V Characteristics ................................................................ 11
±5 V Characteristics ................................................................... 17
±15 V Characteristics ................................................................ 23
Applications Information .............................................................. 29
Functional Description .............................................................. 29
Start-Up Characteristics ............................................................ 30
Input Protection ......................................................................... 30
Output Phase Reversal ............................................................... 30
Designing Low Noise Circuits in Single-Supply Applications .. 31
Comparator Operation .............................................................. 31
Long-Term Drift ......................................................................... 32
Temperature Hysteresis ............................................................. 32
Outline Dimensions ....................................................................... 33
Ordering Guide .......................................................................... 36
REVISION HISTORY
5/2017—Rev. H to Rev. I
Changed CP-8-12 to CP-8-11 ...................................... Throughout
Changed CP-16-26 to CP-16-17 .................................. Throughout
Changes to Features Section............................................................ 1
Added Long-Term Drift Section, Temperature Hysteresis
Section, Figure 112, Figure 113, and Figure 114; Renumbered
Sequentially ..................................................................................... 32
Updated Outline Dimensions ....................................................... 34
Changes to Ordering Guide .......................................................... 36
8/2015—Rev. G to Rev. H
Added 5-Lead SOT-23 ....................................................... Universal
Changes to Pin Connection Diagram Section, Figure 1, and
General Description Section ........................................................... 1
Deleted Figure 3; Renumbered Sequentially ................................. 1
Changes to Large Signal Voltage Gain Parameter, Table 2 .......... 4
Changes to Large Signal Voltage Gain Parameter, Table 3 .......... 5
Changes to Large Signal Voltage Gain Parameter, Table 4 .......... 6
Changes to Table 6 ............................................................................ 7
Moved Figure 3 ................................................................................. 8
Added Pin Configurations and Function Descriptions Section,
Figure 4, Figure 5, Table 7, Table 8, and Table 9; Renumbered
Sequentially ....................................................................................... 8
Added Figure 6, Figure 7, Figure 8, Table 10, and Table 11 ........ 9
Moved Figure 9 ............................................................................... 10
Added Table 12 ............................................................................... 10
Added Figure 11 and Figure 15..................................................... 11
Added Figure 42 and Figure 46..................................................... 17
Added Figure 73 and Figure 77..................................................... 23
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 35
6/2015—Rev. F to Rev. G
Changes to Figure 96 and Figure 97............................................. 24
1/2015—Rev. E to Rev. F
Moved Revision History ................................................................... 3
Changes to Table 5 ............................................................................. 7
Changes to Ordering Guide .......................................................... 29
7/2014—Rev. D to Rev. E
Added ADA4084-1 ............................................................. Universal
Added Figure 1; Renumbered Sequentially ................................... 1
Changes to Output Voltage High Parameter, Table 2 ................... 3
Changes to Current Noise Density Parameter, Table 3 ................ 4
Changes to Current Noise Density Parameter, Table 4 ................ 5
Changes to Figure 8 Caption, and Figure 9 to Figure 11 ............. 7
Changes to Figure 13 ......................................................................... 8
Changes to Figure 21 ......................................................................... 9
Added Figure 31; Renumbered Sequentially .............................. 11
Changes to Figure 30 Caption, and Figure 32 to Figure 34 ...... 11
Changes to Figure 36 Caption to Figure 39 Caption ................. 12
Changes to Figure 50 ...................................................................... 14
Added Figure 60 ............................................................................. 16
Changes to Figure 59 Caption, Figure 62, and Figure 63 .......... 16
Changes to Figure 65 Caption to Figure 68 Caption ................. 17
Changes to Figure 79 ...................................................................... 19
Added Figure 89 ............................................................................. 21
Changes to Figure 88 Caption, Figure 91 Caption, and
Figure 92 Caption ........................................................................... 21
Changes to Ordering Guide .......................................................... 28
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 3 of 36
11/2013—Rev. C to Rev. D
Added 14-Lead TSSOP and 16-Lead LFCSP Packages ....... Universal
Added ADA4084-4 ..................................................................... Universal
Change to Features Section and Applications Section ................. 1
Added Figure 2 and Figure 3; Renumbered Sequentially ............ 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 4
Changes to Table 4 ............................................................................ 5
Changes to Table 5 and Table 6 ....................................................... 6
Changes to Typical Performance Characteristics Section ........... 7
Updated Outline Dimensions ........................................................ 27
Changes to Ordering Guide ........................................................... 28
4/2013—Rev. B to Rev. C
Changes to Figure 48 Caption ....................................................... 15
Updated Outline Dimensions ........................................................ 25
6/2012—Rev. A to Rev. B
Added LFCSP Package....................................................... Universal
Changes to Figure 1 ........................................................................... 1
Changes to Output Voltage High Parameter, Table 4 ................... 5
Added Figure 5 and Figure 7, Renumbered Sequentially ............ 7
Added Figure 30 and Figure 32 ..................................................... 12
Added Figure 55 and Figure 57 ..................................................... 17
Added Startup Characteristics Section ........................................ 23
Moved Figure 78 .............................................................................. 23
Changes to Output Phase Reversal Section and Comparator
Operation Section ........................................................................... 24
Updated Outline Dimensions ........................................................ 25
Changes to Ordering Guide ........................................................... 26
2/2012—Rev. 0 to Rev. A
Changes to Data Sheet Title ............................................................. 1
Changes to Voltage Range in General Description ...................... 1
Changes to Supply Current/Amplifier Parameter, Table 2 .......... 3
Changes to Common-Mode Rejection Ratio Parameter, Table 3 .. 4
Changes to Common-Mode Rejection Ratio Parameter, Table 4 .. 5
Changes to Figure 2 .......................................................................... 6
Changes to Figure 24 ...................................................................... 10
Changes to Figure 32 ...................................................................... 12
Changes to Figure 47 ...................................................................... 14
Changes to Figure 55 ...................................................................... 16
Changes to Figure 62 ...................................................................... 17
Changes to Figure 73 ...................................................................... 20
10/2011—Revision 0: Initial Version
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 4 of 36
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VSY = 3 V, V CM = 1.5 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS SOIC package 20 100 µV
−40°C ≤ TA ≤ +125°C 200 µV
SOT-23, MSOP, TSSOP packages 50 130 µV
−40°C ≤ TA ≤ +125°C 250 µV
ADA4084-2 LFCSP package
80
200
µV
−40°C ≤ TA ≤ +125°C 300 µV
Offset Voltage Drift Δt/ΔT −40°C ≤ TA ≤ +125°C 0.5 1.75 µV/°C
Offset Voltage Matching TA = 25°C 150 µV
ADA4084-4 LFCSP package 200 µV
Input Bias Current IB 140 250 nA
−40°C ≤ TA ≤ +125°C 400 nA
Input Offset Current IOS 5 25 nA
−40°C ≤ TA ≤ +125°C 50 nA
Input Voltage Range 0 3 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 3 V 64 88 dB
−40°C ≤ TA ≤ +125°C 60 dB
A
VO
R
L
= 2 kΩ, 0.5 V ≤ V
OUT
≤ 2.5 V
100
104
dB
−40°C ≤ T
A
≤ +125°C
97
dB
Input Impedance
Differential 100||1.1 kΩ||pF
Common Mode 80||2.9 MΩ||pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VCM 2.90 2.95 V
−40°C ≤ TA ≤ +125°C 2.80 V
RL = 2 kΩ to VCM 2.85 2.9 V
−40°C ≤ TA ≤ +125°C 2.70 V
Output Voltage Low VOL RL = 10 kΩ to VCM 10 20 mV
−40°C ≤ TA ≤ +125°C 40 mV
RL = 2 kΩ to VCM 20 30 mV
−40°C ≤ TA ≤ +125°C 50 mV
Short-Circuit Current ISC −17/+10 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = 1 0.1 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±1.25 V to ±1.75 V 100 110 dB
−40°C ≤ TA ≤ +125°C 90 dB
Supply Current per Amplifier ISY IOUT = 0 mA 0.565 0.650 mA
−40°C ≤ TA ≤ +125°C 0.950 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 2.0 2.6 V/µs
GBP
V
IN
= 5 mV p-p, R
L
= 10 kΩ, A
V
= 100
15.4
MHz
Unity-Gain Crossover UGC VIN = 5 mV p-p, RL = 10 kΩ, AV = 1 8.08 MHz
Phase Margin ΦM 86 Degrees
−3 dB Closed-Loop Bandwidth −3 dB AV = 1, VIN = 5 mV p-p 12.3 MHz
Settling Time tS AV = 10, VIN = 2 V p-p, 0.1% 4 µs
Total Harmonic Distortion Plus Noise THD + N VIN = 300 mV rms, RL = 2 kΩ, f = 1 kHz 0.009 %
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.14 µV p-p
Voltage Noise Density en f = 1 kHz 3.9 nV/√Hz
i
n
f = 1 kHz
0.55
pA/√Hz
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 5 of 36
VSY = ±5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS SOIC package 30 100 µV
−40°C ≤ TA ≤ +125°C 200 µV
SOT-23, MSOP, TSSOP packages 60 130 µV
−40°C ≤ TA ≤ +125°C 250 µV
ADA4084-2 LFCSP package
90
200
µV
−40°C ≤ TA ≤ +125°C 300 µV
Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +125°C 0.5 1.75 µV/°C
Offset Voltage Matching TA = 25°C 150 µV
ADA4084-4 LFCSP package 200 µV
Input Bias Current IB 140 250 nA
−40°C ≤ TA ≤ +125°C 400 nA
Input Offset Current IOS 5 25 nA
−40°C ≤ TA ≤ +125°C 50 nA
Input Voltage Range −5 +5 V
Common-Mode Rejection Ratio CMRR VCM = ±4 V, −40°C ≤ TA ≤ +125°C 106 124 dB
VCM = ±5 V 76 dB
V
CM
= ±5 V, −40°C ≤ T
A
≤ +125°C
70
dB
Large Signal Voltage Gain
A
VO
R
L
= 2 kΩ, −4 V ≤ V
OUT
≤ 4 V
108
112
dB
−40°C ≤ TA ≤ +125°C 103 dB
Input Impedance
Differential 100||1.1 kΩ||pF
Common Mode 200||2.5 MΩ||pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VCM 4.9 4.95 V
−40°C ≤ TA ≤ +125°C 4.8 V
RL = 2 kΩ to VCM 4.8 4.85 V
−40°C ≤ T
A
≤ +125°C
4.7
V
Output Voltage Low VOL RL = 10 kΩ to VCM −4.95 −4.9 V
−40°C ≤ TA ≤ +125°C −4.8 V
RL = 2 kΩ to VCM −4.95 −4.8 V
−40°C ≤ TA ≤ +125°C −4.7 V
Short-Circuit Current ISC −24/+17 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = 1 0.1 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±2 V to ±18 V 110 120 dB
−40°C ≤ TA ≤ +125°C 105 dB
Supply Current per Amplifier ISY IOUT = 0 mA 0.595 0.700 mA
−40°C ≤ TA ≤ +125°C 1.00 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ to VCM 2.4 3.7 V/µs
Gain Bandwidth Product GBP VIN = 5 mV p-p, RL = 10 kΩ, AV = 100 15.9 MHz
Unity-Gain Crossover UGC VIN = 5 mV p-p, RL = 10 kΩ, AV = 1 9.6 MHz
Phase Margin ΦM 85 Degrees
−3 dB Closed-Loop Bandwidth −3 dB AV = 1, VIN = 5 mV p-p 13.9 MHz
Settling Time tS AV = 10, VIN = 8 V p-p, 0.1% 4 µs
Total Harmonic Distortion Plus Noise THD + N VIN = 2 V rms, RL = 2 kΩ, f = 1 kHz 0.003 %
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.14 µV p-p
Voltage Noise Density
e
n
f = 1 kHz
3.9
nV/√Hz
Current Noise Density in f = 1 kHz 0.55 pA/√Hz
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 6 of 36
VSY = ±15.0 V, VCM = 0 V, T A = 25°C, unless otherwise noted.
Table 4.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS SOIC package 40 100 µV
−40°C ≤ TA ≤ +125°C 200 µV
SOT-23, MSOP, TSSOP packages 70 130 µV
−40°C ≤ TA ≤ +125°C 250 µV
ADA4084-2 LFCSP package
100
200
µV
−40°C ≤ TA ≤ +125°C 300 µV
Offset Voltage Drift ΔVOS/ΔT 0.5 1.75 µV/°C
Offset Voltage Matching TA = 25°C 150 µV
ADA4084-4 LFCSP package 200 µV
Input Bias Current IB 140 250 nA
−40°C ≤ TA ≤ +125°C 400 nA
Input Offset Current IOS 5 25 nA
−40°C ≤ TA ≤ +125°C 50 nA
Input Voltage Range −15 +15 V
Common-Mode Rejection Ratio CMRR VCM = ±14 V, −40°C ≤ TA ≤ +125°C 106 124 dB
VCM = ±15 V 85 dB
V
CM
= ±15 V, −40°C ≤ T
A
≤ +125°C
80
dB
Large Signal Voltage Gain
A
VO
R
L
= 2 kΩ, −13.5 V ≤ V
OUT
≤ +13.5 V
110
117
dB
−40°C ≤ TA ≤ +125°C 105 dB
Input Impedance
Differential 100||1.1 kΩ||pF
Common Mode 200||2.5 MΩ||pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VCM 14.85 14.9 V
−40°C ≤ TA ≤ +125°C 14.8 V
RL = 2 kΩ to VCM 14.5 14.6 V
−40°C ≤ T
A
≤ +125°C
14.0
V
Output Voltage Low VOL RL = 10 kΩ to VCM −14.95 −14.9 V
−40°C ≤ TA ≤ +125°C −14.8 V
RL = 2 kΩ to VCM −14.9 −14.8 V
−40°C ≤ TA ≤ +125°C −14.7 V
Short-Circuit Current ISC ±30 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = +1 0.1 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±2 V to ±18 V 110 120 dB
−40°C ≤ TA ≤ +125°C 105 dB
Supply Current per Amplifier ISY IOUT = 0 mA 0.625 0.750 mA
−40°C ≤ TA ≤ +125°C 1.050 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 2.4 4.6 V/µs
Gain Bandwidth Product GBP VIN = 5 mV p-p, RL = 10 kΩ, AV = 100 15.9 MHz
Unity-Gain Crossover UGC VIN = 5 mV p-p, RL = 10 kΩ, AV = 1 9.9 MHz
Phase Margin ΦM 86 Degrees
−3 dB Closed-Loop Bandwidth −3 dB AV = 1, VIN = 5 mV p-p 13.9 MHz
Settling Time tS AV = 10, VIN = 10 V p-p, 0.1% 4 µs
Total Harmonic Distortion Plus Noise THD + N VIN = 5 V rms, RL = 2 kΩ, f = 1 kHz 0.003 %
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.1 µV p-p
Voltage Noise Density
e
n
f = 1 kHz
3.9
nV/√Hz
Current Noise Density in f = 1 kHz 0.55 pA/√Hz
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 7 of 36
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Supply Voltage ±18 V
Input Voltage
V− ≤ V
IN
≤ V+
Differential Input Voltage1 ±0.6 V
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec)
300°C
ESD
Human Body Model2 4.5 kV
Machine Model3 200 V
Field-Induced Charged-Device Model
(FICDM)4
1.25 kV
1 For input differential voltages greater than 0.6 V, limit the input current to
less than 5 mA to prevent degradation or destruction of the input devices.
2 Applicable standard: MIL-STD-883, Method 3015.7.
3 Applicable standard: JESD22-A115-A (ESD machine model standard of
JEDEC).
4 Applicable standard: JESD22-C101-C (ESD FICDM standard of JEDEC).
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the device soldered on a 4-layer JEDEC
standard printed circuit board (PCB) with zero airflow.
Table 6. Thermal Resistance
Package Type θJA θJC Unit
5-Lead SOT-23 (RJ-5) 219.4 155.6 °C/W
8-Lead SOIC_N (R-8) 121 43 °C/W
8-Lead MSOP (RM-8)
142
45
°C/W
8-Lead LFCSP (CP-8-11)1, 3 84 40 °C/W
14-Lead TSSOP (RU-14) 112 43 °C/W
16-Lead LFCSP (CP-16-17)2, 3
55 30 °C/W
1 Values are based on 4-layer (2S2P) JEDEC standard PCB, with four thermal
vias. Exposed pad soldered to PCB.
2 Values are based on 4-layer (2S2P) JEDEC standard PCB, with nine thermal
vias. Exposed pad soldered to PCB.
3 θJC measured on top of package.
ESD CAUTION
D2
D101
D100
D5 D4
D1
Q1
Q4 Q3
Q24
Q21 D20
Q13
Q18
Q19
Q23
Q2
FOLDED
CASCADE
V
EE
V
OUT
V
CC
V
BIAS
MIRROR
08237-002
R4
R5
R6
R7 C2
C1
R1 R2
R3
Figure 2. Simplified Schematic
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 8 of 36
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NIC
1
–IN
2
+IN
3
V–
4
NIC
8
V+
7
OUT
6
NIC
5
NOTES
1. NI C = NOT INT E RNALL Y CONNECT E D.
ADA4084-1
TOP VIEW
(No t t o Scal e)
08237-101
Figure 3. ADA4084-1, 8-Lead SOIC (R)
Table 7. 8-Lead SOIC, ADA4084-1 Pin Function Descriptions
Pin No. Mnemonic Description
1 NIC Not Internally Connected
2 −IN Negative Input
3 +IN Positive Input
4 V− Negative Supply
5 NIC Not Internally Connected
6 OUT Output
7 V+ Positive Supply
8
NIC
Not Internally Connected
OUT
1
V–
2
+IN
3
V+
5
ADA4084-1
–IN
4
08237-301
Figure 4. ADA4084-1, 5-Lead SOT-23 (RJ)
Table 8. 5-Lead SOT-23, ADA4084-1 Pin Function Descriptions
Pin No. Mnemonic Description
1
OUT
Output
2 V− Negative Supply
3 +IN Positive Input
4 −IN Negative Input
5 V+ Positive Supply
08237-104
NOTES
1. FOR THE LF CS P P ACKAGE,
THE EXPOSED PAD MUST BE
CONNE CTED T O V–.
+IN A
V–
OUT A
–IN A
–IN B
+IN B
V+
OUT B
3
4
1
2
6
5
8
7
ADA4084-2
TOP VIEW
(Not to Scal e)
Figure 5. ADA4084-2, 8-Lead LFCSP (CP)
Table 9. 8-Lead LFCSP, ADA4084-2 Pin Function Descriptions
Pin No. Mnemonic Description
1 OUT A Output, Channel A
2 −IN A Negative Input, Channel A
3 +IN A Positive Input, Channel A
4 V− Negative Supply
5 +IN B Positive Input, Channel B
6 −IN B Negative Input, Channel B
7 OUT B Output, Channel B
8 V+ Positive Supply
EPAD Exposed Pad. For the LFCSP package, the exposed pad must be connected to V−.
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 9 of 36
08237-302
+IN A
V–
OUT A
–IN A
–IN B
+IN B
V+
OUT B
1
2
3
4
8
7
6
5
ADA4084-2
TOP VIEW
(Not to Scale)
Figure 6. ADA4084-2, 8-Lead MSOP (RM)
08237-303
OUT A 1
–IN A 2
+IN A 3
V– 4
V+
8
OUT B
7
–IN B
6
+IN B
5
ADA4084-2
TOP VIEW
(Not to Scale)
Figure 7. ADA4084-2, 8-Lead SOIC (R)
Table 10. 8-Lead MSOP, 8-Lead SOIC, ADA4084-2 Pin Function Descriptions
Pin No. Mnemonic Description
1 OUT A Output, Channel A
2 −IN A Negative Input, Channel A
3 +IN A Positive Input, Channel A
4 V− Negative Supply
5 +IN B Positive Input, Channel B
6 −IN B Negative Input, Channel B
7 OUT B Output, Channel B
8 V+ Positive Supply B
OUT B
+IN B
–IN B
V+
–IN A
+IN A
OUT A
OUT C
+IN C
–IN C
V–
–IN D
+IN D
OUT D
1
2
3
4
5
6
7
14
13
12
11
10
9
8
ADA4084-4
TOP VIEW
(Not to Scale)
0
8237-102
Figure 8. ADA4084-4, 14-Lead TSSOP (RU)
Table 11. 14-Lead TSSOP, ADA4804-4 Pin Function Descriptions
Pin No. Mnemonic Description
1 OUT A Output, Channel A
2 −IN A Negative Input, Channel A
3 +IN A Positive Input, Channel A
4 V+ Positive Supply
5 +IN B Positive Input, Channel B
6 −IN B Negative Input, Channel B
7 OUT B Output, Channel B
8 OUT C Output, Channel C
9 −IN C Negative Input, Channel C
10 +IN C Positive Input, Channel C
11 V− Negative Supply
12 +IN D Positive Input, Channel D
13 −IN D Negative Input, Channel D
14 OUT D Output, Channel D
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 10 of 36
12
11
10
1
3
4
–IN D
+I N D
V–
9+I N C
–IN A
V+
2
+I N A
+I N B
6OUT B
5–IN B
7OUT C
8
–IN C
16 NIC
15 OUT A
14 OUT D
13 NIC
TOP
VIEW
ADA4084-4
NOTES
1. NIC = NOT INT E RNALL Y CONNECT E D.
2. FOR THE LF CSP PACKAGE, THE EXPOSED PAD
MUST BE CO NNE CTED TO V –.
08237-103
Figure 9. ADA4084-4, 16-Lead LFCSP (CP)
Table 12. 16-Lead LFCSP, ADA4084-4 Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN A Negative Input Channel A
2 +IN A Positive Input, Channel A
3 V+ Positive Supply
4 +IN B Positive Input, Channel B
5 −IN B Negative Input, Channel B
6 OUT B Output, Channel B
7 OUT C Output, Channel C
8 −IN C Negative Input, Channel C
9 +IN C Positive Input, Channel C
10
V−
Negative Supply
11 +IN D Positive Input, Channel D
12 −IN D Negative Input, Channel D
13 NIC Not Internally Connected
14 OUT D Output, Channel D
15 OUT A Output, Channel A
16
NIC
Not Internally Connected
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 11 of 36
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
±1.5 V CHARACTERISTICS
120
0
–100 –50 500100
NUMBER O F AMP LI FI E RS
V
OS
(µV)
20
40
60
80
100
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= ∞
–25 25–75 75
08237-003
Figure 10. Input Offset Voltage (VOS) Distribution, SOIC
0
10
20
30
40
50
60
70
80
90
100
–100 –75 –50 –25 025 50 75 100
NUMBER O F AMPLIFIERS
V
OS
(µV)
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= ∞
08237-306
Figure 11. Input Offset Voltage (VOS) Distribution, SOT-23
50
0
–100 –50 –25 25–75 75500100
NUMBER O F AMP LI FI E RS
V
OS
(µV)
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= ∞
5
10
15
20
25
30
35
40
45
08237-004
Figure 12. Input Offset Voltage (VOS) Distribution, MSOP and TSSOP
0
50
100
150
200
–200 –150 –100 –50 050 100
NUMBER OF AMPLIFIERS
V
OS
(µV)
08237-081
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= ∞
Figure 13. Input Offset Voltage (VOS) Distribution, LFCSP
60
002.0
NUMBER O F AMP LI FI E RS
TCV
OS
(µV/°C)
V
SY
= ±1. 5V
R
L
= ∞
–40°C ≤ T
A
≤ +125°C
10
20
30
40
50
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
08237-005
Figure 14. TCVOS Distribution, SOIC, MSOP, and TSSOP
0
2
4
6
8
10
12
14
16
18
20
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
NUMBER O F AMPLIFIERS
TCV
OS
(µV/°C)
V
SY
= ±1. 5V
R
L
= ∞
–40°C ≤T
A
≤+125°C
08237-309
Figure 15. TCVOS Distribution, SOT-23
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 12 of 36
0
5
10
15
20
25
30
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
NUMBER OF AMPLIFIERS
TCV
OS
(µV/°C)
08237-082
V
SY
= ±1. 5V
R
L
= ∞
–40°C ≤ T
A
≤ +125°C
Figure 16. TCVOS Distribution, LFCSP
500
–500
–1.50 –1.00 –0.50 01.501.000.50
INPUT OFFSET VOLTAGE (µV)
COMMON-MODE VOLTAGE (V)
–400
–300
–200
–100
0
100
200
300
400
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= ∞
08237-006
Figure 17. Input Offset Voltage vs. Common-Mode Voltage
–100
–75
–50
–25
0
25
50
75
100
–50–25 0 25 50 75 100125150
INPUT OFFSET VOLTAGE (µV)
TEMPERATURE (°C)
08237-108
VSY = ±1.5V
Figure 18. Input Offset Voltage vs. Temperature
–250
–200
–150
–100
50
–50 –25 025 50 75 100 125 150
08237-213
VSY = ± 1.5V
VCM = 0V
RL = ∞
INPUT BI AS CURRE NT (nA)
TEMPERATURE (°C)
IB+
IB–
Figure 19. Input Bias Current vs. Temperature
600
–600
–1.5 –1.0 1.0–0.5 0.501.5
INPUT BI AS CURRE NT (nA)
VCM (V)
–400
–200
0
200
400
TA = +85°C
TA = +25°C
TA = +125°C
TA = –40° C
VSY = ±1.5V
08237-008
Figure 20. Input Bias Current vs. VCM for Various Temperatures
1000
100
10
1
0.001 0.01 0.1 110
V
DO
(mV)
SOURCE CURRE NT (mA)
V
SY
= ±1. 5V
T
A
= 25° C
(V+) – V
OH
08237-009
Figure 21. Dropout Voltage (VDO) vs. Source Current
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 13 of 36
1000
100
10
1
0.001 0.01 0.1 110
V
DO
(mV)
SINK CURRE NT (mA)
V
SY
= ±1. 5V
T
A
= 25° C
V
OL
– (V–)
08237-010
Figure 22. Dropout Voltage (VDO) vs. Sink Current
120
–40
270
–90
0.1 100k
GAIN (d B)
PHASE ( Degrees)
FREQUENCY ( kHz )
–45
0
45
90
135
180
225
–20
20
0
40
60
80
100
110 100 1k 10k
VSY = ± 1.5V
TA = 25° C
RL = 10kΩ
08237-011
Figure 23. Open-Loop Gain and Phase vs. Frequency
60
–2010 100M
GAIN (d B)
FREQUENCY ( Hz )
–10
0
10
20
30
40
50
100 1k 10k 100k 10M1M
A
V
= +100
A
V
= +10
A
V
= +1
V
SY
= ±1. 5V
T
A
= 25° C
08237-012
Figure 24. Closed-Loop Gain vs. Frequency
1000
100
10
1
0.10
0.0110 100M
Z
OUT
(Ω)
FREQUENCY ( Hz )
100 1k 10k 100k 10M1M
V
SY
= ±1. 5V
T
A
= 25° C
A
V
= +10
A
V
= +100 A
V
= +1
08237-013
Figure 25. Output Impedance (ZOUT) vs. Frequency
140
–2010 100M
PSRR ( dB)
FREQUENCY ( Hz )
0
20
40
60
80
100
120
100 1k 10k 100k 10M1M
V
SY
= ±1. 5V
T
A
= 25° C
PSRR–
PSRR+
08237-014
Figure 26. PSRR vs. Frequency
140
120
100
80
60
40
20
010 100M
CMRR (dB)
FREQUENCY ( Hz )
100 1k 10k 100k 10M1M
V
SY
= ±1. 5V
T
A
= 25° C
08237-221
Figure 27. CMRR vs. Frequency
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 14 of 36
1.5
1.0
0.5
0
–1.5
–1.0
–0.5
0 2 4 6 8 10 12 14 16 18
VOLT AGE (V)
TIME (µs)
VSY = ± 1.5V
TA = 25° C
RL = 2kΩ
CL = 100pF
08237-016
Figure 28. Large Signal Transient Response
80
60
40
20
0
–80
–60
–40
–20
018
VOLT AGE (mV)
TIME (µs)
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= 2kΩ
C
L
= 100pF
08237-017
2 4 6 8 10 12 14 16
Figure 29. Small Signal Transient Response
2
–10
–8
–6
–4
–2
0
0.08
–0.04
–0.02
0
0.02
0.04
0.06
–1 0 21 43 7 865 9
VOLTAGE (V)
VOLTAGE (V)
TIME (µs)
VSY = ± 1.5V
TA = 25° C
OUTPUT
INPUT
08237-018
Figure 30. Settling Time
10
4
1110 100 1k 10k 100k
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY ( Hz )
V
SY
= ±1. 5V
T
A
= 25° C
08237-019
Figure 31. Voltage Noise Density vs. Frequency
60
50
40
30
20
10
01100010010
OVERSHOOT (%)
LO AD CAP ACIT ANCE ( pF )
V
SY
= ±1. 5V
V
IN
= 100mV p - p
R
L
= 2kΩ
T
A
= 25° C OS+
OS–
08237-020
Figure 32. Overshoot vs. Load Capacitance
80
–80 012345678910
VOLTAGE NOISE (nV)
TIME (Seconds)
–60
–40
–20
0
20
40
60
V
SY
= ±1. 5V
T
A
= 25° C
08237-021
Figure 33. Voltage Noise, 0.1 Hz to 10 Hz
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 15 of 36
0
–160
–140
–120
–100
–80
–60
–40
–20
100 1k 10k 100k
CHANNEL S E P ARATI ON (dB)
FREQUENCY ( Hz )
VSY = ± 1.5V
TA = 25° C
VIN = 1V p-p
08237-022
2kΩ
–
+
10V p-p CH A
V
CC
V
EE
–
+
2kΩ
10kΩ
1kΩ
CH B,
CH C,
CH D
V
CC
V
EE
Figure 34. Channel Separation vs. Frequency
1
0.1
0.01
THD + N ( %)
0.001
0.0001
0.001 0.01
AMPLITUDE (V
RMS
)
0.1 1
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= 10kΩ
V
IN
AT 1kHz
08237-125
Figure 35. THD + N vs. Amplitude
0.01
THD + N ( %)
0.001
0.01 0.1
FREQUENCY (kHz)
110 100
VSY = ±1.5V
TA = 25° C
VIN = 300mV rms
500kHz F ILTER
RL = 10kΩ
RL = 2kΩ
08237-126
Figure 36. THD + N vs. Frequency, 500 kHz Filter
0.1
0.01
0.001
0.000110 100 1k 10k 100k
THD + N ( %)
FREQUENCY ( Hz )
08237-231
V
SY
= ±1. 5V
T
A
= 25° C
V
IN
= 300mV rms
80kHz FIL TER
R
L
= 2kΩ
R
L
= 10kΩ
Figure 37. THD + N vs. Frequency, 80 kHz Filter
2.0
–2.0 01000
VOLT AGE (V)
TIME (µs)
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
100 200 300 400 500 600 700 800 900
V
SY
= ±1. 5V
T
A
= 25° C
OUTPUT
INPUT
08237-025
Figure 38. No Phase Reversal
0.5
–2.0
–1.5
–1.0
–0.5
0
4
–1
0
1
2
3
–2 0 42 86 14 161210 18
VOLT AGE (V)
VOLT AGE (V)
TIME (µs)
VSY = ± 1.5V
TA = 25° C
OUTPUT
08237-233
INPUT
Figure 39. Positive 50% Overload Recovery
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 16 of 36
0.5
–2.0
–1.5
–1.0
–0.5
0
3
–2
–1
0
1
2
–2 0 42 86 14 161210 18
VOLT AGE (V)
VOLT AGE (V)
TIME (µs)
V
SY
= ±1. 5V
T
A
= 25° C
OUTPUT
08237-234
INPUT
Figure 40. Negative 50% Overload Recovery
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 17 of 36
±5 V CHARACTERISTICS
120
0
–100 –50 50–25 250–75 75 100
NUMBER O F AMP LI FI E RS
V
OS
(µV)
20
40
60
80
100
V
SY
= ±5V
T
A
= 25° C
R
L
= ∞
08237-026
Figure 41. Input Offset Voltage (VOS) Distribution, SOIC
0
20
40
60
80
100
120
–100 –75 –50 –25 025 50 75 100
NUMBER O F AMPLIFIERS
V
OS
(µV)
V
SY
= ±5V
T
A
= 25° C
R
L
= ∞
08237-335
Figure 42. Input Offset Voltage (VOS) Distribution, SOT-23
60
0
–100 100
NUMBER O F AMP LI FI E RS
V
OS
(µV)
10
20
30
40
50
–50 50–25 250–75 75
V
SY
= ±5V
T
A
= 25° C
R
L
= ∞
08237-027
Figure 43. Input Offset Voltage (VOS) Distribution, MSOP and TSSOP
0
50
100
150
200
250
–200 –150 –100 –50 050 100
NUMBER OF AMPLIFIERS
VOS (µV)
08237-080
VSY = ±5V
TA = 25° C
RL = ∞
Figure 44. Input Offset Voltage (VOS) Distribution, LFCSP
50
002.0
NUMBER O F AMP LI FI E RS
TCV
OS
(µV/°C)
5
10
15
20
25
30
35
40
45
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
V
SY
= ±5V
R
L
= ∞
–40°C ≤ T
A
≤ +125°C
08237-028
Figure 45. TCVOS Distribution, SOIC, MSOP, and TSSOP
0
2
4
6
8
10
12
14
16
18
20
00.2 0.4 0.6 0.8 11.2 1.4 1.6 1.8 2
NUMBER OF AMPLIFIERS
TCV
OS
(µV/°C)
V
SY
= ±5V
R
L
= ∞
–40°C ≤T
A
≤+125°C
08237-338
Figure 46. TCVOS Distribution for SOT-23
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 18 of 36
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
NUMBER OF AMPLIFIERS
TCV
OS
(µV/°C)
0
5
10
15
20
25
30
35
08237-084
V
SY
= ±5V
R
L
= ∞
–40°C ≤ T
A
≤ +125°C
Figure 47. TCVOS Distribution, LFCSP
600
–600–5 5
INPUT OFFSET VOLTAGE (µV)
COMMON-MODE VOLTAGE (V)
–400
–500
–300
–200
–100
0
100
200
300
400
500 V
SY
= ±5V
T
A
= 25° C
R
L
= ∞
–4 –3 –2 –1 0 1 2 3 4
08237-029
Figure 48. Input Offset Voltage vs. Common-Mode Voltage
–100
–75
–50
–25
0
25
50
75
100
–50–25 0 25 50 75 100125150
INPUT OFFSET VOLTAGE (µV)
TEMPERATURE (°C)
08237-133
VSY = ±5V
Figure 49. Input Offset Voltage vs. Temperature
–50
–100
–150
–200
–250
–40 125
INPUT BI AS CURRE NT (nA)
TEMPERATURE (°C)
–25 –10 520 35 50 65 80 95 110
VSY = ± 5V
VCM = 0V
RL = ∞
IB+
IB–
08237-030
Figure 50. Input Bias Current vs. Temperature
800
–800–5 5
INP UT BIAS CURRE NT (nA)
VCM (V)
–400
–600
–200
0
200
400
600
TA = +125°C
TA = –40° C
VSY = ±5V
–4 –3 –2 –1 0 1 2 3 4
TA = +25°C
TA = +85°C
08237-031
Figure 51. Input Bias Current vs. VCM for Various Temperatures
1000
100
10
1
0.001 0.01 0.1 110
V
DO
(mV)
SOURCE CURRE NT (mA)
V
SY
= ±5V
T
A
= 25° C
(V+) – V
OH
08237-032
Figure 52. Dropout Voltage (VDO) vs. Source Current
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 19 of 36
1000
100
10
1
0.001 0.01 0.1 110
V
DO
(mV)
SINK CURRE NT (mA)
V
SY
= ±5V
T
A
= 25° C
V
OL
– (V–)
08237-033
Figure 53. Dropout Voltage (VDO) vs. Sink Current
120
–40
270
–90
0.1 100k
GAIN (d B)
PHASE ( Degrees)
FREQUENCY ( kHz )
–45
0
45
90
135
180
225
–20
20
0
40
60
80
100
110 100 1k 10k
VSY = ± 5V
TA = 25° C
RL = 10kΩ
08237-034
Figure 54. Open-Loop Gain and Phase vs. Frequency
60
–2010 100M
GAIN (d B)
FREQUENCY ( Hz )
–10
0
10
20
30
40
50
100 1k 10k 100k 10M1M
V
SY
= ±5V
T
A
= 25° C
08237-035
A
V
= +100
A
V
= +10
A
V
= +1
Figure 55. Closed-Loop Gain vs. Frequency
1000
100
10
1
0.10
0.0110 100M
Z
OUT
(Ω)
FREQUENCY ( Hz )
100 1k 10k 100k 10M1M
V
SY
= ±5V
T
A
= 25° C
A
V
= +100
A
V
= +1
A
V
= +10
08237-036
Figure 56. Output Impedance (ZOUT) vs. Frequency
140
–2010 100M
PSRR ( dB)
FREQUENCY ( Hz )
0
20
40
60
80
100
120
100 1k 10k 100k 10M1M
V
SY
= ±5V
T
A
= 25° C
PSRR–
PSRR+
08237-037
Figure 57. PSRR vs. Frequency
140
120
100
80
60
40
20
010 100M
CMRR (dB)
FREQUENCY ( Hz )
100 1k 10k 100k 10M1M
V
SY
= ±5V
T
A
= 25° C
08237-221
Figure 58. CMRR vs. Frequency
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 20 of 36
5
–5
VOLT AGE (V)
TIME (µs)
VSY = ± 5V
TA = 25° C
RL = 2kΩ
CL = 100pF
–4
–3
–2
–1
0
1
2
3
4
08237-039
0182 4 6 8 10 12 14 16
Figure 59. Large Signal Transient Response
80
60
40
20
0
–80
–60
–40
–20
VOLT AGE (mV)
TIME (µs)
V
SY
= ±5V
T
A
= 25° C
R
L
= 2kΩ
C
L
= 100pF
08237-040
0102 31 4 6 75 8 9
Figure 60. Small Signal Transient Response
10
–25
–20
–5
–10
–15
0
5
0.16
–0.12
–0.08
–0.04
0
0.04
0.08
0.12
–2 02486 18161210 14
VOLTAGE (V)
VOLTAGE (V)
TIME (µs)
VSY = ± 5V
TA = 25° C
OUTPUT
INPUT
08237-041
Figure 61. Settling Time
10
1110 100 1k 10k 100k
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY ( Hz )
V
SY
= ±5V
T
A
= 25° C
08237-042
4
Figure 62. Voltage Noise Density vs. Frequency
60
50
40
30
20
10
01100010010
OVERSHOOT (%)
LO AD CAP ACIT ANCE ( pF )
V
SY
= ±5V
V
IN
= 100mV p - p
R
L
= 2kΩ
T
A
= 25° C OS+
OS–
08237-043
Figure 63. Overshoot vs. Load Capacitance
80
–80 012345678910
VOLTAGE NOISE (nV)
TIME (Seconds)
–60
–40
–20
0
20
40
60
VSY = ± 5V
TA = 25° C
08237-044
Figure 64. Voltage Noise, 0.1 Hz to 10 Hz
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 21 of 36
0
–160
–140
–120
–100
–80
–60
–40
–20
100 1k 10k 100k
CHANNEL S E P ARATI ON (dB)
FREQUENCY ( Hz )
VSY = ± 5V
TA = 25° C
VIN = 5V p-p
08237-045
2kΩ
–
+
10V p-p CH A
V
CC
V
EE
–
+
2kΩ
10kΩ
1kΩ
CH B,
CH C,
CH D
V
CC
V
EE
Figure 65. Channel Separation vs. Frequency
1
0.1
0.01
THD + N ( %)
0.001
0.0001
0.001 0.01
AMPLITUDE (V
RMS
)
0.1 1
V
SY
= ±5V
T
A
= 25° C
R
L
= 10kΩ
V
IN
AT 1kHz
08237-150
Figure 66. THD + N vs. Amplitude
1
THD + N ( %)
0.001
0.01
0.1
0.0001
0.01 0.1
FREQUENCY (kHz)
110 100
V
SY
= ±5V
T
A
= 25° C
V
IN
= 2V rms
500kHz F ILTER
R
L
= 10kΩ
R
L
= 2kΩ
08237-151
Figure 67. THD + N vs. Frequency, 500 kHz Filter
0.1
0.01
0.001
0.00001
0.0001
10 100 1k 10k 100k
THD + N ( %)
FREQUENCY ( Hz )
08237-260
V
SY
= ±5V
T
A
= 25° C
V
IN
= 300mV rms
80kHz FIL TER
R
L
= 2kΩ
R
L
= 10kΩ
Figure 68. THD + N vs. Frequency, 80 kHz Filter
6
4
2
–4
–2
–6 01000
VOLT AGE (V)
TIME (µs)
0
100 200 300 400 500 600 700 800 900
V
SY
= ±5V
T
A
= 25° C
OUTPUT
INPUT
08237-048
Figure 69. No Phase Reversal
1
–5
–4
–3
–2
–1
0
10
–2
0
2
4
6
8
–2 0 42 86 14 161210 18
VOLT AGE (V)
VOLT AGE (V)
TIME (µs)
VSY = ± 5V
TA = 25° C
08237-262
INPUT
OUTPUT
Figure 70. Positive 50% Overload Recovery
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 22 of 36
1
–5
–4
–3
–2
–1
0
6
–6
–4
–2
0
2
4
–2 0 42 86 14 161210 18
VOLT AGE (V)
VOLT AGE (V)
TIME (µs)
V
SY
= ±5V
T
A
= 25° C
08237-263
INPUT
OUTPUT
Figure 71. Negative 50% Overload Recovery
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 23 of 36
±15 V CHARACTERISTICS
100
0
–100 –50 50–25 250–75 75 100
NUMBER O F AMP LI FI E RS
V
OS
(µV)
20
30
10
40
50
60
70
80
90 V
SY
= ±15V
T
A
= 25° C
R
L
= ∞
08237-049
Figure 72. Input Offset Voltage (VOS) Distribution, SOIC
0
10
20
30
40
50
60
70
80
90
100
–100 –75 –50 –25 025 50 75 100
NUMBER O F AMPLIFIERS
V
OS
(µV)
V
SY
= ±1. 5V
T
A
= 25° C
R
L
= ∞
08237-364
Figure 73. Input Offset Voltage (VOS) Distribution, SOT-23
60
0
–100 100
NUMBER O F AMP LI FI E RS
V
OS
(µV)
10
20
30
40
50
–50 50–25 250–75 75
V
SY
= ±15V
T
A
= 25° C
R
L
= ∞
08237-050
Figure 74. Input Offset Voltage (VOS) Distribution, MSOP and TSSOP
0
50
100
150
200
–200 –150 –100 –50 050 100
NUMBER OF AMPLIFIERS
V
OS
(µV)
08237-079
V
SY
= ±15V
T
A
= 25° C
R
L
= ∞
Figure 75. Input Offset Voltage (VOS) Distribution, LFCSP
60
002.0
NUMBER O F AMP LI FI E RS
TCVOS (µV/°C)
10
20
30
40
50
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
VSY = ±15V
RL = ∞
–40°C ≤ TA ≤ +125°C
08237-051
Figure 76. TCVOS Distribution, SOIC, MSOP, and TSSOP
0
5
10
15
20
25
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
NUMBER O F AMPLIFIERS
VSY = ±15V
RL = ∞
–40°C ≤TA≤+125°C
TCVOS (µV)
08237-367
Figure 77. TCVOS Distribution, SOT-23
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 24 of 36
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
NUMBER OF AMPLIFIERS
TCV
OS
(µV/°C)
0
5
10
15
20
25
30
08237-085
V
SY
= ±15V
R
L
= ∞
–40°C ≤ T
A
≤ +125°C
Figure 78. TCVOS Distribution, LFCSP
600
–600
–15 –10 –5 51510
INPUT OFFSET VOLTAGE (µV)
COMMON-MODE VOLTAGE (V)
–400
–500
–300
–200
–100
0
100
200
300
400
500 V
SY
= ±15V
T
A
= 25° C
R
L
= ∞
0
08237-052
Figure 79. Input Offset Voltage vs. Common-Mode Voltage
–100
–75
–50
–25
0
25
50
75
100
–50 –25 025 50 75 100 125 150
INPUT OFFSET VOLTAG E (µV)
TEMPERAT URE ( °C)
08237-165
V
SY
= ±15V
Figure 80. Input Offset Voltage vs. Temperature
–50
–100
–150
–200
–250
–40 125
INPUT BI AS CURRE NT (nA)
TEMPERATURE (°C)
–25 –10 520 35 50 65 80 95 110
VSY = ± 15V
VCM = 0V
RL = ∞
IB+
IB–
08237-053
Figure 81. Input Bias Current vs. Temperature
1200
–1200
–15 –10 –5 510 15
INPUT BI AS CURRE NT (nA)
VCM (V)
–400
–800
0
400
800
TA = +125°C
TA = –40° C
VSY = ±15V
0
TA = +25°C
TA = +85°C
08237-054
Figure 82. Input Bias Current vs. VCM for Various Temperatures
1000
10000
100
10
1
0.001 0.01 0.1 110
V
DO
(mV)
SOURCE CURRE NT (mA)
V
SY
= ±15V
T
A
= 25° C
(V+) – V
OH
08237-055
Figure 83. Dropout Voltage (VDO) vs. Source Current
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 25 of 36
1000
10000
100
10
1
0.001 0.01 0.1 110
V
DO
(mV)
SINK CURRE NT (mA)
V
SY
= ±15V
T
A
= 25° C
V
OL
– (V–)
08237-056
Figure 84. Dropout Voltage (VDO) vs. Sink Current
120
–40
270
–90
100 100M
GAI N (dB)
PHASE ( Degrees)
FREQUENCY ( Hz )
–45
0
45
90
135
180
225
–20
20
0
40
60
80
100
1k 10k 100k 1M 10M
V
SY
= ±15V
T
A
= 25° C
R
L
= 10kΩ
08237-057
Figure 85. Open-Loop Gain and Phase vs. Frequency
60
–2010 100M
GAIN (d B)
FREQUENCY ( Hz )
–10
0
10
20
30
40
50
100 1k 10k 100k 10M1M
V
SY
= ±15V
T
A
= 25° C
08237-058
A
V
= +100
A
V
= +10
A
V
= +1
Figure 86. Closed-Loop Gain vs. Frequency
1000
100
10
1
0.1
0.0110 100M
Z
OUT
(Ω)
FREQUENCY ( Hz )
100 1k 10k 100k 10M1M
V
SY
= ±15V
T
A
= 25° C
A
V
= +100
A
V
= +1
A
V
= +10
08237-059
Figure 87. Output Impedance (ZOUT) vs. Frequency
140
–2010 100M
PSRR ( dB)
FREQUENCY ( Hz )
0
20
40
60
80
100
120
100 1k 10k 100k 10M1M
V
SY
= ±15V
T
A
= 25° C
PSRR–
PSRR+
08237-060
Figure 88. PSRR vs. Frequency
140
120
100
80
60
40
20
010 100M
CMRR (dB)
FREQUENCY ( Hz )
100 1k 10k 100k 10M1M
V
SY
= ±15V
T
A
= 25° C
08237-279
Figure 89. CMRR vs. Frequency
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 26 of 36
15
10
–15
–10
–5
0
5
0 4 8 12 3628 32242016
VOLTAGE (V)
TIME (µs)
V
SY
= ±15V
T
A
= 25° C
R
L
= 2kΩ
C
L
= 100pF
08237-062
Figure 90. Large Signal Transient Response
80
60
40
20
0
–80
–60
–40
–20
0 21 43 7 8 965 10
VOLT AGE (mV)
TIME (µs)
V
SY
= ±15V
T
A
= 25° C
R
L
= 2kΩ
C
L
= 100pF
08237-063
Figure 91. Small Signal Transient Response
10
–25
–20
–5
–10
–15
0
5
0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
–2 0 2 486 18161210 14
VOLTAGE (V)
VOLTAGE (V)
TIME (µs)
VSY = ± 15V
TA = 25° C
INPUT
OUTPUT
08237-064
Figure 92. Settling Time
10
1110 100 1k 10k 100k
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY ( Hz )
V
SY
= ±15V
T
A
= 25° C
08237-065
4
Figure 93. Voltage Noise Density vs. Frequency
70
50
60
40
30
20
10
01100010010
OVERSHOOT (%)
LO AD CAP ACIT ANCE ( pF )
V
SY
= ±15V
V
IN
= 100mV p - p
R
L
= 2kΩ
T
A
= 25° C OS+
OS–
08237-066
Figure 94. Overshoot vs. Load Capacitance
0246810
60
–60
VOLTAGE NOISE (nV)
TIME (Seconds)
–40
–20
0
20
40
V
SY
= ±15V
T
A
= 25° C
08237-067
Figure 95. Voltage Noise 0.1 Hz to 10 Hz
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 27 of 36
0
–180
–140
–160
–120
–100
–80
–60
–40
–20
100 1k 10k 100k
CHANNEL S E P ARATI ON (dB)
FREQUENCY ( Hz )
VSY = ± 15V
TA = 25° C
VIN = 10V p-p
08237-068
2kΩ
–
+
10V p-p CH A
VCC
VEE
–
+
2kΩ
10kΩ
1kΩ
CH B,
CH C,
CH D
VCC
VEE
Figure 96. Channel Separation vs. Frequency
1
0.1
0.01
THD + N ( %)
0.001
0.0001
0.001 0.01
AMPLITUDE (V
RMS
)
0.1 110
V
SY
= ±15V
R
L
= 10kΩ
V
IN
AT 1kHz
08237-175
Figure 97. THD + N vs. Amplitude
1
THD + N ( %)
0.001
0.01
0.1
0.0001
0.01 0.1
FREQUENCY (kHz)
110 100
V
SY
= ±15V
T
A
= 25° C
V
IN
= 5V rms
500kHz F ILTER
R
L
= 10kΩ
R
L
= 2kΩ
08237-176
Figure 98. THD + N vs. Frequency, 500 kHz Filter
0.1
0.01
0.001
0.00001
0.0001
10 100 1k 10k 100k
THD + N ( %)
FREQUENCY ( Hz )
08237-289
V
SY
= ±15V
T
A
= 25° C
V
IN
= 300mV rms
80kHz FIL TER
R
L
= 2kΩ
R
L
= 10kΩ
Figure 99. THD + N vs. Frequency, 80 kHz Filter
20
15
10
5
–15
–10
–5
–20 01000
VOLT AGE (V)
TIME (µs)
0
100 200 300 400 500 600 700 800 900
VSY = ± 15V
TA = 25° C
OUTPUT
INPUT
08237-071
Figure 100. No Phase Reversal
CH2 5VCH1 100mV
CH1 AMPL
202mV
M1µs A CH1 –84mV
1
2
T 10.2%
08237-178
V
IN
V
OUT
V
SY
= ±15V
Figure 101. Positive 50% Overload Recovery
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 28 of 36
CH2 5VCH1 100mV
CH1 AMPL
200mV
M2µs A CH1 44mV
1
2
T 10.4%
08237-179
V
IN
V
OUT
V
SY
= ±15V
Figure 102. Negative 50% Overload Recovery
1000
0036
ISY/AMPLIFIER (µA)
VSY (V)
100
200
300
400
500
600
700
800
900
4 8 12 16 20 24 28 32
TA = 25° C
RL = ∞
+125°C
+25°C
–40°C
+85°C
08237-072
Figure 103. Supply Current (ISY) per Amplifier vs. Supply Voltage (VSY) for
Various Temperatures
–50 –25 025 50 75 100 125 150
CMRR (dB)
TEMPERAT URE ( °C)
0
20
60
40
80
100
120
140
V
CM
= ±14V
V
CM
= ±1. 5V
V
CM
= ±4V
08237-180
Figure 104. CMRR vs. Temperature
–50 –25 025 50 75 100 125 150
PSRR ( dB)
TEMPERATURE (°C)
50
60
80
70
90
100
120
150
140
130
110
V
SY
= ±1. 25V TO ± 1.75V, V
CM
= 0V
08237-181
V
SY
= ±2V TO ±18V , V
CM
= 0V
Figure 105. PSRR vs. Temperature
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 29 of 36
APPLICATIONS INFORMATION
FUNCTIONAL DESCRIPTION
The ADA4084-1/ADA4084-2/ADA4084-4 devices are precision
single-supply, rail-to-rail operational amplifiers. Intended for
portable instrumentation, the ADA4084-1/ADA4084-2/
ADA4084-4 devices combine the attributes of precision, wide
bandwidth, and low noise, making them an ideal choice in
single-supply applications that require both ac and precision dc
performance. Other low supply voltage applications for which
the ADA4084-1/ADA4084-2/ADA4084-4 devices are well suited
include active filters, audio microphone preamplifiers, power
supply control, and telecommunications. To combine all of
these attributes with rail-to-rail input/output operation, novel
circuit design techniques are used.
D2
D101
D100
D5 D4
D1
Q1
Q4 Q3
Q2
08237-073
R4
R1 R2
R3
Figure 106. Equivalent Input Circuit
For example, Figure 106 illustrates a simplified equivalent
circuit for the input stage of the ADA4084-1/ADA4084-2/
ADA4084-4. It comprises a PNP differential pair, Q1 and Q2,
and an NPN differential pair, Q3 and Q4, operating concurrently.
Diode D100 and Diode D101 serve to clamp the applied
differential input voltage to the ADA4084-1/ADA4084-2/
ADA4084-4, thereby protecting the input transistors against Zener
breakdown of the emitter-base junctions. Input stage voltage
gains are kept low for input rail-to-rail operation. The two pairs of
differential output voltages are connected to the second stage of
the ADA4084-1/ADA4084-2/ADA4084-4, which is a modified
compound folded cascade gain stage. It is also in the second
gain stage that the two pairs of differential output voltages are
combined into a single-ended output signal voltage used to
drive the output stage.
A key issue in the input stage is the behavior of the input bias
currents over the input common-mode voltage range. Input bias
currents in the ADA4084-1/ADA4084-2/ADA4084-4 are the
arithmetic sum of the base currents in Q1 and Q4 and in Q2 and
Q3. As a result of this design approach, the input bias currents in
the ADA4084-1/ADA4084-2/ADA4084-4 not only exhibit
different amplitudes, but they also exhibit different polarities. This
effect is best shown in Figure 19, Figure 20, Figure 50, Figure 51,
Figure 81, and Figure 82. It is, therefore, important that the
effective source impedances that are connected to the ADA4084-1/
ADA4084-2/ADA4084-4 inputs be balanced for optimum dc
and ac performance.
To achieve rail-to-rail output, the ADA4084-1/ADA4084-2/
ADA4084-4 output stage design employs a unique topology for
both sourcing and sinking current. This circuit topology is shown
in Figure 107. The output stage is voltage driven from the second
gain stage. The signal path through the output stage is inverting;
that is, for positive input signals, Q13 provides the base current
drive to Q19 so that it conducts (sinks) current. For negative input
signals, the signal path via Q18 to the mirror to Q24 provides
the base current drive for Q23 to conduct (source) current. Both
transistors provide output current until they are forced into
saturation.
Q24
Q21 D20
Q13
Q18
Q19
Q23
V
EE
V
OUT
V
CC
V
BIAS
MIRROR
08237-074
R5
R6
R7 C2
C1
Figure 107. Equivalent Output Circuit
Thus, the saturation voltage of the output transistors sets the
limit on the ADA4084-1/ADA4084-2/ADA4084-4 maximum
output voltage swing. Output short-circuit current limiting is
determined by the maximum signal current into the base of
Q13 from the second gain stage. The output stage also exhibits
voltage gain. This is accomplished by the use of common-emitter
amplifiers, and, as a result, the voltage gain of the output stage
(thus, the open-loop gain of the device) exhibits a dependence
on the total load resistance at the output of the ADA4084-1/
ADA4084-2/ADA4084-4.
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 30 of 36
START-UP CHARACTERISTICS
The ADA4084-1/ADA4084-2/ADA4084-4 are specified to operate
from 3 V to 30 V (±1.5 V to ±15 V) under nominal power
supplies. During power-up as the supply voltage increases from
0 V to the nominal power supply voltage, the supply current (ISY)
increases as well, to the point at which it stabilizes and the amplifier
is ready to operate. The stabilization varies with temperature, as
shown in Figure 103. For example, at −40°C, it requires a higher
voltage and stabilizes at a lower supply current than at hot
temperatures. At hot temperatures, it requires a lower voltage but
stabilizes at a higher current. In all cases, the ADA4084-1/
ADA4084-2/ADA4084-4 are specified to start up and operate at
a minimum of 3 V under all temperature conditions.
INPUT PROTECTION
As with any semiconductor device, if conditions exist where the
applied input voltages to the device exceed either supply voltage,
the input overvoltage I-to-V characteristic of the device must be
considered. When an overvoltage occurs, the amplifier may be
damaged, depending on the magnitude of the applied voltage
and the magnitude of the fault current.
The D1, D2, D4, and D5 diodes conduct when the input common-
mode voltage exceeds either supply pin by a diode drop. This
diode drop voltage varies with temperature and is in the range
of 0.3 V to 0.8 V. As shown in the simplified equivalent input
circuit of Figure 106, the ADA4084-1/ADA4084-2/ADA4084-4
do not have any internal current limiting resistors; thus, fault
currents can quickly rise to damaging levels.
This input current is not inherently damaging to the device,
provided that it is limited to 5 mA or less. If a fault condition
causes more than 5 mA to flow, add an external series resistor at
the expense of additional thermal noise. Figure 108 shows a
typical noninverting configuration for an overvoltage protected
amplifier, where the series resistance (R1) is chosen, such that
( )
mA5
SUPPLY
MAX
IN
VV
R1 −
=
For example, a 1 kΩ resistor protects the ADA4084-1/ADA4084-2/
ADA4084-4 against input signals up to 5 V above and below the
supplies. Note that the thermal noise of a 1 kΩ resistor at room
temperature is 4 nV/√Hz, which exceeds the voltage noise of the
ADA4084-1/ADA4084-2/ADA4084-4. For other configurations
in which both inputs are used, add a series resistor to limit the
input current. To ensure optimum dc and ac performance,
balance the source impedance levels.
R1
R2
VIN
VOUT
1/2
ADA4084-1/
ADA4084-2/
ADA4084-4
08237-075
Figure 108. Resistance in Series with the Input
Limits Overvoltage Currents to Safe Values
To protect the Q1/Q2 and Q3/Q4 pairs from large differential
voltages that may result in Zener breakdown of the emitter-base
junction, D100 and D101 are connected between the two inputs.
This precludes operation as a comparator. For a more complete
description, see the MT-035 Tutorial, Op Amp Inputs, Outputs,
Single-Supply, and Rail-to-Rail Issues; the MT-083 Tutorial,
Comparators; the MT-084 Tutorial, Using Op Amps as
Comparators; and the AN-849 Application Note, Using Op
Amps as Comparators.
OUTPUT PHASE REVERSAL
Some operational amplifiers designed for single-supply operation
exhibit an output voltage phase reversal when their inputs are
driven beyond their useful common-mode range. Typically, for
single-supply bipolar op amps, the negative supply determines
the lower limit of their common-mode range. With these devices,
external clamping diodes, with the anode connected to ground
and the cathode to the inputs, prevent input signal excursions
from exceeding the negative supply of the device (that is, GND),
preventing a condition that causes the output voltage to change
phase. JFET input amplifiers can also exhibit phase reversal, and, if
so, a series input resistor is usually required to prevent it.
The ADA4084-1/ADA4084-2/ADA4084-4 are free from
reasonable input voltage range restrictions, provided that input
voltages no greater than the supply voltages are applied (see
Figure 38, Figure 69, and Figure 100).
Although device output does not change phase, large currents can
flow through the input protection diodes. Therefore, apply the
technique recommended in the Input Protection section to
those applications where the likelihood of input voltages
exceeding the supply voltages is high.
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 31 of 36
DESIGNING LOW NOISE CIRCUITS IN SINGLE-
SUPPLY APPLICATIONS
In single-supply applications, devices like the ADA4084-1/
ADA4084-2/ADA4084-4 extend the dynamic range of the
application through the use of rail-to-rail operation. Referring to
the op amp noise model circuit configuration illustrated in
Figure 109, the expression for the total equivalent input noise
voltage of an amplifier for a source resistance level, RS, is given by
[
]
22
2
)()()(2
nOA
SnOA
nR
nT
eee Ri +×+=
, units in
Hz
V
where:
(enR)2 is the source resistance thermal noise voltage power (4kTR).
k is the Boltzmann’s constant, 1.38 × 10–23 J/K.
T is the ambient temperature in Kelvin of the circuit, 273.15 +
TA (°C).
(inOA)2 is the op amp equivalent input noise current spectral
power (1 Hz bandwidth).
RS = 2R, the effective, or equivalent, circuit source resistance.
(enOA)2 is the op amp equivalent input noise voltage spectral
power (1 Hz bandwidth).
enR
enR
enOA
inOA
inOA
R
NOISELESS
R
NOISELESS
08237-076
IDEAL
NOISELESS
OP AMP
R
S
= 2R
Figure 109. Op Amp Noise Circuit Model Used to Determine Total Circuit
Equivalent Input Noise Voltage and Noise Figure
As a design aid, Figure 110 shows the equivalent thermal noise
of the ADA4084-1/ADA4084-2/ADA4084-4 vs. the total source
resistance. Note that for source resistance less than 1 kΩ, the
equivalent input noise voltage of the ADA4084-1/ADA4084-2/
ADA4084-4 is dominant.
08237-077
TOTAL SOURCE RE S ISTANCE, RS (Ω)
100
1
EQUIVALENT THERMAL NOISE (nV/ Hz)
10
10k
ADA4084-1/ADA4084-2/ADA4084-4
TOTAL EQUIVALENT NOISE
RESIST OR T HE RM AL
NOISE ONLY
100 1k 100k
FRE QUENCY = 1kHz
TA = 25° C
Figure 110. Equivalent Thermal Noise vs. Total Source Resistance
Because circuit SNR is the critical parameter in the final analysis,
the noise behavior of a circuit is sometimes expressed in terms
of its noise figure (NF). The noise figure is defined as the ratio
of the signal-to-noise output of a circuit to its signal-to-noise input.
Noise figure is generally used for RF and microwave circuit analysis
in a 50 Ω system. This is not very useful for op amp circuits where
the input and output impedances can vary greatly. For a more
complete description of noise figure, see the MT-052 Tutorial,
Op Amp Noise Figure: Don’t be Misled.
Signal levels in the application invariably increase to maximize
circuit SNR, which is not an option in low voltage, single-supply
applications.
Therefore, to achieve optimum circuit SNR in single-supply
applications, choose an operational amplifier with the lowest
equivalent input noise voltage, along with source resistance
levels that are consistent with maintaining low total circuit noise.
COMPARATOR OPERATION
Although op amps are quite different from comparators,
occasionally an unused section of a dual or a quad op amp can
be used as a comparator; however, this is not recommended for
any rail-to-rail output op amps. For rail-to-rail output op amps,
the output stage is generally a ratioed current mirror with bipolar
or MOSFET transistors. With the device operating open-loop,
the second stage increases the current drive to the ratioed mirror
to close the loop. However, the loop cannot close, which results in
an increase in supply current. With the op amp configured as a
comparator, the supply current can be significantly higher (see
Figure 111). Configure an unused section as a voltage follower
with the noninverting input connected to a voltage within the
input voltage range. The ADA4084-1/ADA4084-2/ADA4084-4
have unique second stage and output stage designs that greatly
reduce the excess supply current when the op amp is operating
open-loop.
800
0036
SUPPLY CURRE NT (µ A)
V
SY
(V)
08237-078
100
200
300
400
500
600
700
4 8 12 16 20 24 28 32
T
A
= 25° C
R
L
= ∞
COMPARATOR
OUTPUT LOW
COMPARATOR
OUTPUT HIGH
BUFFER
Figure 111. Supply Current vs. Supply Voltage (VSY)
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 32 of 36
LONG-TERM DRIFT
The stability of a precision signal path over its lifetime or
between calibration procedures is dependent on the long-term
stability of the analog components in the path, such as op amps,
references, and data converters. To help system designers
predict the long-term drift of circuits that use the ADA4084-1/
ADA4084-2/ADA4084-4, Analog Devices measured the offset
voltage of multiple units for 10,000 hours (more than 13 months)
using a high precision measurement system, including an
ultrastable oil bath. To replicate real-world system performance,
the devices under test (DUTs) were soldered onto an FR4 PCB
using a standard reflow profile (as defined in the JEDEC J-STD-
020D standard), as opposed to testing them in sockets. This
manner of testing is important because expansion and
contraction of the PCB can apply stress to the integrated circuit
(IC) package and contribute to shifts in the offset voltage.
The ADA4084-1/ADA4084-2/ADA4084-4 have extremely low
long-term drift, as shown in Figure 112. The red, blue, and
green traces show sample units. Note that the mean drift of the
ADA4084-1/ADA4084-2/ADA4084-4 over 10,000 hours is less
than 3 μV, or less than 3% of their maximum specified offset
voltage of 100 µV at room temperature.
CHANGE IN OFFSET VOLTAGE (µV)
08237-112
15
–15
10
5
0
–5
–10
TIME (Hours)
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10,000
V
SY
= 10V
27 UNITS
T
A
= 25° C
MEAN
MEAN P LUS O NE S TANDARD DEV IAT ION
MEAN M INUS O NE S TANDARD DEV IAT ION
SAMPLE 1
SAMPLE 2
SAMPLE 3
Figure 112. Measured Long-Term Drift of the ADA4084-1/ADA4084-2/
ADA4084-4 Offset Voltage over 10,000 Hours
TEMPERATURE HYSTERESIS
In addition to stability over time as described in the Long-Term
Drift section, it is useful to know the temperature hysteresis,
that is, the stability vs. cycling of temperature. Hysteresis is an
important parameter because it tells the system designer how
closely the signal returns to its starting amplitude after the
ambient temperature changes and subsequent return to room
temperature. Figure 113 shows the change in input offset
voltage as the temperature cycles three times from room
temperature to +125°C to −40°C and back to room temperature.
The dotted line is an initial preconditioning cycle to eliminate
the original temperature-induced offset shift from exposure to
production solder reflow temperatures. In the three full cycles,
the offset hysteresis is typically only 4 μV, or 2% of its 200 µV
maximum offset voltage over the full operating temperature
range. The histogram in Figure 114 shows that the hysteresis is
larger when the device is cycled through only a half cycle, from
room temperature to 125°C and back to room temperature.
TEMPERATURE (°C)
CHANGE IN OFFSET VOLTAGE (µV)
VSY = 10V
08237-113
100
80
–100
–80
–40 –20 020 40 60 80 100 120
60
40
20
0
–20
–40
–60
PRECONDITION
CYCLE 1
CYCLE 2
CYCLE 3
Figure 113. Change in Offset Voltage over Three Full Temperature Cycles
OFFSET VOLTAGE HYSTERESIS (µV)
NUMBER OF DE V ICES
08237-114
0
–40 –32 –24 –18 –8 0 8 18 24 32 40
35
30
40
25
20
15
10
5
0
35
30
40
25
20
15
10
5
HALF CYCLE
FULL CYCLE
VSY = 10V
27 UNITS × 3 CYCL ES
HALF CYCLE = + 26°C, +125°C, +26°C
FULL CYCLE = +2 6° C, + 1 25°C, + 26°C, –40°C, + 26°C
Figure 114. Histogram Showing the Temperature Hysteresis of the Offset
Voltage over Three Full Cycles and over Three Half Cycles
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 33 of 36
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 115. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-178-AA
10°
5°
0°
SEATING
PLANE
1.90
BSC
0.95 BSC
0.60
BSC
5
1 2 3
4
3.00
2.90
2.80
3.00
2.80
2.60
1.70
1.60
1.50
1.30
1.15
0.90
0.15 MAX
0.05 MIN
1.45 MAX
0.95 MIN
0.20 MAX
0.08 MIN
0.50 MAX
0.35 MIN
0.55
0.45
0.35
11-01-2010-A
Figure 116. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 34 of 36
COM P LIANT T O JEDE C S TANDARDS MO-187- AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BS C
0.40
0.25
1.10 M AX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PI N 1
IDENTIFIER
15° M AX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 117. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
2.44
2.34
2.24
0.30
0.25
0.20
PI N 1 I NDE X
AREA
0.80
0.75
0.70
1.70
1.60
1.50
0.203 RE F
0.05 M AX
0.02 NOM
0.50 BS C
3.10
3.00 S Q
2.90
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS M O-229- W3030D-4
0.20 M IN
8
1
5
4
PKG-005136
02-10-2017-C
SEATING
PLANE
TOP VIEW
SIDE VIEW
EXPOSED
PAD
BOTTOM VIEW
FOR PRO P E R CONNECTI ON OF
THE EXPOSED PAD, REFER TO
THE P I N CONF IG URATI ON AND
FUNCTION DES CRIPTIONS
SECTION OF THIS DATA SHEET
PIN 1
INDIC ATOR AREA O P TIONS
(SEE DETAIL A)
1
DETAIL A
(JEDEC 95)
Figure 118. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-11)
Dimensions shown in millimeters
Data Sheet ADA4084-1/ADA4084-2/ADA4084-4
Rev. I | Page 35 of 36
2.70
2.60 SQ
2.50
COMPLIANT
TO
JEDEC STANDARDS M O-220- WGGC.
1
0.65
BSC
16
5
8
9
12
13
4
4.10
4.00 SQ
3.90
0.45
0.40
0.35
0.80
0.75
0.70 0. 05 M AX
0.02 NO M
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.35
0.30
0.25
BOTTOM VIEW
PKG-004828
SEATING
PLANE
TOP VIEW
SIDE VIEW FOR P ROPE R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE P IN CO NFI GURATIO N AND
FUNCT IO N DE S CRIPTIONS
SECTION OF THIS DATA SHEET.
02-22-2017-C
1
PIN 1
INDIC ATOR AREA O P TIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
EXPOSED
PAD
Figure 119. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 075 mm Package Height
(CP-16-17)
Dimensions shown in millimeters
COMP LI ANT T O JEDEC S TANDARDS M O-153- AB- 1
061908-A
8°
0°
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BSC
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 120. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ADA4084-1/ADA4084-2/ADA4084-4 Data Sheet
Rev. I | Page 36 of 36
ORDERING GUIDE
Model
1
Temperature Range
Package Description
Package Option
Branding
ADA4084-1ARZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4084-1ARZ-R7
−40°C to +125°C
8-Lead Standard Small Outline Package [SOIC_N]
R-8
ADA4084-1ARZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4084-1ARJZ-R2 −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A38
ADA4084-1ARJZ-R7 −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A38
ADA4084-1ARJZ-RL −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A38
ADA4084-2ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2Q
ADA4084-2ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2Q
ADA4084-2ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2Q
ADA4084-2ARZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4084-2ARZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4084-2ARZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4084-2ACPZ-R7 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-11 A2Q
ADA4084-2ACPZ-RL −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-11 A2Q
ADA4084-4ACPZ-R7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-17
ADA4084-4ACPZ-RL −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-17
ADA4084-4ARUZ −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14
ADA4084-4ARUZ-RL −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14
1 Z = RoHS Compliant Part.
©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08237-0-5/17(I)