HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Eight Character 5.0 mm (0.2 inch) Glass/Ceramic Intelligent 5x7 Alphanumeric Displays for Military Applications Data Sheet Description The HDSP-2131 (yellow), HDSP-2179 (orange), HDSP-2132 (high efficiency red) and the HDSP-2133 (green) are eight-digit, 5 x 7 dot matrix, alphanumeric displays. The 5.0 mm (0.2 inch) high characters are packaged in a standard 7.64 mm (0.30 inch) 32 pin DIP. The on-board CMOS IC has the ability to decode 128 ASCII characters, which are permanently stored in ROM. In addition, 16 programmable symbols may be stored in an on-board RAM. Seven brightness levels provide versatility in adjusting the display intensity and power consumption. The HDSP-213x and HDSP-2179 are designed for standard microprocessor interface techniques. The display and special features are accessed through a bidirectional eight-bit data bus. These features make the HDSP-213x and HDSP-2179 ideally suited for applications where a hermetic, low power alphanumeric display is required. Devices Yellow HDSP-2131 High Efficiency Red HDSP-2132 High Performance Green HDSP-2133 Orange HDSP-2179 Features * Wide operating temperature range -55C to +85C * Smart alphanumeric display - On-board CMOS IC - Built-in RAM - ASCII decoder - LED drive circuitry * 128 ASCII character set * 16 user definable characters * Programmable features - Individual character flashing - Full display blinking - Multi-level dimming and blanking - Self test - Clear function * Read/write capability * Full TTL compatibility * HDSP-2131/-2133/-2179 useable in night vision lighting applications * Categorized for luminous intensity * HDSP-2131/2133 categorized for color * Excellent ESD protection * Wave solderable * X-Y stackable * RoHS compliant Package Dimensions 42.72 (1.68) 5.33 TYP. (0.210) 6.10 REF. (0.24) 2.67 TYP. (0.105) 9.91 (0.39) 0.38 TYP. (0.015) PIN 17 4.83 (0.190) 4.96 (0.195) 7.62 (0.300) 2.85 (0.112) PART NUMBER DATE CODE LIGHT INTENSITY CATEGORY COLOR BIN (NOTE 3) PIN #1 IDENTIFIER 6.35 MAX. (0.250) HDSP-XXXX YYWW X 1.78 TYP. (0.070) Z SEATING PLANE 6.00 (0.24) 12.70 (0.50) 2.29 TYP. (0.090) 0.51 TYP. (0.020) 1.27 TYP. (0.050) 2.54 TYP. (0.100) NON-ACCUM. HDSP-213X/2179 PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FUNCTION CLS CLK WR CE RST RD NO PIN NO PIN NO PIN NO PIN D0 D1 D2 D3 NC VDD PIN # 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 FUNCTION GND (SUPPLY) GND (LOGIC) D4 D5 D6 D7 NO PIN NO PIN NO PIN NO PIN FL A0 A1 A2 A3 A4 NOTES: 1. ALL DIMENSIONS ARE IN mm (INCHES). 2. UNLESS OTHERWISE SPECIFIED, TOLERANCE IS 0.30 mm (0.015 INCH). 3. FOR GREEN AND YELLOW DEVICES ONLY. 4. LEADS ARE COPPER ALLOY, SOLDER DIPPED. Absolute Maximum Ratings Supply Voltage, VDD to Ground[1] Operating Voltage, VDD to Ground[2] Input Voltage, Any Pin to Ground Free Air Operating Temperature Range, TA Storage Temperature, TS CMOS IC Junction Temperature, TJ (IC) Soldering Temperature [1.59 mm (0.063 in.) Below Body] Solder Dipping Wave Soldering ESD Protection @ 1.5 k, 100 pF -0.3 to 7.0 V 5.5 V -0.3 to VDD +0.3 V -55C to +85C -55C to +100C +150C 260C for 5 secs 250C for 3 secs VZ = 4 kV (each pin) Notes: 1. Maximum voltage is with no LEDs illuminated. 2. 20 dots ON in all locations at full brightness. ESD WARNING: STANDARD CMOS HANDLING PRECAUTIONS SHOULD BE OBSERVED WITH THE HDSP-2131, HDSP-2132, HDSP-2133, AND HDSP-2179. 2 Character Set D7 D6 0 0 D5 BIT S D4 D3 D2 0 0 0 0 D1 D0 COLUMN ROW 3 0 0 0 0 1 1 0 1 0 0 1 1 0 2 0 1 0 1 3 0 1 0 0 4 0 1 1 1 5 1 X 1 0 6 X 1 7 X 8-F 0000 0 16 0001 1 U S E R 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F D E F I N E D C H A R A C T E R S Recommended Operating Conditions Parameter Supply Voltage Symbol VDD Minimum 4.5 Nominal 5.0 Maximum 5.5 Electrical Characteristics over Operating Temperature Range 4.5 < VDD < 5.5 V (unless otherwise specified) 25C Parameter Symbol Min. Typ.[1] Input Leakage II -10.0 (Input without Pullup) Units V 25C Max.[1] Max.[2] +10.0 Units A 11 18 30 A IDD (BLK) IDD(V) 0.5 200 1.5 255 2.0 330 mA mA IDD(#) 300 370 430 mA VDD +0.3 0.8 V Test Conditions VIN = 0 to VDD, pins CLK, D0-D7, A0-A4 VIN = 0 to VDD, pins RST, CLS, WR, RD, CE, FL VIN = VDD "V" on in all 8 locations "#" on in all 8 locations VDD = 5.5 V V VDD = 4.5 V V VDD = 4.5 V, IOH = -40 A VDD = 4.5 V, IOL = 1.6 mA VDD = 4.5 V, IOL = 40 A Input Current (Input with Pullup) IIP IDD Blank IDD 8 digits 12 Dots/Character[3] IDD 8 digits 20 Dots/Character[3] Input Voltage High VIH 2.0 Input Voltage Low VIL Output Voltage High VOH GND -0.3 V 2.4 Output Voltage Low D0-D7 Output Voltage Low CLK Thermal Resistance IC Junction-to-PIN VOL RqJ-PIN -30.0 11 0.4 V 0.4 V C/W Notes: 1. VDD = 5.0 V. 2. Maximum IDD occurs at -55C. 3. Average IDD measured at full brightness. See Table 2 in Control Word Section for IDD at lower brightness levels. Peak IDD = 28/15 x Average IDD (#). 4 Optical Characteristics at 25C[4] VDD = 5.0 V at Full Brightness High Efficiency Red HDSP-2132 Description Luminous Intensity Character Average (#) Peak Wavelength Dominant Wavelength Symbol IV lPEAK ld Minimum 2.5 Typical 7.5 635 626 Units mcd nm nm Orange HDSP-2179 Description Luminous Intensity Character Average (#) Peak Wavelength Dominant Wavelength Symbol IV lPEAK ld Minimum 2.5 Typical 7.5 600 602 Units mcd nm nm Yellow HDSP-2131 Description Luminous Intensity Character Average (#) Peak Wavelength Dominant Wavelength Symbol IV lPEAK ld Minimum 2.5 Typical 7.5 583 585 Units mcd nm nm High Performance Green HDSP-2133 Description Luminous Intensity Character Average (#) Peak Wavelength Dominant Wavelength Symbol IV lPEAK ld Minimum 2.5 Typical 7.5 568 574 Units mcd nm nm Note: 4. Refers to the initial case temperature of the device immediately prior to the light measurement. 5 AC Timing Characteristics over Temperature Range VDD = 4.5 to 5.5 V unless otherwise specified Reference Number Symbol Description 1 tACC Display Access Time Write Read 2 tACS Address Setup Time to Chip Enable 3 tCE Chip Enable Active Time[2,3] Write Read 4 tACH Address Hold Time to Chip Enable 5 tCER Chip Enable Recovery Time 6 tCES Chip Enable Active Prior to Rising Edge of[1,2] Write Read 7 tCEH Chip Enable Hold Time to Rising Edge of Read/Write Signal[2,3] 8 tW Write Active Time[2,3] 9 tWD Data Valid Prior to Rising Edge of Write Signal 10 tDH Data Write Hold Time 11 tR Chip Enable Active Prior to Valid Data 12 tRD Read Active Prior to Valid Data 13 tDF Read Data Float Delay - tRC Reset Active Time[4] Min.[1] Units 210 230 10 ns ns 140 160 20 60 ns ns ns 140 160 ns 0 100 50 20 160 75 10 300 ns ns ns ns ns ns ns ns Notes: 1. Worst case values occur at an IC junction temperature of 150C. 2. For designers who do not need to read from the display, the Read line can be tied to VDD and the Write and Chip Enable lines can be tied together. 3. Changing the logic levels of the Address lines when CE = "0" may cause erroneous data to be entered into the Character RAM, regardless of the logic levels of the WR and RD lines. 4. The display must not be accessed until after 3 clock pulses (110 s min. using the internal refresh clock) after the rising edge of the reset line. 6 AC Timing Characteristics Over Temperature Range VDD = 4.5 V to 5.5 V unless otherwise specified. Symbol Description 25C Typical FOSC Oscillator Frequency 57 FRF[5] Display Refresh Rate 256 FFL[6] Character Flash Rate 2 tST[7] Self Test Cycle Time 4.6 Minimum[1] 28 128 1 9.2 Units kHz Hz Hz Sec Notes: 5. FRF = FOSC/224. 6. FFL = FOSC/28,672. 7. tST = 262,144/FOSC. Write Cycle Timing Diagram 1 A0 -A4 FL 4 2 3 CE 6 7 8 WR 10 9 D0 -D7 INPUT PULSE LEVELS: 0.6 V to 2.4 V 7 2 5 Read Cycle Timing Diagram 1 A0 -A4 FL 4 2 2 5 3 CE 6 7 11 RD 12 13 D0 -D7 INPUT PULSE LEVELS: 0.6 V to 2.4 V OUTPUT REFERENCE LEVELS: 0.6 V to 2.2 V OUTPUT LOADING = 1 TTL LOAD AND 100 pF Character Font Relative Luminous Intensity vs. Temperature 2.85 TYP. (0.112) C2 0.76 TYP. (0.030) C3 C4 C5 R1 R2 R3 R4 R5 R6 0.254 TYP. (0.010) R7 8 3.5 HDSP-2132 (HER) -2179 (ORANGE) HDSP-2131 (YELLOW) HDSP-2133 (GREEN) 3.0 2.5 2.0 1.5 1.0 0.5 0 -55 0.65 TYP. (0.026) NOTE: NOT TO SCALE 4.83 TYP. (0.190) RELATIVE LUMINOUS INTENSITY (NORMALIZED TO 1 AT 25C) C1 4.0 -35 -15 5 25 45 65 85 TA - AMBIENT TEMPERATURE - C 105 Electrical Description Pin Function Description RESET (RST, Pin 5) Reset initializes the display. FLASH (FL, Pin 27) FL low indicates an access to the Flash RAM and is unaffected by the state of address lines A3-A4. ADDRESS INPUTS (A0-A4, Pins 28-32) Each location in memory has a distinct address. Address inputs (A0-A2) select a specific location in the Character RAM, the Flash RAM or a particular row in the UDC (User-Defined Character) RAM. A3-A4 are used to select which section of memory is accessed. Table 1 shows the logic levels needed to access each section of memory. Table 1. Logic Levels to Access Memory FL A4 A3 Section of Memory A2 A1 A 0 0 X X Flash RAM Character Address 1 0 0 UDC Address Register Don't Care 1 0 1 UDC RAM Row Address 1 1 0 Control Word Register Don't Care 1 1 1 Character RAM Character Address CLOCK SELECT (CLS, Pin 1) This input is used to select either an internal (CLS = 1) or external (CLS = 0) clock source. CLOCK INPUT/OUTPUT (CLK, Pin 2) Outputs the master clock (CLS = 1) or inputs a clock (CLS = 0) for slave displays. WRITE (WR, Pin 3) Data is written into the display when the WR input is low and the CE input is low. CHIP ENABLE (CE, Pin 4) This input must be at a logic low to read or write data to the display and must go high between each read and write cycle. READ (RD, Pin 6) Data is read from the display when the RD input is low and the CE input is low. DATA Bus (D0-D7, Pins 11-14, 19-22) The Data bus is used to read from or write to the display. GND(SUPPLY) (Pin 17) This is the analog ground for the LED drivers. GND(LOGIC) (Pin 18) This is the digital ground for internal logic. VDD(POWER) (Pin 16) This is the positive power supply input. 9 10 CLS CLK RST RD WR D0-D7 A0-A2 A3 A4 FL CE OCS A3 A4 FL CE A3 A4 FL CE UDC ADDR CLR1 RESET A3 A4 FL CE INTENSITY FLASH BLINK RESET CLOCK FLASH TEST OK CLR2 TIMING AND CONTROL TEST OK SELF TEST SELF TEST IN VISUAL TEST ROM TEST SELF TEST CLR START TIMING ROW SET CHAR ADDR EN FLASH RD DATA WR FLASH D0 RAM A0-A2 RESET CHAR ADDR 8x8 EN CHARACTER RD D0-D6 RAM WR D7 D0-D7 A0-A2 RESET CHAR ADDR Figure 1. HDSP-213x/-2179 internal block diagram. CONTROL WORD REGISTER EN 0 INTENSITY RD 1 WR 2 FLASH D0-D7 3 BLINK 4 RESET SELF TEST 6 SELF TEST 7 RESULT FL CE A3 A4 FL CE PRE SET CLR RD WR D0-D7 EN UDC ADDR REGISTER UDC RAM ROW SEL SELF TEST D0-D6 DOT DATA DECODER(*) EN EN RD WR DOT D0-D4 A0-A2 DATA UDC ADDR ROW SET EN D0-D4 TIMING DOT DRIVERS DOT DATA TIMING ROW DRIVERS 8 5x7 LED CHARACTERS Display Internal Block Diagram Figure 1 shows the internal block diagram of the HDSP-213x/-2179 display. The CMOS IC consists of an 8 byte Character RAM, an 8 bit Flash RAM, a 128 character Character RAM Flash RAM User-Defined Character RAM (UDC RAM) User-Defined Character Address Register (UDC Address Register) Control Word Register eight 5 x 7 dot matrix characters. The major user accessible portions of the display are listed below: ASCII decoder, a 16 character UDC RAM, a UDC Address Register, a Control Word Register, and the refresh circuitry necessary to synchronize the decoding and driving of This RAM stores either ASCII character data or a UDC RAM address. This is a 1 x 8 RAM which stores Flash data. This RAM stores the dot pattern for custom characters. This register is used to provide the address to the UDC RAM when the user is writing or reading a custom character. This register allows the user to adjust the display brightness, flash individual characters, blink, self test, or clear the display. Character Ram Figure 2 shows the logic levels needed to access the HDSP-213x/ -2179 Character RAM. During a normal access the CE = "0" and either RD = "0" or WR = "0". However, erroneous data may be written into the Character RAM if the Address lines are unstable when CE = "0" regardless of the logic levels of the RD or WR lines. Address lines A0-A2 are used to select the location in the Character RAM. Two types of data can be stored in each Character RAM location: an ASCII code or a UDC RAM address. Data bit D7 is used to differentiate between an ASCII character and a UDC RAM address. D7 = 0 enables the ASCII decoder and D7 = 1 enables the UDC RAM. D0-D6 are used to input ASCII data and D0-D3 are used to input a UDC address. RST CE 1 0 WR 0 0 1 1 RD 0 1 0 1 UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED CONTROL SIGNALS FL 1 A4 1 A3 1 A2 A1 A0 000 = LEFT MOST 111 = RIGHT MOST CHARACTER ADDRESS CHARACTER RAM ADDRESS D7 D6 D5 0 D4 D3 D2 D1 D0 128 ASCII CODE 1 X X X UDC CODE CHARACTER RAM DATA FORMAT DIG0 DIG1 DIG2 DIG3 DIG4 DIG5 DIG6 DIG7 000 001 010 011 100 101 110 111 SYMBOL IS ACCESSED IN LOCATION SPECIFIED BY THE CHARACTER ADDRESS ABOVE DISPLAY 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE Figure 2. Logic levels to access the character RAM. 11 UDC RAM and UDC Address Register Figure 3 shows the logic levels needed to access the UDC RAM and the UDC Address Register. The UDC Address Register is eight bits wide. The lower four bits (D0D3) are used to select one of the 16 UDC locations. The upper four bits (D4-D7) are not used. Once the UDC address has been stored in the UDC Address Register, the UDC RAM can be accessed. To completely specify a 5 x 7 character requires eight write cycles. One cycle is used to store the UDC RAM address in the UDC Address Register. Seven cycles are used to store dot data in the UDC RAM. Data is entered by rows. One cycle is needed to access each row. Figure 4 shows the organization of a UDC character assuming the symbol to be stored is an "F." A0-A2 are used to select the row to be accessed and D0-D4 are used to transmit the row dot data. The upper three bits (D5-D7) are ignored. D0 (least significant bit) corresponds to the right most column of the 5 x 7 matrix and D4 (most significant bit) corresponds to the left most column of the 5 x 7 matrix. Flash RAM Figure 5 shows the logic levels needed to access the Flash RAM. The Flash RAM has one bit associated with each location of the Character RAM. The Flash input is used to select the Flash RAM. Address lines A3-A4 are ignored. Address lines A0-A2 are used to select the location in the Flash RAM to store the attribute. D0 is used to store or remove the flash attribute. D0 = "1" stores the attribute and D0 = "0" removes the attribute. When the attribute is enabled through bit 3 of the Control Word and a "1" is stored in the Flash RAM, the corresponding character 12 RST CE 1 0 WR 0 0 1 1 RD 0 1 0 1 UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED CONTROL SIGNALS FL A4 A3 A2 A1 A0 1 0 0 X X X UDC ADDRESS REGISTER ADDRESS D7 D6 D5 D4 X X X X D3 D2 D1 D0 UDC CODE UDC ADDRESS REGISTER DATA FORMAT RST CE 1 0 WR 0 0 1 1 RD 0 1 0 1 UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED CONTROL SIGNALS FL A4 A3 1 0 1 A2 A1 A0 ROW SELECT 000 = ROW 1 110 = ROW 7 UDC RAM ADDRESS D7 D6 D5 X X X D4 D3 D2 D1 D0 DOT DATA UDC RAM DATA FORMAT C O L 1 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE C O L 5 Figure 3. Logic levels to access a UDC character. C C C O O O L L L 1 2 3 D4 D3 D2 1 1 1 1 0 0 1 0 0 1 1 1 1 0 0 1 0 0 1 0 0 IGNORED C O L 4 D1 1 0 0 1 0 0 0 C O L 5 D0 1 0 0 0 0 0 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 UDC CHARACTER * * * * * * * * * * * * * * HEX CODE 1F 10 10 1D 10 10 10 0 = LOGIC 0; 1 = LOGIC 1; * = ILLUMINATED LED Figure 4. Data to load "F" into the UDC RAM. will flash at approximately 2 Hz. The actual rate is dependent on the clock frequency. For an external clock the flash rate can be calculated by dividing the clock frequency by 28,672. RST 1 CE 0 WR 0 0 1 1 RD 0 1 0 1 RST UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED 1 CONTROL SIGNALS FL 0 A4 X A3 X D6 A2 A1 A0 000 = LEFT MOST 111 = RIGHT MOST CHARACTER ADDRESS X X D5 X 0 WR 0 0 1 1 UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED FL A4 A3 A2 A1 A0 1 1 0 X X X CONTROL WORD ADDRESS D4 X D3 X D2 X D1 D0 X 0 1 FLASH RAM DATA FORMAT REMOVE FLASH AT SPECIFIED DIGIT LOCATION STORE FLASH AT SPECIFIED DIGIT LOCATION D7 D6 D5 D4 D3 D2 D1 D0 C S S BL F B B B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 DISABLE FLASH 1 ENABLE FLASH 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE Figure 5. Logic levels to access the flash RAM. Control Word Register Figure 6 shows how to access the Control Word Register. This is an eight bit register which performs five functions. They are Brightness control, Flash RAM control, Blinking, Self Test and Clear. Each function is independent of the others. However, all bits are updated during each Control Word write cycle. Brightness (Bits 0-2) Bits 0-2 of the Control Word adjust the brightness of the display. Bits 0-2 are interpreted as a three bit binary code with code (000) corresponding to maximum brightness and code (111) corresponding to a blanked display. In addition to varying the display brightness, bits 0-2 also vary the average value of IDD. IDD can be calculated at any brightness level by multiplying the percent bright-ness level by the value of IDD at the 100% brightness level. These values of IDD are shown in Table 2. Flash Function (Bit 3) Bit 3 determines whether the flashing character attribute is on or off. When bit 3 is a "1," the output of the Flash RAM is checked. If the content of a location in the Flash RAM is a "1," the associated digit will flash at 13 RD 0 1 0 1 CONTROL SIGNALS FLASH RAM ADDRESS D7 CE 0 1 0 1 0 1 0 1 100% 80% 53% BRIGHTNESS 40% CONTROL 27% LEVELS 20% 13% 0% 0 DISABLE BLINKING 1 ENABLE BLINKING 0 1 X NORMAL OPERATION; X IS IGNORED X START SELF TEST; RESULT GIVEN IN X X = 0 FAILED X = 1 PASSED 0 NORMAL OPERATION 1 CLEAR FLASH AND CHARACTER RAMS CONTROL WORD DATA FORMAT 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE Figure 6. Logic levels to access the control word register. Table 2. Current Requirements at Different Brightness Levels Symbol IDD (V) D2 0 0 0 0 1 1 1 D1 0 0 1 1 0 0 1 D0 0 1 0 1 0 1 0 approximately 2 Hz. For an external clock, the blink rate can be calculated by driving the clock frequency by 28,672. If the flash enable bit of the Control Word is a "0," the content of the Flash RAM is ignored. To use this function with multiple display systems see the Reset section. Blink Function (Bit 4) Bit 4 of the Control Word is used to synchronize blinking of all eight % Brightness 100 80 53 40 27 20 13 25C Typ. 200 160 106 80 54 40 26 Units mA mA mA mA mA mA mA digits of the display. When this bit is a "1" all eight digits of the display will blink at approximately 2 Hz. The actual rate is dependent on the clock frequency. For an external clock, the blink rate can be calculated by dividing the clock frequency by 28,672. This function will override the Flash function when it is active. To use this function with multiple display systems see the Reset section. Setting bit 6 to a logic 1 will start the self test function. The built-in self test function of the IC consists of two internal routines which exercises major portions of the IC and illuminates all of the LEDs. The first routine cycles the ASCII decoder ROM through all states and performs a checksum on the output. If the checksum agrees with the correct value, bit 5 is set to "1." The second routine provides a visual test of the LEDs using the drive circuitry. This is accomplished by writing checkered and inverse checkered patterns to the display. Each pattern is displayed for approximately 2 seconds. During the self test function the display must not be accessed. The time needed to execute the self test function is calculated by multiplying the clock period by 262,144. For example, assume a clock frequency of 58 KHz, then the time to execute the self test function frequency is equal to (262,144/58,000) = 4.5 second duration. At the end of the self test function, the Character RAM is loaded with blanks, the Control Word Register is set to zeros except for bit 5, and the Flash RAM is cleared and the UDC Address Register is set to all ones. Clear Function (Bit 7) Bit 7 of the Control Word will clear the Character RAM and the Flash RAM. Setting bit 7 to a "1" will start the clear function. Three 14 clock cycles (110 s min. using the internal refresh clock) are required to complete the clear function. The display must not be accessed while the display is being cleared. When the clear function has been completed, bit 7 will be reset to a "0." The ASCII character code for a space (20H) will be loaded into the Character RAM to blank the display and the Flash RAM will be loaded with "0"s. The UDC RAM, UDC Address Register, and the remainder of the Control Word are unaffected. Display Reset Figure 7 shows the logic levels needed to Reset the display. The display should be Reset on Powerup. The external Reset clears the Character RAM, Flash RAM, Control Word and resets the internal counters. After the rising edge of the Reset signal, three clock cycles (110 s min. using the internal refresh clock) are required to complete the reset sequence. The display must not be accessed while the display is being reset. The ASCII Character code for a space (20H) will be loaded into the Character RAM to blank the display. The Flash RAM and Control Word Register are loaded with all "0"s. The UDC RAM and UDC Address Register are unaffected. All displays which operate with the same clock source must be simultaneously reset to synchronize the Flashing and Blinking functions. RST CE WR RD FL 0 1 X X X A4 -A0 D7 -D0 X X 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE NOTE: IF RST, CE, AND WR ARE LOW, UNKNOWN DATA MAY BE WRITTEN INTO THE DISPLAY. Figure 7. Logic levels to reset the display. Mechanical and Electrical Considerations The HDSP-213x/-2179 is a 32 pin dual-in-line package with 24 external pins, which can be stacked horizontally and vertically to create arrays of any size. The HDSP-213x/-2179 is designed to operate continuously from -55C to +85C with a maximum of 20 dots ON per character. Illuminating all thirty-five dots at full brightness is not recommended. The HDSP-213x/-2179 is assembled by die attaching and wire bonding 280 LED chips and a CMOS IC to a ceramic sub-strate. A glass window is placed over the ceramic substrate creating an air gap over the LED wire bonds. A second glass window creates an air gap over the CMOS IC. This package construction makes the display highly tolerant to temperature cycling and allows wave soldering and visual inspection of the IC. The inputs to the CMOS IC are protected against static discharge and input current latchup. However, for best results standard CMOS handling precautions should be used. Prior to use, the HDSP-213X should be stored in 4.0 PD - POWER DISSIPATION - W Self Test Function (Bits 5, 6) Bit 6 of the Control Word Register is used to initiate the self test function. Results of the internal self test are stored in bit 5 of the Control Word. Bit 5 is a read only bit where bit 5 = "1" indicates a passed self test and bit 5 = "0" indicates a failed self test. 3.0 2.0 RqJ-A = 30C/W 1.0 0 25 35 45 55 65 75 85 95 TA - AMBIENT TEMPERATURE - C Figure 8. Maximum power dissipation vs. ambient temperature derating based on TJMAX = 125C. 105 antistatic packages or conductive material. During assembly, a grounded conductive work area should be used, and assembly personnel should wear conductive wrist straps. Lab coats made of synthetic material should be avoided since they are prone to static charge buildup. Input current latchup is caused when the CMOS inputs are subjected to either a voltage below ground (VIN < ground) or to a voltage higher than VDD (VIN > VDD) and when a high current is forced into the input. To prevent input current latchup and ESD damage, unused inputs should be connected either to ground or to VDD. Voltages should not be applied to the inputs until VDD has been applied to the display. Transient input voltages should be eliminated. Thermal Considerations The HDSP-213x/-2179 has been designed to provide a low thermal resistance path from the CMOS IC to the 24 package pins. This heat is then typically conducted through the traces of the user's printed circuit board to free air. For most applications no additional heatsinking is required. The maximum operating IC junction temperature is 150C. The maximum IC junction temperature can be calculated using the following equation: The logic ground should be connected to the same ground potential as the logic interface circuitry. The analog ground and the logic ground should be connected at a common ground which can withstand the current introduced by the switching LED drivers. When separate ground connections are used, the analog ground can vary from -0.3 V to +0.3 V with respect to the logic ground. Voltage below -0.3 V can cause all dots to be on. Voltage above +0.3 V can cause dimming and dot mismatch. IDDMAX = 370 mA with 20 dots ON in eight character locations at 25C ambient. This value is from the Electrical Characteristics table. For further information on soldering and post solder cleaning, see Application Note 1027, Soldering LED Components. LAMINAR WAVE HOT AIR KNIFE TURBULENT WAVE 250 TEMPERATURE - C PDMAX = (VDDMAX) (IDDMAX) Proper handling is imperative to avoid excessive thermal stresses to component when heated. Therefore, the solder PCB must be allowed to cool to room temperature, 25C, before handling. ESD Susceptibility These displays have ESD susceptibility ratings of CLASS 3 per DOD-STD-1686 and CLASS B per MIL-STD-883C. TJ(IC) MAX = TA + (PDMAX) (RqJ-PIN + RqPIN-A) Where Soldering and Post Solder Cleaning Instructions for the HDSP-213x/-2179 The HDSP-213x/-2179 may be hand soldered or wave soldered with lead-free solder. When hand soldering it is recommended that an electronically temperature controlled and securely grounded soldering iron be used. For best results, the iron tip temperature should be set at 315C (600F). For wave soldering, a rosin-based RMA flux can be used. The solder wave temperature should be set at 245C 5C (473F 9F), and dwell in the wave should be set between 11/2 to 3 seconds for optimum soldering. The preheat temperature should not exceed 105C (221F) as measured on the solder side of the PC board. Ground Connections Two ground pins are provided to keep the internal IC logic ground clean. The designer can, when necessary, route the analog ground for the LED drivers separately from the logic ground until an appropriate ground plane is available. On long interconnects between the display and the host system, the designer can keep voltage drops on the analog ground from affecting the display logic levels by isolating the two grounds. BOTTOM SIDE OF PC BOARD TOP SIDE OF PC BOARD 200 CONVEYOR SPEED = 1.83 M/MIN (6 FT/MIN) PREHEAT SETTING = 150C (100C PCB) SOLDER WAVE TEMPERATURE = 245C AIR KNIFE AIR TEMPERATURE = 390C AIR KNIFE DISTANCE = 1.91 mm (0.25 IN.) AIR KNIFE ANGLE = 40 150 FLUXING 100 50 30 0 NOTE: ALLOW FOR BOARDS TO BE SUFFICIENTLY COOLED BEFORE EXERTING MECHANICAL FORCE. PREHEAT 10 20 30 40 50 60 70 80 90 100 TIME - SECONDS PDMAX = (5.5 V) (0.370 A) = 2.04 W 15 Figure 9. Recommended wave soldering profile for lead-free Smart Display. Contrast Enhancement When used with the proper contrast enhancement filters, the HCMS-213x/-2179 series displays are readable daylight ambients. Refer to Application Note 1029 Luminous Contrast and Sunlight Readability of the HDSP-235x Series Alphanumeric Displays for Military Applications for information on contrast enhancement for daylight ambients. Refer to Application Note 1015 Contrast Enhancement Techniques for LED Displays for information on contrast enhancement in moderate ambients. Intensity Bin Limits Intensity Range (mcd) Bin Min. Max. G 2.50 4.00 H 3.41 6.01 I 5.12 9.01 J 7.68 13.52 K 11.52 20.28 Color Bin Limits Color Green Yellow Note: Test conditions as specified in Optical Characteristic table. Note: Test conditions as specified in Optical Characteristic table. Night Vision Lighting When used with the proper NVG/ DV filters, the HDSP-2131, HDSP2179 and HDSP-2133 may be used in night vision lighting applications. The HDSP-2131 (yellow), HDSP-2179 (orange) displays are used as master caution and warning indicators. The HDSP2133 (high per-formance green) displays are used for general instrumenta-tion. For a list of NVG/DV filters and a discussion on night vision lighting technology, refer to Application Note 1030 LED Displays and Indicators and Night Vision Imaging System Lighting. An external dimming circuit must be used to dim these displays to night vision lighting levels to meet NVIS radiance requirements. Refer to AN 1039 Dimming HDSP-213x Displays to Meet Night Vision Lighting Levels. For product information and a complete list of distributors, please go to our website: Bin 1 2 3 4 3 4 5 6 Color Range (nm) Min. Max. 576.0 580.0 573.0 577.0 570.0 574.0 567.0 571.5 581.5 585.0 584.0 587.5 586.5 590.0 589.0 592.5 www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright (c) 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5989-3182EN AV02-0190EN March 6, 2007