Devices High High
Efficiency Performance
Yellow Red Green Orange
HDSP-2131 HDSP-2132 HDSP-2133 HDSP-2179
Description
The HDSP-2131 (yellow), HDSP-2179 (orange),
HDSP-2132 (high efficiency red) and the HDSP-2133
(green) are eight-digit, 5 x 7 dot matrix, alphanu-
meric displays. The 5.0 mm (0.2 inch) high characters
are packaged in a standard 7.64 mm (0.30 inch) 32
pin DIP. The on-board CMOS IC has the ability to
decode 128 ASCII characters, which are permanently
stored in ROM. In addition, 16 programmable
symbols may be stored in an on-board RAM. Seven
brightness levels provide versatility in adjusting the
display intensity and power consumption. The
HDSP-213x and HDSP-2179 are designed for stan-
dard microprocessor interface techniques. The
display and special features are accessed through a
bidirectional eight-bit data bus. These features
make the HDSP-213x and HDSP-2179 ideally suited
for applications where a hermetic, low power alpha-
numeric display is required.
Features
• Wide operating temperature range -55°C to +85°C
• Smart alphanumeric display
– On-board CMOS IC
– Built-in RAM
– ASCII decoder
– LED drive circuitry
• 128 ASCII character set
• 16 user definable characters
• Programmable features
– Individual character flashing
– Full display blinking
– Multi-level dimming and blanking
– Self test
– Clear function
• Read/write capability
• Full TTL compatibility
• HDSP-2131/-2133/-2179 useable in night vision
lighting applications
• Categorized for luminous intensity
• HDSP-2131/2133 categorized for color
• Excellent ESD protection
• Wave solderable
• X-Y stackable
• RoHS compliant
HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179
Eight Character 5.0 mm (0.2 inch) Glass/Ceramic
Intelligen t 5x7 Alphanumeric Displa ys
for Military Applications
Data Sheet
2
Package Dimensions
ESD WARNING: STANDARD CMOS HANDLING PRECAUTIONS SHOULD BE OBSERVED WITH THE
HDSP-2131, HDSP-2132, HDSP-2133, AND HDSP-2179.
Absolute Maximum Ratings
Supply Voltage, VDD to Ground[1] -0.3 to 7.0 V
Operating Voltage, VDD to Ground[2] 5.5 V
Input Voltage, Any Pin to Ground -0.3 to VDD +0.3 V
Free Air Operating Temperature Range, TA-55°C to +85°C
Storage Temperature, TS-55°C to +100°C
CMOS IC Junction Temperature, TJ (IC) +150°C
Soldering Temperature [1.59 mm (0.063 in.) Below Body]
Solder Dipping 260°C for 5 secs
Wave Soldering 250°C for 3 secs
ESD Protection @ 1.5 kΩ, 100 pF VZ = 4 kV (each pin)
Notes:
1. Maximum voltage is with no LEDs illuminated.
2. 20 dots ON in all locations at full brightness.
TYP.
PART NUMBER
DATE CODE
LIGHT INTENSITY CATEGORY
COLOR BIN (NOTE 3)
6.00
(0.24)
4.83
(0.190)
9.91
(0.39)
6.35
(0.250)
4.96
(0.195)
1.78
(0.070)
TYP.
0.51
(0.020)
TYP.
1.27
(0.050)
TYP.
MAX.
2.29
(0.090)TYP.
SEATING
PLANE
2.54
(0.100)
NON-ACCUM.
6.10
(0.24)
7.62
(0.300)
REF.
0.38
(0.015)TYP.
PIN # FUNCTION PIN # FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLS
CLK
WR
CE
RST
RD
NO PIN
NO PIN
NO PIN
NO PIN
D0
D1
D2
D3
NC
V
DD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND (SUPPLY)
GND (LOGIC)
D4
D5
D6
D7
NO PIN
NO PIN
NO PIN
NO PIN
FL
A0
A1
A2
A3
A4
2.85
(0.112)
PIN 17
TYP.
2.67
(0.105)
42.72 (1.68)
TYP.
5.33
(0.210)
PIN #1
IDENTIFIER
NOTES:
1. ALL DIMENSIONS ARE IN mm (INCHES).
2. UNLESS OTHERWISE SPECIFIED, TOLERANCE IS ± 0.30 mm (0.015 INCH).
3. FOR GREEN AND YELLOW DEVICES ONLY.
4. LEADS ARE COPPER ALLOY, SOLDER DIPPED.
12.70
(0.50)
HDSP-213X/2179
HDSP-XXXX YYWW X Z
3
Character Set
D7
D6 D5 D4
BITS
D3 D0D2 D1 ROW COLUMN
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9
1010 A
1011 B
1100 C
1101 D
1110 E
1111 F
0
000
0
0
001
1
0
010
2
0
011
3
0
100
4
0
101
5
0
110
6
0
111
7
1
XXX
8–F
16
U
S
E
R
D
E
F
I
N
E
D
C
H
A
R
A
C
T
E
R
S
4
Recommended Operating Conditions
Parameter Symbol Minimum Nominal Maximum Units
Supply Voltage VDD 4.5 5.0 5.5 V
Electrical Characteristics over Operating Temperature Range
4.5 < VDD < 5.5 V (unless otherwise specified) 25°C25°C
Parameter Symbol Min. Typ.[1] Max.[1] Max.[2] Units Test Conditions
Input Leakage II-10.0 +10.0 µAV
IN = 0 to VDD,
(Input without Pullup) pins CLK, D0-D7,
A0-A4
Input Current IIP -30.0 11 18 30 µAV
IN = 0 to VDD,
(Input with Pullup) pins RST, CLS, WR,
RD, CE, FL
IDD Blank IDD (BLK) 0.5 1.5 2.0 mA VIN = VDD
IDD 8 digits IDD(V) 200 255 330 mA "V" on in all 8
12 Dots/Character[3] locations
IDD 8 digits IDD(#) 300 370 430 mA "#" on in all 8
20 Dots/Character[3] locations
Input Voltage High VIH 2.0 VDD VV
DD = 5.5 V
+0.3
Input Voltage Low VIL GND 0.8 V VDD = 4.5 V
-0.3 V
Output Voltage High VOH 2.4 V VDD = 4.5 V,
IOH = -40 µA
Output Voltage Low VOL 0.4 V VDD = 4.5 V,
D0-D7IOL = 1.6 mA
Output Voltage Low 0.4 V VDD = 4.5 V,
CLK IOL = 40 µA
Thermal Resistance RqJ-PIN 11 °C/W
IC Junction-to-PIN
Notes:
1. VDD = 5.0 V.
2. Maximum IDD occurs at -55°C.
3. Average IDD measured at full brightness. See Table 2 in Control Word Section for IDD at lower brightness levels. Peak IDD = 28/15 x Average IDD (#).
5
Optical Characteristics at 25°C[4]
VDD = 5.0 V at Full Brightness
High Efficiency Red HDSP-2132
Description Symbol Minimum Typical Units
Luminous Intensity Character Average (#) IV2.5 7.5 mcd
Peak Wavelength lPEAK 635 nm
Dominant Wavelength ld626 nm
Orange HDSP-2179
Description Symbol Minimum Typical Units
Luminous Intensity Character Average (#) IV2.5 7.5 mcd
Peak Wavelength lPEAK 600 nm
Dominant Wavelength ld602 nm
Yellow HDSP-2131
Description Symbol Minimum Typical Units
Luminous Intensity Character Average (#) IV2.5 7.5 mcd
Peak Wavelength lPEAK 583 nm
Dominant Wavelength ld585 nm
High Performance Green HDSP-2133
Description Symbol Minimum Typical Units
Luminous Intensity Character Average (#) IV2.5 7.5 mcd
Peak Wavelength lPEAK 568 nm
Dominant Wavelength ld574 nm
Note:
4. Refers to the initial case temperature of the device immediately prior to the light measurement.
6
AC Timing Characteristics over Temperature Range
VDD = 4.5 to 5.5 V unless otherwise specified
Reference
Number Symbol Description Min.[1] Units
1t
ACC Display Access Time
Write 210
Read 230 ns
2t
ACS Address Setup Time to Chip Enable 10 ns
3t
CE Chip Enable Active Time[2,3]
Write 140
Read 160 ns
4t
ACH Address Hold Time to Chip Enable 20 ns
5t
CER Chip Enable Recovery Time 60 ns
6t
CES Chip Enable Active Prior to Rising Edge of[1,2]
Write 140
Read 160 ns
7t
CEH Chip Enable Hold Time to Rising Edge of
Read/Write Signal[2,3] 0ns
8t
WWrite Active Time[2,3] 100 ns
9t
WD Data Valid Prior to Rising Edge of Write Signal 50 ns
10 tDH Data Write Hold Time 20 ns
11 tRChip Enable Active Prior to Valid Data 160 ns
12 tRD Read Active Prior to Valid Data 75 ns
13 tDF Read Data Float Delay 10 ns
–t
RC Reset Active Time[4] 300 ns
Notes:
1. Worst case values occur at an IC junction temperature of 150°C.
2. For designers who do not need to read from the display, the Read line can be tied to VDD and the Write and Chip Enable lines can be tied together.
3. Changing the logic levels of the Address lines when CE = “0” may cause erroneous data to be entered into the Character RAM, regardless of the
logic levels of the WR and RD lines.
4. The display must not be accessed until after 3 clock pulses (110 µs min. using the internal refresh clock) after the rising edge of the reset line.
7
Write Cycle Timing Diagram
AC Timing Characteristics Over Temperature Range
VDD = 4.5 V to 5.5 V unless otherwise specified.
Symbol Description 25°C Typical Minimum[1] Units
FOSC Oscillator Frequency 57 28 kHz
FRF[5] Display Refresh Rate 256 128 Hz
FFL[6] Character Flash Rate 2 1 Hz
tST[7] Self Test Cycle Time 4.6 9.2 Sec
Notes:
5. FRF = FOSC/224.
6. FFL = FOSC/28,672.
7. tST = 262,144/FOSC.
1
9
8
6
32
CE
7
10
4 2
5
A
0
-A
4
FL
D
0
-D
7
WR
INPUT PULSE LEVELS: 0.6 V to 2.4 V
8
Read Cycle Timing Diagram
Character Font Relative Luminous Intensity vs. Temperature
1
12
11
6
3
2
CE
7
13
4 2
5
A0 -A4
FL
D0 -D7
RD
INPUT PULSE LEVELS: 0.6 V to 2.4 V
OUTPUT REFERENCE LEVELS: 0.6 V to 2.2 V
OUTPUT LOADING = 1 TTL LOAD AND 100 pF
0.65
(0.026)
C1 C2 R1
R2
R3
R4
R5
R6
R7
C3 C4 C5
4.83
(0.190)
0.76
(0.030)
0.254
(0.010)
2.85
(0.112)
NOTE: NOT TO SCALE
TYP.
TYP.
TYP.
TYP.
TYP.
RELATIVE LUMINOUS INTENSITY
(NORMALIZED TO 1 AT 25°C)
-55
0
TA – AMBIENT TEMPERATURE – °C
85
-15
65 105
4.0
3.5
3.0
2.0
1.5
1.0
0.5
25 455
2.5
-35
HDSP-2133 (GREEN)
HDSP-2132 (HER) -2179 (ORANGE)
HDSP-2131 (YELLOW)
9
Electrical Description
Pin Function Description
RESET (RST, Pin 5) Reset initializes the display.
FLASH (FL, Pin 27) FL low indicates an access to the Flash RAM and is unaffected by the
state of address lines A3-A4.
ADDRESS INPUTS Each location in memory has a distinct address. Address inputs (A0-A2)
(A0-A4, Pins 28-32) select a specific location in the Character RAM, the Flash RAM or a
particular row in the UDC (User-Defined Character) RAM. A3-A4 are used to
select which section of memory is accessed. Table 1 shows the logic levels
needed to access each section of memory.
Table 1. Logic Levels to Access Memory
FL A4A3Section of Memory A2A1A0
0 X X Flash RAM Character Address
1 0 0 UDC Address Register Don't Care
1 0 1 UDC RAM Row Address
1 1 0 Control Word Register Don't Care
1 1 1 Character RAM Character Address
CLOCK SELECT This input is used to select either an internal (CLS = 1) or external
(CLS, Pin 1) (CLS = 0) clock source.
CLOCK INPUT/OUTPUT Outputs the master clock (CLS = 1) or inputs a clock (CLS = 0) for slave
(CLK, Pin 2) displays.
WRITE (WR, Pin 3) Data is written into the display when the WR input is low and the CE input
is low.
CHIP ENABLE (CE, Pin 4) This input must be at a logic low to read or write data to the display and
must go high between each read and write cycle.
READ (RD, Pin 6) Data is read from the display when the RD input is low and the CE
input is low.
DATA Bus (D0-D7, The Data bus is used to read from or write to the display.
Pins 11-14, 19-22)
GND(SUPPLY) (Pin 17) This is the analog ground for the LED drivers.
GND(LOGIC) (Pin 18) This is the digital ground for internal logic.
VDD(POWER) (Pin 16) This is the positive power supply input.
10
Figure 1. HDSP-213x/-2179 internal block diagram.
A
3
A
4
FL EN
UDC ADDR REGISTER
UDC
ADDR
RD
WR
D
0
-D
7
CLR
PRE SET
CE
A
3
A
4
A
0
-A
2
D
0
-D
7
FL
CE
WR
RD
A
3
A
4
FL
CE
FL
CE
A
3
A
4
FL
CE
A
3
A
4
FL
CE
EN 8 x 8
CHARACTER
RAM D
0
-D
6
RD
WR
D
0
-D
7
A
0
-A
2
RESET
CHAR ADDR
D
7
EN
FLASH
RAM
FLASH
DATA
RD
WR
D
0
A
0
-A
2
RESET
CHAR ADDR
EN
UDC RAM
DOT
DATA
RD
WR
D
0
-D
4
D
0
-D
4
A
0
-A
2
UDC ADDR
ROW SET
EN
EN
ROW
SEL
SELF
TEST
DECODER(*)
DOT
DATA
D
0
-D
6
TIMING
TIMING
DOT
DRIVERS
DOT
DATA
EN
FLASH
CONTROL WORD
REGISTER 0
1
RD
WR
RST
CLK
OCS
CLS
CLR1
CLR2
D
0
-D
7
RESET
SELF TEST
RESULT
2
3
4
6
7
SELF
TEST
IN
SELF TEST
SELF TEST SELF
TEST
START
8 5x7
LED
CHARACTERS
ROW DRIVERS
VISUAL
TEST
ROM
TEST
CLR
TEST OK
TEST OK
INTENSITY
INTENSITY
FLASH
FLASH
BLINK
BLINK
RESET
RESET
CLOCK
TIMING
AND
CONTROL
CHAR
ADDR
ROW SET
TIMING
11
eight 5 x 7 dot matrix
characters. The major user
accessible portions of the dis-
play are listed below:
ASCII decoder, a 16 character
UDC RAM, a UDC Address
Register, a Control Word
Register, and the refresh
circuitry necessary to synchron-
ize the decoding and driving of
Character Ram
Figure 2 shows the logic levels
needed to access the HDSP-213x/
-2179 Character RAM. During a
normal access the CE = “0” and
either RD = “0” or WR = “0”.
However, erroneous data may be
written into the Character RAM if
the Address lines are unstable
when CE = “0” regardless of the
logic levels of the RD or WR lines.
Address lines A0-A2 are used to
select the location in the Charac-
ter RAM. Two types of data can be
stored in each Character RAM
location: an ASCII code or a UDC
RAM address. Data bit D7 is used
to differentiate between an ASCII
character and a UDC RAM
address. D7 = 0 enables the ASCII
decoder and D7 = 1 enables the
UDC RAM. D0-D6 are used to
input ASCII data and D0-D3 are
used to input a UDC address.
Figure 2. Logic levels to access the character RAM.
Display Internal Block Diagram
Figure 1 shows the internal block
diagram of the HDSP-213x/-2179
display. The CMOS IC consists of
an 8 byte Character RAM, an 8
bit Flash RAM, a 128 character
Character RAM This RAM stores either ASCII character data or a UDC RAM address.
Flash RAM This is a 1 x 8 RAM which stores Flash data.
User-Defined Character RAM This RAM stores the dot pattern for custom characters.
(UDC RAM)
User-Defined Character This register is used to provide the address to the UDC RAM when the user is writing or
Address Register reading a custom character.
(UDC Address Register)
Control Word Register This register allows the user to adjust the display brightness, flash individual
characters, blink, self test, or clear the display.
CE
FL A
4
A
3
A
2
A
1
A
0
RST WR RD
CHARACTER
ADDRESS
SYMBOL IS ACCESSED IN LOCATION
SPECIFIED BY THE CHARACTER ADDRESS ABOVE
01
00
01
1
111
0
11
UNDEFINED
CONTROL SIGNALS
CHARACTER RAM ADDRESS
CHARACTER RAM DATA FORMAT
WRITE TO DISPLAY
READ FROM DISPLAY
UNDEFINED
000 = LEFT MOST
111 = RIGHT MOST
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0 128 ASCII CODE
X X X UDC CODE1
DISPLAY
0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE
DIG
0
DIG
1
DIG
2
DIG
3
DIG
4
DIG
5
DIG
6
DIG
7
001 010 011 100 101 110 111000
12
UDC RAM and UDC Address Register
Figure 3 shows the logic levels
needed to access the UDC RAM
and the UDC Address Register.
The UDC Address Register is eight
bits wide. The lower four bits (D0-
D3) are used to select one of the
16 UDC locations. The upper four
bits (D4-D7) are not used. Once
the UDC address has been stored
in the UDC Address Register, the
UDC RAM can be accessed.
To completely specify a 5 x 7
character requires eight write
cycles. One cycle is used to store
the UDC RAM address in the UDC
Address Register. Seven cycles
are used to store dot data in the
UDC RAM. Data is entered by
rows. One cycle is needed to
access each row. Figure 4 shows
the organization of a UDC
character assuming the symbol to
be stored is an “F.” A0-A2 are used
to select the row to be accessed
and D0-D4 are used to transmit
the row dot data. The upper three
bits (D5-D7) are ignored. D0 (least
significant bit) corresponds to the
right most column of the 5 x 7
matrix and D4 (most significant
bit) corresponds to the left most
column of the 5 x 7 matrix.
Flash RAM
Figure 5 shows the logic levels
needed to access the Flash RAM.
The Flash RAM has one bit
associated with each location of
the Character RAM. The Flash
input is used to select the Flash
RAM. Address lines A3-A4 are
ignored. Address lines A0-A2 are
used to select the location in the
Flash RAM to store the attribute.
D0 is used to store or remove the
flash attribute. D0 = “1” stores the
attribute and D0 = “0” removes the
attribute.
When the attribute is enabled
through bit 3 of the Control Word
and a "1" is stored in the Flash
RAM, the corresponding character
will flash at approximately 2 Hz.
The actual rate is dependent on
the clock frequency. For an
external clock the flash rate can
be calculated by dividing the clock
frequency by 28,672.
Figure 4. Data to load “F” into the UDC RAM.
Figure 3. Logic levels to access a UDC character.
CE
FL A
4
A
3
A
2
A
1
A
0
RST WR RD
01
00
01
1
001XXX
0
11
UNDEFINED
CONTROL SIGNALS
UDC ADDRESS REGISTER ADDRESS
UDC ADDRESS REGISTER DATA FORMAT
WRITE TO DISPLAY
READ FROM DISPLAY
UNDEFINED
000 = ROW 1
110 = ROW 7
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
X UDC CODE
XXX
FL A
4
A
3
A
2
A
1
A
0
011 ROW SELECT
UDC RAM ADDRESS
UDC RAM C C
DATA FORMAT O O
L L
1 5
0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
X DOT DATA
XX
CERST WR RD
01
00
01
10
11
UNDEFINED
CONTROL SIGNALS
WRITE TO DISPLAY
READ FROM DISPLAY
UNDEFINED
C C C C C
O O O O O
L L L L L
1 2 3 4 5
D
4
D
3
D
2
D
1
D
0
UDC CHARACTER HEX CODE
1 1 1 1 1 ROW 1 • • • • • 1F
1 0 0 0 0 ROW 2 • 10
1 0 0 0 0 ROW 3 • 10
1 1 1 1 0 ROW 4 • • • • 1D
1 0 0 0 0 ROW 5 • 10
1 0 0 0 0 ROW 6 • 10
1 0 0 0 0 ROW 7 • 10
IGNORED
0 = LOGIC 0; 1 = LOGIC 1; * = ILLUMINATED LED
13
Control Word Register
Figure 6 shows how to access the
Control Word Register. This is an
eight bit register which performs
five functions. They are Bright-
ness control, Flash RAM control,
Blinking, Self Test and Clear.
Each function is independent of
the others. However, all bits are
updated during each Control
Word write cycle.
Brightness (Bits 0-2)
Bits 0-2 of the Control Word
adjust the brightness of the
display. Bits 0-2 are interpreted
as a three bit binary code with
code (000) corresponding to
maximum brightness and code
(111) corresponding to a blanked
display. In addition to varying the
display brightness, bits 0-2 also
vary the average value of IDD. IDD
can be calculated at any bright-
ness level by multiplying the
percent bright-ness level by the
value of IDD at the 100%
brightness level. These values of
IDD are shown in Table 2.
Flash Function (Bit 3)
Bit 3 determines whether the
flashing character attribute is on
or off. When bit 3 is a “1,” the
output of the Flash RAM is
checked. If the content of a loca-
tion in the Flash RAM is a “1,” the
associated digit will flash at
approximately 2 Hz. For an
external clock, the blink rate can
be calculated by driving the clock
frequency by 28,672. If the flash
enable bit of the Control Word is a
“0,” the content of the Flash RAM
is ignored. To use this function
with multiple display systems see
the Reset section.
Blink Function (Bit 4)
Bit 4 of the Control Word is used
to synchronize blinking of all eight
digits of the display. When this bit
is a “1” all eight digits of the
display will blink at approxi-
mately 2 Hz. The actual rate is
dependent on the clock frequency.
For an external clock, the blink
rate can be calculated by dividing
the clock frequency by 28,672.
This function will override the
Flash function when it is active.
To use this function with multiple
display systems see the Reset
section.
Figure 5. Logic levels to access the flash RAM.
Figure 6. Logic levels to access the control word register.
Table 2. Current Requirements at Different Brightness Levels
Symbol D2D1D0% Brightness 25°C Typ. Units
IDD (V) 0 0 0 100 200 mA
00180 160 mA
01053 106 mA
01140 80 mA
10027 54 mA
10120 40 mA
11013 26 mA
CE
FL A4A3A2A1A0
RST WR RD
01
00
01
1
XX0
0
11
UNDEFINED
REMOVE FLASH AT
SPECIFIED DIGIT LOCATION
STORE FLASH AT
SPECIFIED DIGIT LOCATION
CONTROL SIGNALS
FLASH RAM ADDRESS
FLASH RAM DATA FORMAT
0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE
WRITE TO DISPLAY
READ FROM DISPLAY
UNDEFINED
D7D6D5D4D3D2D1D0
XXXXXXX0
1
CHARACTER
ADDRESS 000 = LEFT MOST
111 = RIGHT MOST
CE
FL A
4
A
3
A
2
A
1
A
0
RST WR RD
01
00
01
1
10XXX1
0
11
UNDEFINED
CONTROL SIGNALS
CONTROL WORD ADDRESS
CONTROL WORD DATA FORMAT
0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE
0 DISABLE FLASH
1 ENABLE FLASH
BRIGHTNESS
CONTROL
LEVELS
0 DISABLE BLINKING
1 ENABLE BLINKING
0 NORMAL OPERATION
1 CLEAR FLASH AND CHARACTER RAMS
0 X NORMAL OPERATION; X IS IGNORED
1 X START SELF TEST; RESULT GIVEN IN X
X = 0 FAILED X = 1 PASSED
WRITE TO DISPLAY
READ FROM DISPLAY
UNDEFINED
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
CSSBLFB
000100%
00180%
01053%
01140%
10027%
10120%
11013%
1110%
BB
14
Self Test Function (Bits 5, 6)
Bit 6 of the Control Word Register
is used to initiate the self test
function. Results of the internal
self test are stored in bit 5 of the
Control Word. Bit 5 is a read only
bit where bit 5 = “1” indicates a
passed self test and bit 5 = “0”
indicates a failed self test.
Setting bit 6 to a logic 1 will start
the self test function. The built-in
self test function of the IC consists
of two internal routines which
exercises major portions of the IC
and illuminates all of the LEDs.
The first routine cycles the ASCII
decoder ROM through all states
and performs a checksum on the
output. If the checksum agrees
with the correct value, bit 5 is set
to “1.” The second routine
provides a visual test of the LEDs
using the drive circuitry. This is
accomplished by writing
checkered and inverse checkered
patterns to the display. Each
pattern is displayed for approxi-
mately 2 seconds.
During the self test function the
display must not be accessed. The
time needed to execute the self
test function is calculated by
multiplying the clock period by
262,144. For example, assume a
clock frequency of 58 KHz, then
the time to execute the self test
function frequency is equal to
(262,144/58,000) = 4.5 second
duration.
At the end of the self test function,
the Character RAM is loaded with
blanks, the Control Word Register
is set to zeros except for bit 5, and
the Flash RAM is cleared and the
UDC Address Register is set to all
ones.
Clear Function (Bit 7)
Bit 7 of the Control Word will
clear the Character RAM and the
Flash RAM. Setting bit 7 to a "1"
will start the clear function. Three
clock cycles (110 µs min. using the
internal refresh clock) are
required to complete the clear
function. The display must not be
accessed while the display is being
cleared. When the clear function
has been completed, bit 7 will be
reset to a “0.” The ASCII character
code for a space (20H) will be
loaded into the Character RAM to
blank the display and the Flash
RAM will be loaded with “0”s. The
UDC RAM, UDC Address Register,
and the remainder of the Control
Word are unaffected.
Display Reset
Figure 7 shows the logic levels
needed to Reset the display. The
display should be Reset on Power-
up. The external Reset clears the
Character RAM, Flash RAM,
Control Word and resets the
internal counters. After the rising
edge of the Reset signal, three
clock cycles (110 µs min. using the
internal refresh clock) are
required to complete the reset
sequence. The display must not be
accessed while the display is being
reset. The ASCII Character code
for a space (20H) will be loaded
into the Character RAM to blank
the display. The Flash RAM and
Control Word Register are loaded
with all "0"s. The UDC RAM and
UDC Address Register are un-
affected. All displays which
operate with the same clock
source must be simultaneously
reset to synchronize the Flashing
and Blinking functions.
Mechanical and Electrical
Considerations
The HDSP-213x/-2179 is a 32 pin
dual-in-line package with 24
external pins, which can be
stacked horizontally and verti-
cally to create arrays of any size.
The HDSP-213x/-2179 is designed
to operate continuously from
-55°C to +85°C with a maximum
of 20 dots ON per character.
Illuminating all thirty-five dots at
full brightness is not
recommended.
The HDSP-213x/-2179 is
assembled by die attaching and
wire bonding 280 LED chips and a
CMOS IC to a ceramic sub-strate.
A glass window is placed over the
ceramic substrate creating an air
gap over the LED wire bonds. A
second glass window creates an
air gap over the CMOS IC. This
package construction makes the
display highly tolerant to temper-
ature cycling and allows wave
soldering and visual inspection of
the IC.
The inputs to the CMOS IC are
protected against static discharge
and input current latchup. How-
ever, for best results standard
CMOS handling precautions
should be used. Prior to use, the
HDSP-213X should be stored in
Figure 7. Logic levels to reset the display. Figure 8. Maximum power dissipation vs.
ambient temperature derating based on
TJMAX = 125°C.
CERST WR RD
0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE
NOTE:
IF RST, CE, AND WR ARE LOW, UNKNOWN
DATA MAY BE WRITTEN INTO THE DISPLAY.
FL
01XXXXX
A
4
-A
0
D
7
-D
0
PD – POWER DISSIPATION – W
25
0
TA – AMBIENT TEMPERATURE – °C
95
35 45 85 105
4.0
3.0
1.0
65 7555
2.0 RqJ-A = 30°C/W
15
Soldering and Post Solder
Cleaning Instructions for the
HDSP-213x/-2179
The HDSP-213x/-2179 may be
hand soldered or wave soldered
with lead-free solder. When hand
soldering it is recommended that
an electronically temperature con-
trolled and securely grounded
soldering iron be used. For best
results, the iron tip temperature
should be set at 315°C (600°F).
For wave soldering, a rosin-based
RMA flux can be used. The solder
wave temperature should be set at
245°C ± 5°C (473°F ± 9°F), and
dwell in the wave should be set
between 11/2 to 3 seconds for
optimum soldering. The preheat
temperature should not exceed
105°C (221°F) as measured on
the solder side of the PC board.
Proper handling is imperative to
avoid excessive thermal stresses
to component when heated.
Therefore, the solder PCB must be
allowed to cool to room
temperature, 25°C, before
handling.
For further information on
soldering and post solder
cleaning, see Application Note
1027, Soldering LED Components.
antistatic packages or conductive
material. During assembly, a
grounded conductive work area
should be used, and assembly
personnel should wear conductive
wrist straps. Lab coats made of
synthetic material should be
avoided since they are prone to
static charge buildup. Input
current latchup is caused when
the CMOS inputs are subjected to
either a voltage below ground
(VIN < ground) or to a voltage
higher than VDD (VIN > VDD) and
when a high current is forced into
the input. To prevent input cur-
rent latchup and ESD damage,
unused inputs should be con-
nected either to ground or to VDD.
Voltages should not be applied to
the inputs until VDD has been
applied to the display. Transient
input voltages should be eliminated.
Thermal Considerations
The HDSP-213x/-2179 has been
designed to provide a low thermal
resistance path from the CMOS IC
to the 24 package pins. This heat is
then typically conducted through
the traces of the user’s printed
circuit board to free air. For most
applications no additional
heatsinking is required.
The maximum operating IC
junction temperature is 150°C.
The maximum IC junction tem-
perature can be calculated using
the following equation:
TJ(IC) MAX = TA
+ (PDMAX) (RqJ-PIN + RqPIN-A)
Where
PDMAX = (VDDMAX) (IDDMAX)
IDDMAX = 370 mA with 20 dots
ON in eight character locations at
25°C ambient. This value is from
the Electrical Characteristics
table.
PDMAX = (5.5 V) (0.370 A)
= 2.04 W
Ground Connections
Two ground pins are provided to
keep the internal IC logic ground
clean. The designer can, when
necessary, route the analog
ground for the LED drivers sep-
arately from the logic ground until
an appropriate ground plane is
available. On long interconnects
between the display and the host
system, the designer can keep
voltage drops on the analog
ground from affecting the display
logic levels by isolating the two
grounds.
The logic ground should be con-
nected to the same ground poten-
tial as the logic interface circuitry.
The analog ground and the logic
ground should be connected at a
common ground which can
withstand the current introduced
by the switching LED drivers.
When separate ground connec-
tions are used, the analog ground
can vary from -0.3 V to +0.3 V
with respect to the logic ground.
Voltage below -0.3 V can cause all
dots to be on. Voltage above +0.3
V can cause dimming and dot
mismatch.
ESD Susceptibility
These displays have ESD sus-
ceptibility ratings of CLASS 3 per
DOD-STD-1686 and CLASS B per
MIL-STD-883C.
LAMINAR W A VE BOTTOM SIDE
OF PC BOARD
HOT AIR KNIFE
TURBULENT W A VE
FLUXING
PREHEAT
01020
30
50
100
150
200
250
30 40 50
TIME – SECONDS
TEMPERATURE – °C
60 70 80 90 100
TOP SIDE OF
PC BOARD
CONVEYOR SPEED = 1.83 M/MIN (6 FT/MIN)
PREHEAT SETTING = 150°C (100°C PCB)
SOLDER WAVE TEMPERATURE = 245°C
AIR KNIFE AIR TEMPERATURE = 390°C
AIR KNIFE DISTANCE = 1.91 mm (0.25 IN.)
AIR KNIFE ANGLE = 40°
NOTE: ALLOW FOR BOARDS TO BE
SUFFICIENTLY COOLED BEFORE
EXERTING MECHANICAL FORCE.
Figure 9. Recommended wave soldering profile for lead-free Smart Display.
Intensity Bin Limits
Intensity Range (mcd)
Bin Min. Max.
G 2.50 4.00
H 3.41 6.01
I 5.12 9.01
J 7.68 13.52
K 11.52 20.28
Note: Test conditions as specified in Optical
Characteristic table.
Color Bin Limits Color Range (nm)
Color Bin Min. Max.
Green 1 576.0 580.0
2 573.0 577.0
3 570.0 574.0
4 567.0 571.5
Yellow 3 581.5 585.0
4 584.0 587.5
5 586.5 590.0
6 589.0 592.5
Note: Test conditions as specified in Optical
Characteristic table.
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5989-3182EN
AV02-0190EN March 6, 2007
Contrast Enhancement
When used with the proper con-
trast enhancement filters, the
HCMS-213x/-2179 series displays
are readable daylight ambients.
Refer to Application Note 1029
Luminous Contrast and Sunlight
Readability of the HDSP-235x
Series Alphanumeric Displays
for Military Applications for
information on contrast en-
hancement for daylight ambients.
Refer to Application Note 1015
Contrast Enhancement Techniques
for LED Displays for information
on contrast enhancement in
moderate ambients.
Night Vision Lighting
When used with the proper NVG/
DV filters, the HDSP-2131, HDSP-
2179 and HDSP-2133 may be used
in night vision lighting applica-
tions. The HDSP-2131 (yellow),
HDSP-2179 (orange) displays are
used as master caution and
warning indicators. The HDSP-
2133 (high per-formance green)
displays are used for general
instrumenta-tion. For a list of
NVG/DV filters and a discussion
on night vision lighting technol-
ogy, refer to Application Note
1030 LED Displays and Indicators
and Night Vision Imaging System
Lighting. An external dimming
circuit must be used to dim these
displays to night vision lighting
levels to meet NVIS radiance
requirements. Refer to AN 1039
Dimming HDSP-213x Displays to
Meet Night Vision Lighting Levels.
