MicROcHIP 93C56A/B 2K 5.0V Automotive Temperature Microwire Serial EEPROM FEATURES Single supply 5.0V operation Low power CMOS technology - 1mMA active current (typical) - 1A standby current (maximum) 256 x 8 bit organization (93C56A) * 128 x 16 bit organization (98C56B) Self-timed ERASE and WRITE cycles (including auto-erase) Automatic ERAL before WRAL Power on/off data protection circuitry Industry standard 3-wire serial interface Device status signal during ERASE/WRITE cycles Sequential READ function 1,000,000 E/W cycles guaranteed Data retention > 200 years 8-pin PDIP and SOIC packages Available for the following temperature ranges: '- Automotive (E): -40C to +125C DESCRIPTION The Microchip Technology Inc. 93C56A/B is a 2K-bit, low-voitage serial Electrically Erasable PROM. The device memory is configured as 256 x 8 bits (93C56A) or 128 x 16 bits (93C56B). Advanced CMOS technol- ogy makes this device ideal for low-power, nonvolatile memory applications. The 93C56A/B is available in standard 8-pin DIP and surface mount SOIC Packages. This device is only recommeded for 5V automotive temperature applications. For all commercial and industrial applications, the 93LC56A/B is recom- mended. Microwire is a registered trademark of National Semiconductor. 1998 Microchip Technology inc. PACKAGE TYPE PDIP = esc}; Y atl cuK (2 8 7 CINe a ois S 6 [Ine po [4 5{lVss soic = ost gS BE avce a exc? 9 7 Tone a orcs 5 6 Tne poc_|4 5 [vss BLOCK DIAGRAM | MEMORY {vJADDRESS ARRAY IDECODER! } ADDRESS| COUNTER! DATA REGISTER a CS e| MEMORY DECODE LOGIC CLOCK CLK GENERATOR DS21206C-page 4-35 a a i. 5 oe93C56A/B 1.0 ELECTRICAL CHARACTERISTICS 1.1. Maximum Ratings* Vec sesvsanseaenee TOV. All inputs and outputs witt. Vss. vou -0.6V to Veo +1.0V Storage temperature .....cccsccesesesscveressessscesseses 65C to +150C Ambient temp. with power applied................. 65C to +125C Soldering temperature of leads (10 seconds) .........0... +300C ESD protection on alll Pins............scccccsscsessssscessessssssceseose 4kV Notice: Stresses above those listed under Maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the devica.at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri- ods may affect device reliability. TABLE 1-2: TABLE 1-1: PIN FUNCTION TABLE Name Function cs Chip Select CLK Serial Data Clock . Dl Serial Data Input DO. Serial Data Output Vss Ground NC No Connect Vec Power Supply DC AND AC ELECTRICAL CHARACTERISTICS All parameters apply over the |Automotive (E)Vcc = +4.5V to +5.5VTamb = -40C to +125C specified operating ranges unless otherwise noted Parameter Symbol Min. Max. Unks Conditions High level input voltage Vin 2.0 Voc +1 Vv (Note 2) Low level input voltage Vit 0.3 0.8 Vv Low level output voltage VOL _ 0.4 Vv IOL = 2.1 MA; Vcc = 4.5V High level output voltage VOH 2.4 ~ v IOH = -400 pA; Voc = 4,5V Input leakage current Iu 10 10 pA VIN = Vss to Vcc Output leakage current iLo -10 10 pA VouT = Vss to Vcc (areusiae) oncom] | 7 | pr [yWonoviois 183 Operating current Ic write 1s mA Icc read _- 1 mA Standby current Iccs _ 1 pA CS = Vss; DI = Vss Clock frequency FCLiK = 2 MHz Clock high time TCKH 250 _ ns Clock low time TOK 250 _- ns Chip select setup time Tess 50 _ ns Relative to CLK. Chip select hold time TcsH 0 - ns Relative to CLK Chip select low time TCst 250 => ns Data input setup time Tors 100 ~ ns Relative to CLK Data input hold time TDIH 100 _ ns Relative to CLK Data output delay time TPO _ 400 ns CL = 100 pF Data output disable time Tez _ 100 ns CL = 100 pF (Note 2) Status valid time Tsv _ 500 ns Ci = 100 pF Twe > 2 ms ERASE/WRITE mode Program cycle time Tec ~_ 6 ms ERAL mode TWL _- 18 ms WRAL mode Endurance _ 1M _ cycles |25C, Vcc = 5.0V, Block Mode (Note 3) Note 1: This parameter is tested at Tamb = 25C and FCLK = 1 MHz. 2: This parameter is periodically sampled and not 100% tested. 3: This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which may be obtained on our website. DS21206C-page 4-36 1998 Microchip Technology inc.93C56A/B 2.0 PIN DESCRIPTION 2.1 Chip Select (CS) A high level selects the device. A low level deselects the device and forces it into standby mode. However, a programming cycle which is already in progress will be completed, regardless of the CS input signal. If CS is brought low during a program cycle, the device will go into standby mode as soon as the programming cycle is completed. CS must be tow for 250 ns minimum (TCSL) between consecutive instructions. If CS is low, the internal con- trol logic is held in a RESET status. 2.2 rial Clock The Serial Clock is used to synchronize the communi- cation between a master device and the 93C56A/B. Opcode, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TcKH) and clock low time (TcxL). This gives the controlling master freedom in preparing opcode, address, and data. CLK is a Don't Care if CS is low (device deselected). {f CS is high, but the START condition has not been detected, any number of clock cycles can be received by the device without changing its status (ie., waiting for a START condition). CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle. After detecting a START condition, the specified num- ber of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (Table 2-1 and Table 2-2). CLK and DI then become don't care inputs waiting for a new START condition to be detected. 2.3 Data In (DI) Data In is used to clock in a START bit, opcode, address, and data synchronously with the CLK input. 2.4 Data Out (DQ) Data Out is used in the READ mode to output data syn- chronously with the CLK input (Trp after the positive edge of CLK). This pin also provides READY/BUSY status informa- tion during ERASE and WRITE cycles. READY/BUSY Status information is available on the DO pin if CS is brought high after being low for minimum chip select low time (TcsL) and an ERASE or WRITE operation has been initiated. The status signal is not available on DO, if CS is held tow during the entire ERASE or WRITE cycle. in this case, DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, the data line will be high to indicate the device is ready. TABLE 2-1: INSTRUCTION SET FOR 93C56A Instruction | SB | Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 1 X A7 AB AS Ad AB A2 Al AO _ (RDY/BSY) 12 ERAL 1 00 1 0 X X X xX xX xX xX (RDY/BSY) 12 EWwbds 1 00 Oo Oo X X X X X x xX _ HIGH-Z 12 EWEN 1 00 1 31 X X X xX X xX xX _ HIGH-Z 12 READ 1 10 X A7 AB AS A4 AB AZ AL AD _ D7-00 20 WRITE 1 01 X A7 AB AS Ad A3 A2 A1 AO| D7-DO | (RDY/BSY) 20 WRAL 1 00 o 1 X X X X X X X| D7-DO | (RDY/BSY) 20 TABLE 2-2: INSTRUCTION SET FOR 93C56B Instruction | SB | Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 11 X AG AS A4 AB AZ AL AO = (RDY/BSY) 11 ERAL 1 00 1 0 -% X X xX x xX _ (RDY/BSY) 11 EWDS 1 00 0 0 xX xX X xX xX xX _ HIGH-Z 11 EWEN 1 00 1 #14 X X X xX X X - HIGH-Z 1 READ 1 10 X AGB AS AS AB AZ AI AO _ Di5- DO 27 WRITE 1 01 X AB AS Ad AB A2 A1 AO] DI5-DO| (RDY/BSY) 27 WRAL 1 00 o 1 X X X X X xX |015-DO] (RDOYBSY) 27 ry 1998 Microchip Technology inc. DS21206C-page 4-37 rd ce a es ie} Pe a93C56A/B == 3.0 FUNCTIONAL DESCRIPTION Instructions, addresses, and write data are clocked into the Df pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/BUSY status during a programming operation. The READY/BUSY status can be verified during an ERASEMWRITE operation by polling the DO pin; DO low indicates that programming is stil! in Progress, while DO high indicates the device is ready. The DO wilt enter the HIGH-Z state on the falling edge of the CS. 3.1 START Condition The START bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device oper- ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL, and WRAL). As soon as CS is high, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcode, address and data bits for any particular instruction is clocked in. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new START concition is detected. FIGURE 3-1: _ SYNCHRONOUS DATA TIMING 3.2 ita IN It is possible to connect the Data In (Dl) and Data Out (DO) pins together. However, with this configuration, if AO is a logic-high level, it is possible for a bus conflict to occur during the dummy zero that precedes the READ operation. Under such a condition, the voltage level seen at DO is undefined and will depend upon the relative impedances of DO and the signal source driv- ing AO. The higher the current sourcing capability of AO, the higher the voltage at the DO pin. 3.3 Data Protection During power-up, all programming modes of operation are inhibited until Vec has reached a level greater than 3.8V. During power-down, the source data protection Circuitry acts to inhibit all programming modes when Vcc has fallen below 3.8V at nominal conditions. The ERASE/WRITE Disable (EWDS) and ERASE WRTE Enable (EWEN) commands give additional pro- tection against accidentally programming during nor- mal operation. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed. cs ViK Vit VI CLK VIL Vir DI VIL DO VOH (READ) DO VoH (PROGRAM) VoL Note: AC Test Conditions: ViL = 0.4V, VIH = 2.4V, STATUS VALID EEE DS21206C-page 4-38 1998 Microchip Technology inc.93C56A/B 3.4 ERASE The ERASE instruction forces all data bits of the spec- ified address to the logical 1 state. This cycle begins on the rising clock edge of the last address bit. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (Tcst). DO at logical 0 indicates that program- ming is still in progress. DO at logical 1 indicates that the register at the specified address has been erased and the device is ready for another instruction. FIGURE 3-2: ERASE TIMING 3.5 Erase All (ERAL) The ERAL instruction will erase the entire memory array to the logical 1 state. The ERAL cycle is identi- cal to the ERASE cycle, except for the different opcode. The ERAL cycle is completely self-timed and com- mences at the rising clock edge of the last address bit. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle. The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (TcSL) and before the entire ERAL cycle is com- plete. CHECK STATUS M Tsv Tez BUSY READY HIGH-Z Twe FIGURE 3-3: ERAL TIMING HIGH-Z an a Lt | Tec 1998 Microchip Technology Inc. 0S21206C-page 4-3993C56A/B 3.6 ERASE/WRITE Disable and Enable {EWDS/EWEN) The device powers up in the ERASE/WRITE Disable (EWDS) state. All programming modes must be pre- ceded by an ERASE/WRITE Enable (EWEN) instruc- tion. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruc- tion is executed or Vcc is removed from the device. To protect against accidental data disturbance, the EWDS instruction can be used to disable all ERASE/WRITE functions and should follow. all programming opera- tions. Execution of a READ instruction is independent of both the EWEN and EWDS instructions. FIGURE 3-4: READTIMING 3.7 READ The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 8-bit (93C56A) or 16-bit (93C56B) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (Te). Sequential read is possible when CS is held high. The memory data will automati- cally cycle to the next register and output sequentially. cs / Do HIGH-Z a Tb FIGURE 3-5: EWDS TIMING cs / DI 1 0 0 0 L, Teste, | FIGURE 3-6: EWEN TIMING ol L Tesx , | DS21206C-page 4-40 1998 Microchip Technology Inc.93C56A/B 3.8 WRITE The WRITE instruction is followed by 8-bits (93C56A) 16-bits (98C56B) of data which are written into the specified address. After the last data bit is clocked into the Di pin, the self-timed auto-erase and programming cycle begins. The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is com- plete. DO at logical 0 indicates that programming is Still in progress. DO at logical 1 indicates that the reg- ister at the specified address has been written with the data specified and the device is ready for another instruction. FIGURE 3-7: WRITE TIMING 3.9 Write All (WRAL) The Write All (WRAL) instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and com- mences at the rising clock edge of the last data bit. Clocking of the CLK pin is not necessary after the device has entered the WRAL cycle. The WRAL com- mand does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (Test). Ren] sn cs / HIGH-Z ah an hand S eo PLU La a A a sy + Testy RON ae Tsv Tez BUSY READY HIGH-Z Twe FIGURE 3-8: WRAL TIMING CSL. HIGH-Z cc 1998 Microchip Technology Inc. Ds2t 206C-page 4-4193C56A/B 93C56A/B PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. 93C56A/B IP P = Plastic DIP (300 mil Body), 8-lead LL Package: ( y) SN = Plastic SOIC (150 mil Body), 8-lead Temperature E = -40C to +125C Range: 93C56A 2K Microwire Serial EEPROM (x8) Device: 93C56AT 2K Microwire Serial EEPROM (x8) Tape and Reel . 93C56B 2K Microwire Serial EEPROM (x16) 93C56BT 2K Microwire Serial EEPROM (x16) Tape and Reel Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip Worldwide Web Site (www.microchip.com) DS21206C-page 4-42 1998 Microchip Technology Inc.