1K/4K/16K x36 Unidirectional Synchronous
FIFO with Bus Matching
CY7C43643
CY7C43663
CY7C43683
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06021 Rev. *B Revised December 26, 2002
Features
• High-speed, low-power, Unidirectional, First-in,
First-out (FIFO) me mories w/bus matching capa bilities
• 1Kx36 (CY7C43643)
• 4Kx36 (CY7C43663)
• 16Kx36 (CY7C43683)
• 0.35-micron CMOS for optimum speed/power
• High-spee d 133-MHz op eration (7.5 ns read/write cycle
times)
• Low power
—ICC = 100 mA
—ISB = 10 mA
• Fully asynchronous and simultaneous read and write
operation permitt ed
• Mailbox bypass register for each FIFO
• Parallel and Serial Programmable Almost Full and
Almost Em pty flags
• Retransmit function
• Standard or FWFT mode user selectable
• Partial Reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Easily expandable in width and depth
Table 1.
Logic Block Diagram
Port A
Control
Logic Port B
Control
Logic
Mail1
Register
Input
Register
Output
Register
Write
Pointer Read
Pointer
Status
Flag Logic
Programmable
Flag Offset Timing
Mode
1K/4K/16K
Dual Ported
Memory
Mail2
Register
FIFO,
Mail1
CLKA
CSA
W/RA
ENA
MBA
RT
MRS1
PRS
FF/IR
AF
SPM
FS0/SD
FS1/SEN
A0–35
MBF2
BE/FWFT
B0–35
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
EF/OR
AE
MBF1
Mail2
Reset
Logic
Bus Matching
36
36
MRS2
Registers
x36
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 2 of 29
Pin Configuration
Selection Guide
CY7C43643/63/83
–7CY7C43643/63/83
–10 CY7C43643/63/83
–15 Unit
Maximum Frequency 133 100 66.7 MHz
Maximum Access Time 6 8 10 ns
Minimum Cycle Time 7.5 10 15 ns
Minimum Data or Enable Set-up 3 4 5 ns
Minimum Data or Enable Hold 0 0 0 ns
Maximum Flag Delay 6 8 8 ns
Active Power Supply
Current (ICC1)Commercial 100 100 100 mA
Industrial 100
CY7C43643 CY7C43663 CY7C43683
Density 1K x 36 4K x 36 16K x 36
Package 128 TQFP 128 TQFP 128 TQFP
CY7C43643
CY7C43663
CY7C43683
TQFP
Top View
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
FS0/SD
MRS2
FS1/SEN
GND
GND
MRS1
MBA
MBF2
NC
AF
VCC
PRS
FF/IR
CSA
ENB
W/RB
CSB
GND
NC
EF/OR
NC
AE
VCC
MBF1
MBB
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
B30
B26
B27
B28
B29
B31
GND
GND
B32
B33
B34
B35
VCC
VCC
CLKB
GND
SIZE
B16
B17
B18
B19
B20
B21
B22
B23
GND
BM
B24
B25
RT
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A2
B0
GND
A0
A1
VCC
SPM
A3
A4
A5
GND
A6
A7
A8
A9
B9
B8
B7
VCC
B6
GND
B5
B4
B3
B2
B1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
VCC
A29
GND
A30
A31
A32
A34
A35
GND
CLKA
ENA
W/RA
A12
A20
GND
A18
A19
A21
VCC
A22
GND
BE/FWFT
A23
A24
A25
A26
A27
A28
A33
72
71
70
69
68
67
66
65
B12
B10
B11
GND
B13
B14
B15
VCC
30
31
32
33
34
35
36
37
38
VCC
A10
A11
GND
A13
A14
A15
A16
A17
NC
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 3 of 29
Pin Definitions
Signal Name Description I/O Function
A0–35 Port A Data I36-bit unidirectional data port for side A.
AE Almost Empty
Flag (Por t B) OProgrammable Almost Empty flag synchronized to CLKA. It is LOW when the
number o f w ord s in the FIFO2 is le ss th an or equal to the value in th e Al mo st Emp ty A
offset register, X.[1]
AF Almost Full Flag OProgrammable Almost Full flag synchronized to CLKA. It is L OW when the number
of empty locations in the FIFO is less than or equal to the value in the Almost Full A
offset register, Y.[1]
B0–35 Port B Data O36-bit unidirectional data port for side B.
BE/FWFT Big
Endian/First-Wor
d Fall-Through
Select
IThis is a dual-purpos e pin. During M aster Reset, a HIGH on BE will sele ct Big Endi an
operation . In this case, de pending on the bus size, th e most sig nificant byte or word on
Port A is transferre d to Po rt B firs t. A LO W on BE will s ele ct L ittle Endian operati on. In
this case , the leas t significa nt byte or word on Port A is transferred to Port B first. After
Master Rese t, t his p in s elect s the ti ming mode. A H IGH on FW FT selec ts CY S t and ard
Mode, a LOW select s First-Word Fall-Throug h Mode. Once the timi ng mode has been
selected, the level on FWFT must be static throughout device operation.
BM Bus Match
Select (Port B) IA HIGH on this pin e nables e ither byte or word bus width on Port B, dependin g on
the sta t e of SIZE. A LO W sele cts long-word op era tion . BM works with SI ZE and BE to
select the bus size and endi an arrang em ent for Port B. The lev el of BM must be s t ati c
throughout device operation.
CLKA Port A Clock ICLKA is a continuous clock that synchronizes all data transfers through Port A
and can be as ynchrono us or coinc ident to CL KB. FF/IR and AF are all synchronized to
the LOW-to-HIGH transition of CLKA.
CLKB Port B Clock ICLKB is a continuous clock that synchronizes all data transfers through Port B
and can be asynchrono us or c oincident t o CLKA. FB/IR, EF/OR, AF, and AE are all
synchronized to the LOW-to-HIGH transition of CLKB.
CSA Port A Chip
Select ICSA must be LOW to enable a LOW-to HIGH tran sition of CLKA to read or write on
Port A. The A0–35 outputs are in the high-impedance state when CSA is HIGH.
CSB Port B Chip
Select ICSB must be LOW to enable a LOW-to HIGH tran sition of CLKB to read or write on
Port B. The B0–35 outputs are in the high-impedance state when CSB is HIGH.
EF/OR Empty/Output
Ready Flag
(Port B)
OThis is a dual-fun ction pin. In the C Y S tand ard Mode, the EF fun ction is se lected. EF
indicates whether or not the FIFO memory is empty . In the FWFT mode, the OR function
is selected. OR indicates the presence of val id data on A0–35 outputs, available for
reading. EF/OR is synchronized to the LOW-to-HIGH transition of CLKB. [2]
ENA Port A Enable IENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write
data on Port A.
ENB Port B Enable IENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write
data on Port B.
FF/IR Port B Full/Inpu t
Ready Flag OThis is a dual- functi on pin. I n the CY S t and ard Mo de, the FF func tion is select ed. FF
indicate s wheth er or not the FIFO mem ory is full. In the FWFT mo de, the IR fu nction is
selected. IR indicates whether or not there is space available for writing to the FIFO
memory. FF/IR is synchronized to the LOW-to-HIGH transition of CLKA.
Notes:
1. When reading from the FIFO under FWFT , ORA/ORB signal should be included in the read logic to ensure proper operation. T o read without gating the boundary
flag (e.g., in bursts), use CY standard mode.
2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to three clock cycles for flag assertion an d dea s ser t io n. R efe r t o
“Designing with CY7C436xx Synchronous FIFO” application notes for more details on flag uncertainties.
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 4 of 29
FS1/SEN Flag Offset
Select 1/Serial
Enable
IFS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register
programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select
the flag offset programming method. Three offset register programming methods are
available: automatically load one of three preset values (8, 16, or 64), parallel load from
Port A, and serial load. When serial load is selected for flag offset register programming,
FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA.
When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into
the X and Y regist ers. The nu mber o f bit wr ites req uired t o pr ogram t he of fse t regis ters
is 20 for the CY 7C4364 3, 24 for the CY7C43 663, and 28 for the C Y7C4368 3. The firs t
bit write stores the Y-register MSB and the last bit write stores the X-register LSB.
FS0/SD Flag Offs et
Select 0/Serial
Data
I
MBA Port A Mailbox
Select IA HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
MBB Port B Mailbox
Select IA HIGH level on MBB chooses a mailbox register for a Port B read or write operation.
When a read operation i s performe d on Port B, a H IGH leve l on MBB sel ects d ata from
the Mail1 register for output and a LOW level selects FIFO output register data for output.
Data can only be written into Mail 2 register through Port B (MBB HIGH) and not into
the FIFO memory.
MBF1 Mail1 Register
Flag OMBF1 is set LOW by a LOW -to-HIGH transition of CLKA that writ es data to the Mail1
register . Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH
by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB is HIGH.
MBF1 is set HIGH following either a Master or Partial Reset.
MBF2 Mail2 Register
Flag OMBF2 is set LOW by a LOW -to-HIGH transition of CLKB that writ es data to the Mail2
register . Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH
by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA is HIGH.
MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
MRS1 Master Reset IA LOW on this pin initializes the FIFO read and write pointers to the first location
of memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1
selects the programming method (serial or parallel) and one of three programmable flag
default offsets. It also configures Port B for bus size and endian arrangement. Four
LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while MRS1 is LOW.
MRS2 Master Reset IA LOW on this pin initializes the Mail2 register.
PRS Par tial Re set IA LOW on this pin initializes the FIFO read and write pointers to the first location
of memory and sets the Port B output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
RT Retransmit IA LOW strobe on this pin will retransmit data on the FIFO. This is achieved by
bringing the read po inte r bac k to loc ation zero. The user will sti ll need to pe rform read
operation to retr ansmit t he dat a. Retransm it funct ion appli es to CY sta ndard mod e only.
SIZE Bus Size Select IA HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW
on this pin when BM is HIGH sel ec t s word (18-b it) bus size. SIZE works with BM and
BE to selec t the bus si ze and endia n arrangement for P ort B. The level of SIZE must be
static throughout device operation.
SPM Serial
Programming IA LOW on this pin selects serial programming of partial flag offsets. A HIGH on
this pin selects parallel programming or default offsets (8, 16, or 64).
W/RA Port A
Write/Read
Select
IA HIGH selects a write operation and a LOW selects a read operation on Port A
for a LOW-to-HIGH transition of CLKA. The A0–35 outputs are in the high-impedance
st ate when W/RA is HIGH.
W/RB Port B
Write/Read
Select
IA LOW selects a write operation and a HIGH selects a read operation on Port B
for a LOW-to-HIGH transition of CLKB. The B0–35 outputs are in the high-impedance
st ate when W/RB is LOW.
Pin Definitions (continued)
Signal Name Description I/O Function
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 5 of 29
Functional Description
The CY7C436x3 is a monolithic, high-speed, low-power,
CMOS Unidirectional Synchronous (clocked) FIFO memory
whic h supports clock frequ encies up to 133 MHz an d has read
access times as fast as 6 ns. Two independent 1K/4K/16K x
36 dual-port SRAM FIFOs on board each chip buffer data in
opposite directions. FIFO data on Port B can be output in
36-bit, 18-bit, or 9-bit formats with a choice of Big or Little
Endi an con fig urations.
The CY7C436x3 is a synchronous (clocked) FIFO, meaning
each po rt em plo ys a sy nc hro nou s i nterface. All data tran sfers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or
coinc ide nt. T he e nab les for e ac h po rt are a rran ged to pro vi de
a simple unidirectional interface between microprocessors
and/or buses with synchronous control.
Comm unicati on between ea ch port may bypas s the FIFO s via
two mailbox registers. The mailbox registers’ width matches
the sele cted Port B bus width. Each mailbox register has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
Two kinds of reset are available on the CY7C436x3: Master
Reset an d Partia l Rese t. Mas ter Rese t init ializes the rea d and
write pointers to the first location of the memory array,
config ures the FIFO for Big or Lit tle End ian byte arrang em ent
and selects serial flag programming, parallel flag
programming, or one of the three possible default flag offset
settings, 8, 16, or 64. The FIFO also has two Master Reset
pins , MRS1 and MRS2.
Partial Reset also sets the read and write pointers to the first
location of the memory. Unlike Master Reset, any settings
existing prior to Partial Reset (i.e., programming method and
parti al flag d efa ult o ffsets) are retained. Part ial R e se t is useful
since it permits flushing of the FIFO memory without changing
any co nfigura tion settin gs. The FIFO ha s it s own indepe ndent
Partial Reset pin, PRS.
The CY7C436x3 have two modes of operation: In the CY
Standard Mode, the first word written to an empty FIFO is
deposited into the memory array. A read operation is required
to access that word (along with all other words residing in
memory). In the First-Word Fall-Through Mode (FWFT), the
first lon g-word (36-b it wide) w ritten to an empt y FIFO appea rs
automatically on the outputs, no read operation required
(nev ertheless, a ccessi ng subs equent words does n ecessit ate
a form al rea d reques t). The state of the B E/FWF T pin during
FIFO operation determines the mode in use.
The FIFO has a combined Empty/Output Ready flag (EF/OR)
and a c ombin ed Full /Input Re ady fl ag (FF/IR). T he EF an d FF
functio ns are s electe d in the CY S t and ard Mod e. EF indic ates
whether the memory is full or not. Th e IR and OR functions are
selected in the First-Word Fall-Through Mode. IR indicates
whether or not the FIFO has available memory locations. OR
shows w hether the FI FO has dat a availa ble for readi ng or not.
It marks the presence of valid data on the outputs.[1]
The FI FO has a prog ram ma ble Almos t Emp ty flag (AE) and a
programmable Almost Full flag (AF). AE indicates when a
selected number of words written to FIFO memory achieve a
predetermined “almost empty state.” AF indicates when a
selected number of words written to the memory achieve a
predetermined “almost full state.”[2]
IR and AF are synchronized to the port clock that writes data
into its array. OR and AE are synchronized to the port clock
that re ads dat a fr om its array. Program mable of fset fo r AE and
AF can be loaded in parallel using Port A or in serial via the
SD input. Three default offset settings are also provided. The
AE threshold can be set at 8, 16, or 64 locations from the
empty boundary and AF threshold can be set at 8, 16, or 64
locations from the full boundary. All these choices are made
using the FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths.
The CY7C436x3 are characterized for operation from 0°C to
70°C commercial, and from –40°C to 85°C industrial. Input
ESD protection is greater than 2001V, and latch-up is
prevented by the use of guard rings.
Signal Description
Master Reset (MRS 1, MRS2)
The FIFO memory of the CY7C436x3 undergoes a complete
reset by taking its associated Master Reset (MRS1, MRS2)
input LOW for at least four Port A clock (CLKA) and four Port
B clock (CLKB) LOW-to-HIGH transitions. The Master Reset
input can switch asynchronously to the clocks. A Master Reset
initializes the internal read and write pointers and forces the
Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready
flag (EF/OR) LOW , the Almost Empty flag (AE) LOW, and the
Almost Full flag (AF) HIGH. A Master Reset also forces the
Mailbox flag (MBF1, MBF2) of the parallel mailbox register
HIGH. After a Master Reset, the FIFO’s Full/Input Ready flag
is set HIGH after two clock cycles to begin normal operation.
A Master Reset must be performed on the FIFO after power
up, before data is written to its memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latche s th e va lue of the Big End ian (BE) inp ut or
determining the order by which bytes are transferred through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Flag select (FS0, FS1) and
Serial Programming Mode (SPM) inputs for choosing the
Almost Full and Almost Empty offset programming method
(see Almost Empty and Almost Full flag offset programming
below).
Partial Reset (PRS)
Each of the two FIFO memories of the CY7C436x3 undergoes
a limited reset by taking its associated Partial Reset (PRS)
input LOW for at least four Port A clock (CLKA) and four Port
B clock (CLKB) LOW-to-HIGH transitions. The Partial Reset
input s can switc h asynchro nously to th e clocks . A Partial Rest
initializes the internal read and write pointers and forces the
Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready
flag (EF/OR) LOW , the Almost Empty flag (AE) LOW, and the
Almost Full flag (AF) HIGH. A Partial Reset also forces the
Mailbox flag (MBF1, MBF2) of the parallel mailbox register
HIGH. After a Partial Reset, the FIFO’s Full/Input Ready flag
is set HIGH after two clock cycles to begin normal operation.
Whatever flag offsets, programming method (parallel or
serial), and timing mode (FWFT or IDT Standard mode) are
currentl y selected at the time a Partial Res et is initiated , those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 6 of 29
reprogramming a FIFO following a Master Reset would be
inconvenient.
Big Endian/First-Word Fall-Through (BE/FWFT)
This i s a dual-purpo se pin. At the time of Master Reset, the BE
select function is active, permitting a choice of Big or Little
Endian byte arrangement for data written to or read from Port
B. This selection determines the order by which bytes (or
words) of data are transferred through this port. For the
following illustrations, assume that a byte (or word) bus size
has been selected for Port B. (Note that when Port B is
configured for a long-word size, the Big Endian function has
no application and the BE input is a “Don’t Care.”
A HIGH on the BE/FWFT input when the Master Reset (MRS1,
MRS2) inputs go from LOW to HIGH will select a Big Endian
arrangement. When data is moving in the direction from Port
A to Port B, the most significant byte (word) of the long-word
written to Port A will be transferred to Port B first; the least
signif icant byte (wo rd) of the long-wo rd written to Port A will be
transferred to Port B last.
A LOW on the BE/FWF T input when the Master Reset (MRS1,
MRS2) input s go from LOW to HI GH wi ll sel ect a Little Endian
arrangement. When data is moving in the direction from Port
A to Port B, the least significant byte (word) of the long-word
written to Port A will be transferred to Port B first; the most
signif icant byte (wo rd) of the long-wo rd written to Port A will be
transferred to Port B last. After Master Reset, the FWFT select
function is active, permitting a choice between two possible
timin g mo de s: CY Sta n da rd Mo de or Fi r st -Wor d Fall - Th ro ug h
(FWFT) Mode. Once the Mast er Reset ( MRS1, MRS2) input
is HIGH, a HIGH on the BE/FWFT input at the second
LOW-to-HIGH transition of CLKA will select CY Standard
Mode. This mode uses the Empty Flag function (EF) to
indicate whether or not there are any words present in the
FIFO memory. It uses the Full Flag function (FF) to indicate
whether or not the FIFO memory has any free space for
writin g. In CY S tandard M ode, every word read from the FIFO,
including the first, must be requested using a formal read
operation.
Once th e Maste r Rese t (MRS 1, MRS2) input is HIGH, a LO W
on the BE/FWFT input during the next LOW-to-HIGH transition
of CLKA will select FWFT Mode. This mode uses the Output
Ready function (OR) to indicate whether or not there is valid
data at the data outputs (B0–35). It also uses the Input Ready
function (IR) to indicate whether or not the FIFO memory has
any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes direct ly to data output s, no read
request necessary. Subsequent words must be accessed by
performing a formal read operation.
Following Master Reset, the level applied to the BE/FWFT
input to choose the desired timing mode must remain static
through out the FIFO opera tio n.
Programming the Almost Empty and Almost Full Flags
Two registers in the CY7C436x3 are used to hold the offset
values for th e Almo st Emp ty and Almost F ull fl ags. Th e Port B
Almost Empty fl ag (AE) of fset registe r is labele d X. The Port A
Almost Full flag (AF) offset register is labeled Y. The index of
each re gister nam e corresp onds with pr eset v alues during the
rese t o f a FIF O, pro grammed in parallel usin g the FIFO’s P ort
A data inputs, or programmed in serial using the Serial Data
(SD) input (see Table 2).
To load a FIFO’s Almost Empty flag and Almost Fu ll flag of fset
registers with one of the three preset values listed in Table 2,
the Serial Program Mode (SPM) and at least one of the
flag-select inputs must be HIGH during the LOW-to-HIGH
transition of its Master Reset input (MRS1, MRS2). For
example, to load the preset value of 64 into X and Y, SPM, FS0
and FS1 must be HIGH when the FIFO reset (MRS1, MRS2 )
returns HIGH. When using on e of the preset values for the flag
offsets, the FIFO can be reset simultaneously or at different
times.
To program the X and Y registers from Port A, perform a
Master Reset on both FIFOs simultaneously with SPM HIGH
and FS0 and FS 1 LO W du ring the LO W-to-HIGH transitio n of
MRS1/MRS2. After this reset is complete, the first two writes
to the FIFO do not store data in RAM but load the offset
registers in the order Y and X. The Port A data inputs used by
the offset registers are (A0–9), (A0–11), or (A0–13),for the
CY7C436x3, respectively . The highest numbered input is used
as the most significant bit of the binary number in each case.
Valid programming values for the registers range from 0 to
1023 for the CY7C43643; 0to 4095 for the CY7C43663; 0 to
16383 for the CY7C43683. Before programming the offset
register, FF/IR is set HIGH. FIFOs begin normal operation
after programming is done.
To program the X and Y registers serially, initiate a Master
Reset with SPM LOW, FS0/SD LOW, and FS1/SEN HIGH
during the LOW-to-HIGH transition of MRS1/MRS2. After this
reset is complete, the X and Y register values are loaded
bit-wise through the FS0/SD input on each LOW-to-HIGH
transition of CLKA that the FS1/SEN input is LOW. Twenty,
twenty four, or twenty eight bit writes are needed to complete
the programming for the CY7C436x3, respectively. The two
registers are written in the order Y then finally X. The first-bit
write stores the most significant bit of the Y register and the
last-bit write stores the least significant bit of the X register.
Each reg ister value can be programm ed from 0 to 10 23 for the
CY7C43643; 0to 4095 for the CY7C43663; 0 to 16383
(Cy7c43683).
When the option to program the offset registers serially is
chosen, th e Port A Full/Inp ut Ready (FF/IR) flag remains LOW
until all register bits are written. FF/IR is set HIGH by the
LOW -to -HIG H transiti on of CLKA after th e last bit is loade d to
allow normal FIFO operation.
SPM, FS0/SD, and FS1/SEN function the same way in both
CY Standa rd and FWFT mode s.
FIFO Wr ite/Read Operation
The state of the Port A data (A0–35) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the high-impedance state when either
CSA or W/RA is HIGH. The A0–35 lines are active mail 2
register outputs when both CSA and W/RA are LOW.
Data is loaded into the FIFO from the A0–35 inputs on a
LOW-to -HIGH transition of CLKA when CSA is LOW, W/RA is
HIGH, ENA is HIGH, MBA is LOW, and FF/IR is HIGH (see
Table 3). FIFO writes on Port A are independent of any
concurrent Port B operation.
The Port B c ont rol s ig nal s a r e i den tic al to those of Port A w i th
the exception that the Port B Write/Read Select (W/RB) is the
inverse of the Port A Write/Read Select (W/RA). The state of
the Port B data (B0–35) lines is controlled by the Port B Chip
Select (CSB) and Po rt B Write/Read Select (W/RB). The B0–35
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lines are in the high-impedance state when either CSB is HIGH
or W/RB is LOW. The B0–35 lines are active outputs when CSB
is LOW and W/RB is HIGH.
Data is read from the FIFO to the B0–35 outputs by a
LOW -to-HIGH tran sition of CLKB whe n CSB is LOW , W/RB is
HIGH, ENB is HIGH, MBB is LOW, and EF/OR is HIG H (see
Table 4). FIFO reads and writes on Port B are independent of
any concurrent Port A operation.
The Set-up and hold time co nstrai nts to the port clocks fo r the
port Chip Selects and Write/Read Selects are only for enabling
write and read operations and are not related to
high-im pe dan ce control of the data output s. I f a p ort e nable is
LOW during a clock cycle, the port’s Chip Select and
Write/Read Select may change states during the Set-up and
hold time window of the cycle.
When operating the FIFO in FWFT Mode with the Output
Ready flag LOW, the next word wr itten is automati cally sent to
the FIFO’s output register by the LOW-to-HIGH transition of
the port clock that sets the Output Ready flag HIGH, data
residing in the FIFO’s memory array is clocked to the output
register only when a read is selected using the port’s Chip
Select, Write/Read Select, Enable, and Mailbox Select.
When op erating the FIFO in C Y S ta ndard Mod e, regardle ss of
whether the Empty Flag is LOW or HIGH, data residing in the
FIFO’s memory array is clocked to the output register only
when a read is selected using the port’s Chip Select,
Write/Read Select, Enable, and Mailbox Select.
Synch roniz ed FIFO Flags
Each FIFO is synchronized to its port clock through at least two
flip-flop stages. This is don e to improve f lag-signal reliability by
reducing the probability of the metastable events when CLKA
and CLKB operate asynchronously to one another . EF/OR and
AE are synchronize d to CLKA. FF/IR and AF are synchronized
to CLKB. Table 5 shows the relationship of each port flag to
the FIFO.
Empty/Output Ready Flags (EF/OR)
These a r e du al-p urp ose fla gs . In the FWFT Mode, the Output
Ready (OR) f unctio n is selected . When the Output R eady fl ag
is HIGH, new data is present in the FIFO output register . When
the Output Ready flag is LOW, the previous data word is
presen t in th e FIFO output regis ter and attem pted FIF O read s
are ignored.[1]
In the CY Standard Mode, the Empty Flag (EF) function is
selected. When the Empty Flag is HIGH, data is available in
the FIFO’s RAM memory for reading to the output register.
When the Empty Flag is LOW, the previous data word is
presen t in th e FIFO output regis ter and attem pted FIF O read s
are ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the
port clock that reads data from its array. For both the FWFT
and CY S tandard modes, the FIFO read pointer is incremented
each time a new word is clocked to its output register. The
state machine that controls an Output Ready flag monitors a
write poi nte r a nd read po in ter c om p a rator that ind ic ates w h en
the FIFO SR AM status is empty, or empty+1.
In FWFT Mode, from the time a word is written to a FIFO, it
can be shifted to the FIFO output register in a minimum of
three cycles of the Output Ready flag synchronizing clock.
Therefore, an Output Ready flag is LOW if a word in memory
is the next data to be sent to the FIFO output register and three
cycl es have not elapse d sinc e th e ti me the w ord was wri tt en.
The Output Ready flag of the FIFO remains LOW until the third
LOW-to-HIGH transition of the synchronizing clock occurs,
simultaneously forcing the Output Ready flag HIGH and
shifting the word to the FIFO output register.
In the CY Standard Mode, from the time a word is written to a
FIFO, the Empty Flag will indicate the presence of data
available for reading in a minimum of two cycles of the Empty
Flag sy nc hron iz ing clock. Therefore, an Empty Flag is LO W if
a word in memory is the next data to be sent to the FIFO output
register and two cycles have not elapsed since the time the
word was written. The Empty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing
clock occurs, forc ing the Empty F lag HIGH; onl y then can da ta
be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synch ronizi ng cloc k begin s the first sy nchro nizat ion cycle of a
write if the clock transition occurs at time tSKEW1 or greater
after the write. Otherwise, the subsequent clock cycle can be
the first synchronization cycle.
Full/Input Ready Flags (FF/IR)
This is a dual-purpose flag. In FWFT Mode, the Input Ready
(IR) function is selected. In CY Standard Mode, the Full Flag
(FF) function is selected. For both timing modes, when the
Full/Inp ut Rea dy fl ag is HIGH, a m emory l ocati on is f ree in t he
SRAM to receive new data. No memory locations are free
when the Full/Input Ready flag is LOW and attempted writes
to the FIFO are ignored.
The Full/Input Read y flag of a FIF O is sync hronized to the p ort
clock that writes data to its array. For both FWFT and CY
Standard modes, each time a word is written to a FIFO, its
write pointer is incremented. The state machine that controls
a Full/Input Ready flag monitors a write pointer and read
pointer comparator that indicates when the FIFO SRAM status
is full, or full–1. From the time a word is read from a FIFO, its
previous memory location is ready to be written to in a
minimum of two cycles of the Full/Input Ready flag synchro-
nizing clock. The refore, an Full/ Input Ready flag is LOW if l ess
than two cycles of the Full/Input Ready flag synchronizing
clock ha ve el apsed sinc e the ne xt me mory w rite locati on h as
been read. The second LOW-to-HIGH transition on the
Full/Input Ready flag synchronizing clock after the read sets
the Full/Input Ready flag HIGH.
A LOW -to-HIGH trans ition on a Fu ll/Input Rea dy flag synch ro-
nizing clock begins the first synchronization cycle of a read if
the clock transition occurs at time tSKEW1 or greater after the
read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle.
Almost Empty Flags (AE)
The Almost Empty flag of the FIFO is synchronized to port B
clock. The state machine that controls an Almost Empty flag
monitors a write pointer and read pointer comparator that
indicates when the FIFO SRAM status is almost empty, or
almost empty+1. The Almost Empty state is defined by the
contents of register X for AE. These registers are loaded with
preset values during a FIFO reset, programmed from Port A,
or programmed serially (see Almost Empty flag and Almost
Full flag offset programming above). An Almost Empty flag is
LOW when its FIFO contains X or less words and is HIGH
when its FIFO contains (X+1) or more words[2].
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Two LOW-to-HIGH transitions of the Almost Empty flag
synchronizing clock are required after a FIFO write for its
Almost Empty f lag to refle ct the new le vel of fill . Therefore, the
Almost empty flag of a FIFO containing (X+1) or more words
rem ains LOW if tw o cycl es of it s sync hroniz ing clo ck hav e not
elapsed since the write that filled the memory to the (X+1)
level. An Almost Empty flag is set HIGH by the second
LOW-to-HIGH transition of its synchronizing clock after the
FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH
transition of an Almost Empty flag synchronizing clock begins
the first synchronization cycle if it occurs at time tSKEW2 or
greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle may be
the first synchronization cycle.
Almost Full Flags (AFA, AFB)
The Almost Full flag of the FIFO is synchronized to port A
clock. The state machine that controls an Almost Full flag
monitors a write pointer and read pointer comparator that
indica tes when the FIFO SRAM st atus is almost full, or al most
full–1. The Almost Full state is defined by the contents of
register Y for AF. These registers are loaded with preset
values during a FIFO reset, programmed from Port A, or
programmed serially (see Almost Empty flag and Almost Full
flag offset programming above). An Almost Full flag is LOW
when the nu mb er o f wo rds in its FIFO is g reat er th an or equal
to (1024–Y), (4096–Y), or (16384–Y) for the CY7C436x3
respectively. An Almost Full flag is HIGH when the number of
words in its FIFO is less than or equal to [1024–(Y+1)],
[4096–(Y+1)], or [16384–(Y+1)], for the CY7C436x3 respec-
tively.[2]
Two LO W-to-HIGH transi tions o f the Almost Full flag synchro-
nizing clock are required after a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [1024/4096/16384–(Y+1)] or less
words remains LOW if two cycles of its synchronizing clock
have not elapsed since the read that reduced the number of
words i n mem ory to [102 4/4096/16 384–(Y+1)]. An Al most Full
flag is set HIGH by the second LOW-to-HIGH transition of its
synchronizing clock after the FIFO read that reduces the
number of words in memory to [1024/4096/16384–(Y+1)]. A
LOW-to-HIGH transition of an Almost Full flag synchronizing
clock begins the first synchronization cycle if it occurs at time
tSKEW2 or greater after the read that reduces the number of
words in memory to [1 024/4096/1638 4–(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first
synchronization cycle.
Mailbox Registers
Each FIFO h as a 36 -bit byp ass re gister to p ass comm and and
control information between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usable width of both the Mail1 and Mail2
registers matches the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes A0-35 data to the
Mail1 Register w hen a Port A wr ite is selec ted by CSA, W/R A,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register
emplo ys data lines A0–35. If th e sele cted Port A bus s ize is 18
bits , then th e u sa ble width of the Mail1 Register employs da t a
lines A0-17. (In this case, A18–35 are “don’t care” inp ut s .) If the
selec ted Port A bus si ze is 9 bits, then the usabl e width of the
Mail1 Register employs data lines A0–8. (In this case, A9–35 are
“don’t care” inputs.)
A LOW-to-HIGH transition on CLKB writes B0-35 data to the
Mail2 register when a Port B write is selected by CSB, W/RB,
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register
employ s dat a lines B0–35. If the sele cte d Port B bus si ze is 18
bits, then the usable width of the Mail2 register employs data
lines B0–17. (In this case, B18–35 are “don’t care” in put s.) If the
selec ted Po rt B bus si ze is 9 bit s , the n th e us abl e width of the
Mail2 R egister emp loys data lines B0-8. (In t his case, B9-35 are
“don’t care” inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW . Attemp ted writes to a mail reg ister are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select inp ut is HI GH .
The Mail1 Register flag (MBF1) is set HIGH by a
LOW-to-HIGH transition on CLKB when a Port B read is
selected by CSB, W/RB, and ENB with MBB HIGH. For a
36-bit bus size, 36 bits of mailbox data are placed on B0–35.
For an 18-bit bus size, 18 bits of mailbox data are placed on
B0–17. (In th is c ase, B 18–35 are indetermi nate.) For a 9-b it bus
size, 9 bits of mailbox data are placed on B0–8. (In this case,
B9–35 are indeterminate.)
The Mail2 Register flag (MBF2) is set HIGH by a
LOW-to-HIGH transition on CLKA when a Port A read is
selected by CSA, W/RA, and ENA with MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on
A0–35. For an 18-bit bus size, 18 bits of mailbox data are
placed on A0–17. (In this case, A18–35 are indeterminate.) For
a 9-bit bus size, 9 bits of mailbox data are placed on A0–8. (In
this case, A9–35 are indeterminate.)
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Bus Sizing
The Port B bus can be config ured in a 36- bit long -word, 18-b it
word, or 9-bit byte format for data read from FIFO. The levels
applied to the Port B Bus Size Select (SIZE) and the Bus
Match Select (BM) determine the Port B bus size. These levels
should be static throughout FIFO operation. Both bus size
selections are implemented at the completion of Master Reset,
by the time the Full/Input Ready flag is set HIGH.
Two different methods for sequencing data transfer are
available for Port B when the bus size selection is either
byte-or word-size. They are referred to as Big Endian (most
significant byte first) and Little Endian (least significant byte
first). The level applied to the Big Endian Select (BE) input
during the LOW-to-HIGH transition of MRS1/MRS2 selects the
endian method t hat will be acti ve during FIFO operati on. BE i s
a don’t care input when the bus size selected for Port B is
long-word. The endian method is implemented at the
completion of Master Reset, by the time the Full/Input Ready
flag is set HIGH.
Only 36-bit long-word data is written to or read from the two
FIFO mem ories on the CY7C436x 3. Bus-matching operat ions
are done after data is read from the FIFO. These bus-matching
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operations are not available when transferring data via
mailbox registers. Furthermore, both the word- and byte-size
bus s ele cti ons l im it t he wi d th of the data bus that can be us ed
for mail register ope ration s. In this case , only t hose byte lane s
belonging to the selected word- or byte-size bus can carry
mailbox data. The remaining data outputs will be indeter-
minate. The remaining data inputs will be don’t care inputs. For
examp le, when a word-siz e bus is selected, the n mailbox dat a
can be transmitted only between A0–17 and B0–17. When a
byte-size bus is selected, then mailbox data can be trans-
mitted only betwe en A0–8 and B0–8.
Bus-Match ing FIFO Reads
Data is read from the FIFO RAM in 36-bit long-word incre-
ment s. I f a long -word bus size i s impl emented, the enti re long-
word immediately shifts to the FIFO output register. If byte or
word size is implemented on Port B, only the first one or two
bytes appear on the selected portion of the FIFO output
register, with the rest of the long-word stored in auxiliary
regi sters. In thi s case, subsequ ent FIFO rea ds output the rest
of the long-word to the FIFO output register.
When reading data from the FIFO in the byte or word format,
the unused B0–35 outpu t s are indeterminate.
Retransmit (RT)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. Retransmit
function applies to CY standard mode only.
The number of 36-/18-/9-bit words written into the FIFO should
be less than full depth min us 2/4/8 word s betwe en the rese t of
the FIFO (master or partial) and Retransmit setup. A LOW
pulse on RT resets the internal read pointer to the first physical
location o f the FIFO. CLKA and CLKB may be free-running but
ENB must be disabled during and tRTR after the retransmit
pulse. With every valid read cycle after retransmit, previously
accessed data is read and the read pointer is incremented until
it is equal to the write pointer. Flags are governed by the
relative locations of the read and write pointers and are
updated during a retransmit cycle. Data written to the FIFO
after activation of RT are transmitted al so. The ful l depth of t he
FIFO can be repeatedly transmitted.
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B27–35 B18–26 B9–17 B0–8
A
A27–35
B
A18–26
C
A9–17
D
A0–8
A
B27–35
B
B18–26
C
B9–17
D
B0–8
AB
CD
CD
AB
A
B
C
D
(a) L ONG WORD SI ZE
(b) WORD SIZE – BIG ENDIAN
(c) WORD SIZE – LITTLE ENDIAN
(d) BYTE SIZE – BIG ENDIAN
BE BM SIZE
XLX
BE BM SIZE
HHL
BE BM SIZE
LHL
BE BM SIZE
HHH
Write to FIFO
Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
3rd: Read from
FIFO
4th: Read from
FIFO
BYTE OR DER ON
PORT A:
D
C
B
A
(e) BYTE SIZE – LITT LE ENDIAN
BE BM SIZE
LHH
1st: Read from
FIFO
2nd: Read from
FIFO
3rd: Read from
FIFO
4th: Read from
FIFO
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
B27–35 B18–26 B9–17 B0–8
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Table 2. Flag Program ming [2]
SPM FS1/SEN FS0/SD MRS1/MRS2 X and Y Registers[3]
H H H ↑64
H H L ↑16
H L H ↑8
H L L ↑Parallel programming via Port A
L H L ↑Serial programming via SD
L H H ↑Reserved
L L H ↑Reserved
L L L ↑Reserved
Table 3. Port A Enable Function
CSA W/RA ENA MBA CLKA A0–35 Outputs Port Function
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H L ↑In high-impe dan ce state FIFO write
L H H H ↑In high-impe dan ce state Mail1 write
L L L L X Active, Mail2 register None
L L H L ↑Active, Mail2 register None
L L L H X Active, Mail2 register None
L L H H ↑Active, Mail2 register Mail2 read (set MBF2 HIGH)
Table 4. Port B Enable Function
CSB W/RB ENB MBB CLKB B0–35 Outputs Port Function
H X X X X In high-impedance state None
L L L X X In high-impedance state None
L L H L ↑In high-impedance state None
L L H H ↑In high-impedance state Mail2 write
L H L L X Active, FIFO output register None
L H H L ↑Active, FIFO output register FIFO read
L H L H X Active, Mail1 regis ter None
L H H H ↑Active, Mail1 register Mail1 read (set MBF1 HIGH)
Table 5. FIFO Flag Operation (CY Standard and FWFT Modes)[2]
Number of Words in FIFO Memory[4, 5, 6, 7] Synchronized to CLKB Synchronized to CLKA
CY7C43643 CY7C43663 CY7C43683 EF/OR AE AF FF/IR
0 0 0 L L H H
1 TO X1 1 TO X1 1 TO X1 H L H H
(X1+1) to [1024–(Y1+1)] (X1+1) to [4096–(Y1+1)] ( X1+1) to [16384–(Y1+1)] H H H H
(1024–Y1) to 1023 (4096–Y1) to 4095 (16384–Y1) to 1638 3 H H L H
1024 4096 16384 H H L L
Notes:
3. X register holds the offset for AE; Y register holds the offset for AF.
4. X is the Almost Empty offset for FIFO used by AE. Y is the Almost Full offset for FIFO used by AF. Both X and Y are selected d uring a FIFO reset or port A
programming.
5. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
6. Data in the output register does not count as a “word in FIFO me mory ”. Since in FWFT Mode, the first word written to an empty FIFO goes unrequested to the
output register (no read operation necessary), it is not included in the FIFO memory count.
7. The OR and IR functions are active during FWFT mode; the EF and FF functions are active in CY Standard Mode.
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Table 6. Data Size for FIFO Long-Word Reads
Size Mode[9] Data Written to FIFO Data Read From FIFO
BM SIZE BE A27–35 A18–26 A9–17 A0–8B27–35 B18–26 B9–17 B0–8
L X X A B C D A B C D
Table 7. Data Size for Word Reads
Size Mode[9] Data Written to FIFO Read No. Data Read From FIFO
BM SIZE BE A27–35 A18–26 A9–17 A0–8B9–17 B0–8
H L H A B C D 1 A B
2 C D
H L L A B C D 1 C D
2 A B
Table 8. Data Size for Byte Reads from FIFO
Size Mode[9] Data Written to FIFO Read No. Dat a Read From
FIFO
BM SIZE BE A27–35 A18–26 A9–17 A0–8B0–8
HHHABCD1 A
2B
3C
4D
HHLABCD1 D
2C
3B
4A
Notes:
8.
9. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
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Maximum Ratings[10,12]
(Abov e wh ic h th e us eful life ma y be imp aire d. For user guide-
lines, not tested.)
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State[11].....................................–0.5V to VCC+0.5V
DC Input Voltage[11] .................................–0.5V to VCC+0.5V
Output Current into Outpu t s (LO W)..................... ........20 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range Ambient
Temperature VCC[13]
Commercial 0°C to +70 °C 5.0V ± 0.5V
Industrial ∠40°C to +85°C 5.0V ± 0.5V
Electri cal Characteristics Over the Operating Range
Parameter Description Test Conditions
CY7C43643/63/83
UnitMin. Max.
VOH Output HIGH Voltage VCC = 4.5V,
IOH = ∠4.0 mA 2.4 V
VOL Output LOW Voltage VCC = 4.5V,
IOL = 8.0 mA 0.5 V
VIH Input HIGH Voltage 2.0 VCC V
VIL Input LOW Volta ge ∠0.5 0.8 V
IIX Input Leaka ge Cu rren t VCC = Max. ∠10 +10 µA
IOZL
IOZH Output OFF, High-Z Current OE > VIH,
VSS < VO< VCC ∠10 +10 µA
ICC1[14] Active Power Supply Current Com’l100 mA
Ind 100 mA
ISB[15] Avera ge Standb y Cu rren t Com’l10 mA
Ind 10 mA
Capacitance[16]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25 °C, f = 1 MHz,
VCC = 3.3V 4pF
COUT Output Capacitance 8pF
AC Test Loads and Waveforms (-10 and -15)
Notes:
10. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to abso-
lute-maximum-rated conditions for extended periods may affect device reliability.
11. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
12. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
13. Operating VCC range for -7 spee d is 5.0V ±0.25V.
14. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unlo ade d.
15. All inputs = VCC – 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
16. Tested initially and after any design or process changes that may affect these parameters.
3.0V
5V
OUTPUT
R2 = 680ΩCL = 30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤3ns ≤3ns
ALL INPUT PULSES
R1 = 1.1KΩ
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Document #: 38-06021 Rev. *B Page 14 of 29
AC Test Loads and Waveforms (-7)
Switching Characteristics Over the Operating Range
Parameter Description
CY7C43643/
63/83
–7
CY7C43643/
63/83
–10
CY7C43643/
63/83
–15 UnitMin. Max. Min. Max. Min. Max.
fSClock Frequency, CLKA or CLKB 133 100 67 MHz
tCLK Clock Cycl e Time, CLKA or CLKB 7.5 10 15 ns
tCLKH Pulse Duration, CLKA or CLKB HIGH 3.5 4 6 ns
tCLKL Pulse Duration, CLKA or CLKB LOW 3.5 4 6 ns
tDS Set-up Time, A0–35 before CLKA↑ and B0–35
before CLKB↑3 4 5 ns
tENS Set-up Time, CSA, W/RA, ENA, and MBA before
CLKA↑; CSB, W/RB, ENB, and MBB before
CLKB↑
3 4 5 ns
tRSTS Set-up Time, MRS1/MRS2, PRS or RT 1 LOW
before CLKA↑ or CLKB↑[17] 2.5 4 5 ns
tFSS Set-up Time, FS0 and FS1 before MRS1/MRS2
HIGH 6 7 7.5 ns
tBES Set-up T ime, BE/FWFT before MRS1/MRS2 HIGH 5 7 7.5 ns
tSPMS Set-up Time, SPM before MRS1/MRS2 HIGH 5 7 7.5 ns
tSDS Set-up Time, FS0/SD before CLKA↑3 4 5 ns
tSENS Set-up Time, FS1/SEN before CLKA↑3 4 5 ns
tFWS Set-up Time, FWFT before CLKA↑0 0 0 ns
tDH Hold Time, A0–35 after CLKA↑ and B0–35 afte r
CLKB↑0 0 0 ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after
CLKA↑; CSB, W/RB, ENB, and MBB after CLKB↑0 0 0 ns
tRSTH Hold Time, MRS1/MRS2, PRS or RT1 LOW after
CLKA↑ or CLKB↑[17] 1 2 4 ns
tFSH Hold Time, FS0 an d FS1 afte r MRS1 /MRS2 HIGH 1 1 2 ns
tBEH Hold Time, BE/FWFT after MRS1/MRS2 HIGH 1 1 2 ns
tSPMH Hold Time, SPM after MRS1/MRS2 HIGH 1 1 2 ns
tSDH Hold T im e, FS0/SD after CLKA↑0 0 0 ns
tSENH Hold Time, FS1/SEN after CLKA↑0 0 0 ns
tSPH Hold Time, FS1/SEN HIGH after MRS1/MRS2
HIGH 0 1 2 ns
Note:
17. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3.0V
GND
90%
10%
90%
10%
≤3ns ≤3ns
ALL INPUT PULSES
I/O
50Ω
V
CC
/2
Z0 = 50Ω
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 15 of 29
tSKEW1[18] Skew Time between CLKA↑ and CLKB↑ for EF/OR
and FF/IR 5 5 7.5 ns
tSKEW2[18] Skew Time between CLKA↑ and CLKB↑ for AE
and AF 7 8 12 ns
tAAccess Time, CLKA↑ to A0–35 and CLKB↑ to B0–35 1 6 1 8 3 10 ns
tWFF Propagation Delay Time, CLKA↑ to FF/IR 1 6 1 8 2 8 ns
tREF Propagation Delay Time, CLKB↑ to EF/OR 1 6 1 8 1 8 ns
tPAE Propagation Delay Time, CLKB↑ to AE 1 6 1 8 1 8 ns
tPAF Propagation Delay Time, CLKA↑ to AF 1 6 1 8 1 8 ns
tPMF Propaga tion Delay T ime , CLKA↑ to MBF1 LOW or
MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1
HIGH
0 6 0 8 0 12 ns
tPMR Propagation Delay Time, CLKA↑ to B0–35[19] and
CLKB↑ to A0–35[20] 1 7 2 11 312 ns
tMDV Propagation Delay Time, MBA to A0–35 Valid and
MBB to B0–35 Valid 1 6 2 9 3 11 ns
tRSF Propagation Delay Time, MRS1/MRS2 or PRS
LOW to AE LOW, AF HIGH , F F /IR LOW, EF/OR
LOW and MBF1/MBF2 HIGH
1 6 1 10 115 ns
tEN Enable Time, CSA or W/RA LOW to A0–35 Active
and CSB LOW and W/RB HIGH to B0–35 Active 1 6 2 8 2 10 ns
tDIS Disable T ime, CSA or W/RA HIGH to A0–35 at High
Impedance and CSB HIGH or W/RB LOW to B0–35
at High Impedance
1 5 1 6 1 8 ns
tRTR Re tran smit Recovery Time 90 90 90 ns
Notes:
18. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
19. Writing data to the Mail1 register when the B0–35 outputs are active and MBB is HIGH.
20. Writing data to the Mail2 register when the A0–35 outputs are active and MBA is HIGH.
Switching Characteristics Over the Operating Range (continued)
Parameter Description
CY7C43643/
63/83
–7
CY7C43643/
63/83
–10
CY7C43643/
63/83
–15 UnitMin. Max. Min. Max. Min. Max.
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 16 of 29
Switching Waveforms
Note:
21. MRS1/MRS2 must be HIGH during Partial Reset.
Master Reset Loading X and Y with a Preset Va lue of Eight
CLKA
tRSF
tRSF
tRSF
tWFF
tFSS tFSH
tSPMS tSPMH
tBES tBEH
tRSTH
tRSTS
tFWS
CLKB
MRS1,
MRS2
BE/FWFT
SPM
FS1/SEN,
FS0/SD
FF/IR
EF/OR
AE
AF
MBF1
[21]
tRSF
tRSF
Partial Reset (CY Standard and FWFT Modes )
tRSF
tRSF
tRSF
tRSTS tRSTH
CLKA
CLKB
PRS
FF/IR
EF/OR
AE
AF
MBF1
[21]
tWFF
tRSF
tRSF
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 17 of 29
Notes:
22. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
23. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB for FF/IR to transition HIGH in the next cycle. If the time between the rising edge
of CLKA and rising edge of CLKB is less than tSKEW1, then F F/IR may transition HIGH one cycle later than shown.
24. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set HIGH.
25. Programmable offsets are written serially to the SD input in the order AF offset (Y) then AE offset (X).
Switching Waveforms (continued)
Parallel Programming of the Almost Full Flag and Almost Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes)
tWFF
tFSS
tDS
tFSS tFSH
tFSH
tENS tENH
tDH
tSKEW1[23]
AF Of fset (Y) First Wor d to F IFO
CLKA
MRS1,
MRS2
SPM
FS1/SEN,
FS0/SD
FF/IR
ENA
A0−35
[22]
AE Offset (X)
Serial Programming of the Almost Full Flag and Almost Empty Flag
Offset Values (CY Standard and FWFT Modes)
tFSS tSPH tSENS tSENH tSENH
tSENS
tSDH
tSDS tSDH
tSDS
tWFF
AF Of fset (Y) MSB
tFSS tFSH
CLKA
MRS1, MRS2
SPM
FF/IR
FS1/SEN
[24]
FS0/SD [25]
AE Offset (X) LSB
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 18 of 29
Notes:
26. Read fro m FIF O.
27. If W/RB switches from read to write before the assertion of CSB, tENS = tDIS+tENS.
28. Unused word B18–35 contains all zeroes for word-size reads.
Switching Waveforms (continued)
OR
tCLKH tCLKL
tENS
tDIS
tENS tEN
tCLK
tDIS
tENH
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV
W1[26] W2[26]
W1[26] W2[26]
W3[26]
Previous Data
No Operation
CLKB
EF/OR
CSB
W/RB[27]
MBB
ENB
B0–35
(Standard Mode )
B0–35
(FWFT Mode)
Port B Long-Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes)[1]
OR
CLKB
EF/OR
CSB
W/RB[27]
MBB
ENB
Port B Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes)
tDIS
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
Previous
Read 1
Read 1
Read 2
Read 2
Read 3
No Operation
B0–17
(Standard Mode)
B0–17
(FWFT Mode)
[1, 28]
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 19 of 29
Notes:
29. Unused bytes B9–17, B18–26, and B27–35 contain all zeroes for byte-size reads.
Switching Waveforms (continued)
OR
CLKB
EF/OR
CSB
W/RB[27]
MBB
ENB
Port B Byte Read Cycle Timing for FIFO (CY Standard and FWFT Modes)
tDIS
tENStENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
tA
tA
tA
tA
Previous
Read 1
Read 1
Read 2
Read 2
Read 3
Read 3
Read 4
Read 4
Read 5
No Operation
HIGH
B0–8
(Standard Mode)
B0–8
(FWFT Mode)
[1, 29]
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 20 of 29
Notes:
30. If Port B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively.
31. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output register
in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and load of the first
word to the output register may occur one CLKB cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS
tCLK
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO Emp ty
LOW
HIGH
LOW
Old Data in FIFO Outp ut Register W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tSKEW1[31]
CLKA
CSA
W/RA
MBA
ENA
FF/IR
A0–35
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–35
OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode)[1, 30]
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 21 of 29
Notes:
32. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the rising
CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO Empty
LOW
HIGH
LOW
W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tCLK
tSKEW[32]
CLKA
CSA
W/RA
MBA
ENA
FF/IR
A0–35
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–35
EF Flag Timing and First Data Read Fall Through when FIFO is Empty (CY Standard Mode)[30]
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 22 of 29
Notes:
33. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.
34. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising
CLKB edge and rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
HIGH
HIGH
FIFO Full
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[34]
tDH
tDS
tENH
tENS
Previous Word in FIFO
Output Register Next W ord From FIFO
To FIFO
CLKB
CSB
W/RB
MBB
ENB
EF/OR
B0–35
CLKA
FF/IR
CSA
W/RA
MBA
ENA
A0–35
IR Flag Timing and First Available Write when FIFO is Full (FWFT Mode)[33]
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 23 of 29
Note:
35. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the rising
CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FF HIGH may occur one CLKA cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
HIGH
HIGH
FIFO Full
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[35]
tDH
tDS
tENH
tENS
Previous Word in FIFO
Output Re gister Next Wor d From FI FO
CLKB
CSB
W/RB
MBB
ENB
EF/OR
B0–35
CLKA
FF/IR
CSA
W/RA
MBA
ENA
A0−35
FF Flag Timing and First Available Write when FIFO is Full (CY Standard Mode)[33]
LOW
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 24 of 29
Notes:
36. FIFO Write (CSA = LOW , W/RA = HIGH, MBA = LOW), FIFO Read (CSB = LOW , W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read
from the FIFO.
37. D = Maximum FIFO Depth 1K for the CY7C43643, 4K for the 43663, and 16K for the CY7C43683.
38. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
39. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising
CLKA edge and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKB cycle later than shown.
40. FIFO Write (CSA = LOW , W/RA = LOW, MBA = LOW), FIFO Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read
from the FIFO.
41. If Port B size is word or byte, AE is set LOW by the last word or byte read from FIFO, respectively.
42. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising
CLKA edge and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
Switching Waveforms (continued)
Tim ing for AF when FIFO is Almost Full (CY Standard and FWFT Modes)
tSKEW2[39]
CLKA
ENA
AF
CLKB
ENB
[2, 36, 37, 38]
tPAF
tENH
tENS
tPAF
tENS tENH
[D–(Y1+1)] Words in FIFO1 (D–Y1)W ords in FIFO1
CLKA
ENA
CLKB
AE
ENB
Timing for AE when FIFO is Almost Empty (CY Standard and FWFT Modes)[40, 41, 2]
tPAE
tPAE
tENH
tENS
tSKEW2[42]
tENS tENH
X1 Wor d in FIFO (X1+1)Words in FIFO
(X1+1) Word in FIFO
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 25 of 29
Note:
43. If Port B is configured for word size, data can be written to the Mail1 register using A0–17 (A18–35 are “don’t care” inputs). In this first case B0–17 will have valid
data (B18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0–8 (A9–35 are “don’t care” inputs). In
this second case, B0–8 will have valid data (B9–35 will be indeterminate).
44. If W/RA switches from read to write before the assertion of CSA, tENS = tDIS+tENS.
45. Simultaneous writing to and reading from mailbox register is not allowed.
Switching Waveforms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO Output Register W1 (Remains valid in Mail1 Register af ter read)
CLKA
CSA
W/RA[44]
MBA
ENA
A0–35
CLKB
MBF1
CSB
W/RB[27]
MBB
ENB
Timing for Mail1 Re gister and MBF1 Flag (CY Standard and FWFT Modes) [43,45]
B0−35
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 26 of 29
Notes:
46. If Port B is configured for word size, data can be written to the Mail2 register using B0–17 (B18–35 ar e “don’t care” inputs). In this first case, A0–17 will have valid
data (A18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0–8 (B9–35 are “don’t care” inputs). In
this second case, A0–8 will have valid data (A9–35 will be indeterminate).
47. Retransmit is performed in the same manner for FIFO2.
48. Clocks are free-running in this case. CY standard mode only. Write operation should be prohibited one write clock cycle before the falling edge of RT1, and
during the retransmit operation, i.e. when RT1 is LOW and tRTR after the RT1 rising edge.
49. The Empty and Full flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
50. For the AEA, AEB, AFA, and AFB flags, two clock cycle are necessary after tRTR to upda te these flags.
51. The number of 36-/18-/9-bit words written into the FIFO should be less than full depth minus 2/4/8 words between the reset of the FIFO (master or partial) and
the Retransmit setup.
Switching Waveforms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO2 Output Register W1 (Remains valid i n Mail2 Register after read)
CLKB
CSB
W/RB[27]
MBB
ENB
B0–35
CLKA
MBF2
CSA
W/RA[44]
MBA
ENA
A0−35
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)[46,45]
FIFO1 Retransmit Timing
ENB
RT1 tRTR
EFB/FFA
[47, 48, 49, 50, 51]
tRSTS tRSTH
CLKA
CLKB
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 27 of 29
Ordering Information
1K x36 Unidirectional Synchronous FIFO w/ Bus Matching
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
7 CY7C43643–7AC A128 128-lead Thin Quad Flat Package Commercial
10 CY7C43643–10AC A128 128-lead Thin Quad Flat Package Commercial
15 CY7C43643–15AC A128 128-lead Thin Quad Flat Package Commercial
4K x36 Unidirectional Synchronous FIFO w/ Bus Matching
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
7 CY7C43663–7AC A128 128-lead Thin Quad Flat Package Commercial
10 CY7C43663–10AC A128 128-lead Thin Quad Flat Package Commercial
15 CY7C43663–15AC A128 128-lead Thin Quad Flat Package Commercial
16K x36 Unidirectional Synchronous FIFO w/ Bu s Matching
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
7 CY7C43683–7AC A128 128-lead Thin Quad Flat Package Commercial
10 CY7C43683–10AC A128 128-lead Thin Quad Flat Package Commercial
15 CY7C43683–15AC A128 128-lead Thin Quad Flat Package Commercial
15 CY7C43683–15AI A128 128-lead Thin Quad Flat Package Industrial
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 28 of 29
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
All product and company names mentioned in this document are the trademarks of their respective holders.
Package Diagram
128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128
51-85101-*B
CY7C43643
CY7C43663
CY7C43683
Document #: 38-06021 Rev. *B Page 29 of 29
Document Title: CY7C43643/ CY7C43663/ CY7C43683 1K/4K/16K x36 Unidirectional Synchronous FIFO
with Bus Matching
Document Number: 38-06021
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 106563 05/17/01 SZV Change from Spec #: 38-00699 to 39-06021
*A 117172 09/05/02 OOR Added footnote to retransmit timing
Added note to retransmit section
*B 122273 12/26/02 RBI Power up requirements added to Maximum Ratings Information
