November 1995 os Edition 1.5 FU} ITSU CG51/CE51 SERIES 3V, 0.50 MICRON HIGH PERFORMANCE/LOW POWER CMOS GATE ARRAYS DESCRIPTION The Fujitsu CG51/CE51 is a series of ultra high performance CMOS gate arrays. The CG51 is a high density Sea-of-Gates array for applications requiring high levels of integration or low power. The CE51 is a high performance embedded gate array family offering full support of diffused high soeed RAMS, ROMS and embedded megafunctions. The CE51 series offers density and performance approaching that achievable with standard cell solutions with the time-to-market advantage of a gate array. True 3V products, the CG51/CE51 feature very low power (1.2 microwatt/Mhz) and both 3.3V and 5.0V compatible I/Os. These advanced product families are targeted at users who are seeking very high performance or very high levels of integration. Potential end-user applications include computers, supercomputers, workstations, graphic terminals, telecom networking, and signal processing. FEATURES 0.5 Micron Drawn Channel Length Triple layer metal 3.3V + 0.3V supply voltage Fujitsu Microelectronics, Inc.s CE51654 647,000 Available Gate .5 Micron Embedded Internal gate delay of 210ps, F/O = 2, L= 1mm Array, Containing 28 Embedded Macro Cells Chanelless, Sea-of-gates Architecture e Low power consumption: 1.2 microwatt/gate/Mhz Maximum toggle frequency: 600Mhz PRODUCT SUMMARY High speed I/Os: PCML (PECL), LVTC Device Available Number of Metal Name Gates Pads Wiring Supports 3.3V and 5.0V VO ; ; ; CG51754 753,768 496 3LM e RAM compiler supports Single/Dual/Triple port RAM ; CG51654 647,948 456 3LM Supports JTAG boundary scan, full and partial scan . . CG51484 477,632 400 3LM e Phase Locked Loop for interchip clock skew control _ : CG51364 363,084 352 3LM Clock net for optimized on-chip clock skew control CG51284 277,380 304 3LM e Advanced packaging options include QFP, PGA, BGA, , and MCM CG51214 214,760 272 3LM e High drive capability: 2, 4, 8, 12, or 24mA CG51164 160,140 240 3LM Supports all major third party EDA tools including: CG51114 113,520 208 3LM Cadence, Mentor, Synopsys CG51343 34,272 120 3LM Copyright 1994 by FUJITSU LIMITEDCG51/CE51 SERIES DC CHARACTERISTICS Measuring conditions: Vpp = 3.3V + 0.3V,Vsg = OV, Tj = 0 to 100C a Requirements | Parameter Symbol Test Conditions 7 Unit Min. Typ. Max. CG51343 to CG51214 1.0 - 1.0 Supply current? Ipps Standby mode! Cee taed to -2.0 - 2.0 mA CG51654 to CG51754 3.0 - 3.0 CMOS Normal cell Vpp X 0.7 - Vpp High-level ah el input voltage Vin level Schmitt trigger cell Vpp X 0.8 - Vpp V TTL level Normal cell 2.2 - Vpp CMOS Normal cell Vss - Vpp X 0.2 Low-level ah el input voltage? VIL level Schmitt trigger cell Vss - Vpp X 0.2 V TTL level Normal cell Vss - 0.8 High-level output voltage P VoH lou = -2. 4, -8, -12, -18 Vpp -0.4 - Vpp Vv Low-level output voltage VoL lot = 2, 4, 8, 12, 18 Vss 0 0.4 Vv Input leakage current lu -10 - 10 (Tri-state pin input)* Iz OD) 10 _ 10 HA Input pull-up/ Pull-up V| = Vpp pull-down resistor Rp Pull-down V| = OV 20 80 140 KO Type Condition Vo =Vpp Vo =O0V Low power Io, = 2mA -20 +20 Output Short-circuit Normal lo_ = 4mA 40 +40 48 lo mA curren Output buffer Power Io, = 8mA -80 +80 High power lo, = 12mA -120 +120 Very high power Io = 24mA -180 +180 NOTES: 1. When Viy = Vpp and Vi_ = Vss, memory is in the standby mode. 2. If an input buffer with pull-up/pull-down resistor is used, the supply current may not be assured depending on the circuit configuration. 3. 5V interface is only for CMOS level. 4. If an input buffer with pull-up/pull-down resistor is used, the input leakage current may exceed the above value. 5. Either a buffer without a resistor or with a pull-up/pulldown resistor can be selected from the input and bidirectional buffers. 6. Maximum supply current at the short-circuit of output and Vpp or Vss.CG51/CE51 SERIES ABSOLUTE MAXIMUM RATINGS Parameter Symbol Requirements Unit VppE (External) Vgg" -0.5 to 6.0 Supply voltage ; Vv VppI (Internal) Vgg 0.5 to 4.0 Input voltage Vi Vgg -0.5 to Vpp +0.5 V Output voltage Vo Vgg -0.5 to Vpp +0.5 V Plastic -55 to +125 Storage ambient temperature Tst C Ceramic 65 to +150 : For one Vpp pin 90 Supply pin current Ip mA For one Vgg pin 90 Low power-type output buffer Io, - 2 mA +14 Normal-type output buffer Io. = 4mA 414 Output current lo Power-type output buffer Io, = 8mA 414 mA High-power type output buffer Io. = 12mA +21 Very high-power type of output buffer 58 lo. = 24mA + * Ves = 0V Requirements Parameter Symbol Unit Min. Typ. Max. Vv 3.0 3.3 3.6 Supply voltage DDE Vv VppI 3.0 3.3 46 CMOS level Vpp x 0.7 - Vv High-level input voltage Vin pp opr Vv TTL level 2.2 - VppI CMOS level Vss = Vpp! X 0.2 Low-level input voltage VIL ss por Vv TTL level Vss - 0.8 Junction temperature Tj 0 - 100 C * Ves = 0VCG51/CE51 SERIES THIRD PARTY EDA TOOL SUPPORTED Fujitsu supports a third party environment allowing an ASIC ASIC back end environment. These kits provide an easy designer the widest possible range of design options. Both environment for design entry, design rule checking. They also the CG51 gate array and CE51 embedded array product provide a complete pre- and post-layout timing back families are fully supported by Fujitsus ASIC design kits, annotating capabilities. The following leading third party tools running on leading workstations and provides a seamless are supported. link from leading third party ASIC design flows to Fujitsus Cadence: Verilog-XL Mentor: Design Architect 8.2, Autologic |, QuickSim II Motive: Motive 4.2 (Static Timing Analyzer) Sunrise Systems: ATPG 2.1 Synopsys: Design Analyzer 3.2a, VSSCG51/CE51 SERIES PACKAGE OPTIONS In addition to offering plastic and ceramic versions of industry standard packages such as POFPs and PGAs, Fujitsu also offers an impressive array of advanced packaging technology. Our long experience with high speed logic and thermal management has led us to develop some of the most advanced packaging available anywhere. From cost Packaging Options 343 114 164 214 Quad Flat Package (1.0, 0.8, 0.65 mm pin pitch) 100 P 120 P 160 P,C P,C P,C Shrink Quad Flat Package (0.5 mm pin pitch) 80 P 100 P 120 P 144 P P P effective, single chip packages to sophisticated multichip modules, Fujitsu has a packaging option to suit your requirements. Whether you need a 208 POFP, the newest in high I/O count surface mounted Ball Grid Array (BGA) packages or full custom packaging we can deliver the optimal solution. 176 208 240 256 304 P,C P,C P,C P,C P,C Fine Pitch Flat Package (0.4 mm pin pitch) 304 Pin Grid Array Package 256 299 321 361 401 Ball Grid Array (BGA) 256 352 416 576 NOTES: 1: Under Development C: Ceramic Package P: Plastic Package P,C P,C P,C 284 364 484 654 754 Cc PC PC PC PC P PC PC PC PC PC PC PC PC PC PC PC PC PC PC Ci Ci Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc Cc P P P P Pt Pt PtCG51/CE51 SERIES FRONT-END DESIGN FLOW Design Specification Schematic Entry Logic Synthesis Netlist EDIF VHDL FMI Design Kit Logic Design Rule Check KK IDRC >| Netlist & Delay Generator fldl_gen |g Ke or any other CAE netlist in ascii format Simulation Stimulus Test Pattern Editor KK CAE-Software Simulator Hardware Accelator N Trace ftdl_ed Test Pattern Generator ftdl_gen Netlist FLDL Back Annotation Z\ PDIL Layout GlosCAD f Logic Verification Test Pattern V LCADFE FTDLCG51/CE51 SERIES CLOCK SKEW CONTROL To maximize performance in high speed, high density arrays, of clock tree parameters, interactive clock tree a designer must maintain tight clock skew control. In addition implementation, simplifies trade-offs between clock tree delay to an available PLL to manage interchip clock skew, Fujitsus and clock skew, early verification of potential design hold clock driven design methodology (CDDM) offers accurate on time errors and race conditions. chip clock skew control. CDDM offers accurate RC extraction al 5 eoecee eeeee CK Global Clock Driver Local CK 1/0-GCD Clock QO Skew Driver GCD-LCD QO Skew Up to 10 LCDs LCD-FF Skew<.165ps Up to 160FFs 8FF-Bars (20FFs/FF-Bar)