TPS71750QDRVRQ1 - Texas Instruments

PSRR (dB)

10 100k 10M

Frequency (Hz)

1k 10k100 1M

C = 1 F

C = 10 nF

OUT

150 mA

10 mA

75 mA

Power-Supply Rejection Ratio (V V = 1 V)

IN OUT

TPS717-Q1

GNDEN NR

IN OUT

VIN VOUT

1 Fm

Ceramic

0.01 Fm

(Optional)

1 Fm

Ceramic

VEN

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS717-Q1

SLVSBM4C –SEPTEMBER 2012–REVISED JANUARY 2016

TPS717-Q1

Low-Noise, High-Bandwidth PSRR, Low-Dropout, 150-mA Linear Regulator

1 Features

1• AEC-Q100 Qualified with the Following Results:

– Device Temperature Grade 1: –40°C to 125°C

Ambient Operating Temperature Range

– Device HBM ESD Classification Level 2

– Device HBM ESD Classification Level C4B

• Input Voltage: 2.5 V to 6.5 V

• Available in Multiple Output Versions:

– Fixed Output with Voltages from 0.9 V to 5 V

– Adjustable Output Voltage from 0.9 V to 6.2 V

• Ultra-High PSRR:

– 70 dB at 1 kHz, 67 dB at 100 kHz, and 45 dB

at 1 MHz

• Excellent Load and Line Transient Response

• Very Low Dropout: 170 mV typical at 150 mA

• Low Noise: 30 μVRMS typical (100 Hz to 100 kHz)

• Small 5-pin SOT, 2-mm × 2-mm WSON-6, and

1.5-mm × 1.5-mm WSON-6 Packages

2 Applications

• PLLs

• VCOs

• Camera Sensor Power

• Microcontroller Power

• Wireless LAN, Bluetooth®

• ADAS and Infotainment Systems

3 Description

The TPS717-Q1 family of low-dropout (LDO), low-

power linear regulators offers very high power-supply

rejection (PSRR) and maintains very low 45-μA

ground current in an ultra-small, five-pin SOT

package. The family uses an advanced BiCMOS

process and a PMOSFET pass device to achieve fast

start-up, very low noise, excellent transient response,

and excellent PSRR performance. The TPS717-Q1 is

stable with a 1-μF ceramic output capacitor and uses

a precision voltage reference and feedback loop to

achieve a worst-case accuracy of 3% over all load,

line, process, and temperature variations. The device

family is fully specified from TJ, TA= –40°C to 125°C

and is offered in a small SOT (SC70-5) package, a

2-mm × 2-mm WSON-6 package with a thermal pad,

and a 1.5-mm × 1.5-mm WSON-6 package, which

are ideal for small form-factor portable equipment

(such as wireless handsets and PDAs). The TPS717-

Q1 family of LDOs is qualified for AEC-Q100 grade 1.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS717-Q1 SOT (5) 2.00 mm × 1.25 mm

WSON (6) 2.00 mm × 2.00 mm

WSON (6) 1.50 mm × 1.50 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Typical Application Circuit for Fixed-Voltage

Versions PSRR vs Frequency

TPS717-Q1

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 4

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 7

6.6 Typical Characteristics.............................................. 8

7 Detailed Description............................................ 13

7.1 Overview................................................................. 13

7.2 Functional Block Diagrams ..................................... 13

7.3 Feature Description................................................. 14

7.4 Device Functional Modes........................................ 15

8 Application and Implementation ........................ 17

8.1 Application Information............................................ 17

8.2 Typical Application.................................................. 18

8.3 Do's and Don'ts ...................................................... 20

9 Power Supply Recommendations...................... 20

10 Layout................................................................... 21

10.1 Layout Guidelines ................................................. 21

10.2 Layout Examples................................................... 21

11 Device and Documentation Support................. 23

11.1 Device Support .................................................... 23

11.2 Documentation Support ....................................... 23

11.3 Community Resources.......................................... 23

11.4 Trademarks........................................................... 24

11.5 Electrostatic Discharge Caution............................ 24

11.6 Glossary................................................................ 24

12 Mechanical, Packaging, and Orderable

Information........................................................... 24

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (December 2014) to Revision C Page

• Moved AEC-Q100 qualification bullet to first in Features list................................................................................................. 1

• Added TI Design .................................................................................................................................................................... 1

• Changed TPS717xx-Q1 to TPS717-Q1 throughout document ............................................................................................. 1

• Added footnote and CIN, R2, and CNR parameters to Recommended Operating Conditions table ....................................... 6

• Changed VFB parameter in Electrical Characteristics table ................................................................................................... 7

• Changed ΔVOUT(ΔIOUT) parameter typical specification in Electrical Characteristics table ..................................................... 7

• Changed units of Vnparameter in Electrical Characteristics table......................................................................................... 7

• Deleted UVLO parameter minimum specification from Electrical Characteristics table......................................................... 7

• Changed TAto TJin x-axis of Figure 7,Figure 10, and Figure 11......................................................................................... 9

• Changed 40 mV/div to 40 mA/div in y-axis of Figure 28 ..................................................................................................... 12

• Added last two sentences to Undervoltage Lockout (UVLO) section .................................................................................. 15

• Changed last bulleted condition in Normal Operation section ............................................................................................ 15

• Changed TJspecification in Normal mode row of Table 1 .................................................................................................. 16

• Added last sentence to Input and Output Capacitor Requirements section......................................................................... 17

• Clarified discussion of R2in second paragraph of Design Considerations section ............................................................. 19

• Changed first and third paragraphs of Do's and Don'ts section .......................................................................................... 20

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Changes from Revision A (August 2013) to Revision B Page

• Changed format to meet latest data sheet standards............................................................................................................ 1

• Changed Features list on front page: added, deleted, and reordered several bullets .......................................................... 1

• Added ESD Ratings table and Feature Description,Device Functional Modes,Application and

Implementation,Power Supply Recommendations,Layout,Device and Documentation Support, and Mechanical,

Packaging, and Orderable Information sections..................................................................................................................... 1

• Added several Applications list bullets on front page ............................................................................................................ 1

• Deleted pinout drawings from front page .............................................................................................................................. 1

• Changed pin descriptions throughout Pin Functions table..................................................................................................... 4

• Added parametric measurement for ISHDN for DRV package ................................................................................................ 7

• Changed Figure 1,Figure 2,Figure 3, and Figure 4: removed legend, added call-outs for clarity ....................................... 8

• Changed title of Figure 15 and Figure 17............................................................................................................................... 9

• Changed Overview section .................................................................................................................................................. 13

• Corrected input and output symbols in operational amplifiers in Functional Block Diagrams ............................................. 13

• Changed Undervoltage Lockout (UVLO) section text: reworded for clarity.......................................................................... 15

• Deleted Reverse Current Protection section ....................................................................................................................... 17

• Changed Equation 4 ............................................................................................................................................................ 19

Changes from Original (September 2012) to Revision A Page

• Changed front page to two-column format............................................................................................................................. 1

• Added part number TPS71745-Q1......................................................................................................................................... 1

• Changed C3B to C4B in Features list .................................................................................................................................... 1

• Removed Ordering Information table ..................................................................................................................................... 4

• Added Junction Temperature to Absolute Maximum Ratings table ....................................................................................... 5

• Changed C3B to C4B in Absolute Maximum Ratings table................................................................................................... 5

• Changed Application Information section to one-column format.......................................................................................... 18

N/C(1)

OUT

GND

NR/FB

OUT

NR/FB

GND

3 4

N/C(1)

OUT

NR/FB

GND

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5 Pin Configuration and Functions

DCK Package

5-Pin SOT

Top View DRV Package

2-mm × 2-mm, 6-Pin WSON

Top View

DSE Package

1.5-mm × 1.5-mm, 6-Pin WSON

Top View

(1) N/C = No connection

Pin Functions

I/O DESCRIPTION

NAME NO.

DCK

(SOT) DRV

(WSON) DSE

(WSON)

EN 3 4 4 I Driving the enable pin (EN) above VEN(high) turns on the regulator. Driving

this pin below VEN(low) puts the regulator into standby mode, thereby

disabling the output and reducing operating current.

FB 4 2 3 I Adjustable voltage version only. The voltage at this pin is fed to the error

amplifier. A resistor divider from OUT to FB sets the output voltage when in

regulation.

GND 2 3 2 — Ground

IN 1 6 6 I Input to the device. A 0.1-μF to 1-μF capacitor is recommended for better

performance.

N/C — 5 5 — Not connected. This pin can be tied to ground to improve thermal

dissipation.

NR 4 2 3 — Fixed voltage versions only. An external capacitor connected to this pin

bypasses noise generated by the internal band gap, thus lowering output

noise.

OUT 5 1 1 O This pin is the regulated output voltage. A minimum capacitance of 1 μF is

required for stability from this pin to ground.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) VEN absolute maximum rating is VIN + 0.3 V or 7 V, whichever is greater.

6 Specifications

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted), all voltages are with respect to GND(1)

MIN MAX UNIT

Voltage

VIN –0.3 7

VFB –0.3 3.6

VNR –0.3 3.6

VEN –0.3 VIN + 0.3 V(2)

VOUT –0.3 7

Current IOUT Internally limited A

Continuous total power dissipation PDISS See Thermal Information table

Ambient temperature TA–40 125 °C

Operating junction temperature TJ–55 150 °C

Storage temperature Tstg –55 150 °C

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V

TPS717-Q1 in DCK and DSE packages

V(ESD) Electrostatic discharge Charged device model (CDM), per AEC Q100-011

All pins ±750

Corner pins,

DCK (1, 3, 4, and 5) ±750

Corner pins,

DSE (1, 3, 4, and 6) ±750

TPS717-Q1 in DRV package

V(ESD) Electrostatic discharge Charged device model (CDM), per AEC Q100-011 All pins ±500 V

Corner pins (1, 3, 4, and 6) ±750

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(1) Adjustable voltage version only. When using feedback resistors that are smaller than recommended, the minimum output capacitance

must be greater than 5 µF.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

VIN Input voltage 2.5 6.5 V

VOUT Output voltage 0.9 5 V

IOUT Output current 0 150 mA

VEN Enable voltage 0 VIN V

CIN Input capacitor 1 µF

R2Lower feedback resistor 160 320 332 kΩ

CNR Noise reduction capacitor 10 nF

COUT Output capacitor 1(1) 100 µF

TJJunction temperature –40 125 °C

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.4 Thermal Information

THERMAL METRIC(1) TPS717-Q1

UNITDCK (SOT) DRV (WSON) DSE (WSON)

5 PINS 6 PINS 6 PINS

RθJA Junction-to-ambient thermal resistance 279.2 71.1 190.5 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 57.5 96.5 94.9 °C/W

RθJB Junction-to-board thermal resistance 74.1 40.5 149.3 °C/W

ψJT Junction-to-top characterization parameter 0.8 2.7 6.4 °C/W

ψJB Junction-to-board characterization parameter 73.1 40.9 152.8 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 10.7 n/a °C/W

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(1) Minimum VIN = VOUT + VDO or 2.5 V, whichever is greater.

(2) Does not include external resistor tolerances.

(3) VDO is not measured for devices with VOUT(nom) < 2.6 V because minimum VIN = 2.5 V.

(4) Maximum VEN(high) = VIN + 0.3 or 6.5 V, whichever is smaller.

6.5 Electrical Characteristics

Over operating temperature range (TJ, TA= –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT =

0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701-Q1), VOUT =

2.8 V. Typical values are at TA= 25°C.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIN Input voltage range(1) 2.5 6.5 V

VFB Feedback pin voltage (TPS71701) IOUT = 5 mA –2% 0.793 2% V

VOUT Output voltage range TPS717-Q1 0.9 5 V

TPS71701-Q1 0.9 6.5 – VDO

VOUT

Output accuracy (nominal) TA= 25°C ±2.5 mV

Output accuracy

(VOUT < 1 V) Over VIN, IOUT,

temperature(2) VOUT + 0.5 V ≤VIN ≤6.5 V,

0 mA ≤IOUT ≤150 mA –30 30

Output accuracy

(VOUT ≥1 V) Over VIN, IOUT,

temperature(2) VOUT + 0.5 V ≤VIN ≤6.5 V,

0 mA ≤IOUT ≤150 mA –3% 3%

ΔVOUT(ΔVIN) Line regulation(1) VOUT(nom) + 0.5 V ≤VIN ≤6.5 V,

IOUT = 5 mA 125 μV/V

ΔVOUT(ΔIOUT) Load regulation 0 mA ≤IOUT ≤150 mA 70 μV/mA

VDO Dropout voltage(3)

(VIN = VOUT(nom) – 0.1 V) IOUT = 150 mA 170 300 mV

ILIM (fixed) Output current limit (fixed output) VOUT = 0.9 × VOUT(nom) 200 325 575 mA

ILIM (adjustable) Output current limit (TPS71701-Q1) VOUT = 0.9 × VOUT(nom) 200 325 575 mA

IGND Ground pin current IOUT = 0.1 mA 45 80 μA

IOUT = 150 mA 100

ISHDN Shutdown current (IGND)

VEN ≤0.4 V, 2.5 V ≤VIN < 4.5 V,

TA= –40°C to 125°C 0.20 1.5

μA

VEN ≤0.4 V, 4.5 V ≤VIN ≤6.5 V,

TA= –40°C to 125°C 0.90

VEN ≤0.4 V, 2.5 V ≤VIN < 4.5 V,

TA= –40°C to 125°C, DRV package 2

IFB Feedback pin current (TPS71701-Q1) 0.02 1 μA

PSRR Power-supply rejection ratio VIN = 3.8 V,

VOUT = 2.8 V,

IOUT = 150 mA

f = 100 Hz 70

f = 1 kHz 70

f = 10 kHz 67

f = 100 kHz 67

f = 1 MHz 45

VnOutput noise voltage

BW = 100 Hz to

100 kHz,

VIN = 3.8 V,

VOUT = 2.8 V,

IOUT = 10 mA

CNR = none 95 × VOUT

μVRMS/V

CNR = 0.001 μF 25 × VOUT

CNR = 0.01 μF 12.5 × VOUT

CNR = 0.1 μF 11.5 × VOUT

tSTR Startup time

VOUT = 90%

VOUT(nom),

RL= 19 Ω,

COUT = 1 μF

0.9 V ≤VOUT ≤1.6 V,

CNR = 0.001 μF0.700 ms

1.6 V < VOUT < VOUT(max),

CNR = 0.01 μF0.160

VEN(high) Enable high (enabled) VIN ≤5.5 V 1.2 6.5(4) V

5.5 V < VIN ≤6.5 V 1.25 6.5

VEN(low) Enable low (shutdown) 0 0.4 V

IEN(high) Enable pin current, enabled EN = 6.5 V 0.02 1 μA

Tsd Thermal shutdown temperature Shutdown, temperature increasing 160 °C

Reset, temperature decreasing 140

UVLO Undervoltage lockout VIN rising 2.45 2.49 V

Hysteresis VIN falling 150 mV

1.5

0.5

1.5

DV (%)

OUT

-40 65 125

T ( C)

J°

5 35-25 -10 20 50 80 95 110

I = 100 Am

OUT

I = 5 mA

OUT

I = 150 mA

OUT

250

200

150

100

0 100 150

I (mA)

OUT

V (mV)

T = 125 C

A°

T = 85 C

A°

T = 25 C

A°

T = -40 C

A°

0.8

0.6

0.4

0.2

0.4

0.6

0.8

2.5 5.5 6.5

V (V)

DV (%)

OUT

3.5 4.5

T = 40 C-

T = 25 C

T = 85 C

T = 125 C

2.5 5.5 6.5

V (V)

DV (%)

OUT

3.5 4.5

T = 40 C-

T = 25 C

T = 85 C

T = 125 C

0 50 100 150

I (mA)

OUT

DV (mV)

OUT

85 C°

125 C°

25 C°

-40 C°

I (mA)

OUT

DV (mV)

OUT

0 5

1 2 34

125 C°

85 C°

25 C°

-40 C°

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6.6 Typical Characteristics

Over operating temperature range (TJ, TA= –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT =

0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701-Q1), VOUT =

2.8 V. Typical values are at TA= 25°C.

Figure 1. Load Regulation Figure 2. Load Regulation Under Light Loads

Figure 3. Line Regulation (IOUT = 5 mA) Figure 4. Line Regulation (IOUT = 150 mA)

Figure 5. Output Voltage vs Temperature Figure 6. Dropout Voltage vs Output Current

-40 65 125

T ( C)

J°

5 35-25 -10 20 50 80 95 110

I ( A)m

GND

V = 6.5 V

IN V = 4.5 V

V = 3.3 V

V = 0.4 V

600

500

400

300

200

I (mA)

GND

2.5 5.5 6.5

V (V)

3.5 4.5

T =+125 C

J°

T =+85 C

J°

T =+25 C

J°

T = 40 C-

J°

150

120

0 100 150

I (mA)

OUT

I ( A)m

GND

-40 65 125

T ( C)

J°

5 35-25 -10 20 50 80 95 110

150

120

I ( A)m

GND

I = 150 mA

OUT

I = 100 Am

OUT

300

250

200

150

100

V (mV)

-40 65 125

T ( C)

J°

5 35-25 -10 20 50 80 95 110

I = 10 mA

OUT

I = 150 mA

OUT

150

120

2.5 5.5 6.5

V (V)

I ( A)m

GND

3.5 4.5

I = 150 mA

OUT

I = 100 Am

OUT

V = 2.8 V

OUT

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Typical Characteristics (continued)

Over operating temperature range (TJ, TA= –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT =

0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701-Q1), VOUT =

2.8 V. Typical values are at TA= 25°C.

Figure 7. Dropout Voltage vs Temperature Figure 8. Ground Pin Current vs Input Voltage

Figure 9. Ground Pin Current vs Output Current Figure 10. Ground Pin Current vs Temperature (Enabled)

Figure 11. Ground Pin Current vs Temperature (Disabled) Figure 12. Current Limit vs Input Voltage

PSRR (dB)

10 100k 10M

Frequency (Hz)

1k 10k100 1M

C = 10 F

C = 10 nF

OUT

150 mA

10 mA

PSRR (dB)

10 100k 10M

Frequency (Hz)

1k 10k100 1M

C = 10 F

C = 0 nF

OUT

150 mA

10 mA

PSRR (dB)

10 100k 10M

Frequency (Hz)

1k 10k100 1M

C = 1 F

C = 10 nF

OUT

150 mA

10 mA

75 mA

PSRR (dB)

10 100k 10M

Frequency (Hz)

1k 10k100 1M

C = 10 F

C = 10 nF

OUT

150 mA

10 mA

PSRR (dB)

10 100k 10M

Frequency (Hz)

1k 10k100 1M

C = 1 F

C = 10 nF

OUT

150 mA

10 mA

75 mA

PSRR (dB)

10 100k 10M

Frequency (Hz)

1k 10k100 1M

C = 1 F

C = 10 nF

OUT

150 mA

10 mA

75 mA

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Typical Characteristics (continued)

Over operating temperature range (TJ, TA= –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT =

0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701-Q1), VOUT =

2.8 V. Typical values are at TA= 25°C.

Figure 13. Power-Supply Ripple Rejection vs Frequency

(VIN – VOUT = 1 V) Figure 14. Power-Supply Ripple Rejection vs Frequency

(VIN – VOUT = 0.5 V)

Figure 15. Power-Supply Ripple Rejection vs Frequency in

Dropout Conditions (VIN – VOUT = 0.25 V) Figure 16. Power-Supply Ripple Rejection vs Frequency

(VIN – VOUT = 1 V)

Figure 17. Power-Supply Ripple Rejection vs Frequency in

Dropout Conditions (VIN – VOUT = 0.25 V) Figure 18. Power-Supply Ripple Rejection vs Frequency

(VIN – VOUT = 1 V)

Output Noise Density ( V/ )mHz

100 10k 100k

Frequency (Hz)

C = 10 Fm

OUT

C = 1 Fm

OUT

I = 10 mA

C = 10 nF

OUT

Output Spectral Noise Density ( V/ )mHz

100 10k 100k

Frequency (Hz)

C = 0 nF

C = 1 nF

C = 10 nF

C = 100 nF

I = 10 mA

C = 1 F

OUT

OUT m

PSRR (dB)

0 2.5 4

V V (V)-

IN OUT

1 1.5 20.5 3 3.5

100 kHz

I = 150 mA

C = 1 F

C = 10 nF

OUT

1 kHz

1 MHz

10 kHz

Output Noise Density ( V/ )mHz

100 10k 100k

Frequency (Hz)

I = 150 mA

OUT

I = 10 mA

OUT

C = 1 F

C = 10 nF

OUT

PSRR (dB)

0 2.5 4

V V (V)-

IN OUT

11.5 20.5 3 3.5

1 MHz

10 kHz

1 kHz

100 kHz

I = 10 mA

C = 1 F

C = 10 nF

OUT

PSRR (dB)

0 2.5 4

V V (V)-

IN OUT

1 1.5 20.5 3 3.5

1 MHz

10 kHz

1 kHz

100 kHz

I = 75 mA

C = 1 F

C = 10 nF

OUT

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Typical Characteristics (continued)

Over operating temperature range (TJ, TA= –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT =

0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701-Q1), VOUT =

2.8 V. Typical values are at TA= 25°C.

Figure 19. Power-Supply Ripple Rejection vs (VIN – VOUT) Figure 20. Power-Supply Ripple Rejection vs (VIN – VOUT)

Figure 21. Power-Supply Ripple Rejection vs (VIN – VOUT)Figure 22. Output Spectral Noise Density vs

Output Current

Figure 23. Output Spectral Noise Density vs

Output Capacitance Figure 24. Output Spectral Noise Density vs

Noise Reduction

1 V/div

4 V/div

VOUT

VIN

C = 1 Fm

OUT

C = 10 Fm

OUT

1 V/div

6.5 V

0 V

VOUT

50 s/divm

50 ms/div

Volts

VOUT

VIN I = 150 mA

OUT

100 s/divm

1 V/div

6.5 V

10 mV/div

VIN

VOUT

= 1 V/ sm

dVIN

C = 1 F

OUT m

3.3 V

100 s/divm

50 mV/div

40 mA/div IOUT

VOUT

V = 3.3 V

150 mA

1 mA

C = 1 Fm

OUT

300

270

240

210

180

150

120

Total Noise ( V )mRMS

0 10 100

C (nF)

I = 10 mA

C = 1 F

OUT

OUT m

Total Noise ( V )mRMS

0 15 25

C ( F)

OUT m

105 20

V = 2.8 V, C = 10 nF

V = 1.3 V, C = 1 nF

OUT NR

TPS717-Q1

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Typical Characteristics (continued)

Over operating temperature range (TJ, TA= –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT =

0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701-Q1), VOUT =

2.8 V. Typical values are at TA= 25°C.

Figure 25. Total Output Noise vs Noise Reduction Figure 26. Total Output Noise vs Output Capacitance

Figure 27. Line Transient Response Figure 28. Load Transient Response

Figure 29. Turn-On Response Figure 30. Power-Up and Power-Down

OUT

GND

Current

Limit

Thermal

Shutdown

UVLO

1.20-V

Band Gap

250 kW

Quick-Start

V > 1.6 V

OUT

V 1.6 V

OUT £

0.8 V

360 kW

640 kW

2.5 Am

TPS717-Q1

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7 Detailed Description

7.1 Overview

The TPS717-Q1 family of low-dropout (LDO) regulators combines the high performance required by many RF

and precision analog applications with ultra-low current consumption. High PSRR is provided by a high-gain,

high-bandwidth error loop with good supply rejection with very low headroom (VIN – VOUT). Fixed voltage versions

provide a noise reduction pin to bypass noise generated by the band-gap reference and to improve PSRR. A

quick-start circuit fast-charges this capacitor at startup. The combination of high performance and low ground

current also make the TPS717-Q1 family of devices an excellent choice for battery-powered applications. All

versions have thermal and overcurrent protection. These devices are all also AEC-100 qualified for the grade 1

temperature range.

7.2 Functional Block Diagrams

Figure 31. Fixed Voltage Versions

OUT

GND

Current

Limit

Thermal

Shutdown

UVLO

1.20-V

Band Gap

250 kW

0.8 V

360 kW

640 kW

3.3 MW

TPS717-Q1

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Product Folder Links: TPS717-Q1

Functional Block Diagrams (continued)

Figure 32. Adjustable Voltage Version

7.3 Feature Description

7.3.1 Internal Current Limit

The TPS717-Q1 internal current limit helps protect the regulator during fault conditions. During current limit, the

output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, do

not operate the device in a current-limit state for extended periods of time.

The PMOS pass element in the TPS717-Q1 has a built-in body diode that conducts current when the voltage at

OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is

anticipated, external limiting may be appropriate.

7.3.2 Shutdown

The enable pin (EN) is active high and compatible with standard and low voltage, TTL-CMOS levels. When

shutdown capability is not required, EN can be connected to IN.

7.3.3 Startup and Noise Reduction Capacitor

Fixed voltage versions of the TPS717-Q1 use a quick-start circuit to fast-charge the noise reduction capacitor,

CNR, if present (see Figure 31). This circuit allows the combination of very low output noise and fast start-up

times. The NR pin is high impedance, so a low-leakage CNR capacitor must be used; most ceramic capacitors

are appropriate in this configuration.

Note that for fastest startup, apply VIN first, then the enable pin (EN) driven high. If EN is tied to IN, startup is

somewhat slower; see Figure 29 in the Typical Characteristics section. The quick-start switch is closed for

approximately 135 μs. To ensure that CNR is fully charged during the quick-start time, use a 0.01-μF or smaller

capacitor.

t =160 s+(540xC )

START mNRnF sm

TPS717-Q1

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Feature Description (continued)

For output voltages below 1.6 V, a voltage divider on the band-gap reference voltage is employed to optimize

output regulation performance for lower output voltages. This configuration results in an additional resistor in the

quick-start path and combined with the noise reduction capacitor (CNR) results in slower start-up times for output

voltages below 1.6 V.

Equation 1 approximates the start-up time as a function of CNR for output voltages below 1.6 V:

(1)

7.3.4 Undervoltage Lockout (UVLO)

The TPS717-Q1 uses an undervoltage lockout circuit to keep the output shut off until the internal circuitry is

operating properly. The UVLO circuit has a limited glitch immunity so undershoot transients are typically ignored

on the input if these transients are less than 5 μs in duration. Note that a slow VIN ramp can cause the output

voltage to rise when VIN is between 1.1 V to 1.4 V when at hot temperatures. When the input is lower than 1.4 V,

the UVLO circuit may not have enough headroom to keep the output fully off.

7.3.5 Minimum Load

The TPS717-Q1 is stable with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at

very light output loads. The TPS717-Q1 employs an innovative low-current mode circuit to increase loop gain

under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero

output current.

7.3.6 Thermal Protection

Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the

device to cool. When the junction temperature cools to approximately 140°C the output circuitry is again enabled.

Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit can

cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage because of

overheating.

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate

heatsink. For reliable operation, limit junction temperature to 125°C maximum. To estimate the margin of safety

in a complete design (including heatsink), increase the ambient temperature until the thermal protection is

triggered; use worst-case loads and signal conditions. For good reliability, trigger thermal protection at least 35°C

above the maximum expected ambient condition of a particular application. This configuration produces a worst-

case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.

The internal protection circuitry of the TPS717-Q1 is designed to protect against overload conditions. This

circuitry is not intended to replace proper heatsinking. Continuously running the TPS717-Q1 into thermal

shutdown degrades device reliability.

7.4 Device Functional Modes

7.4.1 Normal Operation

The device regulates to the nominal output voltage under the following conditions:

• The input voltage has previously exceeded the UVLO rising voltage and has not decreased below the UVLO

falling threshold.

• The input voltage is greater than the nominal output voltage added to the dropout voltage.

• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased

below the enable falling threshold.

• The output current is less than the current limit.

• The device junction temperature is within the specified junction temperature range.

TPS717-Q1

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Device Functional Modes (continued)

7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this condition, the output

voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is

significantly degraded because the pass device is in a triode state and no longer controls the current through the

LDO. Line or load transients in dropout can result in large output voltage deviations.

7.4.3 Disabled

The device is disabled under the following conditions:

• The input voltage is less than the UVLO falling voltage, or has not yet exceeded the UVLO rising threshold.

• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising

threshold.

• The device junction temperature is greater than the thermal shutdown temperature.

Table 1 shows the conditions that lead to the different modes of operation.

Table 1. Device Functional Mode Comparison

OPERATING MODE PARAMETER

VIN VEN IOUT TJ

Normal mode VIN > VOUT(nom) + VDO and VIN > UVLO VEN > VEN(high) IOUT < ICL TJ< 125°C

Dropout mode UVLO < VIN < VOUT(nom) + VDO VEN > VEN(high) — TJ< 165°C

Disabled mode

(any true condition disables the device) VIN < UVLO – Vhys VEN < VEN(low) — TJ> 165°C

TPS717-Q1

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS717-Q1 belongs to a family of new generation LDO regulators that use innovative circuitry to achieve

ultra-wide bandwidth and high loop gain, resulting in extremely high PSRR at very low headroom (VIN – VOUT).

Fixed voltage versions provide a noise reduction pin to bypass noise generated by the band-gap reference and

to improve PSRR when a quick-start circuit fast-charges this capacitor. These features, combined with low noise,

enable, low ground pin current, and ultra-small packaging, make this part ideal for automotive applications. This

family of regulators offers sub-band-gap output voltages, current limit, and thermal protection, and is fully

specified from –40°C to 125°C.

8.1.1 Transient Response

As with any regulator, increasing the size of the output capacitor reduces overshoot or undershoot magnitude but

increases duration of the transient. The TPS717-Q1 has an ultra-wide loop bandwidth that allows it to respond

quickly to load transient events. As with any regulator, the loop bandwidth is finite and the initial transient voltage

peak is controlled by the sizing of the output capacitor. Typically, larger output capacitors reduce the peak and

also reduce the bandwidth of the LDO, thus slowing the response time.

8.1.2 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-μF or

larger low equivalent series resistance (ESR) capacitor from IN to GND near the regulator. This capacitor

counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A

higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or if the device is

located several inches from the power source. If source impedance is not sufficiently low, a 0.1-μF input

capacitor may be necessary to ensure stability.

The TPS717-Q1 is designed to be stable with ceramic output capacitors of values 1 μF or larger. The X5R- and

X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. The

maximum ESR of the output capacitor must be less than 1 Ω. The minimum output capacitance is increased to

5μF or larger if using an R2value outside of the range of 160 kΩto 320 kΩ.

8.1.3 Dropout Voltage

The TPS717-Q1 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the

dropout voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output

resistance is the RDSon of the PMOS pass element. VDO scales approximately with output current because the

PMOS device functions as a resistor in dropout.

As with any linear regulator, PSRR and transient response are degraded when (VIN – VOUT) approaches dropout.

This effect is illustrated in Figure 15 through Figure 17 in the Typical Characteristics section.

TPS717-Q1

GNDEN NR

IN OUT

VIN VOUT

1 Fm

Ceramic

VEN

Optional 1- F input

capacitor. May improve

source impedance, noise

or PSRR.

Optional 0.01- F bypass

capacitor to reduce

output noise and

increase PSRR.

TPS71701-Q1

GND

EN FB

IN OUT

VIN VOUT

1 Fm

Ceramic

VEN

Optional 1- F input

capacitor. May improve

source impedance, noise

or PSRR.

V =

N11.5 xVOUT

mVRMS

 

D IN OUT OUTP V V I  u

TPS717-Q1

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Product Folder Links: TPS717-Q1

Application Information (continued)

8.1.4 Power Dissipation

The ability to remove heat from the die is different for each package type, presenting different considerations in

the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves

the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the

Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device.

The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.

Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of

the output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 2:

(2)

8.1.5 Output Noise

In most LDOs, the band gap is the dominant noise source. If a noise reduction capacitor (CNR) is used with the

TPS717-Q1, the band gap does not contribute significantly to noise. Instead, noise is dominated by the output

resistor divider and the error amplifier input. To minimize noise in a given application, use a 0.01-μF (minimum)

noise reduction capacitor; for the adjustable version, smaller value resistors in the output resistor divider reduce

noise. A parallel combination that gives 2.5 μA of divider current has the same noise performance as a fixed

voltage version.

Equation 3 approximates the total noise referred to the feedback point (FB pin) when CNR = 0.01 μF:

(3)

8.2 Typical Application

Figure 33 shows the basic circuit connections for the fixed voltage options. Figure 34 gives the connections for

the adjustable output version (TPS71701-Q1). Note that the NR pin is not available on the adjustable

version.

Figure 33. Typical Application Circuit

(Fixed Voltage Versions) Figure 34. Typical Application Circuit

(Adjustable Voltage Version)

SOC

PLL

COUT

GND

CIN

IN OUT

Buck Regulator TPS71701-Q1

3.3 V 2.8 V

V = V x

OUT REF

1 +

TPS717-Q1

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8.2.1 Design Requirements

Table 2 summarizes the design requirements for Figure 35.

Table 2. Design Requirements

PARAMETER DESIGN REQUIREMENT

Input voltage 3.3 V, ±10%

Output voltage 2.8 V, ±5%

Output current 100 mA typical, 150 mA peak

Output voltage transient deviation 5%

Maximum ambient temperature 85°C

8.2.2 Detailed Design Procedure

8.2.2.1 Design Considerations

For the adjustable version (TPS71701-Q1), the NR pin is replaced with a feedback (FB) pin. The voltage on this

pin sets the output voltage and is determined by the values of R1and R2. The values of R1and R2can be

calculated for any voltage using the formula given in Equation 4:

(4)

The value of R2directly affects the operation of the device and must be chosen in the range of approximately

160 kΩto 332 kΩ. Sample resistor values for common output voltages are shown in Table 3.

Table 3. Sample 1% Resistor Values For Common

Output Voltages

VOUT R1R2

1 80.6 kΩ324 kΩ

1.2 162 kΩ324 kΩ

1.5 294 kΩ332 kΩ

1.8 402 kΩ324 kΩ

2.5 665 kΩ316 kΩ

3.3 1.02 MΩ324 kΩ

5 1.74 MΩ332 kΩ

8.2.2.2 Powering a PLL Integrated on an SOC

Figure 35 shows the TPS71701-Q1 powering a phase-locked loop (PLL) that is integrated into a system-on-a-

chip (SOC).

Figure 35. Typical Application Circuit: PLL on an SOC

100 s/divm

50 mV/div

40 mA/div IOUT

VOUT

V = 3.3 V

150 mA

1 mA

C = 1 Fm

OUT

TPS717-Q1

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Product Folder Links: TPS717-Q1

8.2.2.3 Design Considerations

Use the input and output capacitors to ensure the voltage transient requirements. A 1-µF input and 1-µF output

capacitor are selected to maximize the capacitance and minimize capacitor size.

R2 is chosen to be 158 kΩfor optimal noise and PSRR, and by Equation 2, R1 is selected to be 402 kΩ. Both

R1 and R2 must be 1% tolerance resistors to meet the dc accuracy specification over line, load, and

temperature.

8.2.3 Application Curve

Figure 36. Load Transient Response

8.3 Do's and Don'ts

Do place at least one 1-µF ceramic capacitor as close as possible to both the input and output pins of the LDO.

Do not place the output capacitor more than 10 mm away from the regulator.

Do not place any components in the feedback loop except for the input, output, and feed-forward capacitor and

the feedback resistors.

Do not exceed the device absolute maximum ratings.

Do not float the enable (EN) pin.

9 Power Supply Recommendations

The TPS717-Q1 is designed to operate from an input voltage between 2.5 V and 6.5 V. The input supply must

provide adequate headroom for the device to operate in a normal mode of operation.

Connect a low output impedance power supply directly to the IN pin of the TPS717-Q1. Inductive impedances

between the input supply and the IN pin can create significant voltage excursions at the IN pin during startup or

load transient events. If inductive impedances are unavoidable, use an input capacitor. To increase the overall

PSRR of the power solution, use a pi-filter before the input of the LDO or after the FB network of the LDO.

Thermal Pad

OUT

GND

N/C

CIN

COUT

CNR

(1)

TPS717-Q1

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10 Layout

10.1 Layout Guidelines

For best overall performance, place all circuit components on the same side of the circuit board and as near as

practical to the respective LDO pin connections. Place ground return connections to the input and output

capacitor, and to the LDO ground pin as close to the GND pin as possible, connected by wide, component-side,

copper surface area. The use of vias and long traces to create LDO component connections is strongly

discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive

parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground

reference plane is also recommended and is either embedded in the printed circuit board (PCB) itself or located

on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the

output voltage, shields the LDO from noise, and functions similar to a thermal plane to spread (or sink) heat from

the LDO device when connected to the thermal pad. In most applications, this ground plane is necessary to meet

thermal requirements.

10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance

To improve ac performance (such as PSRR, output noise, and transient response), TI recommends that the

board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the

GND pin of the device. In addition, the ground connection for the bypass capacitor must connect directly to the

GND pin of the device.

10.2 Layout Examples

(1) Circles within thermal pad area indicate vias to other layers on the board.

Figure 37. Fixed Voltage Layout

Thermal Pad

OUT

GND

N/C

CIN

COUT

(1)

TPS717-Q1

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Product Folder Links: TPS717-Q1

Layout Examples (continued)

(1) Circles within thermal pad area indicate vias to other layers on the board.

Figure 38. Adjustable Voltage Layout

TPS717-Q1

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(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the

device product folder on www.ti.com.

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Evaluation Module

An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS717.

The TPS717xxEVM-134 evaluation module (and related user guide) can be requested at the Texas Instruments

website through the product folders or purchased directly from the TI eStore.

11.1.2 Device Nomenclature

Table 4. Device Nomenclature(1)

PRODUCT VOUT

TPS717xx(x)QYYYz-Q1

xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used

in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V). An 01

denotes an adjustable voltage version.

YYY is the package designator.

zis the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).

Qand -Q1 denote an automotive device that is qualified at grade 1.

11.2 Documentation Support

11.2.1 Related Documentation

PMP10651 Test Results, TIDUAE4

TPS717xxEVM-134 Evaluation Module User Guide, SLVU148

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

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11.4 Trademarks

E2E is a trademark of Texas Instruments.

Bluetooth is a registered trademark of Bluetooth SIG, Inc.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 2-Jun-2016

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TPS71701QDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 13B

TPS71709QDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SHW

TPS71709QDSERQ1 ACTIVE WSON DSE 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BD

TPS71712QDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SHX

TPS71715QDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SHY

TPS71718QDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SHZ

TPS71725QDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIA

TPS71728QDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIB

TPS71730QDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIC

TPS71733QDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SID

TPS71745QDCKRQ1 ACTIVE SC70 DCK 5 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SHF

TPS71745QDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIE

TPS71750QDRVRQ1 ACTIVE WSON DRV 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIF

TPS71750QDSERQ1 ACTIVE WSON DSE 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM AV

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

PACKAGE OPTION ADDENDUM

www.ti.com 2-Jun-2016

Addendum-Page 2

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS717-Q1 :

•Catalog: TPS717

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS71701QDRVRQ1 WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2

TPS71709QDRVRQ1 WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2

TPS71709QDSERQ1 WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2

TPS71712QDRVRQ1 WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2

TPS71715QDRVRQ1 WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2

TPS71718QDRVRQ1 WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2

TPS71725QDRVRQ1 WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2

TPS71728QDRVRQ1 WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2

TPS71730QDRVRQ1 WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2

TPS71733QDRVRQ1 WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2

TPS71745QDCKRQ1 SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3

TPS71745QDRVRQ1 WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2

TPS71750QDRVRQ1 WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2

TPS71750QDSERQ1 WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 4-Feb-2018

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS71701QDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0

TPS71709QDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0

TPS71709QDSERQ1 WSON DSE 6 3000 203.0 203.0 35.0

TPS71712QDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0

TPS71715QDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0

TPS71718QDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0

TPS71725QDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0

TPS71728QDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0

TPS71730QDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0

TPS71733QDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0

TPS71745QDCKRQ1 SC70 DCK 5 3000 180.0 180.0 18.0

TPS71745QDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0

TPS71750QDRVRQ1 WSON DRV 6 3000 203.0 203.0 35.0

TPS71750QDSERQ1 WSON DSE 6 3000 203.0 203.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 4-Feb-2018

Pack Materials-Page 2

GENERIC PACKAGE VIEW

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

DRV 6 WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

4206925/F

www.ti.com

PACKAGE OUTLINE

6X 0.35

0.25

1.6 0.1

6X 0.3

0.2

1.3

1 0.1

4X 0.65

0.8

0.7

0.05

0.00

B2.1

1.9 A

2.1

1.9

(0.2) TYP

WSON - 0.8 mm max heightDRV0006A

PLASTIC SMALL OUTLINE - NO LEAD

4222173/B 04/2018

PIN 1 INDEX AREA

SEATING PLANE

0.08 C

(OPTIONAL)

PIN 1 ID 0.1 C A B

0.05 C

THERMAL PAD

EXPOSED

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 5.500

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

(1)

4X (0.65)

(1.95)

6X (0.3)

6X (0.45)

(1.6)

(R0.05) TYP

( 0.2) VIA

TYP

(1.1)

WSON - 0.8 mm max heightDRV0006A

PLASTIC SMALL OUTLINE - NO LEAD

4222173/B 04/2018

SYMM

LAND PATTERN EXAMPLE

SCALE:25X

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

SOLDER MASK

OPENING

SOLDER MASK

METAL UNDER

SOLDER MASK

DEFINED

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

www.ti.com

EXAMPLE STENCIL DESIGN

6X (0.3)

6X (0.45)

4X (0.65) (0.7)

(1)

(1.95)

(R0.05) TYP

(0.45)

WSON - 0.8 mm max heightDRV0006A

PLASTIC SMALL OUTLINE - NO LEAD

4222173/B 04/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD #7

88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:30X

SYMM

METAL

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Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

TPS71750QDSERQ1 TPS71709QDSERQ1 TPS71745QDCKRQ1 TPS71712QDRVRQ1 TPS71715QDRVRQ1

TPS71718QDRVRQ1 TPS71725QDRVRQ1 TPS71728QDRVRQ1 TPS71730QDRVRQ1 TPS71733QDRVRQ1

TPS71745QDRVRQ1 TPS71750QDRVRQ1 TPS71709QDRVRQ1 TPS71701QDRVRQ1