SST25VF020-20-4C-SAE - MICROCHIP

Microchip Technology Company

Not Recommended for New Designs

www.microchip.com

Features

• Single 2.7-3.6V Read and Write Operations

• Serial Interface Architecture

– SPI Compatible: Mode 0 and Mode 3

• 20 MHz Max Clock Frequency

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption:

– Active Read Current: 7 mA (typical)

– Standby Current: 8 µA (typical)

• Flexible Erase Capability

– Uniform 4 KByte sectors

– Uniform 32 KByte overlay blocks

• Fast Erase and Byte-Program:

– Chip-Erase Time: 70 ms (typical)

– Sector- or Block-Erase Time: 18 ms (typical)

– Byte-Program Time: 14 µs (typical)

• Auto Address Increment (AAI) Programming

– Decrease total chip programming time over Byte-Pro-

gram operations

• End-of-Write Detection

– Software Status

• Hold Pin (HOLD#)

– Suspends a serial sequence to the memory

without deselecting the device

• Write Protection (WP#)

– Enables/Disables the Lock-Down function of the status

• Software Write Protection

– Write protection through Block-Protection bits in status

• Temperature Range

– Commercial: 0°C to +70°C

– Industrial: -40°C to +85°C

– Extended: -20°C to +85°C

• Packages Available

– 8-lead SOIC 150 mil body width

– 8-contact WSON (5mm x 6mm)

• All non-Pb (lead-free) devices are RoHS compliant

2 Mbit SPI Serial Flash

SST25VF020

SST's serial flash family features a four-wire, SPI-compatible interface that allows

for a low pin-count package occupying less board space and ultimately lowering

total system costs. SST25VF020 SPI serial flash memory is manufactured with

SST proprietary, high performance CMOS SuperFlash Technology. The split-gate

cell design and thick-oxide tunneling injector attain better reliability and manufac-

turability compared with alternate approaches.

Not recommended for new designs.

Please use SST25VF020B

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Product Description

The SST serial flash family features a four-wire, SPI-compatible interface that allows for a low pin-

count package occupying less board space and ultimately lowering total system costs. SST25VF020

SPI serial flash memories are manufactured with SST’s proprietary, high performance CMOS Super-

Flash Technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability

and manufacturability compared with alternate approaches.

The SST25VF020 device significantly improves performance, while lowering power consumption. The

total energy consumed is a function of the applied voltage, current, and time of application. Since for

any given voltage range, the SuperFlash technology uses less current to program and has a shorter

erase time, the total energy consumed during any Erase or Program operation is less than alternative

flash memory technologies. The SST25VF020 device operates with a single 2.7-3.6V power supply.

The SST25VF020 device is offered in an 8-lead SOIC 150 mil body width (SA) package, and in an 8-

contact WSON package. See Figure 2 for the pin assignments.

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Block Diagram

Figure 1: Functional Block Diagram

1231 B1.0

I/O Buffers

and

Data Latches

SuperFlash

Memory

X - Decoder

Control Logic

Address

Buffers

and

Latches

CE#

Y - Decoder

SCK SI SO WP# HOLD#

Serial Interface

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Pin Description

Figure 2: Pin Assignments

Table 1: Pin Description

Symbol Pin Name Functions

SCK Serial Clock To provide the timing of the serial interface.

Commands, addresses, or input data are latched on the rising edge of the clock input,

while output data is shifted out on the falling edge of the clock input.

SI Serial Data

Input

To transfer commands, addresses, or data serially into the device.

Inputs are latched on the rising edge of the serial clock.

SO Serial Data

Output

To transfer data serially out of the device.

Data is shifted out on the falling edge of the serial clock.

CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the

duration of any command sequence.

WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.

HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the

device.

VDD Power Supply To provide power supply (2.7-3.6V).

VSS Ground

T1.0 25078

8-lead SOIC 8-contact WSON

CE#

WP#

VSS

Top View

VDD

HOLD#

SCK

1231 08-wson P2.0

CE#

WP#

VSS

VDD

HOLD#

SCK

Top View

1231 08-soic P1.0

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Memory Organization

The SST25VF020 SuperFlash memory array is organized in 4 KByte sectors with 32 KByte overlay

blocks.

Device Operation

The SST25VF020 is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.

The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is

accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).

The SST25VF020 supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference

between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in

Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is

high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock

signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.

Figure 3: SPI Protocol

1231 F02.1

MODE 3

SCK

CE#

MODE 3

DON T CARE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0MODE 0

HIGH IMPEDANCE

MSB

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Hold Operation

HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without resetting

the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD#

mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The

HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state.

If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device

enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the

HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode

when the SCK next reaches the active low state. See Figure 4 for Hold Condition waveform.

Once the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be VIL or

VIH.

If CE# is driven active high during a Hold condition, it returns the device to standby mode. As long as

HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the

device, HOLD# must be driven active high, and CE# must be driven active low. See Figure 18 for Hold

timing.

Figure 4: Hold Condition Waveform

Write Protection

SST25VF020 provides software Write protection. The Write Protect pin (WP#) enables or disables the

lock-down function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status

Protection description.

Write Protect Pin (WP#)

The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register.

When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined

by the value of the BPL bit (see Table 2). When WP# is high, the lock-down function of the BPL bit is

disabled.

Table 2: Conditions to execute Write-Status-Register (WRSR) Instruction

WP# BPL Execute WRSR Instruction

L 1 Not Allowed

L 0 Allowed

H X Allowed

T2.0 25078

Active Hold Active Hold Active

1231 F03.0

SCK

HOLD#

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Status Register

The software status register provides status on whether the flash memory array is available for any

Read or Write operation, whether the device is Write enabled, and the state of the memory Write pro-

tection. During an internal Erase or Program operation, the status register may be read only to deter-

mine the completion of an operation in progress. Table 3 describes the function of each bit in the

software status register.

Busy

The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for

the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is

ready for the next valid operation.

Write Enable Latch (WEL)

The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the

Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset),

it indicates the device is not Write enabled and does not accept any memory Write (Program/Erase)

commands. The Write-Enable-Latch bit is automatically reset under the following conditions:

•Power-up

•Write-Disable (WRDI) instruction completion

•Byte-Program instruction completion

•Auto Address Increment (AAI) programming reached its highest memory address

•Sector-Erase instruction completion

•Block-Erase instruction completion

•Chip-Erase instruction completion

Table 3: Software Status Register

Bit Name Function

Default at

Power-up Read/Write

0 BUSY 1 = Internal Write operation is in progress

0 = No internal Write operation is in progress

1 WEL 1 = Device is memory Write enabled

0 = Device is not memory Write enabled

2 BP0 Indicate current level of block write protection (See Table 4) 1 R/W

3 BP1 Indicate current level of block write protection (See Table 4) 1 R/W

4:5 RES Reserved for future use 0 N/A

6 AAI Auto Address Increment Programming status

1 = AAI programming mode

0 = Byte-Program mode

7 BPL 1 = BP1, BP0 are read-only bits

0 = BP1, BP0 are read/writable

0 R/W

T3.0 25078

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Block Protection (BP1, BP0)

The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table 4, to be

software protected against any memory Write (Program or Erase) operations. The Write-Status-Regis-

ter (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-

Protect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are both 0. After

power-up, BP1 and BP0 are set to 1.

Block Protection Lock-Down (BPL)

WP# pin driven low (VIL), enables the Block-Protection-Lock-Down (BPL) bit. When BPL is set to 1, it

prevents any further alteration of the BPL, BP1, and BP0 bits. When the WP# pin is driven high (VIH),

the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0.

Auto Address Increment (AAI)

The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI

programming mode or Byte-Program mode. The default at power up is Byte-Program mode.

Table 4: Software Status Register Block Protection1

1. Default at power-up for BP1 and BP0 is ‘11’.

Protection Level

Status

Bit

Protected Memory Area

BP1 BP0 2 Mbit

0 0 0 None

1 (1/4 Memory Array) 0 1 030000H-03FFFFH

2 (1/2 Memory Array) 1 0 020000H-03FFFFH

3 (Full Memory Array) 1 1 000000H-03FFFFH

T4.0 25078

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Instructions

Instructions are used to Read, Write (Erase and Program), and configure the SST25VF020. The

instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut-

ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or

Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list

of the instructions is provided in Table 5. All instructions are synchronized off a high to low transition of

CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must

be driven low before an instruction is entered and must be driven high after the last bit of the instruction

has been shifted in (except for Read, Read-ID and Read-Status-Register instructions). Any low to high

transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction

in progress and return the device to the standby mode. Instruction commands (Op Code), addresses,

and data are all input from the most significant bit (MSB) first.

Table 5: Device Operation Instructions1

1. AMS = Most Significant Address

AMS =A

17 for SST25VF020

Address bits above the most significant bit of each density can be VIL or VIH

Bus Cycle2

2. One bus cycle is eight clock periods.

123 4 5

Cycle Type/Operation3,4

3. Operation: SIN = Serial In, SOUT = Serial Out

4. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary)

SIN SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT

Read 03H Hi-Z A23-

A16

Hi-Z A15-

Hi-Z A7-A0Hi-Z X DOUT

Sector-Erase5,6

5. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH

6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable

(WREN) instruction must be executed.

20H Hi-Z A23-

A16

Hi-Z A15-

Hi-Z A7-A0Hi-Z - -

Block-Erase5,7

7. Block addresses for: use AMS-A15, remaining addresses can be VIL or VIH

52H Hi-Z A23-

A16

Hi-Z A15-

Hi-Z A7-A0Hi-Z - -

Chip-Erase660H Hi-Z - - - - - - - -

Byte-Program602H Hi-Z A23-

A16

Hi-Z A15-

Hi-Z A7-A0Hi-Z DI

Hi-Z

Auto Address Increment (AAI)

Program6,8

8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,

followed by the data to be programmed.

AFH Hi-Z A23-

A16

Hi-Z A15-

Hi-Z A7-A0Hi-Z DI

Hi-Z

Read-Status-Register (RDSR) 05H Hi-Z X DOU

- Note

9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.

- Note

- Note9

Enable-Write-Status-Register

(EWSR)10

50H Hi-Z - - - - - - - -

Write-Status-Register

(WRSR)10

01H Hi-Z Data Hi-Z - - -. - - -

Write-Enable (WREN) 06H Hi-Z - - - - - - - -

Write-Disable (WRDI) 04H Hi-Z - - - - - - - -

Read-ID 90H or

ABH

Hi-Z 00H Hi-Z 00H Hi-Z ID

Addr11

Hi-Z X DOUT

T5.0 25078

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Read

The Read instruction outputs the data starting from the specified address location. The data output

stream is continuous through all addresses until terminated by a low to high transition on CE#. The

internal address pointer will automatically increment until the highest memory address is reached.

Once the highest memory address is reached, the address pointer will automatically increment to the

beginning (wrap-around) of the address space, i.e. for 2 Mbit density, once the data from address loca-

tion 3FFFFH had been read, the next output will be from address location 00000H.

The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23-

A0]. CE# must remain active low for the duration of the Read cycle. See Figure 5 for the Read

sequence.

Figure 5: Read Sequence

10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in

conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR

instruction to make both instructions effective.

11. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s

and Device ID output stream is continuous until terminated by a low to high transition on CE#

12. Device ID = 43H for SST25VF020

1231 F04.1

CE#

SCK

ADD.

012345678

ADD. ADD.

HIGH IMPEDANCE

15 16 23 24 31 32 39 40 7047 48 55 56 63 64

N+2 N+3 N+4N N+1

DOUT

MSB MSB

MSB

MODE 0

MODE 3

DOUT DOUT DOUT DOUT

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Byte-Program

The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected

byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction

applied to a protected memory area will be ignored.

Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain

active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by

executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is

input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is exe-

cuted. The user may poll the Busy bit in the software status register or wait TBP for the completion of

the internal self-timed Byte-Program operation. See Figure 6 for the Byte-Program sequence.

Figure 6: Byte-Program Sequence

1231 F05.1

CE#

SCK

ADD.

012345678

ADD. ADD. DIN

HIGH IMPEDANCE

15 16 23 24 31 32 39

MODE 0

MODE 3

MSBMSB

MSB LSB

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Auto Address Increment (AAI) Program

The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the

next sequential address location. This feature decreases total programming time when the entire mem-

ory array is to be programmed. An AAI program instruction pointing to a protected memory area will be

ignored. The selected address range must be in the erased state (FFH) when initiating an AAI program

instruction.

Prior to any write operation, the Write-Enable (WREN) instruction must be executed. The AAI program

instruction is initiated by executing an 8-bit command, AFH, followed by address bits [A23-A0]. Follow-

ing the addresses, the data is input sequentially from MSB (bit 7) to LSB (bit 0). CE# must be driven

high before the AAI program instruction is executed. The user must poll the BUSY bit in the software

status register or wait TBP for the completion of each internal self-timed Byte-Program cycle. Once the

device completes programming byte, the next sequential address may be program, enter the 8-bit

command, AFH, followed by the data to be programmed. When the last desired byte had been pro-

grammed, execute the Write-Disable (WRDI) instruction, 04H, to terminate AAI. After execution of the

WRDI command, the user must poll the Status register to ensure the device completes programming.

See Figure 7 for AAI programming sequence.

There is no wrap mode during AAI programming; once the highest unprotected memory address is

reached, the device will exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0).

Figure 7: Auto Address Increment (AAI) Program Sequence

CE#

SCK

A[23:16] A[15:8] A[7:0]

AF Data Byte 1 AF DataByte2

CE#

SCK

Write Disable (WRDI)

Instruction to terminate

AAI Operation

Read Status Register (RDSR)

Instruction to verify end of

AAI Operation

04Last Data ByteAF 05

DOUT

MODE 3

MODE 0

TBP TBP

TBP

1231 F06.1

012345678 323334353637383915 16 23 24 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 01

012345670123456789101112131415 0123456789101112131415

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Sector-Erase

The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase

instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-

Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the any

command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, fol-

lowed by address bits [A23-A0]. Address bits [AMS-A12](A

MS = Most Significant address) are used to

determine the sector address (SAX), remaining address bits can be VIL or VIH. CE# must be driven high

before the instruction is executed. The user may poll the Busy bit in the software status register or wait

TSE for the completion of the internal self-timed Sector-Erase cycle. See Figure 8 for the Sector-Erase

sequence.

Figure 8: Sector-Erase Sequence

Block-Erase

The Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-Erase

instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-

Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any com-

mand sequence. The Block-Erase instruction is initiated by executing an 8-bit command, 52H, followed

by address bits [A23-A0]. Address bits [AMS-A15](A

MS = Most significant address) are used to deter-

mine block address (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before the

instruction is executed. The user may poll the Busy bit in the software status register or wait TBE for the com-

pletion of the internal self-timed Block-Erase cycle. See Figure 9 for the Block-Erase sequence.

Figure 9: Block-Erase Sequence

CE#

SCK

ADD.

012345678

ADD. ADD.

HIGH IMPEDANCE

15 16 23 24 31

MODE 0

MODE 3

1231 F07.1

MSBMSB

CE#

SCK

ADD.

012345678

ADD. ADD.

HIGH IMPEDANCE

15 16 23 24 31

MODE 0

MODE 3

1231 F08.1

MSB MSB

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Chip-Erase

The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored

if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction

must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence.

The Chip-Erase instruction is initiated by executing an 8-bit command, 60H. CE# must be driven high

before the instruction is executed. The user may poll the Busy bit in the software status register or wait TCE

for the completion of the internal self-timed Chip-Erase cycle. See Figure 10 for the Chip-Erase

sequence.

Figure 10:Chip-Erase Sequence

Read-Status-Register (RDSR)

The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register

may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in

progress, the Busy bit may be checked before sending any new commands to assure that the new

commands are properly received by the device. CE# must be driven low before the RDSR instruction is

entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing

clock cycles until it is terminated by a low to high transition of the CE#. See Figure 11 for the RDSR

instruction sequence.

Figure 11:Read-Status-Register (RDSR) Sequence

CE#

SCK

01234567

HIGH IMPEDANCE

MODE 0

MODE 3

1231 F09.1

MSB

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

1231 F10.1

MODE 3

SCK

CE#

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0

HIGH IMPEDANCE

Status

MSB

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Write-Enable (WREN)

The Write-Enable (WREN) instruction sets the Write-Enable-Latch bit to 1 allowing Write operations to

occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE#

must be driven high before the WREN instruction is executed.

Figure 12:Write Enable (WREN) Sequence

Write-Disable (WRDI)

The Write-Disable (WRDI) instruction resets the Write-Enable-Latch bit and AAI bit to 0 disabling any

new Write operations from occurring. CE# must be driven high before the WRDI instruction is exe-

cuted.

Figure 13:Write Disable (WRDI) Sequence

Enable-Write-Status-Register (EWSR)

The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR)

instruction and opens the status register for alteration. The Enable-Write-Status-Register instruction

does not have any effect and will be wasted, if it is not followed immediately by the Write-Status-Regis-

ter (WRSR) instruction. CE# must be driven low before the EWSR instruction is entered and must be

driven high before the EWSR instruction is executed.

CE#

SCK

01234567

HIGH IMPEDANCE

MODE 0

MODE 3

1231 F11.1

MSB

CE#

SCK

01234567

HIGH IMPEDANCE

MODE 0

MODE 3

1231 F12.1

MSB

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Write-Status-Register (WRSR)

The Write-Status-Register instruction works in conjunction with the Enable-Write-Status-Register

(EWSR) instruction to write new values to the BP1, BP0, and BPL bits of the status register. The Write-

Status-Register instruction must be executed immediately after the execution of the Enable-Write-Sta-

tus-Register instruction (very next instruction bus cycle). This two-step instruction sequence of the

EWSR instruction followed by the WRSR instruction works like SDP (software data protection) com-

mand structure which prevents any accidental alteration of the status register values. The Write-Sta-

tus-Register instruction will be ignored when WP# is low and BPL bit is set to “1”. When the WP# is

low, the BPL bit can only be set from “0” to “1” to lock-down the status register, but cannot be reset

from “1” to “0”. When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0,

and BP1 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP# pin is

driven high (VIH) prior to the low-to-high transition of the CE# pin at the end of the WRSR instruction,

the BP0, BP1, and BPL bit in the status register can all be altered by the WRSR instruction. In this

case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as

altering the BP0 and BP1 bit at the same time. See Table 2 for a summary description of WP# and BPL

functions. CE# must be driven low before the command sequence of the WRSR instruction is entered

and driven high before the WRSR instruction is executed. See Figure 14 for EWSR and WRSR instruc-

tion sequences.

Figure 14:Enable-Write-Status-Register (EWSR) and Write-Status-Register (WRSR)

Sequence

1231 F13.1

MODE 3

HIGH IMPEDANCE

MODE 0

STATUS

76543210

MSBMSBMSB

MODE 3

SCK

CE#

MODE 0

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Read-ID

The Read-ID instruction identifies the device as SST25VF020 and manufacturer as SST. The device

information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A23-

A0]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H and the

device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer’s and

device ID output data toggles between address 00000H and 00001H until terminated by a low to high

transition on CE#.

Figure 15:Read-ID Sequence

Table 6: Product Identification

Address Data

Manufacturer’s ID 00000H BFH

Device ID

SST25VF020 00001H 43H

T6.0 25078

1231 F14.1

CE#

SCK

012345678

00 ADD1

90 or AB

HIGH IMPEDANCE

15 16 23 24 31 32 39 40 47 48 55 56 63

BF Device ID BF Device ID

Note: The manufacturer s and device ID output stream is continuous until terminated by a low to high transition on CE#.

1. 00H will output the manfacturer s ID first and 01H will output device ID first before toggling between the two.

HIGH

IMPEDANCE

MODE 3

MODE 0

MSB MSB

MSB

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Electrical Specifications

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute

Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these conditions or conditions greater than those defined in the

operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating con-

ditions may affect device reliability.)

Temperature Under Bias .............................................. -55°C to +125°C

Storage Temperature................................................. -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential .............................-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential ..................-2.0V to VDD+2.0V

Package Power Dissipation Capability (Ta = 25°C)................................... 1.0W

Surface Mount Solder Reflow Temperature ...........................260°C for 10 seconds

Output Short Circuit Current1................................................... 50mA

1. Output shorted for no more than one second. No more than one output shorted at a time.

Table 7: Operating Range

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V

Industrial -40°C to +85°C 2.7-3.6V

Extended -20°C to +85°C 2.7-3.6V

T7.1 25078

Table 8: AC Conditions of Test1

1. See Figures 20 and 21

Input Rise/Fall Time Output Load

5ns CL=30pF

T8.1 25078

Table 9: DC Operating Characteristics VDD = 2.7-3.6V

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDDR Read Current 10 mA CE#=0.1 VDD/0.9 VDD@20 MHz, SO=open

IDDW Program and Erase Current 30 mA CE#=VDD

ISB Standby Current 15 µA CE#=VDD,V

IN=VDD or VSS

ILI Input Leakage Current 1 µA VIN=GND to VDD,V

DD=VDD Max

ILO Output Leakage Current 1 µA VOUT=GND to VDD,V

DD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 0.7 VDD VV

DD=VDD Max

VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

T9.0 25078

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Table 10:Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

VDD Min to Read Operation 10 µs

TPU-WRITE1VDD Min to Write Operation 10 µs

T10.0 25078

Table 11:Capacitance (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

COUT1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

Output Pin Capacitance VOUT =0V 12pF

CIN1Input Capacitance VIN =0V 6pF

T11.0 25078

Table 12:Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T12.0 25078

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Table 13:AC Operating Characteristics VDD = 2.7-3.6V

Symbol Parameter

Limits

Min Max Units

FCLK Serial Clock Frequency 20 MHz

TSCKH Serial Clock High Time 20 ns

TSCKL Serial Clock Low Time 20 ns

TSCKR Serial Clock Rise Time 5 ns

TSCKF Serial Clock Fall Time 5 ns

TCES1CE# Active Setup Time 20 ns

TCEH1CE# Active Hold Time 20 ns

TCHS1CE# Not Active Setup Time 10 ns

TCHH1CE# Not Active Hold Time 10 ns

TCPH CE# High Time 100 ns

TCHZ CE# High to High-Z Output 20 ns

TCLZ SCK Low to Low-Z Output 0 ns

TDS Data In Setup Time 4 ns

TDH Data In Hold Time 5 ns

THLS HOLD# Low Setup Time 10 ns

THHS HOLD# High Setup Time 10 ns

THLH HOLD# Low Hold Time 15 ns

THHH HOLD# High Hold Time 10 ns

THZ HOLD# Low to High-Z Output 20 ns

TLZ HOLD# High to Low-Z Output 20 ns

TOH Output Hold from SCK Change 0 ns

TVOutput Valid from SCK 23 ns

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 100 ms

TBP Byte-Program 20 µs

T13.2 25078

1. Relative to SCK.

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Figure 16:Serial Input Timing Diagram

Figure 17:Serial Output Timing Diagram

HIGH-Z HIGH-Z

CE#

SCK

MSB LSB

TDS TDH

TCHH TCES TCEH TCHS

TSCKR

TSCKF

TCPH

1231 F15.0

1231 F16.0

CE#

SCK

MSB

TCLZ

TSCKH

TCHZ

TOH

TSCKL

LSB

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Figure 18:Hold Timing Diagram

Figure 19:Power-up Timing Diagram

THZ TLZ

THHH THLS

THLH

THHS

1231 F17.0

HOLD#

CE#

SCK

Time

VDD Min

VDD Max

VDD

Device fully accessible

TPU-READ

TPU-WRITE

Chip selection is not allowed.

All commands are rejected by the device.

1231 F18.0

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Figure 20:AC Input/Output Reference Waveforms

Figure 21:A Test Load Example

1231 F19.1

REFERENCE POINTS OUTPUTINPUT

VHT

VLT

VHT

VLT

VIHT

VILT

AC test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”. Measure-

ment reference points for inputs and outputs are VHT (0.7VDD) and VLT (0.3VDD). Input rise and fall

times (10% 90%) are <5 ns.

Note: VHT -V

HIGH Test

VLT -V

LOW Test

VIHT -V

INPUT HIGH Test

VILT -V

INPUT LOW Test

1231 F20.0

TO TESTER

TO DUT

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Product Ordering Information

Valid combinations for SST25VF020

SST25VF020-20-4C-SAE SST25VF020-20-4C-QAE

SST25VF020-20-4I-SAE SST25VF020-20-4I-QAE

SST25VF020-20-4E-SAE SST25VF020-20-4E-QAE

Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST

sales representative to confirm availability of valid combinations and to determine availability of new combi-

nations.

SST 25 VF 020 - 20 - 4I - QAE

XX XX XXX - XX - XX -XXX

Environmental Attribute

E1= non-Pb

Package Modifier

A = 8 leads or contacts

Package Type

S = SOIC 150 mil body width

Q = WSON

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

E = Extended = -20°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Operating Frequency

20 = 20 MHz

Device Density

020 = 2 Mbit

Voltage

V = 2.7-3.6V

Product Series

25 = Serial Peripheral Interface

flash memory

1. Environmental suffix “E” denotes non-Pb sol-

der. SST non-Pb solder devices are “RoHS

Compliant”.

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Packaging Diagrams

Figure 22: 8-lead Small Outline Integrated Circuit (SOIC) 150 mil body width (4.9mm x 6mm)

SST Package Code: SA

08-soic-5x6-SA-8

Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.

TOP VIEW SIDE VIEW

END VIEW

5.0

4.8

6.20

5.80

4.00

3.80

Pin #1

Identifier

0.51

0.33

1.27 BSC

0.25

0.10

1.75

1.35

7°

4 places

0.25

0.19

1.27

0.40

45° 7°

4 places

0°

8°

1mm

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Figure 23:8-contact Very-very-thin Small Outline No-lead (WSON)

SST Package Code: QA

Note: 1. All linear dimensions are in millimeters (max/min).

2. Untoleranced dimensions (shown with box surround)

are nominal target dimensions.

3. The external paddle is electrically connected to the

die back-side and possibly to certain VSS leads.

This paddle can be soldered to the PC board;

it is suggested to connect this paddle to the VSS of the unit.

Connection of this paddle to any other voltage potential can

result in shorts and/or electrical malfunction of the device.

8-wson-5x6-QA-9.0

4.0

1.27 BSC

Pin #1

0.48

0.35

0.076

3.4

5.00 ±0.10

6.00 ± 0.10 0.05 Max

0.70

0.50

0.80

0.70

0.80

0.70

Pin #1

Corner

TOP VIEW BOTTOM VIEW

CROSS SECTION

SIDE VIEW

1mm

0.2

2 Mbit SPI Serial Flash

SST25VF020

Not Recommended for New Designs

Microchip Technology Company

Table 14:Revision History

Revision Description Date

00 •Initial release of S71231

(2 Mbit and 4 Mbit parts were originally described in data sheet S71192)

Apr 2003

01 •Updated Figures 3, 5 - 15: Aligned SI waveform with rising edge of clock Aug 2003

02 •Added new 8-SOIC (S2A) package and associated MPNs Oct 2003

03 •2004 Data Book

•Updated the Package Outline for S2A

Dec 2003

04 •Added Extended temperature and associated MPNs Jun 2004

05 •Revised Absolute Max. Stress Ratings for Surface Mount Solder Reflow

Temp.

Nov 2005

06 •Updated QA package drawing to revision 9.

•Removed leaded parts.

•Added footnote to product ordering section.

Jan 2006

07 •Removed all references to SST25VF040 due to end of life. New

SST25VF040 EOL data sheet is S71231(04).

•Revised Hold Operation, page 6 paragraph 4, to indicate that device

returns to standby mode when CE# is driven active high during a Hold

Condition.

Oct 2006

A•Applied new document format

•Released document under letter revision system

•Updated spec number from S71231 to DS25078

Nov 2011

SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Tech-

nology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and

registered trademarks mentioned herein are the property of their respective owners.

Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current

package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.

Memory sizes denote raw storage capacity; actual usable capacity may be less.

SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of

Sale.

For sales office locations and information, please see www.microchip.com.

Silicon Storage Technology, Inc.

A Microchip Technology Company

www.microchip.com

ISBN:978-1-61341-680-8