2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM MT58LC128K18B4, MT58LC64K32B4, MT58LC64K36B4; MT58LC128K18E1, MT58LC64K32E1, MT58LC64K36E1 2Mb SYNCBURSTTM SRAM 3.3V VDD, 3.3V or 2.5V I/O, Flow-Through FEATURES * Fast clock and OE# access times * Single +3.3V +0.3V/-0.165V power supply (VDD) * Separate +3.3V or +2.5V isolated output buffer supply (VDDQ) * SNOOZE MODE for reduced-power standby * Common data inputs and data outputs * Individual BYTE WRITE control and GLOBAL WRITE * Three chip enables for simple depth expansion and address pipelining * Clock-controlled and registered addresses, data I/Os and control signals * Internally self-timed WRITE cycle * Burst control pin (interleaved or linear burst) * Automatic power-down for portable applications * 100-lead TQFP package for high density, high speed * Low capacitive bus loading * x18, x32 and x36 versions available OPTIONS * Timing (Access/Cycle/MHz) 7.5ns/8.8ns/113 MHz 8.5ns/10ns/100 MHz 9ns/10.5ns/95 MHz 10ns/15ns/66 MHz * Configurations 3.3V I/O 128K x 18 64K x 32 64K x 36 2.5V I/O 128K x 18 64K x 32 64K x 36 * Package 100-pin TQFP 100-Pin TQFP* (D-1) *JEDEC-standard MS-026 BHA (LQFP). MARKING -7.5 -8.5 -9 -10 peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE#), two additional chip enables for easy depth expansion (CE2, CE2#), burst control inputs (ADSC#, ADSP#, ADV#), byte write enables (BWx#) and global write (GW#). Asynchronous inputs include the output enable (OE#), snooze enable (ZZ) and clock (CLK). There is also a burst mode pin (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE#, is also asynchronous. WRITE cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP#) or address status controller (ADSC#) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV#). Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on the x18 device, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb. During WRITE cycles on the x32 and x36 devices, BWa# MT58LC128K18B4 MT58LC64K32B4 MT58LC64K36B4 MT58LC128K18E1 MT58LC64K32E1 MT58LC64K36E1 LG * Part Number Example: MT58LC64K36B4LG-8.5 GENERAL DESCRIPTION The Micron(R) SyncBurstTM SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. Micron's 2Mb SyncBurst SRAMs integrate a 128K x 18, 64K x 32, or 64K x 36 SRAM core with advanced synchronous 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Y12.p65 - Rev. 3/99 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. All registered and unregistered trademarks are the sole property of their respective companies. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM FUNCTIONAL BLOCK DIAGRAM 128K x 18 17 15 17 ADDRESS REGISTER SA0, SA1, SA 2 MODE 17 SA0-SA1 SA1' BINARY Q1 COUNTER AND LOGIC CLR Q0 ADV# CLK SA0' ADSC# ADSP# BYTE "b" WRITE REGISTER BWb# 9 9 BYTE "a" WRITE REGISTER BWa# BYTE "b" WRITE DRIVER BYTE "a" WRITE DRIVER 9 128K x 9 x 2 MEMORY ARRAY 18 SENSE 18 AMPS OUTPUT BUFFERS 18 9 DQs DQPa DQPb BWE# GW# INPUT REGISTERS 18 ENABLE REGISTER CE# CE2 CE2# 2 OE# FUNCTIONAL BLOCK DIAGRAM 64K x 32/36 16 ADDRESS REGISTER SA0, SA1, SA 16 14 16 SA0-SA1 MODE BINARY Q1 SA1' COUNTER AND LOGIC Q0 CLR SA0' ADV# CLK ADSC# ADSP# BWd# BYTE "d" WRITE REGISTER BYTE "d" WRITE DRIVER BWc# BYTE "c" WRITE REGISTER BYTE "c" WRITE DRIVER BWb# BYTE "b" WRITE REGISTER BWa# BWE# BYTE "a" WRITE REGISTER 64K x 8 x 4 (x32) 64K x 9 x 4 (x36) BYTE "b" WRITE DRIVER SENSE AMPS OUTPUT BUFFERS MEMORY ARRAY BYTE "a" WRITE DRIVER INPUT REGISTERS GW# ENABLE REGISTER CE# CE2 CE2# OE# NOTE: DQs 4 Functional Block Diagrams illustrate simplified device operation. See Truth Table, Pin Descriptions and timing diagrams for detailed information. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Y12.p65 - Rev. 3/99 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM GENERAL DESCRIPTION (continued) controls DQa pins and DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins and DQPc; BWd# controls DQd pins and DQPd. GW# LOW causes all bytes to be written. Parity bits are only available on the x18 and x36 versions. Micron's 2Mb SyncBurst SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are TTLcompatible. Users can choose either a 3.3V or 2.5V I/O version. The device is ideally suited for 486, Pentium(R), 680X0 and PowerPC systems and systems that benefit from a very wide data bus. The device is also ideal in generic 16-, 18-, 32-, 36-, 64- and 72-bit-wide applications. Please refer to the Micron Web site (www.micron.com/ mti/msp/html/sramprod.html) for the latest full-length data sheet. TQFP PIN ASSIGNMENT TABLE PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 x18 NC NC NC NC NC DQb DQb DQb DQb DQb DQb DQb DQb DQPb NC x32/x36 NC/DQPc** DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VSS VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd PIN # 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 x18 x32/x36 VSS VDDQ NC DQd NC DQd NC NC/DQPd** MODE SA SA SA SA SA1 SA0 DNU DNU VSS VDD DNU DNU SA SA SA SA SA SA NC/SA* PIN # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 x18 NC NC NC NC NC DQa DQa DQa DQa DQPa NC x32/x36 NC/DQPa** DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa ZZ VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQb DQb PIN # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 x18 NC NC SA NC NC x32/x36 VSS VDDQ DQb DQb NC/DQPb** SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD CE2# BWa# BWb# BWc# BWd# CE2 CE# SA SA * Pin 50 is reserved for address expansion. ** No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Y12.p65 - Rev. 3/99 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM SA NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC PIN ASSIGNMENT (Top View) 100-Pin TQFP (D-1) SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD CE2# BWa# BWb# NC NC CE2 CE# SA SA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD CE2# BWa# BWb# BWc# BWd# CE2 CE# SA SA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC/DQPb** DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NC/DQPa** NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VSS VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC x18 NC/SA* SA SA SA SA SA SA DNU DNU VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE NC/DQPc** DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VSS VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC/DQPd** x32/x36 NC/SA* SA SA SA SA SA SA DNU DNU VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE * Pin 50 is reserved for address expansion. ** No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Y12.p65 - Rev. 3/99 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM TQFP PIN DESCRIPTIONS x18 x32/x36 37 37 36 36 32-35, 44-49, 32-35, 44-49, 80-82, 99, 81, 82, 99, 100 100 SYMBOL TYPE DESCRIPTION SA0 SA1 SA Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. 93 94 - - 93 94 95 96 BWa# BWb# BWc# BWd# Input Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18 version, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb. For the x32 and x36 versions, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins and DQPc; BWd# controls DQd pins and DQPd. Parity is only available on the x18 and x36 versions. 87 87 BWE# Input Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. 88 88 GW# Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit WRITE to occur independent of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CLK. 89 89 CLK Input Clock: This signal registers the address, data, chip enable, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. 98 98 CE# Input Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP#. CE# is sampled only when a new external address is loaded. 92 92 CE2# Input Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. 97 97 CE2 Input Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. 86 86 OE# Input Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. 83 83 ADV# Input Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait states to be generated (no address advance). To ensure use of correct address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an ADSP# cycle is initiated. 84 84 ADSP# Input Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC#, but dependent upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Powerdown state is entered if CE2 is LOW or CE2# is HIGH. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Y12.p65 - Rev. 3/99 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM TQFP PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL TYPE DESCRIPTION 85 85 ADSC# Input Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when CE# is HIGH. 31 31 MODE Input Mode: This input selects the burst sequence. A LOW on this pin selects "linear burst." NC or HIGH on this pin selects "interleaved burst." Do not alter input state while device is operating. 64 64 ZZ Input Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. (a) 58, 59, (a) 52, 53, 62, 63, 68, 69, 56-59, 62, 63 72, 73 (b) 8, 9, 12, (b) 68, 69, 13, 18, 19, 22, 72-75, 78, 79 23 (c) 2, 3, 6-9, 12, 13 (d) 18, 19, 22-25, 28, 29 74 24 - - 51 80 1 30 DQa DQb Input/ SRAM Data I/Os: For the x18 version, Byte "a" is DQa pins; Byte "b" Output is DQb pins. For the x32 and x36 versions, Byte "a" is DQa pins; Byte "b" is DQb pins; Byte "c" is DQc pins; Byte "d" is DQd pins. Input data must meet setup and hold times around the rising edge of CLK. DQc DQd NC/DQPa NC/DQPb NC/DQPc NC/DQPd NC/ I/O No Connect/Parity Data I/Os: On the x32 version, these pins are No Connect (NC). On the x18 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb. On the x36 version, Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is DQPd. 15, 41, 65, 91 15, 41, 65, 91 VDD 4, 11, 20, 27, 4, 11, 20, 27, 54, 61, 70, 77 54, 61, 70, 77 VDDQ 5, 10, 14, 17, 5, 10, 14, 17, 21, 26, 40, 55, 21, 26, 40, 55, 60, 67, 71, 76, 60, 67, 71, 76, 90 90 VSS 38, 39, 42, 43 38, 39, 42, 43 DNU - Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. Supply Ground: GND. 1-3, 6, 7, 16, 25, 28-30, 51-53, 56, 57, 66, 75, 78, 79, 95, 96 16, 66 NC - No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. 50 50 NC/SA - No Connect: This pin is reserved for address expansion. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Y12.p65 - Rev. 3/99 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X00 X...X11 X...X10 X...X10 X...X11 X...X00 X...X01 X...X11 X...X10 X...X01 X...X00 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X10 X...X11 X...X00 X...X10 X...X11 X...X00 X...X01 X...X11 X...X00 X...X01 X...X10 PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18) FUNCTION GW# BWE# BWa# BWb# READ H H X X READ H L H H WRITE Byte "a" H L L H WRITE Byte "b" H L H L WRITE All Bytes H L L L WRITE All Bytes L X X X PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x32/x36) FUNCTION GW# BWE# READ H H X X X X READ H L H H H H WRITE Byte "a" H L L H H H WRITE All Bytes H L L L L L WRITE All Bytes L X X X X X NOTE: BWa# BWb# BWc# BWd# Using BWE# and BWa# through BWd#, any one or more bytes may be written. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Y12.p65 - Rev. 3/99 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM TRUTH TABLE OPERATION ADDRESS CE# CE2# CE2 USED Deselected Cycle, Power-Down None H X X Deselected Cycle, Power-Down None L X L ZZ L L X L L X X X X X Deselected Cycle, Power-Down None Deselected Cycle, Power-Down None Deselected Cycle, Power-Down None SNOOZE MODE, Power-Down None READ Cycle, Begin Burst External L L L X L H X H X L X L X X H L L L H L L H H X L X L L X X X X X X X READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst External External External External L L L L L L L L H H H H L L L L L H H H X L L L READ Cycle, Continue Burst READ Cycle, Continue Burst Next Next X X X X X X L L H H READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst Next Next Next H H X X X X X X X L L L WRITE Cycle, Continue Burst READ Cycle, Suspend Burst Next Current H X X X X X READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst Current Current Current X H H X X X WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Current Current X H X X NOTE: ADSP# ADSC# ADV# WRITE# OE# CLK DQ X X L-H L-H High-Z High-Z X X X X X X X X X L L-H L-H L-H X L-H High-Z High-Z High-Z High-Z Q X X X X X L H H H X L H L-H L-H L-H L-H High-Z D Q High-Z H H L L H H L H L-H L-H Q High-Z X X H H H H L L L H H L L H X L-H L-H L-H Q High-Z D L L X H H H L H L H X L L-H L-H D Q X X X L L L H X X H H H H H H H H H H L H L-H L-H L-H High-Z Q High-Z X X L L H X H H H H L L X X L-H L-H D D 1. X means "Don't Care." # means active LOW. H means logic HIGH. L means logic LOW. 2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH. 3. BWa# enables WRITEs to DQa pins, DQPa. BWb# enables WRITEs to DQb pins, DQPb. BWc# enables WRITEs to DQc pins, DQPc. BWd# enables WRITEs to DQd pins, DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version. 4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Y12.p65 - Rev. 3/99 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See Micron Technical Note TN-05-14 for more information. ABSOLUTE MAXIMUM RATINGS* Voltage on VDD Supply Relative to VSS ....... -0.5V to +4.6V Voltage on VDDQ Supply Relative to VSS .... -0.5V to +4.6V VIN ......................................................... -0.5V to VDDQ + 0.5V Storage Temperature (plastic) .................... -55C to +150C Junction Temperature** ............................................. +150C Short Circuit Output Current ................................... 100mA 3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0C TA 70C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted) DESCRIPTION CONDITIONS Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Isolated Output Buffer Supply 0V VIN VDD Output(s) disabled, 0V VIN VDD IOH = -4.0mA IOL = 8.0mA SYMBOL MIN MAX UNITS NOTES VIH VIL 2.0 -0.3 VDD + 0.3 0.8 V V 1, 2 1, 2 ILI ILO -1.0 -1.0 1.0 1.0 A A 3 VOH 2.4 - V 1, 4 VOL VDD VDDQ - 3.135 3.135 0.4 3.6 3.6 V V V 1, 4 1 1, 5 2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0C TA 70C; VDD = +3.3V +0.3V/-0.165V; VDDQ = +2.5V +0.4V/-0.125V unless otherwise noted) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Data bus (DQx) Inputs VIHQ VIH 1.7 1.7 VDDQ + 0.3 VDD + 0.3 V V 1, 2 1, 2 VIL -0.3 0.7 V 1, 2 0V VIN VDD ILI -1.0 1.0 A 3 Output(s) disabled, 0V VIN VDDQ (DQx) ILO -1.0 1.0 A Output High Voltage IOH = -2.0mA IOH = -1.0mA VOH VOH 1.7 2.0 - - V V 1 1 Output Low Voltage IOL = 2.0mA IOL = 1.0mA VOL VOL - - 0.7 0.4 V V 1 1 VDD 3.135 3.6 V 1 VDDQ 2.375 2.9 V 1 Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Supply Voltage Isolated Output Buffer Supply NOTE: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH +4.6V for t tKC/2 for I 20mA Undershoot: VIL -0.7V for t tKC/2 for I 20mA Power-up: VIH +3.6V and VDD 3.135V for t 200ms 3. MODE pin has an internal pull-up, and input leakage = 10A. 4. The load used for VOH, VOL testing is shown in Figure 2 for 3.3V I/O. AC load current is higher than the stated DC values. AC I/O curves are available upon request. 5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Y12.p65 - Rev. 3/99 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (Note 1) (0C TA 70C; VDD = +3.3V +0.3V/-0.165V unless otherwise noted) MAX DESCRIPTION CONDITIONS SYM TYP -7.5 -8.5 -9 -10 UNITS NOTES IDD 125 280 250 250 200 mA 2, 3, 4 IDD1 30 85 75 60 60 mA 2, 3, 4 Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDD - 0.2; All inputs static; CLK frequency = 0 ISB2 0.5 10 10 10 10 mA 3, 4 Device deselected; VDD = MAX; All inputs VIL or VIH; All inputs static; CLK frequency = 0 ISB3 6 25 25 25 25 mA 3, 4 Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC MIN ISB4 30 85 75 60 60 mA 3, 4 Power Supply Device selected; All inputs VIL or VIH; Current: Operating Cycle time tKC MIN; VDD = MAX; Outputs open Power Supply Current: Idle Device selected; VDD = MAX; ADSC#, ADSP#, ADV#, GW#, BWx# VIH; All inputs VSS + 0.2 or VDD - 0.2; Cycle time tKC MIN; Outputs open CMOS Standby TTL Standby Clock Running CAPACITANCE DESCRIPTION Control Input Capacitance CONDITIONS SYMBOL TYP MAX UNITS NOTES TA = 25C; f = 1 MHz; CI 2 4 pF 5 VDD = 3.3V Input/Output Capacitance (DQ) CO 3.8 5 pF 5 Address Capacitance CA 2 3.5 pF 5 Clock Capacitance CCK 3 3.5 pF 5 TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Top of Case) NOTE: CONDITIONS Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. SYMBOL 1-layer JA (x32) JC TYP UNITS NOTES 40 C/W 5 8 C/W 5 1. VDDQ = +3.3V +0.3V/-0.165V for 3.3V I/O configuration; VDDQ = +2.5V +0.4V/-0.125V for 2.5V I/O configuration. 2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 3. "Device deselected" means device is in power-down mode as defined in the truth table. "Device selected" means device is active (not in power-down mode). 4. Typical values are measured at 3.3V, 25C and 15ns cycle time. 5. This parameter is sampled. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Y12.p65 - Rev. 3/99 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) (0C TA 70C; VDD = +3.3V +0.3V/-0.165V) DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE# to output valid OE# to output in Low-Z OE# to output in High-Z Setup Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Byte write enables (BWa#-BWd#, GW#, BWE#) Data-in Chip enable (CE#) Hold Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Byte write enables (BWa#-BWd#, GW#, BWE#) Data-in Chip enable (CE#) NOTE: SYMBOL MIN tKC 8.8 fKF tKH tKL tKQLZ 7.5 0 tAS tADSS tAAS tWS tDS tCES tAH tADSH tAAH tWH tDH tCEH 66 4.0 4.0 9.0 3.0 4.0 5.0 5.0 10.0 3.0 4.0 5.0 5.0 0 5.0 MAX 15 3.8 3.8 0 MIN 94 8.5 4.2 -10 MAX 10.5 3.0 4.0 4.2 4.2 tOEHZ -9 MIN 100 1.9 1.9 1.5 1.5 tOEQ -8.5 MAX 10.0 1.9 1.9 tKQHZ tOELZ MIN 113 tKQ tKQX -7.5 MAX 5.0 5.0 0 5.0 5.0 UNITS NOTES ns MHz ns ns 2 2 ns ns ns ns ns ns ns 3 3, 4, 5, 6 3, 4, 5, 6 7 3, 4, 5, 6 3, 4, 5, 6 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns ns ns ns 8, 9 8, 9 8, 9 8, 9 2.0 2.0 2.0 2.0 2.5 2.5 2.5 2.5 ns ns 8, 9 8, 9 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns 8, 9 8, 9 8, 9 8, 9 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns 8, 9 8, 9 1. Test conditions as specified with the output loading shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V +0.3V/-0.165V) and Figure 3 for 2.5V I/O (VDDQ = +2.5V +0.4V/-0.125V). 2. Measured as HIGH above VIH and LOW below VIL. 3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O. 4. This parameter is sampled. 5. Transition is measured 500mV from steady state voltage. 6. Refer to Technical Note TN-58-09, "Synchronous SRAM Bus Contention Design Considerations," for a more thorough discussion on these parameters. 7. OE# is a "Don't Care" when a byte write enable is sampled LOW. 8. A READ cycle is defined by byte write enables all HIGH or ADSP# LOW for the required setup and hold times. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold times. 9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Y12.p65 - Rev. 3/99 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM 3.3V I/O AC TEST CONDITIONS 2.5V I/O AC TEST CONDITIONS Input pulse levels ................... VIH = (VDD/2.2) + 1.5V Input pulse levels ............... VIH = (VDD/2.64) + 1.25V .................... VIL = (VDD/2.2) - 1.5V ................ VIL = (VDD/2.64) - 1.25V Input rise and fall times ....................................... 1ns Input rise and fall times ....................................... 1ns Input timing reference levels ......................... VDD/2.2 Input timing reference levels ....................... VDD/2.64 Output reference levels .............................. VDDQ/2.2 Output reference levels ................................. VDDQ/2 Output load .............................. See Figures 1 and 2 Output load .............................. See Figures 3 and 4 Q Q ZO = 50 ZO = 50 50 50 VT = 1.25V VT = 1.5V Figure 3 2.5V I/O OUTPUT LOAD EQUIVALENT Figure 1 3.3V I/O OUTPUT LOAD EQUIVALENT +2.5V +3.3V 1,667 317 Q Q 351 5pF 1,538 Figure 2 3.3V I/O OUTPUT LOAD EQUIVALENT 5pF Figure 4 2.5V I/O OUTPUT LOAD EQUIVALENT LOAD DERATING CURVES The Micron 128K x 18, 64K x 32, and 64K x 36 SyncBurst SRAM timing is dependent upon the capacitive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Y12.p65 - Rev. 3/99 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM SNOOZE MODE The ZZ pin is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any access pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. SNOOZE MODE is a low-current, "power-down" mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time the ZZ pin is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. SNOOZE MODE ELECTRICAL CHARACTERISTICS DESCRIPTION Current during SNOOZE MODE CONDITIONS SYMBOL ZZ VIH ZZ active to input ignored MAX UNITS ISB2Z 10 mA tZZ tKC ns 1 ns 1 ns 1 ns 1 ZZ inactive to input sampled tRZZ ZZ active to snooze current tZZI tKC tKC tRZZI ZZ inactive to exit snooze current NOTE: MIN 0 NOTES 1. This parameter is sampled. SNOOZE MODE WAVEFORM CLK tRZZ tZZ ZZ tZZI I SUPPLY I SB2 , ,, , , tRZZI ALL INPUTS* * Except ZZ 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Y12.p65 - Rev. 3/99 DON'T CARE 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM READ TIMING ,, ,,,,,,,,,, ,, ,,,,, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,,,,,,, ,,,,,,,,, ,,,,,,,,,,,,, , , , , , , , , , , , , , , , , , , , , , , , , , ,, ,, ,,,, ,, ,, ,,,,,,,, , , ,, ,,,,, ,, ,, , ,, t KC CLK t KL t KH t ADSS tADSH ADSP# t ADSS tADSH ADSC# t AS Deselect Cycle (Note 4) tAH A1 ADDRESS A2 t WS tWH BWE#, GW#, BWa#-BWd# t CES tCEH CE# (NOTE 2) t AAS tAAH ADV# ADV# suspends burst. OE# t OEQ t KQ t OELZ t OEHZ t KQLZ Q Q(A2) Q(A1) High-Z t KQHZ t KQX Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) t KQ Burst wraps around to its initial state. (NOTE 1) Single READ BURST READ ,, DON'T CARE READ TIMING PARAMETERS -7.5 -8.5 -9 -10 -7.5 -8.5 -9 UNDEFINED -10 SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS tKC 8.8 ns MHz ns tAS 2.0 2.0 2.5 2.5 ns tADSS 2.0 2.0 2.0 2.0 2.5 2.5 2.5 2.5 ns ns ns ns tWS 10.0 ns ns ns tAH 2.0 2.0 0.5 2.0 2.0 0.5 2.5 2.5 0.5 2.5 2.5 0.5 ns ns ns 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns tWH 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns fKF tKH 1.9 tKL 1.9 tKQ tKQX tKQLZ 10.0 113 10.5 100 1.9 3.8 1.9 7.5 1.5 1.5 15 94 4.0 3.8 8.5 3.0 4.0 66 4.0 9.0 3.0 4.0 3.0 4.0 tKQHZ 4.2 5.0 5.0 5.0 tOEQ 4.2 5.0 5.0 5.0 tOELZ tOEHZ 0 0 4.2 0 5.0 0 5.0 5.0 tAAS tCES tADSH tAAH tCEH ns NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. 4. Outputs are disabled tKQHZ after deselect. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Y12.p65 - Rev. 3/99 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM WRITE TIMING , , , , , , , ,, ,, ,, ,,,, ,, ,,,,,,,,, , , , , , , , , , , , , , , , , , ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, , , , , , , , , , , , , , , , , , ,, ,,,,,,,,,, ,,,,,,,,,,, , ,, ,, ,,,,,,,,,,,,,,,,, , , , , , , , , , , , , , , , , , , , , , , ,, ,, ,, , ,, , ,, ,, t KC CLK t KH t KL t ADSS tADSH ADSP# ADSC# extends burst. t ADSS tADSH t ADSS tADSH ADSC# t AS tAH A1 ADDRESS A2 A3 BYTE WRITE signals are ignored when ADSP# is LOW. t WS tWH BWE#, BWa#-BWd# (NOTE 5) t WS tWH GW# t CES tCEH CE# (NOTE 2) t AAS tAAH ADV# ADV# suspends burst. (NOTE 4) OE# (NOTE 3) t DS D tDH D(A2) D(A1) High-Z D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) tOEHZ (NOTE 1) Q BURST READ Single WRITE BURST WRITE Extended BURST WRITE DON'T CARE UNDEFINED WRITE TIMING PARAMETERS SYMBOL tKC -7.5 -8.5 -9 -10 MIN MAX MIN MAX MIN MAX MIN MAX UNITS 8.8 10.0 10.5 15 ns fKF 113 tKH 1.9 tKL 1.9 100 1.9 94 3.8 4.0 tAS 2.0 2.0 2.5 2.5 tADSS tAAS 2.0 2.0 2.0 2.0 2.5 2.5 2.5 2.5 ns ns tWS 2.0 2.0 2.5 2.5 ns 4.2 3.8 5.0 4.0 MHz ns ns ns ns tOEHZ 1.9 66 5.0 5.0 SYMBOL -7.5 -8.5 -9 -10 MIN MAX MIN MAX MIN MAX MIN MAX UNITS tDS 2.0 2.0 2.5 2.5 ns tCES 2.0 0.5 2.0 0.5 2.5 0.5 2.5 0.5 ns ns 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns tAH tADSH tDH tAAH tWH tCEH NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable inputs being sampled. 4. ADV# must be HIGH to permit a WRITE to the loaded address. 5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for the x18 version; or GW# HIGH and BWE#, BWa#-BWd# LOW for the x32 and x36 versions. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Y12.p65 - Rev. 3/99 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM READ/WRITE TIMING ,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, , , , , , , , , , , , , , ,,,,,,,,,,,,,,,, ,,,,,,,,, , , , , , , , , , , , , , , , , ,,,,,,,,,,,, ,,,,,,, , t KC CLK t KL t KH t ADSS tADSH ADSP# ADSC# t AS ADDRESS A1 tAH A2 A3 A4 t WS BWE#, BWa#-BWd# (NOTE 4) t CES A5 A6 D(A5) D(A6) tWH tCEH CE# (NOTE 2) ADV# OE# D Q ,,, ,,, High-Z t DS t DH D(A3) tOEHZ Q(A4) Back-to-Back READs Single WRITE -7.5 tKH tKL tKQ tOELZ tADSS NOTE: -9 100 1.9 1.9 7.5 0 tOEHZ tAS -8.5 113 1.9 1.9 -10 8.5 4.2 2.0 2.0 94 3.8 3.8 0 66 4.0 4.0 9.0 0 5.0 2.0 2.0 Q(A4+1) Q(A4+2) Q(A4+3) SYMBOL tWS 10.0 0 5.0 2.5 2.5 5.0 2.5 2.5 tDS MHz ns ns tCES tAH ns ns tADSH ns ns ns tDH tWH tCEH , Back-to-Back WRITEs BURST READ MIN MAX MIN MAX MIN MAX MIN MAX UNITS 8.8 10.0 10.5 15 ns fKF (NOTE 1) DON'T CARE READ/WRITE TIMING PARAMETERS SYMBOL tKC ,,,,,, ,,,,,,, t KQ Q(A2) Q(A1) t OELZ UNDEFINED -7.5 -8.5 -9 -10 MIN MAX MIN MAX MIN MAX MIN MAX UNITS 2.0 2.0 2.5 2.5 ns 2.0 2.0 2.0 2.0 2.5 2.5 2.5 2.5 ns ns 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed. 4. GW# is HIGH. 5. Back-to-back READs may be controlled by either ADSP# or ADSC#. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Y12.p65 - Rev. 3/99 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM 100-PIN PLASTIC TQFP (JEDEC LQFP) D-1 PIN #1 INDEX 0.38 0.22 22.20 21.95 0.65 20.20 19.90 DETAIL A 1.60 1.40 0.10 14.10 13.90 16.20 15.95 0.25 GAGE PLANE 1.45 1.35 0.75 0.45 DETAIL A NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Y12.p65 - Rev. 3/99 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. 1999, Micron Technology, Inc.