Ultraprecision, Low Noise, 2.048 V/2.500 V/
3.00 V/5.00 V XFET® Voltage References
ADR420/ADR421/ADR423/ADR425
Rev. I
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2001–2011 Analog Devices, Inc. All rights reserved.
FEATURES
Low noise (0.1 Hz to 10 Hz)
ADR420: 1.75 μV p-p
ADR421: 1.75 μV p-p
ADR423: 2.0 μV p-p
ADR425: 3.4 μV p-p
Low temperature coefficient: 3 ppm/°C
Long-term stability: 50 ppm/1000 hours
Load regulation: 70 ppm/mA
Line regulation: 35 ppm/V
Low hysteresis: 40 ppm typical
Wide operating range
ADR420: 4 V to 18 V
ADR421: 4.5 V to 18 V
ADR423: 5 V to 18 V
ADR425: 7 V to 18 V
Quiescent current: 0.5 mA maximum
High output current: 10 mA
Wide temperature range: −40°C to +125°C
APPLICATIONS
Precision data acquisition systems
High resolution converters
Battery-powered instrumentation
Portable medical instruments
Industrial process control systems
Precision instruments
Optical network control circuits
PIN CONFIGURATION
02432-001
NIC = NO INTERNAL CONNECTION
TP = TEST PIN (DO NOT CONNECT)
ADR420/
ADR421/
ADR423/
ADR425
TOP VIEW
(Not to Scale)
TP
1
V
IN 2
NIC
3
GND
4
TP
8
NIC
7
V
OUT
6
TRIM
5
Figure 1. 8-Lead SOIC, 8-Lead MSOP
GENERAL DESCRIPTION
The ADR42x are a series of ultraprecision, second generation
eXtra implanted junction FET (XFET) voltage references
featuring low noise, high accuracy, and excellent long-term
stability in SOIC and MSOP footprints.
Patented temperature drift curvature correction technique and
XFET technology minimize nonlinearity of the voltage change
with temperature. The XFET architecture offers superior
accuracy and thermal hysteresis to the band gap references. It
also operates at lower power and lower supply headroom than
the buried Zener references.
The superb noise and the stable and accurate characteristics
of the ADR42x make them ideal for precision conversion
applications such as optical networks and medical equipment.
The ADR42x trim terminal can also be used to adjust the out-
put voltage over a ±0.5% range without compromising any
other performance. The ADR42x series voltage references
offer two electrical grades and are specified over the extended
industrial temperature range of −40°C to +125°C. Devices have
8-lead SOIC or 30% smaller, 8-lead MSOP packages.
ADR42x PRODUCTS
Table 1.
Initial Accuracy
Model Output Voltage, VOUT (V) mV % Temperature Coefficient (ppm/°C)
ADR420 2.048 1, 3 0.05, 0.15 3, 10
ADR421 2.50 1, 3 0.04, 0.12 3, 10
ADR423 3.00 1.5, 4 0.04, 0.13 3, 10
ADR425 5.00 2, 6 0.04, 0.12 3, 10
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Pin Configuration............................................................................. 1
General Description......................................................................... 1
ADR42x Products............................................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
ADR420 Electrical Specifications............................................... 3
ADR421 Electrical Specifications............................................... 4
ADR423 Electrical Specifications............................................... 5
ADR425 Electrical Specifications............................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 16
Device Power Dissipation Considerations.............................. 16
Basic Voltage Reference Connections ..................................... 16
Noise Performance ..................................................................... 16
Turn-On Time ............................................................................ 16
Applications..................................................................................... 17
Output Adjustment .................................................................... 17
Reference for Converters in Optical Network Control
Circuits......................................................................................... 17
High Voltage Floating Current Source.................................... 17
Kelvin Connections.................................................................... 18
Dual-Polarity References........................................................... 18
Programmable Current Source ................................................ 19
Programmable DAC Reference Voltage .................................. 19
Precision Voltage Reference for Data Converters.................. 20
Precision Boosted Output Regulator....................................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 22
REVISION HISTORY
5/11—Rev. H to Rev. I
Added Endnote 1 in Table 2............................................................ 4
Added Endnote 1 in Table 3............................................................ 5
Added Endnote 1 in Table 4............................................................ 6
Added Endnote 1 in Table 5............................................................ 7
Deleted A Negative Precision Reference Without Precision
Resistors Section ............................................................................. 17
Deleted Figure 42; Renumbered Sequentially ............................ 17
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 22
6/07—Rev. G to Rev. H
Changes to Table 2............................................................................ 3
Changes to Table 3............................................................................ 4
Changes to Table 4............................................................................ 5
Changes to Table 5............................................................................ 6
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 22
6/05—Rev. F to Rev. G
Changes to Table 1............................................................................ 1
Changes to Ordering Guide .......................................................... 22
2/05—Rev. E to Rev. F
Updated Format..................................................................Universal
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 22
7/04—Rev. D to Rev. E
Changes to Ordering Guide.............................................................5
3/04—Rev. C to Rev. D
Changes to Table I .............................................................................1
Changes to Ordering Guide.............................................................4
Updated Outline Dimensions....................................................... 16
1/03—Rev. B to Rev. C
Changed Mini_SOIC to MSOP ........................................Universal
Changes to Ordering Guide.............................................................4
Corrections to Y-axis labels in TPCs 21 and 24 ............................9
Enhancement to Figure 13 ............................................................ 15
Updated Outline Dimensions....................................................... 16
3/02—Rev. A to Rev. B
Edits to Ordering Guide ...................................................................4
Deletion of Precision Voltage Regulator section........................ 15
Addition of Precision Boosted Output Regulator section ....... 15
Addition of Figure 13..................................................................... 15
10/01—Rev. 0 to Rev. A
Addition of ADR423 and ADR425 to
ADR420/ADR421...............................................................Universal
5/01—Revision 0: Initial Version
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 3 of 24
SPECIFICATIONS
ADR420 ELECTRICAL SPECIFICATIONS
VIN = 5.0 V to 15.0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT VOLTAGE VOUT
A Grade 2.045 2.048 2.051 V
B Grade 2.047 2.048 2.049 V
INITIAL ACCURACY1 V
OUTERR
A Grade −3 +3 mV
−0.15 +0.15 %
B Grade −1 +1 mV
−0.05 +0.05 %
TEMPERATURE COEFFICIENT TCVOUT −40°C < TA < +125°C
A Grade 2 10 ppm°C
B Grade 1 3 ppm/°C
SUPPLY VOLTAGE HEADROOM VIN − VOUT 2 V
LINE REGULATION ∆VOUT/∆VIN VIN = 5 V to 18 V,
−40°C < TA < +125°C
10 35 ppm/V
LOAD REGULATION ∆VOUT/∆IL IL = 0 mA to 10 mA,
−40°C < TA < +125°C
70 ppm/mA
QUIESCENT CURRENT IIN No load 390 500 μA
−40°C < TA < +125°C 600 μA
VOLTAGE NOISE eN p-p 0.1 Hz to 10 Hz 1.75 μV p-p
VOLTAGE NOISE DENSITY eN 1 kHz 60 nV/√Hz
TURN-ON SETTLING TIME tR 10 μs
LONG-TERM STABILITY ∆VOUT 1000 hours 50 ppm
OUTPUT VOLTAGE HYSTERESIS VOUT_HYS 40 ppm
RIPPLE REJECTION RATIO RRR fIN = 1 kHz −75 dB
SHORT CIRCUIT TO GND ISC 27 mA
1 Initial accuracy does not include shift due to solder heat effect.
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 4 of 24
ADR421 ELECTRICAL SPECIFICATIONS
VIN = 5.0 V to 15.0 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT VOLTAGE VOUT
A Grade 2.497 2.500 2.503 V
B Grade 2.499 2.500 2.501 V
INITIAL ACCURACY1 V
OUTERR
A Grade −3 +3 mV
−0.12 +0.12 %
B Grade −1 +1 mV
−0.04 +0.04 %
TEMPERATURE COEFFICIENT TCVOUT −40°C < TA < +125°C
A Grade 2 10 ppm/°C
B Grade 1 3 ppm/°C
SUPPLY VOLTAGE HEADROOM VIN − VOUT 2 V
LINE REGULATION ∆VOUT/∆VIN VIN = 5 V to 18 V,
−40°C < TA < +125°C
10 35 ppm/V
LOAD REGULATION ∆VOUT/∆IL IL = 0 mA to 10 mA,
−40°C < TA < +125°C
70 ppm/mA
QUIESCENT CURRENT IIN No load 390 500 μA
−40°C < TA < +125°C 600 μA
VOLTAGE NOISE eN p-p 0.1 Hz to 10 Hz 1.75 μV p-p
VOLTAGE NOISE DENSITY eN 1 kHz 80 nV/√Hz
TURN-ON SETTLING TIME tR 10 μs
LONG-TERM STABILITY ∆VOUT 1000 hours 50 ppm
OUTPUT VOLTAGE HYSTERESIS VOUT_HYS 40 ppm
RIPPLE REJECTION RATIO RRR fIN = 1 kHz −75 dB
SHORT CIRCUIT TO GND ISC 27 mA
1 Initial accuracy does not include shift due to solder heat effect.
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 5 of 24
ADR423 ELECTRICAL SPECIFICATIONS
VIN = 5.0 V to 15.0 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT VOLTAGE VOUT
A Grade 2.996 3.000 3.004 V
B Grade 2.9985 3.000 3.0015 V
INITIAL ACCURACY1 V
OUTERR
A Grade −4 +4 mV
−0.13 +0.13 %
B Grade −1.5 +1.5 mV
−0.04 +0.04 %
TEMPERATURE COEFFICIENT TCVOUT −40°C < TA < +125°C
A Grade 2 10 ppm/°C
B Grade 1 3 ppm/°C
SUPPLY VOLTAGE HEADROOM VIN − VOUT 2 V
LINE REGULATION ∆VOUT/∆VIN VIN = 5 V to 18 V,
−40°C < TA < +125°C
10 35 ppm/V
LOAD REGULATION ∆VOUT/∆IL IL = 0 mA to 10 mA,
−40°C < TA < +125°C
70 ppm/mA
QUIESCENT CURRENT IIN No load 390 500 μA
−40°C < TA < +125°C 600 μA
VOLTAGE NOISE eN p-p 0.1 Hz to 10 Hz 2 μV p-p
VOLTAGE NOISE DENSITY eN 1 kHz 90 nV/√Hz
TURN-ON SETTLING TIME tR 10 μs
LONG-TERM STABILITY ∆VOUT 1000 hours 50 ppm
OUTPUT VOLTAGE HYSTERESIS VOUT_HYS 40 ppm
RIPPLE REJECTION RATIO RRR fIN = 1 kHz −75 dB
SHORT CIRCUIT TO GND ISC 27 mA
1 Initial accuracy does not include shift due to solder heat effect.
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 6 of 24
ADR425 ELECTRICAL SPECIFICATIONS
VIN = 7.0 V to 15.0 V, TA = 25°C, unless otherwise noted.
Table 5.
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT VOLTAGE VOUT
A Grade 4.994 5.000 5.006 V
B Grade 4.998 5.000 5.002 V
INITIAL ACCURACY1 V
OUTERR
A Grade −6 +6 mV
−0.12 +0.12 %
B Grade −2 +2 mV
−0.04 +0.04 %
TEMPERATURE COEFFICIENT TCVOUT
A Grade −40°C < TA < +125°C 2 10 ppm/°C
B Grade 1 3 ppm/°C
SUPPLY VOLTAGE HEADROOM VIN − VO 2 V
LINE REGULATION ∆VO/∆VIN VIN = 7 V to 18 V,
−40°C < TA < +125°C
10 35 ppm/V
LOAD REGULATION ∆VO/∆IL IL = 0 mA to 10 mA,
−40°C < TA < +125°C
70 ppm/mA
QUIESCENT CURRENT IIN No load 390 500 μA
−40°C < TA < +125°C 600 μA
VOLTAGE NOISE eN p-p 0.1 Hz to 10 Hz 3.4 μV p-p
VOLTAGE NOISE DENSITY eN 1 kHz 110 nV/√Hz
TURN-ON SETTLING TIME tR 10 μs
LONG-TERM STABILITY ∆VO 1000 hours 50 ppm
OUTPUT VOLTAGE HYSTERESIS VO_HYS 40 ppm
RIPPLE REJECTION RATIO RRR fIN = 1 kHz −75 dB
SHORT CIRCUIT TO GND ISC 27 mA
1 Initial accuracy does not include shift due to solder heat effect.
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
These ratings apply at 25°C, unless otherwise noted.
Table 6.
Parameter Rating
Supply Voltage 18 V
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for devices soldered in the circuit board for surface-
mount packages.
Table 7.
Package Type θJA Unit
8-Lead MSOP (RM) 190 °C/W
8-Lead SOIC (R) 130 °C/W
ESD CAUTION
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 8 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
02432-002
NIC = NO INTERNAL CONNECTION
TP = TEST PIN (DO NOT CONNECT)
ADR420/
ADR421/
ADR423/
ADR425
TOP VIEW
(Not to Scale)
TP
1
V
IN 2
NIC
3
GND
4
TP
8
NIC
7
V
OUT
6
TRIM
5
Figure 2. 8-Lead SOIC, 8-Lead MSOP Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1, 8 TP Test Pin. There are actual connections in TP pins, but they are reserved for factory testing purposes. Users should not
connect anything to TP pins; otherwise, the device may not function properly.
2 VIN Input Voltage.
3, 7 NIC No Internal Connect. NICs have no internal connections.
4 GND Ground Pin = 0 V.
5 TRIM
Trim Terminal. It can be used to adjust the output voltage over a ±0.5% range without affecting the temperature
coefficient.
6 VOUT Output Voltage.
ADR420/ADR421/ADR423/ADR425
Rev. G | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
–40 –10 20 50 80 125110
02432-004
TEMPERATURE (°C)
V
OUT
(V)
2.0495
2.0493
2.0491
2.0489
2.0487
2.0485
2.0483
2.0481
2.0479
2.0477
2.0475
Figure 3. ADR420 Typical Output Voltage vs. Temperature
–40 –10 20 50 80 125110
02432-005
TEMPERATURE (°C)
VOUT (V)
2.4995
2.4997
2.4999
2.5001
2.5003
2.5005
2.5007
2.5009
2.5011
2.5013
2.5015
Figure 4. ADR421 Typical Output Voltage vs. Temperature
–40 –10 20 50 80 125110
02432-006
TEMPERATURE (°C)
VOUT (V)
3.0010
3.0008
3.0006
3.0004
3.0002
3.0000
2.9998
2.9996
2.9994
2.9992
2.9990
Figure 5. ADR423 Typical Output Voltage vs. Temperature
–40 –10 20 50 80 125110
02432-007
TEMPERATURE (°C)
V
OUT
(V)
5.0025
5.0023
5.0021
5.0019
5.0017
5.0015
5.0013
5.0011
5.0009
5.0007
5.0005
Figure 6. ADR425 Typical Output Voltage vs. Temperature
468101214
02432-008
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
0.55
0.50
0.45
0.40
0.35
0.30
0.25
15
+125°C
+25°C
–40°C
Figure 7. ADR420 Supply Current vs. Input Voltage
468101214
02432-009
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
0.55
0.50
0.45
0.40
0.35
0.30
0.25
+125°C
+25°C
–40°C
15
Figure 8. ADR421 Supply Current vs. Input Voltage
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 10 of 24
4 6 8 10 12 1514
02432-010
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
0.55
0.50
0.45
0.40
0.35
0.30
0.25
+125°C
+25°C
–40°C
Figure 9. ADR423 Supply Current vs. Input Voltage
6 8 10 12 1514
02432-011
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
0.55
0.50
0.45
0.40
0.35
0.30
0.25
+125°C
+25°C
–40°C
Figure 10. ADR425 Supply Current vs. Input Voltage
–40 –10 20 50 80 110 125
02432-012
TEMPERATURE (°C)
LOAD REGULATION (ppm/mA)
70
50
60
40
30
20
10
0
I
L
= 0mA TO 5mA
V
IN
= 4.5V
V
IN
= 6V
Figure 11. ADR420 Load Regulation vs. Temperature
–40 –10 20 50 80 110 125
02432-013
TEMPERATURE (°C)
LOAD REGULATION (ppm/mA)
70
50
60
40
30
20
10
0
I
L
= 0mA TO 5mA
V
IN
= 6.5V
V
IN
= 5V
Figure 12. ADR421 Load Regulation vs. Temperature
–40 –10 20 50 80 110 125
02432-014
TEMPERATURE (°C)
LOAD REGULATION (ppm/mA)
70
50
60
40
30
20
10
0
I
L
= 0mA TO 10mA
V
IN
= 15V
V
IN
= 7V
Figure 13. ADR423 Load Regulation vs. Temperature
–40 –10 20 50 80 110 125
02432-015
TEMPERATURE (°C)
LOAD REGULATION (ppm/mA)
35
25
30
20
15
10
5
0
V
IN
= 15V
I
L
= 0mA TO 10mA
Figure 14. ADR425 Load Regulation vs. Temperature
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 11 of 24
–40 –10 20 50 80 110 125
02432-016
TEMPERATURE (°C)
LINE REGULATION (ppm/V)
6
4
5
3
2
1
0
V
IN
= 4.5V TO 15V
Figure 15. ADR420 Line Regulation vs. Temperature
–40 –10 20 50 80 110 125
02432-017
TEMPERATURE (°C)
LINE REGULATION (ppm/V)
6
4
5
3
2
1
0
V
IN
= 5V TO 15V
Figure 16. ADR421 Line Regulation vs. Temperature
–40 –10 20 50 80 110
02432-018
TEMPERATURE (°C)
LINE REGULATION (ppm/V)
9
6
8
4
5
7
3
2
1
0
V
IN
= 5V TO 15V
Figure 17. ADR423 Line Regulation vs. Temperature
–40 –10 20 50 80 110 125
02432-019
TEMPERATURE (°C)
LINE REGULATION (ppm/V)
14
10
12
8
6
4
2
0
V
IN
= 7.5V TO 15V
Figure 18. ADR425 Line Regulation vs. Temperature
01234
02432-020
LOAD CURRENT (mA)
DIFFERENTIAL VOLTAGE (V)
2.5
2.0
1.5
1.0
0.5
0
–40°C
+85°C
+25°C
5
5
Figure 19. ADR420 Minimum Input/Output Voltage
Differential vs. Load Current
01234
02432-021
LOAD CURRENT (mA)
DIFFERENTIAL VOLTAGE (V)
2.5
2.0
1.5
1.0
0.5
0
–40°C
+125°C
+25°C
Figure 20. ADR421 Minimum Input/Output Voltage
Differential vs. Load Current
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 12 of 24
501234
02432-022
LOAD CURRENT (mA)
DIFFERENTIAL VOLTAGE (V)
2.5
2.0
1.5
1.0
0.5
0
–40°C
+125°C
+25°C
Figure 21. ADR423 Minimum Input/Output Voltage
Differential vs. Load Current
01234
02432-023
LOAD CURRENT (mA)
DIFFERENTIAL VOLTAGE (V)
2.5
2.0
1.5
1.0
0.5
0
–40°C
+125°C
+25°C
5
Figure 22. ADR425 Minimum Input/Output Voltage
Differential vs. Load Current
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
110
120
130
MORE
02432-024
DEVIATION (ppm)
NUMBER OF PARTS
30
20
25
15
10
5
0
SAMPLE SIZE – 160
TEMPERATURE
+25°C –40°C
+125°C +25°C
Figure 23. ADR421 Typical Hysteresis
02432-025
TIME (1s/DIV)
1µV/DIV
Figure 24. ADR421 Typical Noise Voltage 0.1 Hz to 10 Hz
02432-026
TIME (1s/DIV)
50µV/DIV
Figure 25. Typical Noise Voltage 10 Hz to 10 kHz
02432-027
FREQUENCY (Hz)
VOLTAGE NOISE DENSITY (nV/ Hz)
ADR423
ADR421
ADR420
ADR425
10 100
10
100
1k
1k 10k
Figure 26. Voltage Noise Density vs. Frequency
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 13 of 24
02432-028
TIME (100µs/DIV)
500mV/DIV
LINE INTERRUPTION
500mV/DIV
C
BYPASS
= 0µF
V
IN
V
OUT
Figure 27. ADR421 Line Transient Response, no CBYPASS
02432-029
TIME (100µs/DIV)
500mV/DIV
LINE INTERRUPTION
500mV/DIV
C
BYPASS
= 0.1µF
V
IN
V
OUT
Figure 28. ADR421 Line Transient Response, CBYPASS = 0.1 μF
02432-030
TIME (100µs/DIV)
2V/DIV
1V/DIV
C
L
= 0µF
LOAD ON
LOAD OFF
V
OUT
1mA LOAD
Figure 29. ADR421 Load Transient Response, no CL
02432-031
TIME (100µs/DIV)
2V/DIV
1V/DIV
C
L
= 100nF
LOAD ON
LOAD OFF
V
OUT
1mA LOAD
Figure 30. ADR421 Load Transient Response, CL = 100 nF
02432-032
TIME (4µs/DIV)
2V/DIV
V
IN
2V/DIV
V
OUT
C
IN
= 0.01µF
NO LOAD
Figure 31. ADR421 Turn-Off Response
02432-033
TIME (4µs/DIV)
2V/DIV
2V/DIV
C
IN
= 0.01µF
NO LOAD
V
IN
V
OUT
Figure 32. ADR421 Turn-On Response
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 14 of 24
02432-034
TIME (4µs/DIV)
2V/DIV
2V/DIV
C
L
= 0.01µF
NO INPUT CAP
V
IN
V
OUT
Figure 33. ADR421 Turn-Off Response
02432-035
TIME (4µs/DIV)
2V/DIV
2V/DIV
C
L
= 0.01µF
NO INPUT CAP
V
IN
V
OUT
Figure 34. ADR421 Turn-On Response
02432-036
TIME (100µs/DIV)
2V/DIV
5V/DIV
V
IN
V
OUT
C
BYPASS
= 0.1µF
R
L
= 500Ω
C
L
= 0
Figure 35. ADR421 Turn-On/Turn-Off Response
ADR425
ADR420
ADR421
ADR423
10 100 1k 10k 100k
02432-037
FREQUENCY (Hz)
OUTPUT IMPEDANCE (Ω)
50
45
40
35
30
25
20
15
10
5
0
Figure 36. Output Impedance vs. Frequency
10 100 10k1k 100k 1M
02432-038
FREQUENCY (Hz)
RIPPLE REJECTION (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Figure 37. Ripple Rejection vs. Frequency
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 15 of 24
TERMINOLOGY
Temperature Coefficient
The change of output voltage over the operating temperature
range is normalized by the output voltage at 25°C, and
expressed in ppm/°C as
()
() ()
()
()
6
10/ ×
−×°
−
=°
12
OUT
1
OUT
2
OUT
OUT TTC25V
TVTV
CppmTCV
where:
VOUT (25°C) = VOUT at 25°C.
VOUT (T1) = VOUT at Temperature 1.
VOUT (T2) = VOUT at Temperature 2.
Line Regulation
The change in output voltage due to a specified change in input
voltage. It includes the effects of self-heating. Line regulation is
expressed in either percent per volt, parts per million per volt,
or microvolts per volt change in input voltage.
Load Regulation
The change in output voltage due to a specified change in load
current. It includes the effects of self-heating. Load regulation is
expressed in either microvolts per milliampere, parts per
million per milliampere, or ohms of dc output resistance.
Long-Term Stability
Typical shift of output voltage at 25°C on a sample of parts
subjected to operation life test of 1000 hours at 125°C.
()
()
1
OUT
0
OUTOUT tVtVV −=Δ
()
()
()
()
6
10×
−
=Δ
0
OUT
1
OUT
0
OUT
OUT tV
tVtV
ppmV
where:
VOUT (t0) = VOUT at 25°C at Time 0.
VOUT (t1) = VOUT at 25°C after 1000 hours operation at 125°C.
Thermal Hysteresis
The change of output voltage after the device is cycled through
temperatures from +25°C to −40°C to +125°C and back to
+25°C. This is a typical value from a sample of parts put
through such a cycle.
(
)
TCOUTOUTHYSOUT VC25VV __ −°
=
()
()
()
6
_
_10×
°
−°
=C25V
VC25V
ppmV
OUT
TCOUTOUT
HYSOUT
where:
VOUT (25°C) = VOUT at 25°C.
VOUT_TC = VOUT at 25 °C after temperature cycle at +25°C to
−40°C to +125°C and back to +25°C.
Input Capacitor
Input capacitors are not required on the ADR42x. There is
no limit for the value of the capacitor used on the input, but a
1 µF to 10 µF capacitor on the input improves transient response
in applications where the supply suddenly changes. An addi-
tional 0.1 µF capacitor in parallel also helps to reduce noise
from the supply.
Output Capacitor
The ADR42x do not need output capacitors for stability under
any load condition. An output capacitor, typically 0.1 µF, filters
out any low level noise voltage and does not affect the operation
of the part. On the other hand, the load transient response can
be improved with an additional 1 F to 10 F output capacitor
in parallel. A capacitor here acts as a source of stored energy for
sudden increase in load current. The only parameter that
degrades by adding an output capacitor is the turn-on time,
which depends on the size of the selected capacitor.
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 16 of 24
THEORY OF OPERATION
The ADR42x series of references uses a reference generation
technique known as XFET (eXtra implanted junction FET).
This technique yields a reference with low supply current, good
thermal hysteresis, and exceptionally low noise. The core of the
XFET reference consists of two junction field-effect transistors
(JFET), one having an extra channel implant to raise its pinch-
off voltage. By running the two JFETs at the same drain current,
the difference in pinch-off voltage can be amplified and used to
form a highly stable voltage reference.
The intrinsic reference voltage is about 0.5 V with a negative
temperature coefficient of about −120 ppm/°C. This slope is
essentially constant to the dielectric constant of silicon and can
be closely compensated by adding a correction term generated
in the same fashion as the proportional-to-temperature (PTAT)
term used to compensate band gap references. The primary
advantage over a band gap reference is that the intrinsic tem-
perature coefficient is approximately 30 times lower (therefore
requiring less correction). This results in much lower noise
because most of the noise of a band gap reference comes from
the temperature compensation circuitry.
Figure 38 shows the basic topology of the ADR42x series. The
temperature correction term is provided by a current source
with a value designed to be proportional to absolute tempera-
ture. The general equation is
VOUT = G × (∆VP − R1 × IPTAT) (1)
where:
G is the gain of the reciprocal of the divider ratio.
∆VP is the difference in pinch-off voltage between the two JFETs.
IPTAT is the positive temperature coefficient correction current.
Each ADR42x device is created by on-chip adjustment of R2
and R3 to achieve the specified reference output.
02432-039
*
R3
GND
*EXTRA CHANNEL IMPLANT
VOUT = G(∆VP – R1 × IPTAT)
R2
IPTAT
∆VPR1
V
IN
VOUT
ADR420/ADR421/
ADR423/ADR425
I1I1
Figure 38. Simplified Schematic
DEVICE POWER DISSIPATION CONSIDERATIONS
The ADR42x family of references is guaranteed to deliver load
currents to 10 mA with an input voltage that ranges from 4.5 V
to 18 V. When these devices are used in applications at higher
currents, the following equation should be used to account for
the temperature effects due to power dissipation increases:
TJ = PD × θJA + TA (2)
where:
TJ and TA are the junction temperature and the ambient
temperature, respectively.
PD is the device power dissipation.
θJA is the device package thermal resistance.
BASIC VOLTAGE REFERENCE CONNECTIONS
Voltage references, in general, require a bypass capacitor
connected from VOUT to GND. The circuit in Figure 39
illustrates the basic configuration for the ADR42x family of
references. Other than a 0.1 µF capacitor at the output to help
improve noise suppression, a large output capacitor at the
output is not required for circuit stability.
02432-040
NIC = NO INTERNAL CONNECTION
TP = TEST PIN (DO NOT CONNECT)
ADR420/
ADR421/
ADR423/
ADR425
TOP VIEW
(Not to Scale)
TP
1
V
IN 2
NIC
3
4
TP
8
NIC
7
OUTPUT
6
TRIM
5
0.1µF
0.1µF10µF +
Figure 39. Basic Voltage Reference Configuration
NOISE PERFORMANCE
The noise generated by ADR42x references is typically less
than 2 µV p-p over the 0.1 Hz to 10 Hz band for the ADR420,
ADR421, and ADR423. Figure 24 shows the 0.1 Hz to 10 Hz
noise of the ADR421, which is only 1.75 µV p-p. The noise
measurement is made with a band-pass filter made of a 2-pole
high-pass filter with a corner frequency at 0.1 Hz and a 2-pole
low-pass filter with a corner frequency at 10 Hz.
TURN-ON TIME
At power-up (cold start), the time required for the output
voltage to reach its final value within a specified error band
is defined as the turn-on settling time. Two components typi-
cally associated with this are the time for the active circuits to
settle and the time for the thermal gradients on the chip to
stabilize. Figure 31 to Figure 35 show the turn-on settling time
for the ADR421.
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 17 of 24
APPLICATIONS
OUTPUT ADJUSTMENT
The ADR42x trim terminal can be used to adjust the output
voltage over a ±0.5% range. This feature allows the system
designer to trim system errors out by setting the reference to
a voltage other than the nominal. This is also helpful if the
part is used in a system at temperature to trim out any error.
Adjustment of the output has a negligible effect on the
temperature performance of the device. To avoid degrading
temperature coefficients, both the trimming potentiometer
and the two resistors need to be low temperature coefficient
types, preferably <100 ppm/°C.
02432-041
ADR420/
ADR421/
ADR423/
ADR425
R2
V
IN
INPUT
GND TRIM
R1
470kΩR
P
10kΩ
10kΩ (ADR420)
15kΩ (ADR421)
OUTPUT
V
OUT
= ±0.5%
V
OUT
2
4
5
6
Figure 40. Output Trim Adjustment
REFERENCE FOR CONVERTERS IN OPTICAL
NETWORK CONTROL CIRCUITS
In the high capacity, all optical router network of Figure 41,
arrays of micromirrors direct and route optical signals from
fiber to fiber, without first converting them to electrical form,
which reduces the communication speed. The tiny micro-
mechanical mirrors are positioned so that each is illuminated
by a single wavelength that carries unique information and
can be passed to any desired input and output fiber. The mirrors
are tilted by the dual-axis actuators controlled by precision
analog-to-digital converters (ADCs) and digital-to-analog
converters (DACs) within the system. Due to the microscopic
movement of the mirrors, not only is the precision of the
converters important, but the noise associated with these
controlling converters is extremely critical, because total noise
within the system can be multiplied by the numbers of
converters used. Consequently, the exceptional low noise of the
ADR42x is necessary to maintain the stability of the control
loop for this application.
02432-042
DAC DACADC
DSP
CONTROL
ELECTRONICS
ACTIVATOR
LEFT
LASER BEAM
SOURCE FIBER
GIMBAL + SENSOR
DESTINATION
FIBER
ACTIVATOR
RIGHT
MEMS MIRROR
AMPLPREAMPAMPL
ADR421
ADR421
ADR421
Figure 41. All Optical Router Network
HIGH VOLTAGE FLOATING CURRENT SOURCE
The circuit in Figure 42 can be used to generate a floating
current source with minimal self-heating. This particular
configuration can operate on high supply voltages determined
by the breakdown voltage of the N-channel JFET.
0
2432-044
+
V
S
–V
S
SST111
VISHAY
V
IN
GND
V
OUT
ADR420/
ADR421/
ADR423/
ADR425
2N3904
R
L
2.10kΩ
OP09
2
4
6
Figure 42. High Voltage Floating Current Source
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 18 of 24
KELVIN CONNECTIONS
In many portable instrumentation applications where PC board
cost and area are important considerations, circuit intercon-
nects are often narrow. These narrow lines can cause large
voltage drops if the voltage reference is required to provide load
currents to various functions. In fact, a circuit’s interconnects
can exhibit a typical line resistance of 0.45 mΩ/square (1 oz. Cu,
for example). Force and sense connections, also referred to as
Kelvin connections, offer a convenient method of eliminating
the effects of voltage drops in circuit wires. Load currents flow-
ing through wiring resistance produce an error (VERROR = R × IL)
at the load. However, the Kelvin connection in Figure 43
overcomes the problem by including the wiring resistance
within the forcing loop of the op amp. Because the op amp
senses the load voltage, op amp loop control forces the output to
compensate for the wiring error and to produce the correct
voltage at the load.
02432-045
A1
V
IN
VIN
RLW
A1 = OP191
RLW
RL
VOUT
SENSE
VOUT
FORCE
GND
VOUT
ADR420/
ADR421/
ADR423/
ADR425
2
4
6
Figure 43. Advantage of Kelvin Connection
DUAL-POLARITY REFERENCES
Dual-polarity references can easily be made with an op amp and
a pair of resistors. In order not to defeat the accuracy obtained
by the ADR42x, it is imperative to match the resistance toler-
ance and the temperature coefficient of all components.
02432-046
V
IN
1µF 0.1µF
R1
10kΩ
R3
5kΩ
R2
10kΩ
+5V
–5V
+10V
–10V
6
2
4
5
V+
V–
U1
ADR425
V
OUT
V
IN
TRIM
GND
Figure 44. +5 V and −5 V Reference Using ADR425
U2
OP1177
02432-047
R1
5.6kΩ
R2
5.6kΩ
+2.5
V
+
10
V
–10V
–2.5V
U1
ADR425
6
2
4
5
V+
V–
V
OUT
V
IN
TRIM
GND
U2
OP1177
Figure 45. +2.5 V and −2.5 V Reference Using ADR425
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 19 of 24
PROGRAMMABLE CURRENT SOURCE
Together with a digital potentiometer and a Howland current
pump, the ADR425 forms the reference source for a program-
mable current as
W
B
B
A
LV
R2
R1
R2R2
I×
⎟
⎠
⎞
⎜
⎝
⎛+
= (3)
and
REF
NV
D
VW ×= 2 (4)
where:
D is the decimal equivalent of the input code.
N is the number of bits.
02432-048
U1
ADR425
V
OUT
V
IN
V
DD
V
DD
V
SS
TRIM
GND A
WB
U2
AD5232
U2
DIGITAL POT
IL
V+
V–
2
5
6
4
A1
OP2177
V
DD
V
SS
V+
V–
A2
OP2177
LOAD
VL
R1
50kΩ
R2
A
1kΩ
R2
B
10Ω
C2
10pF
R2'
1kΩ
R1'
50kΩ
C1
10pF
Figure 46. Programmable Current Source
R1' and R2' must be equal to R1 and R2A + R2B, respectively.
Theoretically, R2B can be made as small as needed to achieve
the current needed within A2 output current driving capability.
In the example shown in Figure 46, OP2177 is able to deliver
a maximum of 10 mA. Because the current pump uses both
positive and negative feedback, capacitors C1 and C2 are needed
to ensure that negative feedback prevails and, therefore, avoiding
oscillation. This circuit also allows bidirectional current flow if
the inputs VA and VB of the digital potentiometer are supplied
with the dual-polarity references as previously shown.
PROGRAMMABLE DAC REFERENCE VOLTAGE
With a multichannel DAC, such as the quad, 12-bit voltage
output AD7398, one of its internal DACs, and an ADR42x
voltage reference can be used as a common programmable
VREFx for the rest of the DACs. The circuit configuration is
shown in Figure 47. The relationship of VREFx to VREF depends
on the digital code and the ratio of R1 and R, and is given by
⎟
⎠
⎞
⎜
⎝
⎛×+
⎟
⎠
⎞
⎜
⎝
⎛+×
=
R1
R2D
R1
R2
V
xV
N
REF
REF
2
1
1
(5)
where:
D is the decimal equivalent of input code.
N is the number of bits.
VREF is the applied external reference.
VREFx is the reference voltage for DACs A to D.
Table 9. VREFx vs. R1 and R2
R1, R2 Digital Code VREF
R1 = R2 0000 0000 0000 2 VREF
R1 = R2 1000 0000 0000 1.3 VREF
R1 = R2 1111 1111 1111 VREF
R1 = 3R2 0000 0000 0000 4 VREF
R1 = 3R2 1000 0000 0000 1.6 VREF
R1 = 3R2 1111 1111 1111 VREF
02432-049
V
IN
DACA
DACB
DACC
DACD
AD7398
ADR425
V
REF
V
REF
AV
OUT
AR1
±0.1%
R2
±0.1%
V
OB
= V
REF
x (D
B
)
V
OC
= V
REF
x (D
C
)
V
OD
= V
REF
x (D
D
)
V
OUT
B
V
OUT
C
V
OUT
D
V
REF
B
V
REF
C
V
REF
D
Figure 47. Programmable DAC Reference
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 20 of 24
PRECISION VOLTAGE REFERENCE FOR DATA
CONVERTERS
PRECISION BOOSTED OUTPUT REGULATOR
A precision voltage output with boosted current capability
can be realized with the circuit shown in Figure 49. In this
circuit, U2 forces VOUT to be equal to VREF by regulating the turn
on of N1. Therefore, the load current is furnished by VIN. In
this configuration, a 50 mA load is achievable at VIN of 5 V.
Moderate heat is generated on the MOSFET, and higher current
can be achieved by replacing the larger device. In addition, for
a heavy capacitive load with step input, a buffer may be added
at the output to enhance the transient response.
The ADR42x family has a number of features that make it ideal
for use with ADCs and DACs. The exceptionally low noise,
tight temperature coefficient, and high accuracy characteristics
make the ADR42x ideal for low noise applications such as
cellular base station applications.
AD7701 is an example of an ADC that is well suited for the
ADR42x. The ADR421 is used as the precision reference for
the converter in Figure 48. The AD7701 is a 16-bit ADC with
on-chip digital filtering intended for measuring wide dynamic
range and low frequency signals, such as those representing
chemical, physical, or biological processes. It contains a charge-
balancing (Σ-∆) ADC, calibration microcontroller with on-chip
static RAM, clock oscillator, and serial communications port.
02432-051
V
IN
V
OUT
R
L
25Ω
N1
5
6
U12
4
U2
AD8601
5V
2N7002
V+
V–
+
–
ADR421
V
IN
V
OUT
TRIM
GND
02432-050
AD7701
ADR420/
ADR421/
ADR423/
ADR425
V
IN
AV
DD
DV
DD
SLEEP
MODE
DRDY
CS
SCLK
SDATA
DATA READY
READ (TRANSMIT)
SERIAL CLOCK
SERIAL CLOCK
CLKIN
CLKOUT
SC1
SC2
DGND
DV
SS
V
REF
BP/UP
CAL
A
IN
AGND
AV
SS
0.1µF
0.1µF 10µF
+5V
ANALOG
SUPPLY
RANGES
SELECT
CALIBRATE
ANALOG
INPUT
ANALOG
GROUND
–5V
ANALOG
SUPPLY
GND
V
OUT
0.1µF
0.1µF
0.1µF
0.1µF 10µF
Figure 49. Precision Boosted Output Regulator
Figure 48. Voltage Reference for 16-Bit ADC AD7701
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 21 of 24
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 50. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 51. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 22 of 24
ORDERING GUIDE
Initial
Accuracy
Model1
Output
Voltage,
VOUT (V) mV %
Temperature
Coefficient
(ppm/°C)
Temperature
Range
Package
Description
Package
Option Branding
ADR420ARZ 2.048 3 0.15 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR420ARZ-REEL7 2.048 3 0.15 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR420ARMZ 2.048 3 0.15 10 −40°C to +125°C 8-Lead MSOP RM-8 L0C
ADR420ARMZ-REEL7 2.048 3 0.15 10 −40°C to +125°C 8-Lead MSOP RM-8 L0C
ADR420BRZ 2.048 1 0.05 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR420BRZ-REEL7 2.048 1 0.05 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR421AR 2.50 3 0.12 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR421ARZ 2.50 3 0.12 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR421ARZ-REEL7 2.50 3 0.12 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR421ARMZ 2.50 3 0.12 10 −40°C to +125°C 8-Lead MSOP RM-8 R06
ADR421ARMZ-REEL7 2.50 3 0.12 10 −40°C to +125°C 8-Lead MSOP RM-8 R06
ADR421BR 2.50 1 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR421BR-REEL7 2.50 1 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR421BRZ 2.50 1 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR421BRZ-REEL7 2.50 1 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR423ARZ 3.00 4 0.13 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR423ARZ-REEL7 3.00 4 0.13 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR423ARMZ 3.00 4 0.13 10 −40°C to +125°C 8-Lead MSOP RM-8 R0U
ADR423ARMZ-REEL7 3.00 4 0.13 10 −40°C to +125°C 8-Lead MSOP RM-8 R0U
ADR423BRZ 3.00 1.5 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR423BRZ-REEL7 3.00 1.5 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR425ARZ 5.00 6 0.12 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR425ARZ-REEL7 5.00 6 0.12 10 −40°C to +125°C 8-Lead SOIC_N R-8
ADR425ARMZ 5.00 6 0.12 10 −40°C to +125°C 8-Lead MSOP RM-8 R7A#
ADR425ARMZ-REEL7 5.00 6 0.12 10 −40°C to +125°C 8-Lead MSOP RM-8 R7A#
ADR425BR 5.00 2 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR425BR-REEL7 5.00 2 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR425BRZ 5.00 2 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
ADR425BRZ-REEL7 5.00 2 0.04 3 −40°C to +125°C 8-Lead SOIC_N R-8
1 Z = RoHS Compliant Part. # denotes RoHS-compliant product may be top or bottom marked.
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 23 of 24
NOTES
ADR420/ADR421/ADR423/ADR425
Rev. I | Page 24 of 24
NOTES
©2001–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02432-0-5/11(I)
©2001–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02432-0-5/11(I)
