1
IS66WV51216EALL
IS66/67WV51216EBLL
Rev. B | 10/14/2015 www.issi.com - SRAM@issi.com
DESCRIPTION
The ISSI IS66WV51216EALL and IS66/67WV51216EBLL are
high-speed,8M bit static RAMs organized as 512K words by
16 bits. It is fabricated using ISSI’s high performance CMOS
technology.
This highly reliable process coupled with innovative circuit
design techniques, yields high-performance and low power
consumption devices.
When CS1# is HIGH (deselected) or when CS2 is LOW
(deselected), the device assumes a standby mode at which
the power dissipation can be reduced down with CMOS input
levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs. The active LOW Write Enable (WE#)
controls both writing and reading of the memory. A data byte
allows Upper Byte (UB#) and Lower Byte (LB#) access.
The IS66WV51216 EALL and IS66/67WV51216EBLL are
packaged in the JEDEC standard 48-ball mini BGA
(6mm x 8mm) and 44-Pin TSOP(TYPE-II). The device is also
available for die sales.
High-Speed access time :
- 70ns ( IS66WV51216EALL )
- 60ns (IS66/67WV51216EBLL )
CMOS Lower Power Operation
Single Power Supply
- VDD =1.7V~1.95V( IS66WV51216EALL )
- VDD =2.5V~3.6V (IS66/67WV51216EBLL )
Three State Outputs
Data Control for Upper and Lower bytes
Lead-free Available
8Mb LOW VOLTAGE,
ULTRA LOW POWER PSEUDO CMOS STATIC RAM
Features
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assu
mes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specificatio
n before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected
to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution,
Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
OCTOBER 2015
FUNCTIONAL BLOCK DIAGRAM
I/O0-I/O7
Lower Byte
A0~A18
CS2
Address
Decode Logic
I/O DATA
CIRCUIT
512K X 16
DRAM
Memory Array
COLUMN
I/O
Control
Logic
I/O8-I/O15
Upper Byte
VDD
GND
CS1#
OE#
WE#
LB#
UB#
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IS66WV51216EALL
IS66/67WV51216EBLL
Rev. B | 10/14/2015 www.issi.com - SRAM@issi.com
48-Ball miniBGA (6mm x 8mm) Ball Assignment
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB# OE# A0
I/Q8 UB# A3
I/Q9 I/Q10 A5
GND IQ11 A17
I/Q14 I/Q13 A14
I/Q15 NC A12
A18 A8 A9
A1 A2 CS2
A4 CS1# I/Q0
A6 I/Q1 IQ2
A7 I/Q3 VDD
A15 I/Q5 I/Q6
A13 WE# I/Q7
A10 A11 NC
VDD IQ12 NC A16 I/Q4 GND
Symbol Type Description
A0~A18 Input Address Inputs
I/Q0~I/Q15 Input /
Output
Data Inputs/Outputs
CS1#, CS2 Input Chip Enable
OE# Input Output Enable
WE# Input Write Enable
UB# Input Upper Byte select
LB# Input Lower Byte select
VDD Power Supply Power
GND Power Supply Ground
PIN DESCRIPTIONS
44-pin TSOP (Type II)
A4 1
A3 2
A2 3
5
7
6
8
10
9
A1 4
11
13
12
14
16
15
17
19
18
20
22
21
34
32
33
31
29
30
28
26
27
25
23
24
44
43
41
42
40
38
39
37
35
36
GND
I/O11
VDD
I/O10
I/O8
I/O9
A18
A9
A8
A10
A17
A11
A5
A6
OE#
A7
UB#
I/O15
LB#
I/O14
I/O12
I/O13
VDD
I/O4
GND
I/O5
I/O7
I/O6
WE#
A15
A16
A14
A12
A13
A0
I/O0
CS1#
I/O1
I/O3
I/O2
PIN CONFIGURATIONS
3
IS66WV51216EALL
IS66/67WV51216EBLL
Rev. B | 10/14/2015 www.issi.com - SRAM@issi.com
POWER UP INITIALIZATION
50 us
VDD
VDD( min)
0V Device Initialization Device for Normal Operation
IS66WV51216EALL and IS66/67WV51216EBLL include an on-chip voltage sensor used to launch the power-up
initialization process. When VDD reaches a stable level at or above the VDD (min) the device will require 50μs
to complete its self-initialization process. During the initialization period, CS1# should remain HIGH. When initialize-
ation is complete, the device is ready for normal operation.
TRUTH TABLE
OPERATING RANGE (VDD)
Range Ambient Temperature IS66WV51216EALL
(70ns)
IS66WV51216EBLL
(55ns, 70ns)
IS66WV51216EBLL
(55ns, 70ns)
Industrial –40°C to +85°C 1.7V – 1.95V 2.5V – 3.6V –
Automotive , A1 –40°C to +85°C – – 2.5V – 3.6V
Automotive , A2 –40°C to +105°C – – 2.5V – 3.6V
Notes:
CS2 input signal pin is only available for 48-ball mini BGA package part. CS2 input is internally enabled for
44-pin TSOP II package part.
Mode WE# CS1# CS2 OE# LB# UB# I/O0 –
I/O7
I/O8 –
I/O15
VDD Current
Not
Selected
X
X
H
X
X
L
X
X
X
X
H
X
High-Z
High-Z
High-Z
High-Z
ISB1,ISB2
ISB1,ISB2
Output
Disabled
H
H
L
L
H
H
H
H
L
X
X
L
High-Z
High-Z
High-Z
High-Z
ICC
ICC
Read
H
H
H
L
L
L
H
H
H
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
ICC
ICC
Write
L
L
L
L
L
L
H
H
H
X
X
X
L
H
L
H
L
L
Din
High-Z
Din
High-Z
Din
Din
ICC
ICC
ICC
4
IS66WV51216EALL
IS66/67WV51216EBLL
Rev. B | 10/14/2015 www.issi.com - SRAM@issi.com
ABSOLUTE MAXIMUM RATINGS
Notes:
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only,
and functional operation of the device at these or any other conditions above those indicated in this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Symbol
Parameter
Test
Conditions
VDD
Min.
Max.
Unit
VOH
Output HIGH Voltage
IoH = -1 mA
2.5-3.6V
2.2
—
V
VOL
Output LOW Voltage
IoL = 2.1 mA
2.5-3.6V
—
0.4
V
VIH
Input HIGH Voltage(1)
2.5-3.6V
2.2
VDD + 0.3
V
VIL
Input LOW Voltage(1)
2.5-3.6V
–0.2
0.6
V
ILI
Input Leakage
GND ≤ VIN ≤ VDD
–1
1
μA
ILo
Output Leakage
GND ≤ VOUT ≤ VDD,
Outputs Disabled
–1
1
μA
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.5V-3.6V (IS66/67WV51216EBLL)
Notes:
1. VILL (min.) = –2.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max.) = VDD + 2.0V AC (pulse width < 10ns). Not 100% test
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 1.7V-1.95V(IS66WV51216EALL)
Symbol
Parameter
Test
Conditions
VDD
Min.
Max
.
Unit
VOH
Output HIGH Voltage
IOH = -0.1 mA
1.7-1.95V
1.4
—
V
VOL
Output LOw Voltage
IOL = 0.1 mA
1.7-1.95V
—
0.2
V
VIH
Input HIGH Voltage(1)
1.7-1.95V
1.4
VDD + 0.2
V
VIL
Input LOw Voltage(1)
1.7-1.95V
–0.2
0.4
V
ILI
Input Leakage
GND ≤ VIN ≤ VDD
–1
1
μA
ILo
Output Leakage
GND ≤ VOUT ≤ VDD,
Outputs Disabled
–1
1
μA
Notes:
1. VILL (min.) = –1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max.) = VDD + 1.0V AC (pulse width < 10ns). Not 100% test
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND -0.2 to VDD + 0.3 V
TBIAS Temperature Under BIAS -40 to +85 °C
VDD VDD Related to GND -0.2 to +3.8 V
TSTG Storage Temperature -65 to +150 °C
PT Power Dissipation 1.0 W
5
IS66WV51216EALL
IS66/67WV51216EBLL
Rev. B | 10/14/2015 www.issi.com - SRAM@issi.com
Symbol Description Conditions MIN MAX Unit
CIN Input Capacitance VIN = 0V - 8 pF
CIO Input/Output Capacitance (DQ) Vout = 0V - 10 pF
CAPACITANCE
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST CONDITIONS
AC TEST LOADS
R1
VTM
OUTPUT
30 pF
Including
Jig and
scope
R2
Figure 1
R1
VTM
OUTPUT
5 pF
Including
Jig and
scope
R2
Figure 2
Symbol 1.7V – 1.95V 2.5V – 3.6V
R1(Ω) 3070 1029
R2(Ω) 3150 1728
VREF 0.9V 1.4V
VTM 1.8V 2.8V
Parameter 1.7V – 1.95V
( Unit )
2.5V – 3.6V
( Unit )
Input Pulse Level 0.4V to VDD – 0.2V 0.4V to VDD – 0.3V
Input Rise and Fall
Time 5ns 5ns
Input and Output
Timing and
Reference Level
VREF VREF
Output Load See Figures 1 and 2 See Figures 1 and 2
6
IS66WV51216EALL
IS66/67WV51216EBLL
Rev. B | 10/14/2015 www.issi.com - SRAM@issi.com
1.7V-1.95V POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Conditions Device TYP. MAX.
70ns Unit
ICC
VDD Dynamic
Operating
Supply Current
VDD=Max.,IOUT=0mA,
f=fMAX , All inputs = 0.4V
or VDD – 0.2V
Com.
Ind.
Auto
-
-
-
20
25
30
mA
ICC1
Operating
Supply Current
VDD=Max.,CS1#=0.2V,
WE#= VDD – 0.2V,
f=1MHz
Com.
Ind.
Auto
-
-
-
8
8
10
mA
ISB1 TTL Standby Current
( TTL Inputs )
VDD=Max.,VIN=VIH or VIL,
CS1# = VIH, CS2=VIL ,
f=1MHz
Com.
Ind.
Auto
-
-
-
0.6
0.6
1
mA
ISB2 CMOS Standby Current
( CMOS Inputs )
VDD=Max.,
CS1# > VDD – 0.2V,
CS2 < 0.2V, VIN > VDD – 0.2V
or VIN < 0.2V, f=0
Com.
Ind.
Auto
-
-
-
100
120
150
uA
Notes:
1. At f = f MAX , address and data inputs are cycling at the maximum frequency , f = 0 means no input lines change.
2.5V-3.6V POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Conditions Device TYP MAX
55ns Unit
ICC
VDD Dynamic
Operating
Supply Current
VDD=Max.,IOUT=0mA,
f=fMAX , All inputs = 0.4V
or VDD – 0.3V
Com.
Ind.
Auto
Typ.(2)
-
-
-
25
28
35
15
mA
ICC1
Operating
Supply Current
VDD=Max.,CS1#=0.2V,
WE#= VDD – 0.2V,
f=1MHz
Com.
Ind.
Auto
-
-
-
8
8
10
mA
ISB1 TTL Standby Current
( TTL Inputs )
VDD=Max.,VIN=VIH or VIL,
CS1# = VIH, CS2=VIL ,
f=1MHz
Com.
Ind.
Auto
-
-
-
0.6
0.6
1
mA
ISB2 CMOS Standby Current
( CMOS Inputs )
VDD=Max.,
CS1# > VDD – 0.2V,
CS2 < 0.2V, VIN > VDD – 0.2V
or VIN < 0.2V ,f=0
Com.
Ind.
Auto
Typ.(2)
-
-
-
100
130
150
75
uA
Notes:
1. At f = f MAX , address and data inputs are cycling at the maximum frequency , f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.0V, Ta = 25 ºC , and not 100% tested.
7
IS66WV51216EALL
IS66/67WV51216EBLL
Rev. B | 10/14/2015 www.issi.com - SRAM@issi.com
READ CYCLE SWITCHING CHARACTERISTICS(1)(Over Operating Range)
Symbol Parameter -55 -70 Unit Notes
Min Max Min Max
tRC Read cycle time 60 - 70 - ns
tAA Address Acess Time - 60 - 70 ns 1
tOHA Output Hold Time 10 - 10 - ns
tACS1/ACS2 CS1#/CS2 Acess Time - 60 - 70 ns
tDOE OE# Access Time - 25 - 35 ns 1
tHZOE OE# to High-Z output - 20 - 25 ns 2
tLZOE OE# to Low-Z output 5 - 5 - ns 2
tCSM Maximum CS1#/CS2 pulse width - 15 - 15 us
tHZCS1/HZCS2 CS1#/CS2 to High-Z output 0 20 0 25 ns 2
tLZCS1/HZCS2 CS1#/CS2 to Low-Z output 10 - 10 - ns 2
tBA UB#/LB# Acess Time - 60 - 70 ns 1
tHZB UB#/LB# to High-Z output 0 20 0 25 ns 2
tLZB UB#/LB# to Low-Z output 0 - 0 - ns 2
tCPH CS1# HIGH (CS2 LOW) time 5 - 5 - ns
AC WAVEFORMS
READ CYCLE NO. 1(1) (Address Controlled, OE#= VIL, WE#=VIH, UB# or LB# = VIL)
CS1#
CS2
tRC
Address
DQ 0-15
tOHA tOHA
tAA
PREVIOUS DATA VALID DATA VALID
tCSM
Notes:
1. WE# is HIGH for a Read Cycle.
Notes:
1. Test conditions and output loading are specified in the AC Test Conditions and AC Test Loads (Figure 1) on page 5.
2. Tested with the load in Figure 2. Transition is measured ±100 mV from steady-state voltage. Not 100% tested.
8
IS66WV51216EALL
IS66/67WV51216EBLL
Rev. B | 10/14/2015 www.issi.com - SRAM@issi.com
READ CYCLE NO. 2(1) (CS1#, CS2, OE# and UB#/LB# Controlled)
Notes:
1. Address is valid prior to or coincident with CS1# LOW (CS2 HIGH) transition, and is valid after or coincident with CS1# HI
GH (CS2 LOW) transition.
OE#
CS1#
CS2
UB#,LB#
DOUT
tAA
ADDRESS
tRC
tOHA
tDOE
tCSM
tCSM
tLZOE
tACE1/tACE2
tLZCS1/
tLZCS2
tHZOE
tHZCS1/
tHZCS2
tHZB
tLZB tBA
HIGH-Z DATA VALID
9
IS66WV51216EALL
IS66/67WV51216EBLL
Rev. B | 10/14/2015 www.issi.com - SRAM@issi.com
WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Notes:
1. Test conditions and output loading are specified in the AC Test Conditions and AC Test Loads (Figure 1) on page 5.
2. The internal write time is defined by the overlap of CS1#, UB#, LB# and WE# LOW, CS2 HIGH . All signals must be
in valid states to initiate a Write, but anyone can go inactive to terminate Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signals that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±100 mV from steady-state voltage. Not 100% tested.
4. tPWE > tHzWE + tSD when OE# is LOW.
5. Chip Select Active Time (both CS1# LOW and CS2 HIGH) must not be longer than tCMS of 15 us.
Symbol Parameter -55 -70 Unit Notes
Min Max Min Max
tWC Write Cycle Time 55 - 70 - ns
tSCS1/SCS2 CS1#/CS2 to Write End 45 - 60 - ns
tCSM Maximum CS1#/CS2 pulse width - 15 - 15 us
tAW Address Setup to Write Time 45 - 60 - ns
tHA Address Hold to End of Write 0 - 0 - ns
tSA Address Setup Time 0 - 0 - ns
tPWB UB#/LB# Valid to End of Write 45 - 60 - ns
tPWE WE# Pulse Width 45 - 60 - ns
tSD Data Setup Time 25 - 30 - ns
tHZWE WE# LOW to High-Z output - 20 - 30 ns 3
tLZWE WE# HIGH to Low-Z output 5 - 5 - ns 3
tCPH CS1# HIGH (CS2 LOW) time 5 - 5 - ns
10
IS66WV51216EALL
IS66/67WV51216EBLL
Rev. B | 10/14/2015 www.issi.com - SRAM@issi.com
AC WAVEFORMS
WRITE CYCLE NO. 1(1) (CS1# Controlled, OE#= HIGH or LOW)
ADDRESS
CS1#
CS2
WE#
UB#,LB#
DOUT
DIN
tWC
tCSM
tHA
tAW tPWE
tPWB
tSA tHZWE tLZWE
tSD tHD
DATA- IN VALID
DATA UNDEFINED HIGH-Z
Notes:
1. Write address is valid prior to or coincident with CS1# LOW (CS2 HIGH) transition, and is valid after or coincident with C
S1# HIGH (CS2 LOW) transition.
WRITE CYCLE NO. 2 (WE# Controlled, OE#= HIGH during Write Cycle)
tWC
tSCS1 tHA
tSCS2
tAW tPWE
tSA tHZWE tLZWE
HIGH-Z
tSD tHD
DATA UNDEFINED
DATA -IN VALID
ADDRESS
CS1#
CS2
WE#
UB#,LB#
DOUT
DIN
OE#
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IS66WV51216EALL
IS66/67WV51216EBLL
Rev. B | 10/14/2015 www.issi.com - SRAM@issi.com
WRITE CYCLE NO. 3 (WE# Controlled, OE#= LOW during Write Cycle)
ADDRESS
CS1#
CS2
WE#
UB#,LB#
DOUT
DIN
tWC
tSCS1 tHA
tSCS2
tAW tPWE
tPWB
tSA tHZWE tLZWE
tSD tHD
DATA-IN VALID
DATA UNDEFINED HIGH-Z
OE#LOW
WRITE CYCLE NO. 4 (UB# / LB# Controlled, CS2 is HIGH during Write Cycle)
ADDRESS
CS1#
WE#
DOUT
DIN
tCSM
tSA
tHZWE
tPWB
tHA
DATA IN
VALID
ADDRESS 1 ADDRESS 2
tWC tWC
tPWB
DATA IN
VALID
DATA UNDEFINED tHD
tSD
HIGH-Z
tLZWE
WORD 1 WORD 2
UB#,LB#
tSA
tHA
13
IS66WV51216EALL
IS66/67WV51216EBLL
Rev. B | 10/14/2015 www.issi.com - SRAM@issi.com
AVOIDABLE TIMING and RECOMMENDATIONS
Figure 4b : Recommendation
WE# ,
UB# , LB#
Address
CS1#
CS1#,WE#
UB# &LB#
Address
Figure 4a : tCSM Violation
15us
15us
15us
Notes:
1. PSRAM uses DRAM cell which needs a REFRESH action periodically to retain the information. This REFRESH
action is performed only when the device is not selected (Chip Select Pins are Disabled). A hidden REFRESH action
has to be executed by the device at least once every 15 μs of tCSM.
2. Figure 3a shows a timing example in which consecutive READ cycles for more than 15 us . This timing should be
avoided for proper REFRESH operation.
REFRESH operation can begin only during Chip Select pins are Disabled (CS1# is High and CS2 is Low ) for more than 5ns.
Example on how to avoid tCSM violation in Figure 3a is shown in Figure 3b.
3. Figure 4a shows a timing example in which a single WRITE operation is maintained for a period greater than 15 μs.
Since a proper REFRESH action cannot be performed during device is selected by Chip Select pins, information
stored in the device will not be retained if this timing occurs.
Figure 4b is a timing example of using CS1# signal toggling for proper the WRITE operation
14
IS66WV51216EALL
IS66/67WV51216EBLL
Rev. B | 10/14/2015 www.issi.com - SRAM@issi.com
Config. Speed (ns) Order Part No. Package
512K x16 55 IS66WV51216EBLL-55TLI
IS66WV51216EBLL-55BLI
TSOP-II, Lead-free
mini BGA(6mm x 8mm), Lead-free
70 IS66WV51216EBLL-70TLI
IS66WV51216EBLL-70BLI
TSOP-II, Lead-free
mini BGA(6mm x 8mm), Lead-free
Notes :
1. Please contact ISSI SRAM marketing at sram@issi.com if you need -40 oC to +105 oC product.
Config. Speed (ns) Order Part No. Package
512K x16 70 IS66WV51216EALL-70TLI
IS66WV51216EALL-70BLI
TSOP-II, Lead-free
mini BGA(6mm x 8mm), Lead-free
IS66WV51216EALL
Industrial Temperature Range: (-40oC to +85oC)
Voltage Range : 1.7V to 1.95V
IS66WV51216EBLL
Industrial Temperature Range: (-40oC to +85oC)
Voltage Range : 2.5V to 3.6V
IS67WV51216EBLL
Automotive (A1) Temperature Range: (-40oC to +85oC)
Voltage Range : 2.5V to 3.6V
Config. Speed (ns) Order Part No. Package
512K x16 55 IS67WV51216EBLL-55TLA1
IS67WV51216EBLL-55BLA1
TSOP-II, Lead-free
mini BGA(6mm x 8mm), Lead-free
70 IS67WV51216EBLL-70TLA1
IS67WV51216EBLL-70BLA1
TSOP-II, Lead-free
mini BGA(6mm x 8mm), Lead-free
