P4C1256 HIGH SPEED 32K x 8 STATIC CMOS RAM FEATURES High Speed (Equal Access and Cycle Times) - 12/15/20/25/35 ns (Commercial) - 15/20/25/35/45 ns (Industrial) - 20/25/35/45/55/70 ns (Military) Low Power Single 5V10% Power Supply Easy Memory Expansion Using CE and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Fast tOE Automatic Power Down Packages - 28-Pin 300 mil DIP, SOJ, TSOP - 28-Pin 300 mil Ceramic DIP - 28-Pin 600 mil Plastic and Ceramic DIP - 28-Pin CERPACK - 28-Pin Solder Seal Flat Pack - 28-Pin SOP - 28-Pin LCC (350 mil x 550 mil) - 32-Pin LCC (450 mil x 550 mil) DESCRIPTION The P4C1256 is a 262,144-bit high-speed CMOS static RAM organized as 32K x 8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V10% tolerance power supply. Access times as fast as 12 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P4C1256 is a member of a family of PACE RAMTM products offering fast access times. The P4C1256 devices provides asynchronous operation Functional Block Diagram with matching access and cycle times. Memory locations are specified on address pins A0 to A14. Reading is accomplished by device selection (CE) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE or OE is HIGH or WE is LOW. Package options for the P4C1256 include 28-pin DIP, SOJ, and TSOP packages. For military temperature range, Ceramic DIP and LCC packages are available. Pin ConfigurationS DIP (P5, P6, C5, C5-1, D5-1, D5-2), SOJ (J5), SOP (S11-1, S11-3) CERPACK (F4, FS-5) SIMILAR LCC and TSOP configurations at end of datasheet Document # SRAM119 REV I Revised July 2010 P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM Maximum Ratings(1) Sym Parameter RECOMMENDED OPERATING CONDITIONS Value Unit V Grade(2) Ambient Temp GND VCC 0C to 70C 0V 5.0V 10% Industrial -40C to +85C 0V 5.0V 10% Military -55C to +125C 0V 5.0V 10% VCC Power Supply Pin with Respect to GND -0.5 to +7 VTERM Terminal Voltage with Respect to GND (up to 7.0V) -0.5 to VCC + 0.5 V TA Operating Temperature -55 to +125 C TBIAS Temperature Under Bias -55 to +125 C TSTG Storage Temperature -65 to +150 C Sym Parameter Commercial CAPACITANCES(4) (VCC = 5.0V, TA = 25C, f = 1.0MHz) PT Power Dissipation 1.0 W CIN Input Capacitance IOUT DC Output Current 50 mA COUT Output Capacitance Conditions Typ Unit VIN=0V 8 pF VOUT=0V 10 pF DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Sym Parameter P4C1256 Test Conditions Max Min Max VCC + 0.5 2.2 VCC + 0.5 V 0.8 V VCC + 0.5 V 0.2 V 0.4 V Input High Voltage 2.2 VIL Input Low Voltage -0.5 VHC CMOS Input High Voltage VLC CMOS Input Low Voltage VOL Output Low Voltage (TTL Load) IOL = +8 mA, VCC = Min VOH Output High Voltage (TTL Load) IOH = - 4 mA, VCC = Min Input Leakage Current VCC = Max, VIN = GND to VCC (3) VCC - 0.2 -0.5 VCC = Max, CE = VIH, VOUT = GND to VCC ILO Output Leakage Current ISB Standby Power Supply Current (TTL Input Levels) CE VIH, VCC = Max, f = Max, CE VHC, VCC = Max, f = 0, ISB1 Standby Power Supply Current (CMOS Input Levels) Outputs Open (3) 0.8 VCC + 0.5 0.2 -0.5 (3) VCC - 0.2 -0.5 (3) 0.4 2.4 2.4 V -10 +10 -5 +5 -5 +5 N/A N/A -10 +10 -5 +5 IND/COM -5 +5 N/A N/A MIL -- 45 -- 30 IND/COM -- 30 -- N/A MIL -- 20 -- 10 IND/COM -- 10 -- N/A MIL A IND/COM MIL A mA Outputs Open VIN VLC or VIN VHC Unit Min VIH ILI P4C1256L mA N/A = Not applicable Document # SRAM119 REV I Page 2 P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM DATA RETENTION CHARACTERISTICS (P4C1256L Military Temperature Only) Sym Parameter Test Conditions Typ* VCC= Min 2.0V Max VCC= 3.0V 2.0V Unit 3.0V VDR VCC for Data Retention 2.0 V ICCDR Data Retention Current CE VCC -0.2V, tCDR Chip Deselect to Data Retention Time VIN VCC -0.2V 0 ns tR Operation Recovery Time or VIN 0.2V tRC ns 10 15 100 200 A * TA = +25C tRC = Read Cycle Time This Parameter is guaranteed but not tested DATA RETENTION WAVEFORM POWER DISSIPATION CHARACTERISTICS VS. SPEED Sym ICC Parameter Dynamic Operating Current* Temperature Range -12 -15 -20 -25 -35 -45 -55 -70 Unit Commercial 170 160 155 150 145 N/A N/A N/A mA Industrial N/A 170 165 160 155 150 N/A N/A mA Military N/A N/A 170 165 160 155 150 150 mA * VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH. AC ELECTRICAL CHARACTERISTICS--READ CYCLE (VCC = 5V 10%, All Temperature Ranges)(2) Sym Parameter -12 Min -15 Max Max 15 Min -25 Max Max Max Max Max Max 20 25 35 45 55 70 ns tAC Chip Enable Access Time 12 15 20 25 35 45 55 70 ns tOH Output Hold from Address Change 2 2 2 3 3 3 3 3 ns tLZ Chip Enable to Output in Low Z 2 2 2 3 3 3 3 3 ns tHZ Chip Disable to Output in High Z 5 8 9 11 15 20 25 30 ns tOE Output Enable Low to Data Valid 5 7 9 10 15 20 25 30 ns tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time 5 0 7 0 12 9 0 15 11 0 20 0 15 0 20 0 20 0 20 70 Unit 15 0 55 Min 12 0 45 Min -70 Address Access Time 0 35 Min -55 tAA 0 25 Min -45 Read Cycle Time 0 20 Min -35 tRC Document # SRAM119 REV I 12 Min -20 0 25 0 25 ns ns 30 0 30 ns ns 35 ns Page 3 P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5) TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED) Notes: 1. Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Maximum rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than -3.0V and -100mA, respectively, are permissible for pulse widths up to 20 ns. Document # SRAM119 REV I 4. This parameter is sampled and not 100% tested. 5. WE is HIGH for READ cycle. 6. CE is LOW and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE transition LOW. 8. Transition is measured 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9. Read Cycle Time is measured from the last valid address to the first transitioning address. Page 4 P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM AC CHARACTERISTICS--WRITE CYCLE (VCC = 5V 10%, All Temperature Ranges)(2) -12 -15 -20 -25 -35 -45 -55 -70 Sym Parameter tWC Write Cycle Time 12 15 20 25 35 45 55 70 ns tCW Chip Enable Time to End of Write 9 10 15 18 22 30 35 40 ns tAW Address Valid to End of Write 9 10 15 20 25 35 40 45 ns tAS Address Setup Time 0 0 0 0 0 0 0 0 ns tWP Write Pulse Width 9 11 15 18 22 25 30 35 ns tAH Address Hold Time 0 0 0 0 0 0 0 0 ns tDW Data Valid to End of Write 8 9 11 13 15 20 25 30 ns tDH Data Hold Time 0 0 0 0 0 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write Min Max Min 7 3 Max Min 8 3 Max Min 10 3 Max Min 11 3 Max Min 15 3 Max Min 18 3 Max Min 25 3 Max 30 3 Unit ns ns TIMING WAVEFORM OF WRITE Cycle No. 1 (WE Controlled)(10,11) Notes: 10. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show tWZ and tOW. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state Document # SRAM119 REV I 13. Write Cycle Time is measured from the last valid address to the first transitioning address. Page 5 P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM Timing Waveform of Write Cycle No. 2 (CE Controlled)(10) AC TEST CONDITIONS Input Pulse Levels TRUTH TABLE GND to 3.0V Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figures 1 and 2 Mode I/O Power CE OE WE Standby H X X High Z Standby DOUT Disabled L H H High Z Active Read L L H DOUT Active Write L X L High Z Active Figure 1. Output Load Figure 2. Thevenin Equivalent Note: Because of the ultra-high speed of the P4C1256, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 F high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.73V (Thevenin Voltage) at the comparator input, and a 116 resistor must be used in series with DOUT to match 166 (Thevenin Resistance). * including scope and test fixture. Document # SRAM119 REV I Page 6 P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM ORDERING INFORMATION Document # SRAM119 REV I Page 7 P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM LCC PIN CONFIGURATIONS 28-Pin LCC (L5) 32-Pin LCC (L6) TSOP (T1) Document # SRAM119 REV I Page 8 P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM SIDE BRAZED CERAMIC DUAL IN-LINE PACKAGE (300 MILS) C5 Pkg # # Pins 28 (300 mil) Symbol Min Max A - 0.225 b 0.014 0.026 b2 0.045 0.065 C 0.008 0.018 D - 1.485 E 0.240 0.310 eA 0.300 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.070 S1 0.005 - S2 0.005 - SIDE BRAZED CERAMIC DUAL IN-LINE PACKAGE (600 MILS) Pkg # C5-1 # Pins 28 (600 mil) Symbol Min Max A - 0.232 b 0.014 0.026 b2 0.045 0.065 C 0.008 0.018 D - 1.490 E 0.500 0.610 eA 0.600 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.060 S1 0.005 - S2 0.005 - Document # SRAM119 REV I Page 9 P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM CERDIP DUAL IN-LINE PACKAGE D5-1 Pkg # # Pins 28 (600 mil) Symbol Min Max A - 0.232 b 0.014 0.026 b2 0.045 0.065 C 0.008 0.018 D - 1.490 E 0.500 0.610 eA 0.600 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.060 S1 0.005 - 0 15 CERDIP DUAL IN-LINE PACKAGE Pkg # D5-2 # Pins 28 (300 mil) Symbol Min Max A - 0.225 b 0.014 0.026 b2 0.045 0.065 C 0.008 0.018 D - 1.485 E 0.240 0.310 eA 0.300 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.060 S1 0.005 - 0 15 Document # SRAM119 REV I Page 10 P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM CERPACK CERAMIC FLAT PACKAGE F4 Pkg # # Pins 28 Symbol Min Max A 0.060 0.090 b 0.015 0.022 c 0.004 0.009 D - 0.730 E 0.330 0.380 e 0.050 BSC k 0.005 0.018 L 0.250 0.370 Q 0.026 0.045 S - 0.085 S1 0.005 - Pkg # FS-5 # Pins 28 SOLDER SEAL FLAT PACK Symbol Min Max A 0.090 0.130 b 0.015 0.022 c 0.004 0.009 D 0.740 E 0.380 0.420 E1 - 0.440 E2 0.180 - E3 0.030 - e 0.050 BSC L 0.250 0.370 Q 0.026 0.045 S1 0.000 - Document # SRAM119 REV I Page 11 P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM SOJ SMALL OUTLINE IC PACKAGE J5 Pkg # # Pins 28 (300 mil) Symbol Min Max A 0.120 0.148 A1 0.078 - b 0.014 0.020 C 0.007 0.011 D 0.700 0.730 e 0.050 BSC E 0.292 0.300 E1 0.335 0.347 E2 0.262 0.272 Q 0.025 - Pkg # L5 # Pins 28 RECTANGULAR LEADLESS CHIP CARRIER (28 PINS) Symbol Min Max A 0.060 0.075 A1 0.050 0.065 B1 0.022 0.028 D 0.342 0.358 D1 0.200 BSC D2 0.100 BSC D3 - 0.358 E 0.540 0.560 E1 0.400 BSC E2 0.200 BSC E3 - 0.558 e 0.050 BSC h 0.040 REF j 0.020 REF L 0.045 0.055 L1 0.045 0.055 L2 0.075 0.095 ND 5 NE 9 Document # SRAM119 REV I Page 12 P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM Pkg # L6 # Pins 32 RECTANGULAR LEADLESS CHIP CARRIER (32 PINS) Symbol Min Max A 0.060 0.075 A1 0.050 0.065 B1 0.022 0.028 D 0.442 0.458 D1 0.300 BSC D2 0.150 BSC D3 - 0.458 E 0.540 0.560 E1 0.400 BSC E2 0.200 BSC E3 - 0.558 e 0.050 BSC h 0.040 REF j 0.020 REF L 0.045 0.055 L1 0.045 0.055 L2 0.075 0.095 ND 7 NE 9 Pkg # P5 # Pins 28 (300 mil) Symbol Min Max A - 0.210 b 0.014 0.023 b2 0.045 0.070 C 0.008 0.014 D 1.345 1.400 E1 0.270 0.300 E 0.300 0.380 A1 e PLASTIC DUAL IN-LINE PACKAGE - 0.100 BSC eB - 0.430 L 0.115 0.150 0 15 Document # SRAM119 REV I Page 13 P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM PLASTIC DUAL IN-LINE PACKAGE P6 Pkg # # Pins 28 (600 mil) Symbol Min Max A 0.090 0.200 A1 0.000 0.070 b 0.014 0.020 b2 0.015 0.065 C 0.008 0.012 D 1.380 1.480 E1 0.485 0.550 E 0.600 0.625 e eB 0.100 BSC 0.600 TYP L 0.100 0.200 0 15 Pkg # T1 # Pins 28 TSOP THIN SMALL OUTLINE PACKACGE (8 x 13.4 mm) Symbol Min Max A 0.039 0.047 A2 0.036 0.040 b 0.007 0.011 D 0.461 0.469 E 0.311 0.319 e HD 0.022 BSC 0.520 0.535 Document # SRAM119 REV I Page 14 P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM SOIC/SOP SMALL OUTLINE IC PACKAGE Pkg # S11-1 # Pins 28 (300 Mil) Symbol Min Max A 0.093 0.104 A1 0.004 0.012 b2 0.013 0.020 C 0.009 0.012 D 0.696 0.712 e 0.050 BSC E 0.291 0.299 H 0.394 0.419 h 0.010 0.029 L 0.016 0.050 0 8 SOIC/SOP SMALL OUTLINE IC PACKAGE Pkg # S11-3 # Pins 28 (300 Mil) Symbol Min Max A 0.094 0.110 A1 0.002 0.014 B 0.014 0.020 C 0.008 0.012 D 0.702 0.710 e 0.050 BSC E 0.291 0.300 H 0.463 0.477 h 0.010 0.029 L 0.020 0.042 0 8 Document # SRAM119 REV I Page 15 P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM REVISIONS DOCUMENT NUMBER SRAM 119 DOCUMENT TITLE P4C1256 HIGH SPEED 32K x 8 STATIC CMOS RAM REV ISSUE DATE ORIGINATOR OR 1997 RKK New Data Sheet A Oct-2005 JDB Changed logo to Pyramid B Oct-2005 JDB Added SOP package C Apr-2006 JDB Added Lead-Free to ordering information D May-2006 JDB Added PDIP to ordering information E Jun-2006 JDB Added ceramic DIP package F Aug-2006 JDB Updated SOJ package information G Jun-2007 JDB Corrected SOP package information H July-2009 JDB Added 28-pin 600 mil CERDIP, 600 mil PDIP. I July 2010 JDB Added 28-pin Solder Seal Flat Pack Document # SRAM119 REV I DESCRIPTION OF CHANGE Page 16