General Description
The MAX8798 includes a high-performance, step-up
regulator; a high-speed operational amplifier; a digitally
adjustable VCOM calibration device with nonvolatile
memory; an I2C interface; and a high-voltage, level-shift-
ing scan driver. The device is optimized for thin-film
transistor (TFT) liquid-crystal display (LCD) applications.
The step-up DC-DC converter provides the regulated
supply voltage for panel source driver ICs. The high
switching frequency allows the use of ultra-small induc-
tors and ceramic capacitors. The current-mode control
architecture provides fast transient response to pulsed
loads typical of source driver loads. The step-up regu-
lator features soft-start and current limit.
The high-current operational amplifier is designed to
drive the LCD backplane (VCOM). The amplifier fea-
tures high output current (±150mA), fast slew rate
(45V/µs), wide bandwidth (20MHz), and rail-to-rail
inputs and outputs.
The programmable VCOM calibrator is externally
attached to the VCOM amplifier’s resistive voltage-divider
and sinks a programmable current to adjust the VCOM
output-voltage level. An internal 7-bit digital-to-analog
converter (DAC) controls the sink current. The DAC is
ratiometric relative to BOOST and is guaranteed to be
monotonic over all operating conditions. The calibrator IC
includes an EEPROM to store the desired VCOM voltage
level. The 2-wire I2C interface between the LCD panel
and the programming circuit minimizes panel connector
lead count and simplifies production equipment.
The high-voltage, level-shifting scan driver is designed
to drive the TFT panel gate drivers. Its three outputs
swing 65V (maximum) between +45V (maximum) and
-25V (minimum) and can swiftly drive capacitive loads.
To save power, the two complementary outputs are
designed to allow charge sharing during state changes.
The MAX8798 is available in a 36-pin, thin QFN pack-
age with a maximum thickness of 0.8mm for ultra-thin
LCD panels.
Applications
Notebook Computer Displays
LCD Monitor Panels
Features
♦1.8V to 5.5V IN Supply Voltage Range
♦1.8V to 4.0V VDD Input Voltage Range
♦1.2MHz Current-Mode Step-Up Regulator
Fast Transient Response
Built-In 20V, 1.9A, 150mΩMOSFET
♦High-Speed (20MHz) Operational Amplifier
±150mA Output Current
♦High-Voltage Drivers with Scan Logic
+45V to -25V Outputs
65V (maximum) Swing
Output Charge Sharing
♦Programmable VCOM Calibrator
7-Bit Adjustable Current-Sink Output
I2C Interface
EEPROM Setting Memory
♦Thermal-Overload Protection
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
SCAN DRIVER
LOGIC
AND
GATE DRIVERS
VMAIN
VIN
VN VP
TO VCOM
BACKPLANE
SDA
COMP
LX
PGND
BGND
VCOM
POS
NEG
FB
VP
SCL
BOOST
GON
IN
SET
STVP
GOFF
CKVBCS
CKV
SHDN
OECON
STV
OE
CPV
WPN
CKVCS
CKVB
WPPSCLS
VDD
OUT
I2C
BUS
VIN
SYSTEM
VN
PANEL
VL 3.3V
LINEAR
REG
VCOM CALIBRATOR
7
GND
AGND
1.9A
STEP-UP
REG
DISH
1kΩ
50kΩ
Simplified Operating Circuit
19-0971; Rev 1; 6/08
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-
PACKAGE
PKG
CODE
MAX8798ETX+ -40°C to +85°C 36 Thin QFN
6mm x 6mm T-3666M-1
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN = VDD = VSHDN = +3V, circuit of Figure 2, VBOOST = 8V, VGON = 23V, VGOFF = -12V, VPOS = 0, VNEG = 1.5V, VOE = VCPV =
VSTV = VOECON = 0, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN, VL, SHDN to AGND .........................................-0.3V to +7.5V
VDD, SDA, SCL, SCLS, WPN, WPP, SET to GND...-0.3V to +4.0V
OECON, CPV, OE, STV to AGND..........................-0.3V to +4.0V
COMP, FB to AGND ......................................-0.3V to (VL + 0.3V)
DISH to GND ............................................................-6V to +2.0V
LX to PGND ............................................................-0.3V to +20V
OUT, VCOM, NEG, POS to BGND........-0.3V to (BOOST + 0.3V)
PGND, BGND, AGND to GND...............................-0.3V to +0.3V
GON to AGND ........................................................-0.3V to +50V
GOFF to AGND .............................................-30V to (VIN + 0.3V)
GON to GOFF ......................................................................+70V
BOOST to BGND ....................................................-0.3V to +20V
CKV, CKVB, STVP, CKVCS,
CKVBCS to AGND..................(GOFF - 0.3V) to (GON + 0.3V)
LX, PGND RMS Current Rating.............................................2.4A
Continuous Power Dissipation (TA= +70°C)
NiPd Lead Frame with Nonconductive Epoxy
36-Pin, 6mm x 6mm Thin QFN
(derate 27.2mW/°C above +70°C) .........................2179.8mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Input Voltage Range 1.8 4.0 V
VDD Quiescent Current VDD = 3V 4 10 μA
VDD Undervoltage Lockout VDD rising; typical hysteresis 100mV 1.3 1.75 V
IN Input Voltage Range (Note 1) 1.8 6.0 V
IN Quiescent Current VIN = 3V, VFB = 1.5V, not switching 0.04 0.1 mA
IN Undervoltage Lockout IN rising; typical hysteresis 100mV 1.4 1.75 V
Thermal Shutdown Rising edge, hysteresis = 15 oC 160
oC
BOOTSTRAP LINEAR REGULATOR (VL)
VL Output Voltage IVL = 100μA 3.15 3.3 3.45 V
VL Undervoltage Lockout VL rising, typical hysteresis 200mV 2.4 2.7 3.0 V
VL Maximum Output Current VFB = 1.1V 10 mA
MAIN DC-DC CONVERTER
LX not switching, no load on VL 1.5 2
BOOST Supply Current LX switching, no load on VL 3 4 mA
Operating Frequency 990 1170 1350 kHz
Oscillator Maximum Duty Cycle 88 92 96 %
FB Regulation Voltage 1.216 1.235 1.254 V
FB Load Regulation 0 < ILOAD < 200mA, transient only -1 %
FB Line Regulation VIN = 1.8V to 5.5V, FB to COMP -0.15 -0.08 +0.15 %/V
FB Input Bias Current VFB = 1.25V 50 125 200 nA
FB Transconductance I = 5μA at COMP 70 160 280 μS
FB Voltage Gain FB to COMP 2400 V/V
FB Fault Timer Trip Threshold Falling edge 0.96 1 1.04 V
LX On-Resistance ILX = 1.2A 150 300 m
LX Leakage Current VLX = 18V 0.01 20 μA
LX Current Limit Duty cycle = 65% 1.6 1.9 2.2 A
Current-Sense Transresistance 0.25 0.42 0.55 V/A
Soft-Start Period 3 ms
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
_______________________________________________________________________________________ 3
PARAMETER CONDITIONS MIN TYP MAX UNITS
OPERATIONAL AMPLIFIER
BOOST Supply Range 5 18 V
BOOST Overvoltage
Fault Threshold (Note 2) 18.1 19 19.9 V
BOOST Undervoltage
Fault Threshold (Note 3) 1.0 1.4 V
Large-Signal Voltage Gain 1V < (VNEG, VPOS) < (VBOOST - 1V) 120 dB
Common-Mode Rejection Ratio 1V < (VNEG, VPOS) < (VBOOST - 1V) 75 dB
1V < (VNEG, VPOS) < (VBOOST - 1V) -25 -5 +25
Input Offset Voltage VBOOST/2 -15 -2.5 +12
mV
Input Bias Current 1V < (VNEG, VPOS) < (VBOOST - 1V) -50 +50 nA
Input Common-Mode
Voltage Range 1V < (VNEG, VPOS) < (VBOOST - 1V) 0 VBOOST V
VCOM Output Voltage
Swing High IVCOM = 5mA VBOOST
- 100
VBOOST
- 50 mV
VCOM Output Voltage Swing Low IVCOM = -5mA 50 100 mV
VCOM Output-Current High VVCOM = VBOOST - 1V -75 mA
VCOM Output-Current Low VVCOM = 1V +75 mA
Slew Rate 1V < (VNEG, VPOS) < (VBOOST - 1V) 40 V/μs
-3dB Bandwidth 1V < (VNEG, VPOS) < (VBOOST - 1V) 20 MHz
Short to VBOOST/2, sourcing 50 150
VCOM Short-Circuit Current Short to VBOOST/2, sinking 50 150 mA
PROGRAMMABLE VCOM CALIBRATOR
GON Input Range 16.1 45.0 V
GON Threshold to Enable Program Rising edge, 60mV hysteresis 15.6 16.0 V
SET Voltage Resolution 7 Bits
SET Differential Nonlinearity Monotonic overtemperature -2 +2 LSB
SET Zero-Scale Error -1 +1 +2 LSB
SET Full-Scale Error -3 +3 LSB
SET Current 120 μA
To GND, VBOOST = 18V 8.5 170.0
SET External Resistance
(Note 4) To GND, VBOOST = 6V 2.5 50.0 k
VSET/VBOOST Voltage Ratio DAC full scale 0.05 V/V
OUT Leakage Current When OUT is off 1 nA
OUT Settling Time To ±0.5 LSB error band 20 μs
OUT Voltage Range VSET +
0.5V 18 V
EEPROM Write Cycles (Note 5) 1000 —
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VDD = VSHDN = +3V, circuit of Figure 2, VBOOST = 8V, VGON = 23V, VGOFF = -12V, VPOS = 0, VNEG = 1.5V, VOE = VCPV =
VSTV = VOECON = 0, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
4 _______________________________________________________________________________________
PARAMETER CONDITIONS MIN TYP MAX UNITS
2-WIRE INTERFACE
Logic-Input Low Voltage (VIL) SDA, SCL, WPN, VDD = 3V 0.3 x
VDD V
Logic-Input High Voltage (VIH) SDA, SCL, WPN, VDD = 3V 0.7 x
VDD V
WPP Logic-Output Low Voltage IWPP = 1mA +0.1 V
WPP Logic-Output High Voltage IWPP = 1mA VDD -
0.1 V
SDA Logic-Output Low Sink Current SDA forced to 3.3V 6 mA
Logic Input Current SDA, SCL, SCL_S,WPN to VDD or GND -1 +1 μA
Input Capacitance SDA, SCL, SCL_S 5 pF
SCL Frequency (fCLK) DC 500 kHz
SCL High Time (tCLH) 600 ns
SCL Low Time (tCLL) 1300 ns
SDA, SCL, SCLS Rise Time (tR) CBUS = total capacitance of bus line in pF 20 + 10
x CBUS 300 ns
SDA, SCL, SCLS Fall Time (tF) CBUS = total capacitance of bus line in pF 20 + 10
x CBUS 300 ns
START Condition Hold Time
(tHDSTT)10% of SDA to 90% of SCL 600 ns
START Condition Setup Time
(tSVSTT) 600 ns
Data Input Hold Time (tHDDAT) 0 ns
Data Input Setup Time (tSUDAT) 150 ns
STOP Condition Setup Time
(tSVSTP) 600 ns
Bus Free Time (tUF) 1300 ns
Input Filter Spike Suppression (tSP) SDA, SCL (Note 5) 250 ns
WPN = GND 1 M
SCL-SCLS Switch Resistance WPN = VDD 20 50
HIGH-VOLTAGE SCAN DRIVER
GON Input Voltage Range 12 45 V
GOFF Input Voltage Range -25 -2 V
GON to GOFF VGON - VGOFF 65 V
GON Supply Current STV, CPV, OE, OECON = AGND 250 350 μA
GOFF Supply Current STV, CPV, OE, OECON = AGND 100 200 μA
Output-Voltage Low CKV, CKVB, STVP,
-5mA output current
VGOFF
+ 0.2
VGOFF
+ 0.05 V
Output-Voltage High CKV, CKVB, STVP,
5mA output current
VGON
- 0.05
VGON
- 0.2 V
Propagation Delay Between OE
Rising Edge and CKV/CKVB Edge VCPV = 0, VSTV = 0, CLOAD = 4.7nF, 50 250 450 ns
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VDD = VSHDN = +3V, circuit of Figure 2, VBOOST = 8V, VGON = 23V, VGOFF = -12V, VPOS = 0, VNEG = 1.5V, VOE = VCPV =
VSTV = VOECON = 0, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
_______________________________________________________________________________________ 5
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Slew Rate CKV, CKVB Without charge sharing,
STV = VDD, CLOAD = 4.7nF, 5020 40 V/μs
Propagation Delay Between
STV and STVP CLOAD = 4.7nF 250 450 ns
STVP Output Slew Rate CLOAD = 4.7nF, 50 20 40 V/μs
Charge-Sharing Discharge
Path Resistance
CKV to CKVCS and
CKVB to CKVBCS 250 400
DISH Turn-On Threshold Dish falling -1.8 V
STV, CPV, OE Input Low Voltage 0.8 V
STV, CPV, OE Input High Voltage 1.6 V
OECON Input Low Voltage 1.5 V
OECON Input High Voltage 2.0 V
OECON Sink Current VOECON = 5V = VDD 0.4 0.8 mA
STV, CPV, OE
Input Current
VSTV = VDD or GND,
VCPV = VDD or GND,
VOE = VDD or GND,
VOECON = VDD or GND
-1 +1 μA
CKV, CKVB, STVP Output
High-Impedance Current
VCKV = GON or GOFF, high impedance
VCKVB = GON or GOFF, high impedance
VCKVCS = GON or GOFF, high impedance
VCKVBCS = GON or GOFF, high impedance
VSTVP = GON or GOFF, high impedance
-1 +1 μA
CONTROL INPUTS
Input Low Voltage SHDN 0.6 V
SHDN, 1.8V < VIN < 3.0V 1.8
Input High Voltage SHDN, 3.0V < VIN < 5.5V 2.0 V
SHDN Input Current VSHDN = 0 or 3V -1 +1 μA
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VDD = VSHDN = +3V, circuit of Figure 2, VBOOST = 8V, VGON = 23V, VGOFF = -12V, VPOS = 0, VNEG = 1.5V, VOE = VCPV =
VSTV = VOECON = 0, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
ELECTRICAL CHARACTERISTICS
(VIN = VDD = VSHDN = +3V, circuit of Figure 2, VBOOST = 8V, VGON = 23V, VGOFF = -12V, VPOS = 0, VNEG = 1.5V, VOE = VCPV =
VSTV = VOECON = 0, TA= -40°C to +85°C, unless otherwise noted.) (Note 6)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Input Voltage Range 1.8 4.0 V
VDD Quiescent Current VDD = 3V 10 μA
VDD Undervoltage Lockout VDD rising; typical hysteresis 100mV 1.75 V
IN Input Voltage Range (Note 1) 1.8 6.0 V
IN Quiescent Current VIN = 3V, VFB = 1.5V, not switching 0.1 mA
IN Undervoltage Lockout VIN rising; typical hysteresis 100mV 1.75 V
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VDD = VSHDN = +3V, circuit of Figure 2, VBOOST = 8V, VGON = 23V, VGOFF = -12V, VPOS = 0, VNEG = 1.5V, VOE = VCPV =
VSTV = VOECON = 0, TA= -40°C to +85°C, unless otherwise noted.) (Note 6)
PARAMETER CONDITIONS MIN TYP MAX UNITS
BOOTSTRAP LINEAR REGULATOR (VL)
VL Output Voltage IVL = 100μA 3.15 3.45 V
VL Undervoltage Lockout VVL rising, typical hysteresis 100mV 2.4 3.0 V
MAIN DC-DC CONVERTER
LX not switching, no load on VL 2
BOOST Supply Current LX switching, no load on VL 4 mA
Operating Frequency 990 1350 kHz
Oscillator Maximum Duty Cycle 88 96 %
FB Regulation Voltage 1.216 1.254 V
FB Line Regulation VIN = 1.8V to 5.5V, FB to COMP -0.15 +0.15 %/V
FB Transconductance I = 5μA at COMP 70 280 μS
FB Fault-Timer Trip Threshold Falling edge 0.96 1.04 V
LX On-Resistance ILX = 1.2A 300 m
LX Current Limit Duty cycle = 65% 1.6 2.2 A
OPERATIONAL AMPLIFIER
BOOST Supply Range 5 18 V
BOOST Overvoltage Fault Threshold (Note 2) 18.1 19.9 V
BOOST Undervoltage Fault Threshold (Note 3) 1.4 V
Input Offset Voltage 1V < (VNEG, VPOS) < (VBOOST - 1V) -25 +25 mV
Input Common-Mode Voltage Range 1V < (VNEG, VPOS) < (VBOOST - 1V) 0 VBOOST V
VCOM Output-Voltage Swing High IVCOM = 5mA VBOOST
- 100 mV
VCOM Output-Voltage Swing Low IVCOM = -5mA 100 mV
Short to VBOOST/2, sourcing 50
VCOM Short-Circuit Current Short to VBOOST/2, sinking 50 mA
PROGRAMMABLE VCOM CALIBRATOR
GON Input Range 16.1 45.0 V
GON Threshold to Enable Program Rising edge, 60mV hysteresis 16.0 V
SET Voltage Resolution 7 Bits
SET Differential Nonlinearity Monotonic overtemperature -2 +2 LSB
SET Zero-Scale Error -1 +2 LSB
SET Full-Scale Error -3 +3 LSB
SET Current 120 μA
To GND, VBOOST = 18V 8.5 170.0
SET External Resistance
(Note 4) To GND, VBOOST = 6V 2.5 50.0 k
OUT Voltage Range VSET +
0.5V 18 V
EEPROM Write Cycles (Note 5) 1000 —
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
_______________________________________________________________________________________ 7
PARAMETER CONDITIONS MIN TYP MAX UNITS
2-WIRE INTERFACE
Logic-Input Low Voltage (VIL) SDA, SCL, WPN, VDD = 3V 0.3 x
VDD V
Logic-Input High Voltage (VIH) SDA, SCL, WPN, VDD = 3V 0.7 x
VDD V
WPP Logic-Output Low Voltage IWPP = 1mA +0.1 V
WPP Logic-Output High Voltage IWPP = -1mA VDD -
0.1 V
SDA Logic-Output Low Sink Current SDA forced to 3.3V 6 mA
SCL Frequency (fCLK) DC 500 kHz
SCL High Time (tCLH) 600 ns
SCL Low Time (tCLL) 1300 ns
SDA, SCLS, and SCL Rise Time (tR) CBUS = total capacitance of bus line in pF 20 + 10
x CBUS 300 ns
SDA, SCLS, and SCL Fall Time (tF) CBUS = total capacitance of bus line in pF 20 + 10
x CBUS 300 ns
START Condition Hold Time
(tHDSTT)10% of SDA to 90% of SCL 600 ns
START Condition Setup Time
(tSVSTT) 600 ns
Data Input Hold Time (tHDDAT) 0 ns
Data Input Setup Time (tSUDAT) 150 ns
STOP Condition Setup Time (tSVSTP) 600 ns
Bus Free Time (tUF) 1300 ns
Input Filter Spike Suppression (tSP) SDA, SCL (Note 5) 250 ns
WPN = GND 1 M
SCL-SCLS Switch Resistance WPN = VDD 50
HIGH-VOLTAGE SCAN DRIVER
GON Input Voltage Range 12 45 V
GOFF Input Voltage Range -25 -2 V
GON to GOFF VGON - VGOFF 65 V
GON Supply Current STV, CPV, OE, OECON = AGND 350 μA
GOFF Supply Current STV, CPV, OE, OECON = AGND 200 μA
Output-Voltage Low CKV, CKVB, STVP,
-5mA output current
VGOFF
+ 0.2 V
Output-Voltage High CKV, CKVB, STVP,
5mA output current
VGON
- 0.2 V
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VDD = VSHDN = +3V, circuit of Figure 2, VBOOST = 8V, VGON = 23V, VGOFF = -12V, VPOS = 0, VNEG = 1.5V, VOE = VCPV =
VSTV = VOECON = 0, TA= -40°C to +85°C, unless otherwise noted.) (Note 6)
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
8 _______________________________________________________________________________________
PARAMETER CONDITIONS MIN TYP MAX UNITS
Propagation Delay Between OE
Rising Edge and CKV/CKVB Edge VCPV = 0, VSTV = 0, CLOAD = 4.7nF, 50 450 ns
Output Slew Rate CKV, CKVB Without charge sharing,
STV = VDD, CLOAD = 4.7nF, 5020 V/μs
Propagation Delay Between STV
and STVP CLOAD = 4.7nF 450 ns
STVP Output Slew Rate CLOAD = 4.7nF, 50 20 V/μs
Charge-Sharing Discharge Path
Resistance
CKV to CKVCS and
CKVB to CKVBCS 400
DISH Turn-On Threshold Dish falling -1.8 V
STV, CPV, OE Input Low Voltage 0.8 V
STV, CPV, OE Input High Voltage 1.6 V
OECON Input Low Voltage 1.5 V
OECON Input High Voltage 2.0 V
OECON Sink Current OECON = STV = VDD 0.4 mA
CONTROL INPUTS
Input Low Voltage SHDN 0.6 V
SHDN, 1.8V < VIN < 3.0V 1.8
Input High Voltage SHDN, 3.0V < VIN < 5.5V 2.0 V
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VDD = VSHDN = +3V, circuit of Figure 2, VBOOST = 8V, VGON = 23V, VGOFF = -12V, VPOS = 0, VNEG = 1.5V, VOE = VCPV =
VSTV = VOECON = 0, TA= -40°C to +85°C, unless otherwise noted.) (Note 6)
Note 1: For 5.5V < VIN < 6.0V, use the MAX8798 for no longer than 1% of IC lifetime. For continuous operation, the input voltage
should not exceed 5.5V.
Note 2: Inhibits boost switching if VBOOST exceeds the threshold This fault is not latched.
Note 3: Step-up regulator switching is not enabled until BOOST is above undervoltage threshold.
Note 4: SET external resistor range is verified at DAC full scale.
Note 5: Guaranteed by design, not production tested.
Note 6: -40°C specs are guaranteed by design, not production tested.
tF
tCLL
tCLH
tHDDAT tSUDAT
tSUSTP tBF
tR
SDA
SCL
VIH
VIL
tHDSTT
Figure 1. Timing Definitions Used in the Electrical Characteristics
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
_______________________________________________________________________________________
9
STEP-UP REGULATOR EFFICIENCY
vs. LOAD CURRENT
MAX17088 toc01
LOAD CURRENT (mA)
EFFICIENCY (%)
10010
50
60
70
80
90
100
40
1 1000
VIN = 5.0V
VIN = 3.0V
VIN = 2.2V
STEP-UP REGULATOR OUTPUT
LOAD REGULATION vs. LOAD CURRENT
MAX17088 toc02
LOAD CURRENT (mA)
OUTPUT ERROR (%)
10010
-0.8
-0.6
-0.4
-0.2
0
0.2
-1.0
1 1000
VIN = 5.0V
VIN = 3.0V
VIN = 2.2V
IN SUPPLY QUIESCENT CURRENT
vs. IN SUPPLY VOLTAGE
MAX17088 toc03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (μA)
4.92.7 3.8
10
30
20
40
50
70
60
80
0
1.6 6.0
0.2A
NO LOAD
STEP-UP REGULATOR SUPPLY CURRENT
vs. TEMPERATURE
MAX17088 toc04
TEMPERATURE (°C)
BOOST SUPPLY CURRENT (mA)
IN SUPPLY CURRENT (μA)
35 60-15 10
0.5
1.0
1.5
2.0
2.5
3.0
0
5
10
15
20
35
30
25
40
0
-40 85
IIN
IBOOST
STEP-UP CONVERTER SWITCHING
FREQUENCY vs. INPUT VOLTAGE
MAX8798 toc05
INPUT VOLTAGE (V)
SWITCHING FREQUENCY (MHz)
4.92.7 3.8
1.11
1.12
1.14
1.13
1.15
1.17
1.16
1.19
1.18
1.20
1.10
1.6 6.0
200mA LOAD
STEP-UP REGULATOR
HEAVY-LOAD SOFT-START
MAX8798 toc06
2ms/div
LX
5V/div
0V
VMAIN
5V/div
0V
IL
500mA/div
0A
0V
SHDN CONTROL
5V/div
STEP-UP REGULATOR LOAD TRANSIENT
RESPONSE (20mA TO 300mA)
MAX8798 toc07
100μs/div
VLX
10V/div
0V
IL
1A/div
0mV
VMAIN (AC-COUPLED)
200mV/div
LOAD CURRENT
200mA/div
L = 3.6μH
RCOMP = 100kΩ
CCOMP1 = 220pF
0A
0mA
Typical Operating Characteristics
(Circuit of Figure 2, VIN = 3V, TA= +25°C, unless otherwise noted.)
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
10 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 2, VIN = 3V, TA= +25°C, unless otherwise noted.)
STEP-UP REGULATOR PULSED LOAD
TRANSIENT RESPONSE (20mA TO 1A)
MAX17088 toc08
10μs/div
VLX
10V/div
L = 3.6μH
RCOMP = 100kΩ
CCOMP1 = 220pF 0V
0A
IL
1A/div
0mV
VMAIN
AC-COUPLED
200mV/div
0A
IMAIN
1A/div
TIMER-DELAY LATCH
RESPONSE TO OVERLOAD
MAX17088 toc09
10ms/div
VLX
10V/div
0V
0V
0A
VMAIN
5V/div
IL
2A/div
0A
LOAD CURRENT
1A/div
BOOST SUPPLY CURRENT
vs. BOOST SUPPLY VOLTAGE
MAX17088 toc11
OUTPUT VOLTAGE (V)
INPUT CURRENT (mA)
1269
0.5
1.0
1.5
2.0
2.5
3.0
0
315
VIN = 3.3V
VIN = 5V
NO LOAD ON VMAIN
BOOST SUPPLY CURRENT
vs. TEMPERATURE
MAX17088 toc12
TEMPERATURE (°C)
BOOST CURRENT (mA)
35 60-15 10
0.5
1.0
1.5
2.0
2.5
3.5
3.0
0
-40 85
VBOOST = 15V
VBOOST = 8V
OPERATIONAL AMPLIFIER
FREQUENCY RESPONSE
MAX17088 toc13
FREQUENCY (Hz)
GAIN (dB)
10k1k
-20
-15
-10
-5
0
10
5
-25
100 100k
NO LOAD
100pF LOAD 33pF LOAD
OPERATIONAL AMPLIFIER PSRR
vs. FREQUENCY
MAX17088 toc14
FREQUENCY (Hz)
GAIN (dB)
10k1k
-40
-35
-30
-25
-20
-15
-10
0
-5
-45
100 100k
OPERATIONAL AMPLIFIER RAIL-TO-RAIL
INPUT/OUTPUT WAVEFORMS
MAX17088 toc15
10μs/div
VPOS
5V/div
0V
0V
VVCOM
5V/div
POWER-UP SEQUENCE
OF ALL SUPPLY OUTPUTS
MAX17088 toc10
2ms/div
VL
5V/div
0V
0V
0V
0V
0V
0V
VGON
20V/div
VCOM
5V/div
VMAIN
5V/div
VIN
5V/div
VGOFF
20V/div
SHDN
5V/div
SHDN
CONTROL
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
______________________________________________________________________________________
11
OPERATIONAL AMPLIFIER
LOAD TRANSIENT RESPONSE
MAX8798 toc16
2μs/div
VVCOM
(AC-COUPLED)
200mV/div
0mV
0mA
IVCOM
100mA/div
OPERATIONAL AMPLIFIER
LARGE-SIGNAL STEP RESPONSE
MAX8798 toc17
200ns/div
VPOS
2V/div
0V
0V
VCOM
2V/div
OPERATIONAL AMPLIFIER
SMALL-SIGNAL STEP RESPONSE
MAX8798 toc18
200ns/div
VPOS
(AC-COUPLED)
100mV/div
0mV
0mV
VCOM
(AC-COUPLED)
100mV/div
Typical Operating Characteristics (continued)
(Circuit of Figure 2, VIN = 3V, TA= +25°C, unless otherwise noted.)
CPV AND OE/CKV AND CKVB INPUT/OUTPUT
WAVEFORMS WITH LOGIC INPUT
(STV = 0V, CLOAD = 5.0nF AND 50Ω, R1, R2 = 200Ω)
MAX8798 toc19_1
4μs/div
CPV
5V/div
0V
OE
5V/div
0V
CKV
20V/div
0V
CKVB
20V/div
0V
STV RISING EDGE
PROPAGATION DELAY
MAX8798 toc20
100ns/div
STV
5V/div
0V
0V
STVP
10V/div
OE/CKV RISING EDGE
PROPAGATION DELAY
MAX8798 toc20_1
100ns/div
OE
5V/div
0V
0V
CKV
10V/div
STV FALLING EDGE
PROPAGATION DELAY
MAX8798 toc21
100ns/div
STV
5V/div
0V
0V
STVP
10V/div
OE/CKV FALLING EDGE
PROPAGATION DELAY
MAX8798 toc21_1
100ns/div
OE
5V/div
0V
0V
CKV
10V/div
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
12 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 2, VIN = 3V, TA= +25°C, unless otherwise noted.)
CALIBRATOR SIGNAL LSB
DOWNWARD STEP RESPONSE
MAX8798 toc22
40μs/div
SCL
5V/div
SDA
5mV/div
0V
0V
0mV
0mV
VCOM
(AC-COUPLED)
10mV/div
VSET
(AC-COUPLED)
10mV/div
CALIBRATOR SIGNAL LSB
UPWARD STEP RESPONSE
MAX8798 toc23
40μs/div
SCL
5V/div
SDA
5V/div
0V
0V
0mV
0mV
VCOM
(AC-COUPLED)
10mV/div
VSET
(AC-COUPLED)
10mV/div
CALIBRATOR FULL-SCALE
UPWARD STEP RESPONSE
MAX8798 toc24
40μs/div
SCL
5V/div
SDA
5V/div
0V
0V
4.025V
2.422V
0mV
VCOM
2V/div
VSET
200mV/div
CALIBRATOR FULL-SCALE
DOWNWARD STEP RESPONSE
MAX8798 toc25
40μs/div
SCL
5V/div
SDA
5V/div
0V
0V
4.025V
2.422V
0mV
VCOM
2V/div
VSET
200mV/div
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
______________________________________________________________________________________ 13
Pin Description
PIN NAME FUNCTION
1 CKV
High-Voltage, Gate-Pulse Output. When enabled, CKV toggles between its high state (connected to
GON) and its low state (connected to GOFF) on each falling edge of the CPV input. Further, CKV is high
impedance whenever CPV and OE are both low or whenever CPV is low and OECON is high.
2 CKVCS
CKV Charge-Sharing Connection. CKVCS connects to CKV whenever CKV is high impedance to allow
connection to CKVB, sharing charge between the capacitive loads on these two outputs.
3 CKVBCS
CKVB Charge-Sharing Connection. CKVBCS connects to CKVB whenever CKVB is high impedance to
allow connection to CKV, sharing charge between the capacitive loads on these two outputs.
4 CKVB
High-Voltage, Gate-Pulse Output. CKVB is the inverse of CKV during active states and is high
impedance whenever CKV is high impedance.
5 STVP
High-Voltage, Start-Pulse Output. STVP is low (connected to GOFF) whenever STV is low and is high
(connected to GON) only when STV is high and CPV and OE are both low. When STV is high and either
CPV or OE is high, STVP is high impedance.
6 STV
Vertical Sync Input. The rising edge of STV begins a frame of data. The STV input is used to generate the
high-voltage STVP output.
7 OECON
Active-Low, Output-Enable Timing Input. OECON is driven by an RC-filtered version of the OE input signal. If
OE remains high long enough for the resistor to charge the capacitor up to the OECON threshold, the OE
signal is masked until OE goes low and the capacitor is discharged below the threshold through the resistor.
8 OE
Active-High, Gate-Pulse Output Enable. CKV and CKVB leave the high-impedance charge-sharing state
on the rising edge of OE.
9 CPV
Vertical Clock-Pulse Input. CPV controls the timing of the CKV and CKVB outputs that change state (by
first sharing charge) on its falling edge.
10 GND Logic Ground
11 DISH
GOFF Discharge Input. Pulling DISH below ground activates an internal connection between GOFF and
GND, rapidly discharging the GOFF supply. Typically, DISH is capacitively connected to IN, so that
when VIN falls GOFF is discharged.
12 VDD Supply Input. Logic supply input for the VCOM calibrator. Bypass to GND through a minimum 0.1μF
capacitor.
13 WPN
Active-Low, Write-Protect Input. When WPN is low, I2C commands are ignored and the VCOM calibrator
settings cannot be modified.
14 SCLS
Alternate I2C-Compatible Clock Input. When WPN is high, SCLS connects to SCL to drive SCL from an
alternate clock source.
15 SCL I2C-Compatible Clock Input and Output
16 SDA I2C-Compatible Serial Bidirectional Data Line
17 WPP
Write-Protect Output. WPP is the inverse of WPN. It can be used to control active-high, write-protect
inputs on other devices.
18 SET
Full-Scale, Sink-Current Adjustment Input. Connect a resistor, RSET, from SET to GND to set the full-
scale adjustable sink current that is VBOOST / (20 x RSET). IOUT is equal to the current through RSET.
19 VL
3.3V On-Chip Regulator Output. This regulator powers internal analog circuitry for the step-up regulator,
op amp, and VCOM calibrator. External loads up to 10mA can be powered. Bypass VL to GND with a
0.22μF or greater ceramic capacitor.
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
14 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
20 BGND Amplifier Ground
21 BOOST
Operational Amplifier Supply Input. Connect to VMAIN (Figure 2) and bypass to BGND with a 1μF or
greater ceramic capacitor.
22 OUT
Adjustable Sink-Current Output. OUT connects to the resistive voltage-divider at the op amp input POS
(between BOOST and GND) that determines the VCOM output voltage. IOUT lowers the divider voltage by
a programmable amount.
23 POS Operational Amplifier Noninverting Input
24 NEG Operational Amplifier Inverting Input
25 VCOM Operational Amplifier Output
26 SHDN Shutdown Control Input. Pull SHDN low to disable the step-up regulator. The VCOM calibrator, op amp,
and scan driver functions remain enabled.
27 IN Step-Up Regulator Supply Input. Bypass IN to AGND (pin 34) with a 1μF or greater ceramic capacitor.
28, 29 LX Switching Node. Connect inductor/catch diode here and minimize trace area for lowest EMI.
30, 31 PGND Power Ground. Source connection of the internal step-up regulator power switch.
32 FB
Feedback Input. Reference voltage is 1.24V nominal. Connect external resistor-divider
midpoint here and minimize trace area. Set VOUT according to: VOUT = 1.24V (1 + R1/R2).
33 COMP
Compensation Input for Error Amplifier. Connect a series RC from COMP to AGND. Typical values are
180k and 470pF.
34 AGND Ground
35 GOFF
Gate-Off Supply. GOFF is the negative supply voltage for the CKV, CKVB, and STVP high-voltage driver
outputs. Bypass to PGND with a minimum of 0.1μF ceramic capacitor.
36 GON
Gate-On Supply. GON is the positive supply voltage for the CKV, CKVB, and STVP high-voltage driver
outputs. Bypass to VMAIN or PGND with a minimum of 0.1μF ceramic capacitor.
— EP
Exposed Backside Pad. Connect to the analog ground plane through multiple vias to enhance thermal
performance.
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
______________________________________________________________________________________ 15
VMAIN
8V, 300mA
VIN
2.2V TO 3.6V
VN
-12V, 20mA
VP
20V, 20mA
TO VCOM
BACKPLANE
SDA
COMP
LX
PGND
BGND
VCOM
POS
NEG
FB
10μF10μF
0.1μF
RCOMP
100kΩ
CCOMP
220pF
SCL
BOOST
R3
200kΩ
R4
200kΩ
2.6μH
IN
SET
GOFF
STVP
GON
CKVBCS
CKV
SHDN
OECON
STV
DISH
OE
CPV
WPN
0.1μF
VP
VN
CKVCS
CKVB
WPPSCLS
VDD
OUT
I2C BUS
VIN
SYSTEM
20kΩ
3nF
PANEL
VL
0.22μF
0.1μF
GND
VL
AGND
1μF
10Ω
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
200Ω
200Ω
20kΩ
20kΩ
RSET
25kΩ
D1
R1
200kΩ
R2
34kΩ
MAX8798
Figure 2. MAX8798 Typical Operating Circuit
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
16 ______________________________________________________________________________________
SCAN DRIVER
LOGIC
AND
GATE DRIVERS
I2C
INTERFACE
VMAIN
VIN
1.8V TO 5.5V
VN VP
TO VCOM
BACKPLANE
SDA
COMP
LX
PGND
BGND
VCOM
POS
NEG
FB
VP
SCL
BOOST
GON
IN
SET
STVP
GOFF
CKVBCS
CKV
SHDN
OECON
STV
DISH
500Ω
250kΩ
OE
CPV
WPN
CKVCS
CKVB
WPPSCLS
VDD
OUT
I2C BUS
VIN
SYSTEM
VN
PANEL
VL VL
DAC
7
GND
VL
AGND
1.6A
min
STEP-UP
Figure 3. MAX8798 Functional Diagram
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
______________________________________________________________________________________ 17
Typical Application Circuit
The MAX8798 typical application circuit (Figure 2) gener-
ates a +8V source-driver supply and approximately +20V
and -12V gate-driver supplies for TFT displays. The input-
voltage range for the IC is from +1.8V to +5.5V; however,
the Figure 2 circuit is designed to operate from 2.2V to
3.6V. Table 1 lists recommended components and Table
2 lists contact information of component suppliers.
Detailed Description
The MAX8798 contains a high-performance step-up
switching regulator; one high-speed operational ampli-
fier; one three-channel, high-voltage level-shifting scan
driver for active-matrix TFT LCDs; and an I2C-controlled
VCOM calibrator. Figure 3 shows the MAX8798 func-
tional diagram.
Step-Up Regulator
The step-up regulator employs a current-mode, fixed-
frequency PWM architecture to maximize loop band-
width and provide fast transient response to pulsed
loads found in source drivers of TFT LCD panels. The
high switching frequency (1.2MHz) allows the use of
low-profile inductors and ceramic capacitors to minimize
the thickness of LCD panel designs. The integrated
high-efficiency MOSFET and the IC’s built-in digital
soft-start functions reduce the number of external com-
ponents required while controlling inrush current. The
output voltage can be set from VIN to 18V with an exter-
nal resistive voltage-divider.
The regulator controls the output voltage and the power
delivered to the output by modulating the duty cycle (D)
of the internal power MOSFET in each switching cycle.
The duty cycle of the MOSFET is approximated by:
DVV
V
MAIN IN
MAIN
≈−
Table 1. Component List
DESIGNATION DESCRIPTION
C1 10μF, 6.3V X5R ceramic capacitor (1206)
TDK C3216X5ROJ106M
C21, C22 4.7μF, 10V X5R ceramic capacitors (1206)
TDK C3216X5R1A475M
D1 3A, 30V Schottky diode (M-flat)
Toshiba CMS02
D2–D5 200mA, 100V, dual, ultra-fast diodes (SOT23)
Fairchild MMBD4148SE
L1 3.6μH, 1.8A inductor
Sumida CM0611BHPNP-3R6MC
Table 2. Component Suppliers
SUPPLIER PHONE FAX WEBSITE
Fairchild Semiconductor 408-822-2000 408-822-2102 www.fairchildsemi.com
Sumida Corp. 847-545-6700 847-545-6720 www.sumida.com
TDK Corp. 847-803-6100 847-390-4405 www.component.tdk.com
Toshiba American Electronic Components, Inc. 949-455-2000 949-859-3963 www.toshibaamerica.com/taec
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
18 ______________________________________________________________________________________
Figure 4 shows the block diagram of the step-up regu-
lator. An error amplifier compares the signal at FB to
1.24V and changes the COMP output. The voltage at
COMP determines the current trip point each time the
internal MOSFET turns on. As the load varies, the error
amplifier sources or sinks current to the COMP output
accordingly to produce the inductor peak current nec-
essary to service the load. To maintain stability at high
duty cycles, a slope-compensation signal is summed
with the current-sense signal.
On the rising edge of the internal clock, the controller
sets a flip-flop, turning on the n-channel MOSFET and
applying the input voltage across the inductor. The cur-
rent through the inductor ramps up linearly, storing
energy in its magnetic field. Once the sum of the cur-
rent-feedback signal and the slope compensation
exceed the COMP voltage, the controller resets the flip-
flop and turns off the MOSFET. Since the inductor cur-
rent is continuous, a transverse potential develops
across the inductor that turns on the diode (D1). The
voltage across the inductor then becomes the differ-
ence between the output voltage and the input voltage.
This discharge condition forces the current through the
inductor to ramp back down, transferring the energy
stored in the magnetic field to the output capacitor and
the load. The MOSFET remains off for the rest of the
clock cycle.
Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) circuit compares the
input voltage at IN with the UVLO threshold (1.3V rising
and 1.2V falling) to ensure that the input voltage is high
enough for reliable operation. The 100mV (typ) hystere-
sis prevents supply transients from causing a restart.
Once the input voltage exceeds the UVLO rising
threshold, startup begins. When the input voltage falls
below the UVLO falling threshold, the controller turns
off the main step-up regulator and the linear regulator,
disables the switch-control block, and the operational
amplifier output becomes high impedance.
SOFT-
START
1.2MHz
OSCILLATOR
TO FAULT LOGIC
1.24V
FB
LX
ILIM
COMPARATOR
ILIMIT
CURRENT
SENSE
PGND
1.0V
COMP
CLOCK
ERROR AMP
PWM
COMPARATOR
SLOPE COMP
FAULT
COMPARATOR
LOGIC AND DRIVER
Figure 4. Step-Up Regulator Block Diagram
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
______________________________________________________________________________________ 19
Linear Regulator (VL)
The MAX8798 includes an internal 3.3V linear regulator.
BOOST is the input of the linear regulator. The input volt-
age range is between 5V and 18V. The regulator powers
all the internal circuitry including the MOSFET gate dri-
ver. Bypass VL to AGND with a 0.22µF or greater ceram-
ic capacitor. Connect BOOST directly to the output of the
step-up regulator. This feature significantly improves the
efficiency at low input voltages.
Bootstrapping and Soft-Start
The MAX8798 features bootstrapping operation. In nor-
mal operation, the internal linear regulator supplies
power to the internal circuitry. Connect the input of the
linear regulator (BOOST) directly to the output of the
step-up regulator. The MAX8798 is enabled when the
voltages at IN and BOOST are above their UVLO
thresholds and the fault latch is not set. After being
enabled, the regulator starts open-loop switching to
generate the supply voltage for the linear regulator. The
internal reference block turns on when the VL voltage
exceeds its 2.7V (typ). When the reference voltage
reaches regulation, the PWM controller and the current-
limit circuit are enabled and the step-up regulator
enters soft-start. During soft-start, the main step-up reg-
ulator directly limits the peak inductor current, allowing
from zero up to the full current-limit value in 128 equal
current steps. The maximum load current is available
after the output voltage reaches regulation (that termi-
nates soft-start), or after the soft-start timer expires in
approximately 3ms. The soft-start routine minimizes
inrush current and voltage overshoot and ensures a
well-defined startup behavior.
Fault Protection
During steady-state operation, the MAX8798 monitors
the FB voltage. If the FB voltage does not exceed 1V
(typ), the MAX8798 activates an internal fault timer. If
there is a continuous fault for the fault-timer duration,
the MAX8798 sets the fault latch, turning off the main
step-up regulator and the linear regulator, disabling the
switch-control block and the operational amplifier.
Once the fault condition is removed, cycle the input
voltage to clear the fault latch and reactivate the
device. The fault-detection circuit is disabled during the
soft-start time.
The MAX8798 monitors BOOST for undervoltage and
overvoltage conditions. If the BOOST voltage is below
1.4V (typ) or above 19V (typ), the MAX8798 disables the
gate driver of the step-up regulator and prevents the
internal MOSFET from switching. The BOOST undervolt-
age and overvoltage conditions do not set the fault latch.
Operational Amplifier
The MAX8798 has an operational amplifier that is typi-
cally used to drive the LCD backplane (VCOM) or the
gamma-correction-divider string. The operational
amplifier features ±150mA output short-circuit current,
40V/µs slew rate, and 20MHz bandwidth. While the op
amp is a rail-to-rail input and output design, its accura-
cy is significantly degraded for input voltages within 1V
of its supply rails (BOOST and BGND).
Short-Circuit Current Limit
The operational amplifier limits short-circuit current to
approximately ±150mA if the output is directly shorted to
BOOST or to AGND. If the short-circuit condition per-
sists, the junction temperature of the IC rises until it
reaches the thermal-shutdown threshold (+160°C typ).
Once the junction temperature reaches the thermal-shut-
down threshold, an internal thermal sensor immediately
sets the thermal-fault latch, shutting off the main step-up
regulator, the linear regulator, the switch-control block,
and the operational amplifier. Those portions of the
device remain inactive until the input voltage is cycled.
Driving Pure Capacitive Loads
The operational amplifier is typically used to drive the
LCD backplane (VCOM) or the gamma-correction-
divider string. The LCD backplane consists of a distrib-
uted series capacitance and resistance, a load that can
be easily driven by the operational amplifier. However,
if the operational amplifier is used in an application with
a pure capacitive load, steps must be taken to ensure
stable operation.
As the operational amplifier’s capacitive load increases,
the amplifier’s bandwidth decreases and gain peaking
increases. A 5Ωto 50Ωsmall resistor placed between
VCOM and the capacitive load reduces peaking, but
also reduces the gain. An alternative method of reducing
peaking is to place a series RC network (snubber) in par-
allel with the capacitive load. The RC network does not
continuously load the output or reduce the gain. Typical
values of the resistor are between 100Ωand 200Ωand
the typical value of the capacitor is 10pF.
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
20 ______________________________________________________________________________________
High-Voltage Level-Shifting Scan Driver
The MAX8798 includes a 3-channel high-voltage (60V)
level-shifting scan driver that includes logic functions
necessary to drive row driver functions on the panel
glass (Figure 5). The driver outputs (CKV, CKVB, STVP)
swing between their power-supply rails (GON and
GOFF) according to the input logic levels on the block’s
inputs (STV, CPV, OE, and OECON) and the internal
logic of the block (Tables 3, 4). STV is the vertical sync
signal. CPV is the horizontal sync signal. OE is the output
enable signal. OECON is a timing signal derived from
OE that blanks OE if it stays high too long. These signals
have CMOS input logic levels set by the IN supply volt-
age. CKV and CKVB are complementary scan clock out-
puts. STVP is the output scan start signal. These output
signals swing from GON to GOFF that have a maximum
range of +45V and -25V. Their 10Ω(typ) output imped-
ance enables them to swiftly drive capacitive loads. The
complementary CKV and CKVB outputs feature power-
saving, charge-sharing inputs (CKVCS, CKVBCS) that
can be used to save power by shorting each output to its
complement during transitions, making a portion of the
transition “lossless.”
PANEL GLASS
COLUMN DRIVER
HIGH-VOLTAGE SHIFT REGISTER
SCAN DRIVER
SYSTEM
VIDEO
TIMING
STV
CKVB
STVP
CKV
OE
CPV
CKV = SCAN CLK ODD
CKVB = SCAN CLK EVEN
STVP = HIGH-VOLTAGE STV
MAX8798
Figure 5. Scan Driver System Diagram
Table 3. STVP Logic
SIGNAL LOGIC STATE
STV H H H L
OECON X X X X
CPV L H X X
OE L X H X
STVP H Hi-Z Hi-Z L
X
= Don’t care.
Table 4. CKV, CKVB Logic
SIGNAL LOGIC STATE
STV H H H L L L L L
OECON X X X L L L H H
CPV L H X L — X L —
OE L X H L X — X X
CKV L H H CS Toggle Toggle CS Toggle
CKVB H L L CS Toggle Toggle CS Toggle
X
= Don’t care. CS = Charge share state.
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
______________________________________________________________________________________ 21
SDA
SCL
VDD
BOOST
RSET
SET
VDD
OUT
VGON
GON
R4
R3
VCOM
VMAIN
EEPROM
BLOCK
DAC
19R
R
7
7
VDD
LINEAR
REGULATOR
POS
NEG
WPN
WPP
SCLS
VCOM
I2C BUS
I2C
CONTROL
INTERFACE
Figure 6. VCOM Calibrator Functional Diagram
GOFF Rapid Discharge Function
(DISH Input)
The DISH input controls a switch between GOFF and
GND. When DISH is pulled below ground by at least
1V, GOFF is rapidly discharged to GND. Typically,
DISH is capacitively coupled to IN so that if IN falls
suddenly, GOFF is discharged to blank the display
(Figure 3).
VCOM Calibrator
The VCOM calibrator is a solid-state alternative to
mechanical potentiometers used for adjusting the LCD
backplane voltage (VCOM) in TFT LCD displays. OUT
attaches to the external resistive voltage-divider at POS
and sinks a programmable current (IOUT), which sets the
VCOM level (Figure 6). An internal 7-bit DAC controls the
sink current and allows the user to increase or decrease
the VCOM level. The DAC is ratiometrically relative to
VBOOST and is monotonic over all operating conditions.
The user can store the DAC setting in an internal
EEPROM. On power-up, the EEPROM presets the DAC
to the last stored setting. The 2-wire I2C interface
between the system controller and the programming cir-
cuit adjusts the DAC and programs the EEPROM when
WPN is high.
The resistive voltage-divider and the BOOST supply set
the maximum value of VCOM. OUT sinks current from the
voltage-divider to reduce the POS voltage level and
VCOM output. The external resistor at SET (RSET) sets the
full-scale sink current and the minimum value of VCOM.
The GON input provides the high voltage required to
program the EEPROM. To allow programming, VGON is
connected to the TFT LCD VGON supply. VGON should
be between 16.1V and 35V. EEPROM programming is
disabled when VGON is below 15.5V (typ). Bypass
VGON to PGND or BOOST (that is bypassed to PGND)
with a 0.1µF or greater capacitor.
Thermal-Overload Protection
The thermal-overload protection prevents excessive
power dissipation from overheating the device. When
the junction temperature exceeds TJ= +160°C, a ther-
mal sensor immediately activates the fault protection
that shuts down the step-up regulator, switch control
block, operational amplifier, and the internal linear reg-
ulator, allowing the device to cool down. Once the
device cools down by approximately 15°C, cycle the
input voltage (below the UVLO falling threshold) to
clear the fault latch and reactivate the device.
The thermal-overload protection protects the controller
in the event of fault conditions. For continuous opera-
tion, do not exceed the absolute maximum junction
temperature rating of TJ= +150°C.
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
22 ______________________________________________________________________________________
Design Procedure
Main Step-Up Regulator
Inductor Selection
The minimum inductance value, peak current rating, and
series resistance are factors to consider when selecting
the inductor. These factors influence the converter’s effi-
ciency, maximum output-load capability, transient
response time, and output-voltage ripple. Physical size
and cost are also important factors to be considered.
The maximum output current, input voltage, output volt-
age, and switching frequency determine the inductor
value. Very high inductance values minimize the cur-
rent ripple, and therefore, reduce the peak current that
decreases core losses in the inductor and I2R losses in
the entire power path. However, large inductor values
also require more energy storage and more turns of
wire that increase physical size and can increase I2R
losses in the inductor. Low inductance values decrease
the physical size, but increase the current ripple and
peak current. Finding the best inductor involves choos-
ing the best compromise between circuit efficiency,
inductor size, and cost.
The equations used here include a constant called LIR
that is the ratio of the inductor peak-to-peak ripple cur-
rent to the average DC inductor current at the full-load
current. The best trade-off between inductor size and
circuit efficiency for step-up regulators generally has an
LIR between 0.3 and 0.5. However, depending on the
AC characteristics of the inductor core material and
ratio of inductor resistance to other power-path resis-
tances, the best LIR can shift up or down. If the induc-
tor resistance is relatively high, more ripple can be
accepted to reduce the number of turns required and
increase the wire diameter. If the inductor resistance is
relatively low, increasing inductance to lower the peak
current can decrease losses throughout the power
path. If extremely thin high-resistance inductors are
used, as is common for LCD panel applications, the
best LIR can increase to between 0.5 and 1.0.
Once a physical inductor is chosen, higher and lower
values of the inductor should be evaluated for efficien-
cy improvements in typical operating regions.
In Figure 2, the LCD’s gate-on and gate-off supply volt-
ages are generated from two unregulated charge
pumps driven by the step-up regulator’s LX node. The
additional load on LX must therefore be considered in
the inductance and current calculations. The effective
maximum output current, IMAIN(EFF) becomes the sum
of the maximum load current of the step-up regulator’s
output plus the contributions from the positive and neg-
ative charge pumps:
where IMAIN(MAX) is the maximum step-up output cur-
rent, nNEG is the number of negative charge-pump
stages, nPOS is the number of positive charge-pump
stages, INEG is the negative charge-pump output cur-
rent, and IPOS is the positive charge-pump output cur-
rent, assuming the initial pump source for IPOS is
VMAIN.
Calculate the approximate inductor value using the typ-
ical input voltage (VIN), the maximum output current
(IMAIN(EFF)), the expected efficiency (ηTYP) taken from
an appropriate curve in the
Typical Operating Char-
acteristics
, and an estimate of LIR based on the above
discussion:
Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input cur-
rent at the minimum input voltage VIN(MIN) using con-
servation of energy and the expected efficiency at that
operating point (ηMIN) taken from an appropriate curve
in the
Typical Operating Characteristics
:
Calculate the ripple current at that operating point and
the peak current required for the inductor:
The inductor’s saturation current rating and the
MAX8798’s LX current limit (ILIM) should exceed IPEAK
and the inductor’s DC current rating should exceed
IIN(DC,MAX). For good efficiency, choose an inductor
with less than 0.1Ωseries resistance.
Considering Figure 2, the maximum load current
(IMAIN(MAX)) is 300mA, with an 8V output and a typical
input voltage of 3.3V. The effective full-load step-up
current is:
ImAmAmAmA
MAIN EFF() ()=+×++×=300 2 20 2 1 20 400
II I
PEAK IN DCMAX RIPPLE
=+
(, ) 2
IVVV
LV f
RIPPLE IN MIN MAIN IN MIN
MAIN OSC
=×−
()
××
() ()
IIV
V
IN DCMAX MAIN EFF MAIN
IN MIN MIN
(, ) ()
()
=×
×η
LV
V
VV
I f LIR
IN
MAIN
MAIN IN
MAIN EFF OSC
TYP
=⎛
⎝
⎜⎞
⎠
⎟−
×
⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟
2
()
η
II nInI
MAIN EFF MAIN MAX NEG NEG POS POS() ( ) ()=+×++×1
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
______________________________________________________________________________________ 23
Choosing an LIR of 0.5 and estimating efficiency of
85% at this operating point:
A 2.6µH inductor is chosen. Then, using the circuit’s
minimum input voltage (3V) and estimating efficiency of
80% at that operating point:
The ripple current and the peak current at that input
voltage are:
Output Capacitor Selection
The total output-voltage ripple has two components: the
capacitive ripple caused by the charging and discharg-
ing of the output capacitance, and the ohmic ripple due
to the capacitor’s equivalent series resistance (ESR):
and:
where IPEAK is the peak inductor current (see the
Inductor Selection
section). For ceramic capacitors, the
output-voltage ripple is typically dominated by
VRIPPLE(C). The voltage rating and temperature charac-
teristics of the output capacitor must also be considered.
Input Capacitor Selection
The input capacitor (CIN) reduces the current peaks
drawn from the input supply and reduces noise injec-
tion into the IC. A 10µF ceramic capacitor is used in
Figure 2 because of the high source impedance seen
in typical lab setups. Actual applications usually have
much lower source impedance since the step-up regu-
lator often runs directly from the output of another regu-
lated supply. Typically, CIN can be reduced below the
values used in Figure 2. Ensure a low noise supply at
IN by using adequate CIN. Alternatively, greater voltage
variation can be tolerated on CIN if IN is decoupled
from CIN using an RC lowpass filter (seen in Figure 2).
Rectifier Diode
The MAX8798’s high switching frequency demands a
high-speed rectifier. Schottky diodes are recommend-
ed for most applications because of their fast recovery
time and low forward voltage. In general, a 2A Schottky
diode complements the internal MOSFET well.
Output Voltage Selection
The output voltage of the main step-up regulator is
adjusted by connecting a resistive voltage-divider from
the output (VMAIN) to AGND with the center tap con-
nected to FB (see Figure 2). Select R2 in the 10kΩto
50kΩrange. Calculate R1 with the following equation:
where VREF, the step-up regulator’s feedback set point,
is 1.235V (typ). Place R1 and R2 close to the IC.
Loop Compensation
Choose RCOMP to set the high-frequency integrator
gain for fast transient response. Choose CCOMP to set
the integrator zero to maintain loop stability.
For low-ESR output capacitors, use the following equa-
tions to obtain stable performance and good transient
response:
To further optimize transient response, vary RCOMP in
20% steps and CCOMP in 50% steps while observing
transient response waveforms.
CVC
IR
COMP OUT OUT
MAIN MAX COMP
≈×
××10 ()
RVV C
LI
COMP IN OUT OUT
MAIN MAX
≈×× ×
×
1000
()
RR V
V
MAIN
REF
12 1=× −
⎛
⎝
⎜⎞
⎠
⎟
VIR
RIPPLE ESR PEAK ESR COUT() ( )
≈
VI
C
VV
Vf
RIPPLE C MAIN
OUT
MAIN IN
MAIN OSC
()
≈−⎛
⎝
⎜⎞
⎠
⎟
VV V
RIPPLE RIPPLE C RIPPLE ESR
=+
() ( )
IA
AA
PEAK =+=133 06
2153...
IVVV
H V MHz A
RIPPLE =×−
()
×× ≈
383
26 8 12 06
..
.
μ
IAV
VA
IN DCMAX(, ) .
..=×
×≈
04 8
308
133
LV
V
VV
A MHz H=⎛
⎝
⎜⎞
⎠
⎟−
×
⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟≈
33
8
833
04 12
085
05 28
2
..
..
.
..μ
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
24 ______________________________________________________________________________________
Setting the VCOM Adjustment Range
The external resistive voltage-divider sets the maximum
value of the VCOM adjustment range. RSET sets the
full-scale sink current, IOUT, which determines the mini-
mum value of the VCOM adjustment range. Large RSET
values increase resolution, but decrease the VCOM
adjustment range. Calculate R3, R4, and RSET using
the following procedure:
1) Choose the maximum VCOM level (VMAX), the mini-
mum VCOM level (VMIN), and the VMAIN supply
voltage.
2) Select R3 between 10kΩand 500kΩbased on the
acceptable power loss from the VMAIN supply rail
connected to BOOST.
3) Calculate R4:
4) Calculate RSET:
5) Verify that ISET does not exceed 120µA:
6) If ISET exceeds 120µA, return to step 2 and choose
a larger value for R1.
7) The resulting resolution is:
A complete design example is given below:
VMAX = 4V, VMIN = 2.4V, VBOOST = 8V
If R3 = 200kΩ, then R4 = 200kΩand RSET =
24.9kΩ.
Resolution = 12.5mV
Applications Information
Power Dissipation
An IC’s maximum power dissipation depends on the
thermal resistance from the die to the ambient environ-
ment and the ambient temperature. The thermal resis-
tance depends on the IC package, PCB copper area,
other thermal mass, and airflow.
The MAX8798, with its exposed backside paddle sol-
dered to 1in2of PCB copper and a large internal
ground plane layer, can dissipate about 2.18W into
+70°C still air. More PCB copper, cooler ambient air,
and more airflow increase the possible dissipation,
while less copper or warmer air decreases the IC’s dis-
sipation capability. The major components of power
dissipation are the power dissipated in the step-up reg-
ulator and the power dissipated by the operational
amplifiers.
The MAX8798’s largest on-chip power dissipation
occurs in the step-up switch, the VCOM amplifier, and
the high-voltage scan-driver outputs.
Visit www.maxim-ic.com/thermal-tutorial for more
information on the general topic of improving thermal
performance.
Step-Up Regulator
The largest portions of the power dissipated by the
step-up regulator are the internal MOSFET, the induc-
tor, and the output diode. If the step-up regulator with
3.3V input and 300mA output has about 85% efficiency,
about 5% of the power is lost in the internal MOSFET,
about 3% in the inductor, and about 5% in the output
diode. The remaining few percent are distributed
among the input and output capacitors and the PCB
traces. If the input power is about 3W, the power lost in
the internal MOSFET is about 150mW.
Operational Amplifier
The power dissipated in the operational amplifier
depends on the output current, the output voltage, and
the supply voltage:
where IVCOM_SOURCE is the output current sourced by
the operational amplifier, and IVCOM_SINK is the output
current that the operational amplifier sinks.
In a typical case where the supply voltage is 8V and
the output voltage is 4V with an output source current
of 30mA, the power dissipated is 120mW.
Scan-Driver Outputs
The power dissipated by the scan-driver outputs (CKV,
CKVB, and STVP) depends on the scan frequency, the
capacitive load, and the difference between the GON
and GOFF supply voltages:
If the scan frequency is 50kHz, the load of the three
outputs is 5nF, and the supply voltage difference is
30V, then the power dissipated is 675mW.
PD f C V V
SCAN SCAN PANEL GON GOFF
=× × × −
()
32
PD I V
SINK VCOM SINK VCOM
=×
_
PD I V V
SOURCE VCOM SOURCE BOOST VCOM
=×−
()
_
(V V
127
MAX MIN
−)
ISET BOOST
=×
V
20 RSET
RR
SET =×−
×
V
20 (V V
MAX
MAX MIN)3
RR43≅
()
×
V
V-V
MAX
BOOST MAX
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
______________________________________________________________________________________ 25
SCL
SDA
START
CONDITION
BUS
FREE
BUS
FREE
S
STOP
CONDITION
P
DATA LINE
STABLE
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 7. I2C Bus START, STOP, and Data Change Conditions
READ BYTE: R/W = 1, MAX8798 OUTPUTS D6–D0 FOLLOWED BY PROG = 0
WRITE BYTE: R/W = 2, DATA = D6–D0, PROG = 1
PROGRAM EEPROM: R/W = 0, D6–D0 = DON'T CARE, PROG = 0
DATA BYTESLAVE ADDRESS
1001111
S
T
A
R
T
S
T
O
P
A
C
K
A
C
K
R/W
P
R
O
G
D6 D0D1D2D3D4D5
Figure 8. I2C Slave Address and Data Byte
VCOM Calibrator Interface
The MAX8798 is a slave-only device with an I2C address
of 9Eh. The 2-wire I2C-bus-like serial interface (SCL and
SDA) is designed to attach to a 1.8V to 4V I2C bus.
Connect both SCL and SDA lines to the VDD supply
through individual pullup resistors. Calculate the
required value of the pullup resistors using:
where tRis the rise time in the
Electrical Characteristics
table, and CBUS is the total capacitance on the bus.
The MAX8798 uses a nonstandard I2C interface proto-
col with mostly standard voltage and timing parame-
ters, as defined in the following subsections.
Bus Free
Both data and clock lines remain HIGH. Data transfers
can be initiated only when the bus is not busy (Figure 7).
START Condition (S)
Starting from an idle bus state (both SDA and SCL are
high), a HIGH to LOW transition of the SDA line while
the clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condition
from a master device on the bus.
STOP Condition (P)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition from
the master device.
Data Valid
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. The
data on the line must be changed during the LOW peri-
od of the clock signal. The master generates one clock
pulse per bit of data during write operations and the
slave device outputs 1 data bit per clock pulse during
read operations. Each data transfer is initiated with a
START condition and terminated with a STOP condition.
Two bytes are transferred between the START and
STOP conditions.
Slave Address
After generating a START condition, the bus master
transmits the slave address consisting of the 7-bit device
code (0b1001110 or 9Eh) for the MAX8798 (Figure 8).
For a read operation the 8th bit is 1 and for write opera-
tions it is 0. The MAX8798 monitors the bus for its corre-
sponding slave address continuously. It generates an
acknowledge bit if it recognizes its slave address and it
is not busy programming the EEPROM.
Rt
PULLUP R
≤CBUS
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
26 ______________________________________________________________________________________
Data Byte
The data byte follows successful transmission of the
MAX8798’s slave address (Figure 8). For a read opera-
tion, the MAX8798 outputs the 7 bits corresponding to
the current DAC setting followed by a 0 bit. For a write
operation, the bus master must provide the 7-bit data
corresponding to the desired DAC setting followed by a
1 bit. To program the IC’s EEPROM, the master must
make the last bit a zero. In this situation, the other 7 bits
of data are ignored. For programming, GON must
exceed its programming threshold. Otherwise, pro-
gramming does not occur and the MAX8798 does not
acknowledge the programming command.
DAC Values
Table 5 lists the DAC values and the corresponding
ISET, VSET, and VOUT values.
Acknowledge/Polling
The MAX8798, when addressed, generates an acknowl-
edge pulse after the reception of each byte (Figure 9).
The master device must generate an extra clock pulse
that is associated with this acknowledge bit. The device
that acknowledges has to pull down the SDA line during
the acknowledge clock pulse so that the SDA line is sta-
ble LOW during the HIGH period of the acknowledge-
related clock pulse. Of course, setup and hold times
must be taken into account. The master signals an end
of data to the slave by not generating an acknowledge
bit on the last byte that has been clocked out of the
slave. In this case, the slave leaves the data line HIGH to
enable the master to generate the STOP condition.
The MAX8798 does not generate an acknowledge
while an internal programming cycle is in progress.
Once the internally timed write cycle has started and
the EEPROM inputs are disabled, acknowledge polling
can be initiated. This involves sending a START condi-
tion followed by the device address byte. Only if the
internal write cycle has completed does the MAX8798
respond with an acknowledge pulse, allowing the read
or write sequence to continue.
The MAX8798 does not acknowledge a command to
program the EEPROM if VGON is not high enough to
properly program the device. Also, a program com-
mand must be preceded by a write command. The IC
does not acknowledge a program command or pro-
gram the EEPROM unless the DAC data has been
modified since the most recent program command.
Table 5. DAC Settings
7-BIT
DATA BYTE
ISET VSET (V) VOUT (V)
0000000 ISET(MAX) VSET(MAX) VMIN
0000001 ISET(MAX) -
1-LSB
VSET(MAX) -
1-LSB
VMIN +
1-LSB
.
.
.
.
.
.
.
.
.
.
.
.
1111110 ISET(MIN) +
1-LSB
VSET(MIN) +
1-LSB
VMAX -
1-LSB
1111111 ISET(MIN) VSET(MIN) VMAX
SCL FROM
MASTER
DATA OUTPUT
BY MAX8798
DATA OUTPUT
BY MASTER
CLK1
START
CONDITION
S
1
CLK2
2
CLK8
8
CLK9
9
ACKNOWLEDGE
CLOCK PULSE
ACKNOWLEDGE
NOT ACKNOWLEDGE
D7 D6 D0
Figure 9. I2C Bus Acknowledge
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
______________________________________________________________________________________ 27
PCB Layout and Grounding
Careful PCB layout is important for proper operation.
Use the following guidelines for good PCB layout:
• Minimize the area of high-current loops by placing
the inductor, output diode, and output capacitors
near the input capacitors and near LX and PGND.
The high-current input loop goes from the positive
terminal of the input capacitor to the inductor, to the
IC’s LX pin, out of PGND, and to the input capaci-
tor’s negative terminal. The high-current output loop
is from the positive terminal of the input capacitor to
the inductor, to the output diode (D1), to the posi-
tive terminal of the output capacitors, reconnecting
between the output capacitor and input capacitor
ground terminals. Connect these loop components
with short, wide connections. Avoid using vias in
the high-current paths. If vias are unavoidable, use
many vias in parallel to reduce resistance and
inductance.
• Create a power ground island (PGND) consisting of
the input and output capacitor grounds, PGND pin,
and any charge-pump components. Connect all
these together with short, wide traces or a small
ground plane. Maximizing the width of the power
ground traces improves efficiency and reduces out-
put-voltage ripple and noise spikes. Create an ana-
log ground plane (AGND) consisting of the AGND
pin, all the feedback-divider ground connections, the
operational-amplifier-divider ground connections,
the COMP capacitor ground connection, the
BOOST and VL bypass capacitor ground connec-
tions, and the device’s exposed backside paddle.
Connect the AGND and PGND islands by connect-
ing the PGND pin directly to the exposed backside
paddle. Make no other connections between these
separate ground planes.
• Place the feedback-voltage-divider resistors as
close as possible to the feedback pin. The divider’s
center trace should be kept short. Placing the resis-
tors far away causes the FB trace to become an
antenna that can pick up switching noise. Care
should be taken to avoid running the feedback
trace near LX or the switching nodes in the charge
pumps.
• Place the IN pin and VL pin bypass capacitors as
close as possible to the device. The ground con-
nections of the IN and VL bypass capacitors should
be connected directly to the AGND pin with a wide
trace.
• Minimize the length and maximize the width of the
traces between the output capacitors and the load
for best transient responses.
• Minimize the size of the LX node while keeping it
wide and short. Keep the LX node away from the
feedback node and analog ground. Use DC traces
as shield if necessary.
Refer to the MAX8798 evaluation kit for an example of
proper board layout.
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
28 ______________________________________________________________________________________
SET
WPP
SCL
SCLS
DISH
GND
WPN
VDD
SDA
PGND
PGND
FB
AGND
GOFF
GON
LX 28
29
30
31
32
33
34
35
36
123456789
27 26 25 24 23 22 21 20 19
18
17
16
15
14
13
12
11
10
STVP
STV
OECON
CPV
CKVB
CKVBCS
CKVCS
CKV
VCOM
NEG
POS
OUT
BOOST
BGND
VL
IN
THIN QFN
MAX8798
TOP VIEW
COMP
OE
LX
SHDN
Pin Configuration Chip Information
TRANSISTOR COUNT: 15,227
PROCESS: BiCMOS
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
______________________________________________________________________________________ 29
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
30 ______________________________________________________________________________________
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX8798
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
31
© 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 9/07 Initial release —
Changes to the Electrical Characteristics table 1–5, 7, 8
1 6/08
Changes throughout the data sheet. 1–8, 13, 14, 17,
19–22, 24, 26, 27