THIS SPEC IS OBSOLETE Spec No: 38-03027 Spec Title: PALCE22V10 FLASH-ERASABLE REPROGRAMMABLE CMOS PAL(R) DEVICE Sunset Owner: Adrian Mendes (AMV) Replaced by: None PALCE22V10 is a replacement device for PALC22V10, PALC22V10B, and PALC22V10D. USE ULTRA37000TM FOR ALL NEW DESIGNS PALCE22V10 Flash-erasable Reprogrammable CMOS PAL(R) Device Features * DIP, LCC, and PLCC available -- 5 ns commercial version 4 ns tCO 3 ns tS 5 ns tPD 181-MHz state machine * Low power -- 90 mA max. commercial (10 ns) -- 130 mA max. commercial (5 ns) * CMOS Flash EPROM technology for electrical erasability and reprogrammability -- 10 ns military and industrial versions 7 ns tCO 6 ns tS 10 ns tPD 110-MHz state machine * Variable product terms -- 2 x(8 through 16) product terms * User-programmable macrocell -- 15-ns commercial, industrial, and military versions -- Output polarity control -- Individually selectable for registered or combinatorial operation -- 25-ns commercial, industrial, and military versions * High reliability -- Proven Flash EPROM technology * Up to 22 input terms and 10 outputs -- 100% programming and functional testing Logic Block Diagram (PDIP/CDIP) VSS 12 I I I I I I I I I I CP/I 11 10 9 8 7 6 5 4 3 2 1 PROGRAMMABLE AND ARRAY (132 X 44) 8 10 12 14 16 16 14 12 10 Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell 8 Reset Macrocell Macrocell Preset 13 14 15 16 17 18 19 20 21 22 23 24 I I/O9 I/O8 I/O 7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC PLCC Top View I I CP/I NC VCC I/O0 I/O1 I I CP/I NC VCC I/O0 I/O1 LCC Top View 4 3 2 1 2827 26 25 24 23 22 21 20 19 5 6 7 8 9 10 11 I/O9 I/O8 3901 North First Street 5 6 7 8 9 10 11 121314 1516 1718 * I * I I I NC I I I I I Cypress Semiconductor Corporation Document #: 38-03027 Rev. *C I I I VSS NC 12131415161718 I/O 2 I/O 3 I/O 4 N/C I/O 5 I/O 6 I/O 7 25 24 23 22 21 20 19 I/O 2 I/O 3 I/O 4 N/C I/O 5 I/O 6 I/O 7 I/O9 I/O8 4 3 2 1 282726 I I I NC I I I VSS NC Pin Configuration San Jose, CA 95134 * 408-943-2600 Revised April 9, 2004 USE ULTRA37000TM FOR ALL NEW DESIGNS PALCE22V10 Selection Guide Generic Part Number tPD ns Com'l tS ns Mil/Ind Com'l tCO ns Mil/Ind Com'l ICC mA Mil/Ind Com'l PALCE22V10-5 5 3 4 130 PALCE22V10-7 7.5 5 5 130 Mil/Ind PALCE22V10-10 10 10 6 6 7 7 90 150 PALCE22V10-15 15 15 10 10 8 8 90 120 PALCE22V10-25 25 25 15 15 15 15 90 120 Functional Description The Cypress PALCE22V10 is a CMOS Flash-erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-products (AND-OR) logic structure and the programmable macrocell. The PALCE22V10 is executed in a 24-pin 300-mil molded DIP, a 300-mil cerDIP, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and provides up to 22 inputs and 10 outputs. The PALCE22V10 can be electrically erased and reprogrammed. The programmable macrocell provides the capability of defining the architecture of each output individually. Each of the ten potential outputs may be specified as "registered" or "combinatorial." Polarity of each output may also be individually selected, allowing complete flexibility of output configuration. Further configurability is provided through "array" configurable "output enable" for each potential output. This feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or alternately used as a combination I/O controlled by the programmable array. PALCE22V10 features a variable product term architecture. There are 5 pairs of product term sums beginning at 8 product terms per output and incrementing by 2 to 16 product terms per output. By providing this variable structure, the PALCE22V10 is optimized to the configurations found in a majority of applications without creating devices that burden the product term structures with unusable product terms and lower performance. Additional features of the Cypress PALCE22V10 include a synchronous preset and an asynchronous reset product term. These product terms are common to all macrocells, eliminating the need to dedicate standard product terms for initialization functions. The device automatically resets upon power-up. The PALCE22V10, featuring programmable macrocells and variable product terms, provides a device with the flexibility to Document #: 38-03027 Rev. *C implement logic functions in the 500- to 800-gate-array complexity. Since each of the ten output pins may be individually configured as inputs on a temporary or permanent basis, functions requiring up to 21 inputs and only a single output and down to twelve inputs and ten outputs are possible. The ten potential outputs are enabled using product terms. Any output pin may be permanently selected as an output or arbitrarily enabled as an output and an input through the selective use of individual product terms associated with each output. Each of these outputs is achieved through an individual programmable macrocell. These macrocells are programmable to provide a combinatorial or registered inverting or non-inverting output. In a registered mode of operation, the output of the register is fed back into the array, providing current status information to the array. This information is available for establishing the next result in applications such as control state machines. In a combinatorial configuration, the combinatorial output or, if the output is disabled, the signal present on the I/O pin is made available to the array. The flexibility provided by both programmable product term control of the outputs and variable product terms allows a significant gain in functional density through the use of programmable logic. Along with this increase in functional density, the Cypress PALCE22V10 provides lower-power operation through the use of CMOS technology, and increased testability with Flash reprogrammability. Configuration Table Registered/Combinatorial C1 C0 Configuration 0 0 Registered/Active LOW 0 1 Registered/Active HIGH 1 0 Combinatorial/Active LOW 1 1 Combinatorial/Active HIGH Page 2 of 13 USE ULTRA37000TM FOR ALL NEW DESIGNS PALCE22V10 Macrocell AR D CP Q OUTPUT SELECT MUX Q S1 S0 SP INPUT/ FEEDBACK MUX S1 C1 C0 Document #: 38-03027 Rev. *C MACROCELL Page 3 of 13 USE ULTRA37000TM FOR ALL NEW DESIGNS Maximum Ratings PALCE22V10 Output Current into Outputs (LOW)............................. 16 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied.............................................-55C to +125C Supply Voltage to Ground Potential (Pin 24 to Pin 12) ........................................... -0.5V to +7.0V DC Programming Voltage............................................. 12.5V Latch-up Current..................................................... > 200 mA Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................ > 2001V Operating Range Range Ambient Temperature VCC Commercial 0C to +75C 5V 5% DC Voltage Applied to Outputs in High-Z State ............................................... -0.5V to +7.0V Industrial -40C to +85C 5V 10% DC Input Voltage............................................ -0.5V to +7.0V Military[1] -55C to +125C 5V 10% Electrical Characteristics Over the Operating Range[2] Parameter Description Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., VIN = VIH or VIL IOH = -3.2 mA IOH = -2 mA Mil/Ind VOL Output LOW Voltage VCC = Min., VIN = VIH or VIL IOL = 16 mA Com'l IOL = 12 mA Mil/Ind VIH Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs[3] 2.0 VIL[4] Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs[3] -0.5 0.8 V IIX Input Leakage Current VSS < VIN < VCC, VCC = Max. -10 10 A VCC = Max., VSS < VOUT < VCC -40 40 A IOZ Output Leakage Current ISC Output Short Circuit Current VCC = Max., VOUT = 0.5V[5,6] ICC1 Standby Power Supply Current VCC = Max., VIN = GND, Outputs Open in Unprogrammed Device Com'l 2.4 0.5 -30 10, 15, 25 ns Com'l 5, 7.5 ns 15, 25 ns Mil/Ind 10 ns ICC2 [6] Operating Power Supply Current VCC = Max., VIL = 0V, VIH = 3V, 10, 15, 25 ns Output Open, Device Programmed 5, 7.5 ns as a 10-bit Counter, 15, 25 ns f = 25 MHz 10 ns V V V -130 mA 90 mA 130 mA 120 mA 120 mA Com'l 110 mA Com'l 140 mA Mil/Ind 130 mA Mil/Ind 130 mA Capacitance[6] Parameter Description CIN Input Capacitance COUT Output Capacitance Max. Unit VIN = 2.0V @ f = 1 MHz Test Conditions Min. 10 pF VOUT = 2.0V @ f = 1 MHz 10 pF Endurance Characteristics[6] Parameter N Description Minimum Reprogramming Cycles Test Conditions Min. Normal Programming Conditions 100 Max. Unit Cycles Notes: 1. TA is the "instant on" case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 4. VIL (Min.) is equal to -3.0V for pulse durations less than 20 ns. 5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 6. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-03027 Rev. *C Page 4 of 13 USE ULTRA37000TM FOR ALL NEW DESIGNS PALCE22V10 AC Test Loads and Waveforms R1238 (319 MIL) 5V R1238 (319 MIL) 5V OUTPUT R2170 (236 MIL) CL OUTPUT R2170 (236 MIL) 5 pF INCLUDING JIG AND SCOPE OUTPUT 750 (1.2K MIL) CL INCLUDING JIG AND SCOPE (a) (b) (c) ALL INPUT PULSES 3.0V 90% 10% GND < 2 ns 90% 10% < 2 ns (d) Equivalent to:THEVENIN Equivalent (Commercial) OUTPUT 99 Equivalent to: THEVENIN Equivalent (Military) 2.08V = VTHC Load Speed CL Package 5, 7.5, 10, 15, 25 ns 50 pF PDIP, CDIP, PLCC, LCC Parameter VX t ER (- ) 1.5V t ER (+) 2.6V t EA (+) 0V t EA (- ) V thc 136 OUTPUT 2.13V = VTHM Output Waveform Measurement Level V OH V OL VX VX VX 0.5V 0.5V VX 1.5V V OH V OL 0.5V (e) Test Waveforms Commercial Switching Characteristics PALCE22V10 22V10-5 Parameter Description [2, 7] 22V10-7 22V10-10 22V10-15 22V10-25 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit 3 5 3 7.5 3 10 3 15 3 25 ns tPD Input to Output Propagation Delay[8] tEA Input to Output Enable Delay[9] 6 8 10 15 25 ns tER Input to Output Disable Delay[10] 6 8 10 15 25 ns 15 ns tCO Clock to Output Delay[8] 2 4 2 5 2 7 2 8 2 Notes: 7. Part (a) of AC Test Loads and Waveforms is used for all parameters except tER and tEA(+). Part (b) of AC Test Loads and Waveforms is used for tER. Part (c) of AC Test Loads and Waveforms is used for tEA(+). 8. Min. times are tested initially and after any design or process changes that may affect these parameters. 9. The test load of (a) of AC Test Loads and Waveforms is used for measuring tEA(-). The test load of (c) of AC Test Loads and Waveforms is used for measuring tEA(+) only. Please see (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels. 10. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to the point at which a previous HIGH level has fallen to 0.5V below VOH min. or a previous LOW level has risen to 0.5V above VOL max. Please see (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels. Document #: 38-03027 Rev. *C Page 5 of 13 USE ULTRA37000TM FOR ALL NEW DESIGNS PALCE22V10 Commercial Switching Characteristics PALCE22V10 (continued)[2, 7] 22V10-5 Parameter Description Min. 22V10-7 Max. Min. Max. 22V10-10 Min. 22V10-15 Max. Min. Max. 22V10-25 Min. Max. Unit tS1 Input or Feedback Set-Up Time 3 5 6 10 15 ns tS2 Synchronous Preset Set-Up Time 4 6 7 10 15 ns tH Input Hold Time 0 0 0 0 0 ns tP External Clock Period (tCO + tS) 7 10 12 20 30 ns tWH Clock Width HIGH[6] 2.5 3 3 6 13 ns tWL Clock Width LOW[6] 2.5 3 3 6 13 ns fMAX1 External Maximum Frequency (1/(tCO + tS))[11] 143 100 76.9 55.5 33.3 MHz fMAX2 Data Path Maximum Frequency (1/(tWH + tWL))[6, 12] 200 166 142 83.3 35.7 MHz fMAX3 Internal Feedback Maximum Frequency (1/(tCF + tS))[6,13] 181 133 111 68.9 38.5 MHz tCF Register Clock to Feedback Input[6,14] tAW Asynchronous Reset Width 8 8 10 15 25 ns tAR Asynchronous Reset Recovery Time 4 5 6 10 25 ns tAP Asynchronous Reset to Registered Output Delay tSPR Synchronous Preset Recovery Time 4 6 8 tPR Power-up Reset Time[6,15] 1 1 1 2.5 2.5 7.5 3 12 13 Military and Industrial Switching Characteristics PALCE22V10 22V10-10 Parameter Description 4.5 13 20 25 ns ns 10 15 ns 1 1 s [2, 7] 22V10-15 22V10-25 Min. Max. Min. Max. Min. Max. Unit 3 10 3 15 3 25 ns tPD Input to Output Propagation Delay[8] tEA Input to Output Enable Delay[9] 10 15 25 ns tER Input to Output Disable Delay[10] 10 15 25 ns 15 ns [8] tCO Clock to Output Delay 2 tS1 Input or Feedback Set-up Time 6 7 10 2 8 18 2 ns tS2 Synchronous Preset Set-up Time 7 10 18 ns tH Input Hold Time 0 0 0 ns tP External Clock Period (tCO + tS) 12 20 33 ns tWH Clock Width HIGH[6] 3 6 14 ns tWL [6] Clock Width LOW 3 6 14 ns fMAX1 External Maximum Frequency (1/(tCO + tS))[11] 76.9 50.0 30.3 MHz fMAX2 Data Path Maximum Frequency (1/(tWH + tWL))[6, 12 ] 142 83.3 35.7 MHz Notes: 11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate. 12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode. 13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate. 14. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note above) minus tS. 15. The registers in the PALCE22V10 have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure proper operation, the rise in VCC must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied. Document #: 38-03027 Rev. *C Page 6 of 13 USE ULTRA37000TM FOR ALL NEW DESIGNS PALCE22V10 Military and Industrial Switching Characteristics PALCE22V10 (continued)[2, 7] 22V10-10 Parameter Description Min. 22V10-15 Max. Min. 111 22V10-25 Max. Min. 68.9 Max. fMAX3 Internal Feedback Maximum Frequency (1/(tCF + tS))[6, 13] tCF Register Clock to Feedback Input[6, 14] tAW Asynchronous Reset Width 10 15 25 ns tAR Asynchronous Reset Recovery Time 6 12 25 ns tAP Asynchronous Reset to Registered Output Delay tSPR Synchronous Preset Recovery Time 8 20 25 ns tPR Power-up Reset Time[6, 15] 1 1 1 s 3 32.2 Unit 4.5 12 MHz 13 20 25 ns ns Switching Waveforms INPUTS I/O, REGISTERED FEEDBACK SYNCHRONOUS PRESET tS t WH tH t WL CP t SPR tP t AW ASYNCHRONOUS RESET t CO t AR t AP tER[10] tEA [9] tER[10] tEA [9] REGISTERED OUTPUTS t PD COMBINATORIAL OUTPUTS Power-Up Reset Waveform[15] POWER SUPPLY VOLTAGE 10% VCC 90% t PR REGISTERED ACTIVE LOW OUTPUTS tS CLOCK tPR MAX = 1 s Document #: 38-03027 Rev. *C t WL Page 7 of 13 USE ULTRA37000TM FOR ALL NEW DESIGNS PALCE22V10 Functional Logic Diagram for PALCE22V10 1 AR OE 0 0 4 S S S 7 8 12 16 20 24 28 32 36 40 Macro- cell 23 Macro- cell 22 Macro- cell 21 Macro- cell 20 Macro- cell 19 Macro- cell 18 Macro- cell 17 Macro- cell 16 Macro- cell 15 Macro- cell 14 OE 0 S S S 2 9 OE 0 S S S 3 11 OE 0 S S S 4 13 OE 0 S S S 5 15 OE 0 S S S 6 15 OE 0 S S S 7 13 OE 0 S S S 8 11 OE 0 S S S 9 9 OE 0 S S S 7 10 SP 11 Document #: 38-03027 Rev. *C 13 Page 8 of 13 USE ULTRA37000TM FOR ALL NEW DESIGNS PALCE22V10 Ordering Information ICC (mA) tPD (ns) tS (ns) tCO (ns) 130 5 3 4 130 7.5 5 5 90 10 6 7 150 10 6 7 90 15 10 8 120 15 10 8 90 25 15 15 120 25 15 15 Ordering Code Package Name Operating Range Package Type PALCE22V10-5PC P13 24-lead (300 MIL) Molded DIP PALCE22V10-5JC J64 28-lead Plastic Leaded Chip Carrier PALCE22V10-7JC J64 28-lead Plastic Leaded Chip Carrier PALCE22V10-7PC P13 24-lead (300-Mil) Molded DIP PALCE22V10-10JC J64 28-lead Plastic Leaded Chip Carrier PALCE22V10-10PC P13 24-lead (300-Mil) Molded DIP PALCE22V10-10JI J64 28-lead Plastic Leaded Chip Carrier PALCE22V10-10PI P13 24-lead (300-Mil) Molded DIP PALCE22V10-10LMB 5962-89841063X L64 28-Square Leadless Chip Carrier PALCE22V10-10KMB 5962-8984106KX K73 24-lead Rectangular Cerpack PALCE22V10-10DMB 5962-8984106LX D14 24-lead (300 MIL) CerDIP PALCE22V10-15JC J64 28-lead Plastic Leaded Chip Carrier PALCE22V10-15PC P13 24-lead (300-Mil) Molded DIP PALCE22V10-15KMB 5962-8984102KX K73 24-lead Rectangular Cerpack PALCE22V10-15KMB 5962-8984103KX K73 24-lead Rectangular Cerpack PALCE22V10-15KMB 5962-8984105KX K73 24-lead Rectangular Cerpack PALCE22V10-15DMB 5962-8984102LX D14 24-lead (300 MIL) CerDIP PALCE22V10-15DMB 5962-8984103LX D14 24-lead (300 MIL) CerDIP PALCE22V10-15LMB 5962-89841033X L64 28-Square Leadless Chip Carrier PALCE22V10-15LMB 5962-89841053X L64 28-Square Leadless Chip Carrier PALCE22V10-25JC J64 28-lead Plastic Leaded Chip Carrier PALCE22V10-25PC P13 24-lead (300-Mil) Molded DIP PALCE22V10-25LMB 5962-89841043X L64 28-square Leadless Chip Carrier MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups VOH 1, 2, 3 VOL 1, 2, 3 VIH 1, 2, 3 VIL 1, 2, 3 IIX 1, 2, 3 IOZ 1, 2, 3 Document #: 38-03027 Rev. *C Commercial Commercial Commercial Industrial Military Commercial Military Commercial Military DC Characteristics Parameter Subgroups ICC 1, 2, 3 Switching Characteristics Parameter Subgroups tPD 9, 10, 11 tCO 9, 10, 11 tS 9, 10, 11 tH 9, 10, 11 Page 9 of 13 USE ULTRA37000TM FOR ALL NEW DESIGNS PALCE22V10 Package Diagrams 24-lead (300-mil) CerDIP D14 MIL-STD-1835D-9 Config.A 51-80031-** 28-lead Plastic Leaded Chip Carrier J64 51-85001-*A Document #: 38-03027 Rev. *C Page 10 of 13 USE ULTRA37000TM FOR ALL NEW DESIGNS PALCE22V10 Package Diagrams (continued) 24-Lead Rectangular Cerpack K73 MIL-STD-1835 F-6 Config. A PIN 1 I.D. PIN 1 I.D. DIMENSIONS IN INCHES MIN. MAX. PIN 1 I.D OPTION PIN 1 I.D. (SEE OPTION) .005 .015 .045 MAX. .015 .019 .050 BSC .590 .620 .005 MIN. .360 .400 .260 .325 Document #: 38-03027 Rev. *C BASE AND SEATING PLANE .026 .040 .004 .009 .260 .325 .060 .090 51-80060-*A Page 11 of 13 USE ULTRA37000TM FOR ALL NEW DESIGNS PALCE22V10 Package Diagrams (continued) 28-Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 51-80051-** Ultra37000 is a trademark of Cypress Semiconductor Corporation. PAL is a registered trademark of Advanced Micro Devices. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-03027 Rev. *C Page 12 of 13 (c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. USE ULTRA37000TM FOR ALL NEW DESIGNS PALCE22V10 Document History Page Document Title: PALCE22V10 Flash-erasable Reprogrammable CMOS PAL(R) Device Document Number: 38-03027 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106372 07/11/01 SZV Change from Spec Number: 38-00447 to 38-03027 *A 114640 06/25/02 OOR Added a note on the title page referring all new designs to this device Added Military Part Numbers *B 213375 See ECN FSG Added note to title page: "Use Ultra37000 For All New Designs" *C 2675372 See ECN AMV Sunset Review: Obsolete product Document #: 38-03027 Rev. *C Page 13 of 13