THIS SPEC IS OBSOLETE
Spec No: 38-03027
Spec Title: PALCE22V10 FLASH-ERASABLE
REPROGRAMMABLE CMOS PAL(R)
DEVICE
Sunset Owner: Adrian Mendes (AMV)
Replaced by: None
Flash-erasable Reprogrammable
CMOS PAL® Device
PALCE22V10
PALCE22V10 is a replacement device for
PALC22V10, PALC22V10B, and PALC22V10D.
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Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-03027 Rev. *C Revised April 9, 2004
Features
•Low power
— 90 mA max. commercial (10 ns)
— 130 mA max. commercial (5 ns)
• CMOS Flash EPROM technology for electrical erasabil-
ity and reprogrammability
• Variable product terms
— 2 ×(8 through 16) product terms
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combina-
torial operation
• Up to 22 input terms and 10 outputs
• DIP, LCC, and PLCC available
— 5 ns commercial version
4 ns tCO
3 ns tS
5 ns tPD
181-MHz state machine
— 10 ns military and industrial versions
7 ns tCO
6 ns tS
10 ns tPD
110-MHz state machine
— 15-ns commercial, industrial, and military versions
— 25-ns commercial, industrial, and military versions
• High reliability
— Proven Flash EPROM technology
— 100% programming and functional testing
Logic Block Diagram (PDIP/CDIP)
Pin Configuration PLCC
Top View
Macrocell
810 12 14 16 16 14 12 10 8
1110 987 65 432112
13 14 15 16 17 18 19 20 21 22 23 24
Preset
PROGRAMMABLE
AND ARRAY
(132 X 44)
I IIII II IIICP/I
V
SS
II/O
9I/O8I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0V
CC
Reset
Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
2
3
4
5
6
7
I
9
I
CP/I
V
I/O
I/O
8
I/O
I/O
I
V
I
I
SS
0
1
CC
N/C
LCC
Top View
5
6
7
8
9
10
11
4 3 2 282726
12131415161718
25
24
23
22
21
20
19
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
2
3
4
5
6
7
I
9
I
CP/I
V
I/O
I/O
8
I/O
I/O
I
V
I
I
SS
0
1
CC
1
N/C
NC
NC
NC
NC
NC
NC
25
24
23
22
21
20
19
5
6
7
8
9
10
11 121314 1516 1718
432 2827261
PALCE22V10
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Document #: 38-03027 Rev. *C Page 2 of 13
Functional Description
The Cypress PALCE22V10 is a CMOS Flash-erasable
second-generation programmable array logic device. It is
implemented with the familiar sum-of-products (AND-OR)
logic structure and the programmable macrocell.
The PALCE22V10 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerDIP, a 28-lead square ceramic leadless chip
carrier, a 28-lead square plastic leaded chip carrier, and
provides up to 22 inputs and 10 outputs. The PALCE22V10
can be electrically erased and reprogrammed. The program-
mable macrocell provides the capability of defining the archi-
tecture of each output individually. Each of the ten potential
outputs may be specified as “registered” or “combinatorial.”
Polarity of each output may also be individually selected,
allowing complete flexibility of output configuration. Further
configurability is provided through “array” configurable “output
enable” for each potential output. This feature allows the 10
outputs to be reconfigured as inputs on an individual basis, or
alternately used as a combination I/O controlled by the
programmable array.
PALCE22V10 features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product
terms per output and incrementing by 2 to 16 product terms
per output. By providing this variable structure, the
PALCE22V10 is optimized to the configurations found in a
majority of applications without creating devices that burden
the product term structures with unusable product terms and
lower performance.
Additional features of the Cypress PALCE22V10 include a
synchronous preset and an asynchronous reset product term.
These product terms are common to all macrocells, elimi-
nating the need to dedicate standard product terms for initial-
ization functions. The device automatically resets upon
power-up.
The PALCE22V10, featuring programmable macrocells and
variable product terms, provides a device with the flexibility to
implement logic functions in the 500- to 800-gate-array
complexity. Since each of the ten output pins may be individ-
ually configured as inputs on a temporary or permanent basis,
functions requiring up to 21 inputs and only a single output and
down to twelve inputs and ten outputs are possible. The ten
potential outputs are enabled using product terms. Any output
pin may be permanently selected as an output or arbitrarily
enabled as an output and an input through the selective use
of individual product terms associated with each output. Each
of these outputs is achieved through an individual program-
mable macrocell. These macrocells are programmable to
provide a combinatorial or registered inverting or non-inverting
output. In a registered mode of operation, the output of the
register is fed back into the array, providing current status
information to the array. This information is available for estab-
lishing the next result in applications such as control state
machines. In a combinatorial configuration, the combinatorial
output or, if the output is disabled, the signal present on the I/O
pin is made available to the array. The flexibility provided by
both programmable product term control of the outputs and
variable product terms allows a significant gain in functional
density through the use of programmable logic.
Along with this increase in functional density, the Cypress
PALCE22V10 provides lower-power operation through the use
of CMOS technology, and increased testability with Flash
reprogrammability.
Selection Guide
Generic Part Number tPD ns tS ns tCO ns ICC mA
Com’l Mil/Ind Com’l Mil/Ind Com’l Mil/Ind Com’l Mil/Ind
PALCE22V10-5 5 3 4 130
PALCE22V10-7 7.5 5 5 130
PALCE22V10-10 1010667790150
PALCE22V10-15 15 15 10 10 8 8 90 120
PALCE22V10-25 25 25 15 15 15 15 90 120
Configuration Table
Registered/Combinatorial
C1C0Configuration
0 0 Registered/Active LOW
0 1 Registered/Active HIGH
1 0 Combinatorial/Active LOW
1 1 Combinatorial/Active HIGH
PALCE22V10
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Document #: 38-03027 Rev. *C Page 3 of 13
Macrocell
OUTPUT
SELECT
MUX
AR
SS
10
Q
QD
CP
SP
INPUT/
FEEDBACK
MUX
1
S
MACROCELL
1
C
0
C
PALCE22V10
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Document #: 38-03027 Rev. *C Page 4 of 13
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ........................................... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
Output Current into Outputs (LOW)............................. 16 mA
DC Programming Voltage............................................. 12.5V
Latch-up Current.....................................................> 200 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................> 2001V
Operating Range
Range
Ambient
Temperature VCC
Commercial 0°C to +75°C 5V ±5%
Industrial –40°C to +85°C5V ±10%
Military[1] –55°C to +125°C 5V ±10%
Electrical Characteristics Over the Operating Range[2]
Parameter Description Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min.,
VIN = VIH or VIL
IOH = –3.2 mA Com’l 2.4 V
IOH = –2 mA Mil/Ind
VOL Output LOW Voltage VCC = Min.,
VIN = VIH or VIL
IOL = 16 mA Com’l 0.5 V
IOL = 12 mA Mil/Ind
VIH Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs[3] 2.0 V
VIL[4] Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs[3] –0.5 0.8 V
IIX Input Leakage Current VSS < VIN < VCC, VCC = Max. –10 10 µA
IOZ Output Leakage Current VCC = Max., VSS < VOUT < VCC –40 40 µA
ISC Output Short Circuit Current VCC = Max., VOUT = 0.5V[5,6] –30 –130 mA
ICC1 Standby Power Supply
Current
VCC = Max.,
VIN = GND,
Outputs Open in Unprogrammed
Device
10, 15, 25 ns Com’l 90 mA
5, 7.5 ns 130 mA
15, 25 ns Mil/Ind 120 mA
10 ns 120 mA
ICC2[6] Operating Power Supply
Current
VCC = Max., VIL = 0V, VIH = 3V,
Output Open, Device Programmed
as a 10-bit Counter,
f = 25 MHz
10, 15, 25 ns Com’l 110 mA
5, 7.5 ns Com’l 140 mA
15, 25 ns Mil/Ind 130 mA
10 ns Mil/Ind 130 mA
Capacitance[6]
Parameter Description Test Conditions Min. Max. Unit
CIN Input Capacitance VIN = 2.0V @ f = 1 MHz 10 pF
COUT Output Capacitance VOUT = 2.0V @ f = 1 MHz 10 pF
Endurance Characteristics[6]
Parameter Description Test Conditions Min. Max. Unit
NMinimum Reprogramming Cycles Normal Programming Conditions 100 Cycles
Notes:
1. TA is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. VIL (Min.) is equal to –3.0V for pulse durations less than 20 ns.
5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems
caused by tester ground degradation.
6. Tested initially and after any design or process changes that may affect these parameters.
PALCE22V10
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Document #: 38-03027 Rev. *C Page 5 of 13
AC Test Loads and Waveforms
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
CL
(a) (b)
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5pF
(c)
OUTPUT
CL
R1238Ω
(319Ω MIL) R1238Ω
(319Ω MIL)
R2170Ω
(236Ω MIL) R2170Ω
(236Ω MIL)
750Ω
(1.2KΩ
MIL)
OUTPUT 2.08V = VTHC OUTPUT 2.13V = VTHM
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
<2ns <2ns
(d)
99Ω136Ω
Equivalent to:THÉ VENIN Equivalent (Commercial) Equivalent to: THÉ VENIN Equivalent (Military)
Load Speed CLPackage
5, 7.5, 10, 15, 25 ns 50 pF PDIP, CDIP,
PLCC, LCC
Commercial Switching Characteristics PALCE22V10 [2, 7]
Parameter Description
22V10-5 22V10-7 22V10-10 22V10-15 22V10-25
UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tPD Input to Output
Propagation Delay[8] 3 5 3 7.5 310 315 325 ns
tEA Input to Output Enable Delay[9] 6 8 10 15 25 ns
tER Input to Output Disable Delay[10] 6 8 10 15 25 ns
tCO Clock to Output Delay[8] 24252728215 ns
Notes:
7. Part (a) of AC Test Loads and Waveforms is used for all parameters except tER and tEA(+). Part (b) of AC Test Loads and Waveforms is used for tER. Part (c) of AC Test
Loads and Waveforms is used for tEA(+).
8. Min. times are tested initially and after any design or process changes that may affect these parameters.
9. The test load of (a) of AC Test Loads and Waveforms is used for measuring tEA(-). The test load of (c) of AC Test Loads and Waveforms is used for measuring tEA(+) only.
Please see (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
10. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to
the point at which a previous HIGH level has fallen to 0.5V below VOH min. or a previous LOW level has risen to 0.5V above VOL max. Please see (e) of AC Test Loads
and Waveforms for enable and disable test waveforms and measurement reference levels.
Parameter VXOutput Waveform Measurement Level
tER (- ) 1.5V VOH 0.5V VX
0.5V
tER (+) 2.6V VOL VX
tEA (+) 0V
0.5V
tEA (- ) Vthc VXVOL
1.5V
VXVOH
(e) Test Waveforms
PALCE22V10
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Document #: 38-03027 Rev. *C Page 6 of 13
tS1 Input or Feedback Set-Up Time 3 5 6 10 15 ns
tS2 Synchronous Preset Set-Up
Time
4 6 7 10 15 ns
tHInput Hold Time 0 0 0 0 0 ns
tPExternal Clock Period (tCO + tS) 7 10 12 20 30 ns
tWH Clock Width HIGH[6] 2.5 3 3 6 13 ns
tWL Clock Width LOW[6] 2.5 3 3 6 13 ns
fMAX1 External Maximum
Frequency (1/(tCO + tS))[11] 143 100 76.9 55.5 33.3 MHz
fMAX2 Data Path Maximum Frequency
(1/(tWH + tWL))[6, 12] 200 166 142 83.3 35.7 MHz
fMAX3 Internal Feedback Maximum
Frequency (1/(tCF + tS))[6,13] 181 133 111 68.9 38.5 MHz
tCF Register Clock to
Feedback Input[6,14] 2.5 2.5 34.5 13 ns
tAW Asynchronous Reset Width 8 8 10 15 25 ns
tAR Asynchronous Reset
Recovery Time 4 5 6 10 25 ns
tAP Asynchronous Reset to
Registered Output Delay 7.5 12 13 20 25 ns
tSPR Synchronous Preset
Recovery Time 4 6 8 10 15 ns
tPR Power-up Reset Time[6,15] 1 1 1 1 1 µs
Military and Industrial Switching Characteristics PALCE22V10 [2, 7]
Parameter Description
22V10-10 22V10-15 22V10-25
UnitMin. Max. Min. Max. Min. Max.
tPD Input to Output
Propagation Delay[8] 310 315 325 ns
tEA Input to Output Enable Delay[9] 10 15 25 ns
tER Input to Output Disable Delay[10] 10 15 25 ns
tCO Clock to Output Delay[8] 2 7 2 8 2 15 ns
tS1 Input or Feedback Set-up Time 610 18 ns
tS2 Synchronous Preset Set-up Time 710 18 ns
tHInput Hold Time 0 0 0 ns
tPExternal Clock Period (tCO + tS)12 20 33 ns
tWH Clock Width HIGH[6] 3 6 14 ns
tWL Clock Width LOW[6] 3 6 14 ns
fMAX1 External Maximum Frequency
(1/(tCO + tS))[11] 76.9 50.0 30.3 MHz
fMAX2 Data Path Maximum Frequency
(1/(tWH + tWL))[6, 12 ] 142 83.3 35.7 MHz
Notes:
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note above) minus tS.
15. The registers in the PALCE22V10 have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a
logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure proper
operation, the rise in VCC must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied.
Commercial Switching Characteristics PALCE22V10 (continued)[2, 7]
Parameter Description
22V10-5 22V10-7 22V10-10 22V10-15 22V10-25
UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
PALCE22V10
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Document #: 38-03027 Rev. *C Page 7 of 13
fMAX3 Internal Feedback Maximum
Frequency (1/(tCF + tS))[6, 13] 111 68.9 32.2 MHz
tCF Register Clock to
Feedback Input[6, 14] 34.5 13 ns
tAW Asynchronous Reset Width 10 15 25 ns
tAR Asynchronous Reset
Recovery Time
612 25 ns
tAP Asynchronous Reset to
Registered Output Delay
12 20 25 ns
tSPR Synchronous Preset
Recovery Time
820 25 ns
tPR Power-up Reset Time[6, 15] 1 1 1 µs
Switching Waveforms
Power-Up Reset Waveform[15]
Military and Industrial Switching Characteristics PALCE22V10 (continued)[2, 7]
Parameter Description
22V10-10 22V10-15 22V10-25
UnitMin. Max. Min. Max. Min. Max.
tStHtWL
tWH
tP
tSPR
tAR
tAW
tAP
tCO
tPD
tER tEA
tER tEA
INPUTS I/O,
REGISTERED
FEEDBACK
SYNCHRONOUS
PRESET
CP
ASYNCHRONOUS
RESET
REGISTERED
OUTPUTS
COMBINATORIAL
OUTPUTS
[10]
[10]
[9]
[9]
tPR
POWER
CLOCK
tS
tWL
10%
REGISTERED
ACTIVE LOW
OUTPUTS
SUPPLY VOLTAGE
tPR MAX = 1 µs
90% VCC
PALCE22V10
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Document #: 38-03027 Rev. *C Page 8 of 13
Functional Logic Diagram for PALCE22V10
0
1
Macro–
cell
Macro–
cell
Macro–
cell
Macro–
cell
Macro–
cell
Macro–
cell
Macro–
cell
Macro–
cell
Macro–
cell
Macro–
cell
2
3
4
5
6
7
8
9
10
11
23
22
21
20
19
18
17
16
15
14
13
16 20 24 28 32 36 40
AR
OE
0
7
OE
0
9
OE
0
11
OE
0
13
OE
0
15
OE
0
15
OE
0
13
OE
0
11
OE
0
9
OE
0
7
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
SP
128
4
PALCE22V10
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Document #: 38-03027 Rev. *C Page 9 of 13
MILITARY SPECIFICATIONS Group A Subgroup
Testing
Ordering Information
ICC
(mA)
tPD
(ns)
tS
(ns)
tCO
(ns) Ordering Code
Package
Name Package Type
Operating
Range
130 5 3 4 PALCE22V10-5PC P13 24-lead (300 MIL) Molded DIP Commercial
PALCE22V10-5JC J64 28-lead Plastic Leaded Chip Carrier
130 7.5 5 5 PALCE22V10-7JC J64 28-lead Plastic Leaded Chip Carrier Commercial
PALCE22V10-7PC P13 24-lead (300-Mil) Molded DIP
90 10 6 7 PALCE22V10-10JC J64 28-lead Plastic Leaded Chip Carrier Commercial
PALCE22V10-10PC P13 24-lead (300-Mil) Molded DIP
150 10 6 7 PALCE22V10-10JI J64 28-lead Plastic Leaded Chip Carrier Industrial
PALCE22V10-10PI P13 24-lead (300-Mil) Molded DIP
PALCE22V10-10LMB
5962-89841063X
L64 28-Square Leadless Chip Carrier Military
PALCE22V10-10KMB
5962-8984106KX
K73 24-lead Rectangular Cerpack
PALCE22V10-10DMB
5962-8984106LX
D14 24-lead (300 MIL) CerDIP
90 15 10 8PALCE22V10-15JC J64 28-lead Plastic Leaded Chip Carrier Commercial
PALCE22V10-15PC P13 24-lead (300-Mil) Molded DIP
120 15 10 8PALCE22V10-15KMB
5962-8984102KX
K73 24-lead Rectangular Cerpack Military
PALCE22V10-15KMB
5962-8984103KX
K73 24-lead Rectangular Cerpack
PALCE22V10-15KMB
5962-8984105KX
K73 24-lead Rectangular Cerpack
PALCE22V10-15DMB
5962-8984102LX
D14 24-lead (300 MIL) CerDIP
PALCE22V10-15DMB
5962-8984103LX
D14 24-lead (300 MIL) CerDIP
PALCE22V10-15LMB
5962-89841033X
L64 28-Square Leadless Chip Carrier
PALCE22V10-15LMB
5962-89841053X
L64 28-Square Leadless Chip Carrier
90 25 15 15 PALCE22V10-25JC J64 28-lead Plastic Leaded Chip Carrier Commercial
PALCE22V10-25PC P13 24-lead (300-Mil) Molded DIP
120 25 15 15 PALCE22V10-25LMB
5962-89841043X L64 28-square Leadless Chip Carrier Military
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
Switching Characteristics
Parameter Subgroups
tPD 9, 10, 11
tCO 9, 10, 11
tS9, 10, 11
tH9, 10, 11
DC Characteristics
Parameter Subgroups
PALCE22V10
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Document #: 38-03027 Rev. *C Page 10 of 13
Package Diagrams
24-lead (300-mil) CerDIP D14
MIL-STD-1835D-9 Config.A
51-80031-**
28-lead Plastic Leaded Chip Carrier J64
51-85001-*A
PALCE22V10
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Document #: 38-03027 Rev. *C Page 11 of 13
Package Diagrams (continued)
.026
.040
.060
.090
.260
.325 .325
.260
.400
.360
.009
.004
BASE AND
SEATING
PLANE
.590
.045 MAX.
.005 MIN.
.050 BSC
.015
.019
PIN 1 I.D.
.005
.015
.620
DIMENSIONS IN INCHES
MIN.
MAX.
PIN 1 I.D. PIN 1 I.D.
PIN 1 I.D OPTION
(SEE OPTION)
24-Lead Rectangular Cerpack K73
MIL-STD-1835 F-6 Config. A
51-80060-*A
PALCE22V10
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Document #: 38-03027 Rev. *C Page 12 of 13
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Ultra37000 is a trademark of Cypress Semiconductor Corporation. PAL is a registered trademark of Advanced Micro Devices.
All product and company names mentioned in this document are the trademarks of their respective holders.
Package Diagrams (continued)
28-Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
51-80051-**
PALCE22V10
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Document #: 38-03027 Rev. *C Page 13 of 13
Document History Page
Document Title: PALCE22V10 Flash-erasable Reprogrammable CMOS PAL® Device
Document Number: 38-03027
REV. ECN NO. Issue Date
Orig. of
Change Description of Change
** 106372 07/11/01 SZV Change from Spec Number: 38-00447 to 38-03027
*A 114640 06/25/02 OOR Added a note on the title page referring all new designs to this device
Added Military Part Numbers
*B 213375 See ECN FSG Added note to title page: “Use Ultra37000 For All New Designs”
*C 2675372 See ECN AMV Sunset Review: Obsolete product
