CLA100PD1200NA High Efficiency Thyristor VRRM = 2x 1200 V I TAV = 100 A VT = 1,21 V Phase leg Part number CLA100PD1200NA Backside: Isolated 4 3 1 2 Features / Advantages: Applications: Package: SOT-227B (minibloc) Thyristor for line frequency Planar passivated chip Long-term stability Line rectifying 50/60 Hz Softstart AC motor control DC Motor control Power converter AC power control Lighting and temperature control Isolation Voltage: 3000 V~ Industry standard outline RoHS compliant Epoxy meets UL 94V-0 Base plate: Copper internally DCB isolated Advanced power cycling Terms Conditions of usage: The data contained in this product data sheet is exclusively intended for technically trained staff. The user will have to evaluate the suitability of the product for the intended application and the completeness of the product data with respect to his application. The specifications of our components may not be considered as an assurance of component characteristics. The information in the valid application- and assembly notes must be considered. Should you require product information in excess of the data given in this product data sheet or which concerns the specific application of your product, please contact the sales office, which is responsible for you. Due to technical requirements our product may contain dangerous substances. For information on the types in question please contact the sales office, which is responsible for you. Should you intend to use the product in aviation, in health or live endangering or life support applications, please notify. For any such application we urgently recommend - to perform joint risk and quality assessments; - the conclusion of quality agreements; - to establish joint measures of an ongoing product survey, and that we may make delivery dependent on the realization of any such measures. IXYS reserves the right to change limits, conditions and dimensions. (c) 2015 IXYS all rights reserved Data according to IEC 60747and per semiconductor unless otherwise specified 20150827b CLA100PD1200NA Ratings Rectifier Conditions Symbol VRSM/DSM Definition max. non-repetitive reverse/forward blocking voltage TVJ = 25C VRRM/DRM max. repetitive reverse/forward blocking voltage TVJ = 25C 1200 I R/D reverse current, drain current VT forward voltage drop min. typ. VR/D = 1200 V TVJ = 25C 50 A TVJ = 125C 2 mA I T = 100 A TVJ = 25C 1,27 V 1,55 V 1,21 V TVJ = 125 C I T = 100 A I T = 200 A I TAV average forward current TC = 85 C I T(RMS) RMS forward current 180 sine VT0 threshold voltage rT slope resistance R thJC thermal resistance junction to case for power loss calculation only RthCH thermal resistance case to heatsink total power dissipation I TSM max. forward surge current It value for fusing V VR/D = 1200 V I T = 200 A Ptot max. Unit 1300 V 1,58 V T VJ = 150 C 100 A 150 A TVJ = 150 C 0,83 V 3,7 m 0,35 K/W 0,10 K/W TC = 25C 350 W t = 10 ms; (50 Hz), sine TVJ = 45C 1,50 kA t = 8,3 ms; (60 Hz), sine VR = 0 V 1,62 kA t = 10 ms; (50 Hz), sine TVJ = 150 C 1,28 kA t = 8,3 ms; (60 Hz), sine VR = 0 V 1,38 kA t = 10 ms; (50 Hz), sine TVJ = 45C 11,3 kAs t = 8,3 ms; (60 Hz), sine VR = 0 V 10,9 kAs t = 10 ms; (50 Hz), sine TVJ = 150 C 8,13 kAs t = 8,3 ms; (60 Hz), sine VR = 0 V CJ junction capacitance VR = 400 V f = 1 MHz TVJ = 25C PGM max. gate power dissipation t P = 30 s T C = 150 C 7,87 kAs 77 t P = 300 s pF 10 W 5 W 0,5 W PGAV average gate power dissipation (di/dt) cr critical rate of rise of current TVJ = 150 C; f = 50 Hz repetitive, IT = 300 A t P = 200 s; di G /dt = 0,5 A/s; (dv/dt)cr critical rate of rise of voltage V = VDRM VGT gate trigger voltage VD = 6 V TVJ = 25 C 1,5 TVJ = -40 C 1,6 V I GT gate trigger current VD = 6 V TVJ = 25 C 40 mA TVJ = -40 C 80 mA VGD gate non-trigger voltage TVJ = 150C 0,2 V I GD gate non-trigger current 5 mA IL latching current TVJ = 25 C 150 mA IG = 0,5 A; V = VDRM 150 A/s non-repet., I T = 100 A 500 A/s 1000 V/s TVJ = 150C R GK = ; method 1 (linear voltage rise) VD = VDRM tp = 10 s IG = 0,5 A; di G /dt = V 0,5 A/s IH holding current VD = 6 V R GK = TVJ = 25 C 100 mA t gd gate controlled delay time VD = 1/2 VDRM TVJ = 25 C 2 s tq turn-off time IG = 0,5 A; di G /dt = 0,5 A/s VR = 100 V; I T = 100 A; V = VDRM TVJ =125 C di/dt = 10 A/s dv/dt = IXYS reserves the right to change limits, conditions and dimensions. (c) 2015 IXYS all rights reserved 150 s 20 V/s t p = 200 s Data according to IEC 60747and per semiconductor unless otherwise specified 20150827b CLA100PD1200NA Package Ratings SOT-227B (minibloc) Symbol I RMS Definition Conditions RMS current per terminal min. TVJ virtual junction temperature T op operation temperature Tstg storage temperature -40 typ. max. 150 Unit A -40 150 C -40 125 C 150 C 30 Weight g MD mounting torque 1,1 1,5 Nm MT terminal torque 1,1 1,5 Nm d Spp/App d Spb/Apb VISOL Product Marking 8,6 Logo C L A 100 PD 1200 NA XXXXX (R) Zyyww abcd Assembly Line DateCode Ordering Standard 50/60 Hz, RMS; IISOL 1 mA 3,2 mm 6,8 mm 3000 V 2500 V Part description Part No. = = = = = = = Thyristor (SCR) High Efficiency Thyristor (up to 1200V) Current Rating [A] Phase leg Reverse Voltage [V] SOT-227B (minibloc) Assembly Code Ordering Number CLA100PD1200NA Similar Part CLA60PD1200NA Equivalent Circuits for Simulation V0 10,5 t = 1 second isolation voltage t = 1 minute I terminal to terminal terminal to backside creepage distance on surface | striking distance through air R0 Marking on Product CLA100PD1200NA Package SOT-227B (minibloc) * on die level Delivery Mode Tube Code No. 509048 Voltage class 1200 T VJ = 150 C Thyristor V 0 max threshold voltage 0,83 V R0 max slope resistance * 1,8 m IXYS reserves the right to change limits, conditions and dimensions. (c) 2015 IXYS all rights reserved Quantity 10 Data according to IEC 60747and per semiconductor unless otherwise specified 20150827b CLA100PD1200NA Outlines SOT-227B (minibloc) 4 IXYS reserves the right to change limits, conditions and dimensions. (c) 2015 IXYS all rights reserved 3 1 2 Data according to IEC 60747and per semiconductor unless otherwise specified 20150827b CLA100PD1200NA Thyristor 200 1300 12000 50 Hz, 80% VRRM VR = 0 V 1200 150 1100 TVJ = 45C 8000 1000 ITSM IT 100 [A] [A] 2 [A s] 800 TVJ = 125C 4000 TVJ = 125C 50 TVJ = 45C 2 It 900 700 125C 150C 600 TVJ = 25C 0 0,5 500 1,0 0 1,5 0,01 0,1 1 2 t [s] VT [V] 4 5 6 7 8 910 t [ms] Fig. 3 I t versus time (1-10 ms) 1000 1: IGD, TVJ = 150C 2: IGT, TVJ = 25C 3: IGT, TVJ = -40C 3 2 Fig. 2 Surge overload current Fig. 1 Forward characteristics 10 1 160 dc = 1 0.5 0.4 0.33 0.17 0.08 140 120 2 VG 100 3 1 1 typ. tgd 100 IT(AV)M Limit 80 6 [V] 4 [s] 5 [A] 10 TVJ = 125C 40 4: PGAV = 0.5 W 20 5: PGM = 1 W 6: PGM = 10 W 0,1 1 10 100 1000 60 1 10 10000 0 100 1000 0 25 IG [mA] IG [mA] Fig. 4 Gate trigger characteristics 50 75 100 125 150 TC [C] Fig. 5 Gate controlled delay time Fig. 6 Max. forward current at case temperature 0,4 RthHA 0.2 0.4 0.6 0.8 1.0 2.0 dc = 1 0.5 0.4 0.33 0.17 0.08 160 120 P(AV) 0,3 ZthJC 0,2 80 Rthi [K/W] [K/W] [W] 0,1 40 0 0,0 0 20 40 60 80 100 120 0 IT(AV) [A] 50 100 150 Tamb [C] (c) 2015 IXYS all rights reserved 10 100 0.011 0.001 0.083 0.096 0.135 0.04 0.40 0.16 1000 10000 t [ms] Fig. 7a Power dissipation versus direct output current Fig. 7b and ambient temperature IXYS reserves the right to change limits, conditions and dimensions. 1 ti [s] 0.022 0.014 Fig. 8 Transient thermal impedance junction to case Data according to IEC 60747and per semiconductor unless otherwise specified 20150827b