FEATURES = 4s Typical Acquisition Time = Guaranteed 0.01% Max. Gain Error m 2mV Typ. Offset Voltage @ 2.5mV Max. Hold Step = Very Low Feedthrough 80dB Min. High Input Impedance Under All Conditions = Logic Inputs Compatible with All Logic Families APPLICATIONS = {2-Bit Data Acquisition Systems = Ramp Generators = Analog Switches Staircase Generators = Sample and Difference Circuits Nt } \ LF398S8 TECHNOLOGY Precision Sample and Hold Amplifier DESCRIPTION The LF398 is a precision sample and hold amplifier which uses a combination of bipolar and junction FET transis- tors to provide precision, high speed, and long hold times. A typical offset voltage of 2mV and gain error of 0.004% al- low this sample and hold amplifier to be used in 12-bit sys- tems. Dynamic performance can be optimized by proper selection of the external hold capacitor. Acquisition times can be as low as 4us for small capacitors while hold step and droop errors can be held below 0.1mV and 30pV/sec re- spectively when using larger capacitors. The LF398 is fixed at unity gain with 10Q input impedance independent of sample/hold mode. The logic inputs are high impedence differential to allow easy in- terfacing to any logic family without ground loop prob- lems. A separate offset adjust pin can be used to zero the offset voltage in either the sample or hold mode. Addi- tionally, the hold capacitor can be driven with an external signal to provide precision level shifting or differencing operation. The device will operate over a wide supply volt- age range from +5V to + 18V with very little change in performance, and key parameters are specified over this full supply range. Basic Sample and Hold ANALOG INPUT V_ we Acquisition Time W=evT0 C10v T=25C = oa TIME (uSEC) s 1000 0.001 0.01 1.0 HOLD CAPACITOR (yF) LI WAR 9-113LF398S8 ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION Input Voltage.............ceeee ee Equal to Supply Voltage Logic to Logic Reference Differential Voltage (Note 2) .........cce cece eee ee ees +30V, -30V Output Short Circuit Duration................5. Indefinite Hold Capacitor Short Circuit Duration ............. 10 sec Lead Temperature (Soldering, 10 seconds) ......... 300C Supply Voltage oo... cece cece e eee e cece e erent ee ees + 18V Power Dissipation (Package Limitation) (Note 1)... ccc ececece esses seeeeaeeeeeeeenes 500mW Operating Temperature Range ............... 0C to 70C Storage Temperature Range............. - 65C to 150C ORDER TOP VIEW PART NUMBER a] vost LF398S8 LOGIC REFERENCE a] 5] OUTPUT PART MARKING S83 PACKAGE PLASTIC SO 308 ELECTRICAL CHARACTERISTICS (ote 3 LF398 PARAMETER CONDITIONS MIN TYP MAX UNITS Input Offset Voltage (Note 6) 2 7 mV e 10 mV Input Bias Current (Note 6) 10 50 nA e 100 nA input impedance 10 Q Gain Error R, = 10k 0.004 -0.01 % e 0.02 % Feedthrough Attenuation Ratio at 1kHz C, = 0.01 pF 80 96 dB Output Impedance HOLD Mode 0.5 4 Q e 6 ] HOLD Step (Note 4) Cy, = 0.01 nF, Voyy = 0 0.5 2.5 mV Supply Current (Note 6) T,225C 45 6.5 mA Logic and Logic Reference Input Current 2 10 pA Leakage Current Into Hold Capacitor (Note 6) HOLD Mode (Note 5) 30 200 pA Acquisition Time to 0.1% AVout = 10V, Cy = 1000pF 4 ps Cy = 0.01 pF 16 uS Hold Capacitor Charging Current Vin Vout = 2V 5 mA Supply Voltage Rejection Ratio Vout =0 80 110 dB Differential Logic Threshold 0.8 1.4 2.4 V The @ denotes the specifications which apply over the full operating temperature range. Note 1: T; max for the LF398S8 is 100C. Note 2: The jogic inputs are protected to + 30V differential as long as the voltage on both pins does not exceed the supply voltage. For proper opera- tion, however, both logic and logic reference pins must be at least 2V below the positive supply and one of these pins must be at least 3V above the negative supply. Note 3: Unless otherwise noted, Vs= + 15V, Tj = 25C, ~11.5V.sVins = +11.5V, Cy =0.01uF, Ry = 10k0 and unit is in sample mode. Logic reference = OV and logic voltage = 2.5V. 9.114 Note 4: The hold step is sensitive to stray capacitance coupling between input logic signals and the hold capacitor. 1pF, for instance, will create an additional 0.5mV step with a 5V logic swing and a 0.01,F hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value. Note 5: Leakage current is measured at a/unction temperature of 25C. The effects of junction temperature rise due to power dissipation or elevat- ed ambient can be calculated by doubling the 25C value for each 11C in- crease in chip temperature. Leakage is guaranteed over full input signal range. Note 6: These parameters are guaranteed over a supply voltage range of +5V to + 18V. DJ Witte