ANALOG DEVICES Quad SPST FET Analog Switch sW06 FEATURES Two Normally Open and Two Normally Closed SPST Switches with Disable Switches Can Be Easily Configured as a Dual SPDT or a DPDT Highly Resistant to Static Discharge Destruction Higher Resistance to Radiation than Analog Switches Designed with MOS Devices Guaranteed Roy Matching: 10% max Guaranteed Switching Speeds Ton = 500 ns max Torr = 400 ns max Guaranteed Break-Before-Make Switching Low ON Resistance: 80 0 max Low Ro, Variation from Analog Input Voltage: 5% Low Total Harmonic Distortion: 0.01% Low Leakage Currents at High Temperature Ta = 125C: 100 nA max Ta = +85C: 30 nA max Digital Inputs TTL/CMOS Compatible and Independent of V+ Improved Specifications and Pin Compatible to LF-11333/13333 Dual or Single Power Supply Operation Available in Die Form GENERAL DESCRIPTION The SW06 is a four channel single-pole, single-throw analog switch that employs both bipolar and ion-implanted FET devices. The SW06 FET switches use bipolar digital logic inputs which are more resistant to static electricity than CMOS devices. Ruggedness and reliability are inherent in the SW06 design and construction technology. Increased reliability is complemented by excellent electrical specifications. Potential error sources are reduced by minimizing ON resistance and controlling leakage currents at high tem - peratures. The switching FET exhibits minimal Row variation over a 20 V analog signal range and with power supply voltage changes. Operation from a single positive power supply voltage is possible. With V+ = 36 V, V-= 0 V, the analog signal range will extend from ground to +32 V. PNP logic inputs are TTL and CMOS compatible to allow the SW06 to upgrade existing designs. The logic 0 and logic 1 input currents are at microampere levels reducing loading on CMOS and TTL logic. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAM Ve . wo = o = a nN LEVEL IN 2 HD SHIFT r Go nN ow wo PPE i ( ow a 16 Ina ED | 15 ba 4 5 13 bis oH GND One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703oW06-- SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ vt = +15, v-- = --15 Vand T= +25, unless otherwise noted) SW 06B SW 06F SW 06G Param eter Sym bol Conditions Min Typ Max | Min Typ Max |Min Typ Max | Units ON RESIST ANCE Ron Vs=OV,ls=1mA 60 30 60 100 100 150 Q Vg=t10V,l,=1mA 65 80 65 100 100 150 Ron MATCH BETWEEN SWITCHES | Ron Match| Vs = 0 V, Is = 100 pat 3 LO 3 20 20 % ANALOG VOLTAGE RANGE Va ls = | mA +10 +11 +10 +11 +10 +11 Vv Is = | mA* -10 -15 -10 -15 -10 -15 ANALOG CURRENT RANGE ls Vs=t10V 10 15 7 12 5 10 mA ARown VS. APPLIED VOLT AGE ARon -l0 Vs Vss LOV, lp = 1.0mA 5 15 10 20 10 20 % SOURCE CURRENT IN OFF CONDITION Isores Vs = 10 V, Vp =-10 V3 0.3 2.0 0.3 2.0 0.3 10 nA DRAIN CURRENT IN QFE CONDITION IDOFFS Vs= 10V, Vp=-loV? 03 2.0 0.3 2.0 03 10 nA SOURCE CURRENT IN lgone Vs = Vp = +10 V3 0.3 2.0 0.3 2.0 0.3 10 nA ON CONDITION lbrom LOGICAL Ll INPUT VOLTAGE Vinu Full Temperature Range** 2.0 2.0 2.0 v LOGICAL 0 INPUT VOLTAGE Vint Full Temperature Range** 0.8 0.8 0.8 v LOGICAL L INPUT CURRENT lia Vin = 2.0 V to 15.0 5 5 5 10 pA LOGICAL *0 INPUT lint Vin = 0.8 V 1.5 3.0 1.5 5.0 15 10.0 | pA TURN-ON TIME ton See Switching Time 340 4500 340 600 340 700 ns Test Circuit* TURN-OFF TIME torr See Switching Time 200 400 200 400 200 500 ns Test Cirenit* BREAK -BEFORE-MAKE TIME tentore Nate 7 50 140 50 140 50 140 ns SOURCE CAPACITANCE Cstarr) V5 = 0 3 7.0 7.0 7.0 pF DRAIN CAPACITANCE Caiores Vs=0V3 5.5 5.5 55 pF CHANNEL ON CAPACITANCE Coron Vs = Vp =0V? 15 15 15 pF Csiony OFF ISOLATION Isqrore) Vs= 5 Vims, Ry = 6800, 58 58 58 dB CL=7 pF, f= 500 kH2 CROSSTALK Cr Vs = 5 Vims, Ry = 6802, 70 70 70 dB CL=7 pF, f= 500 kH2 POSITIVE SUPPLY CURRENT I+ All Channels OFF, 5.0 6.0 5.0 9.0 6.0 9.0 mA DIs = *0"3 NEGATIVE SUPPLY CURRENT l- All Channels OFF, 3.0 5.0 +40 7.0 4.0 7.0 mA Dis = 0 GROUND CURRENT le All Channels ON or 3.0 4.0 3.0 4.0 3.0 5.0 mA OFF REV. AoWO6 (@ Vt = +15 Vee = 15 V, --580 <7, 4+125C for SWO6BQ, --40C < T,< + 85C for ELECTRI CAL CHARACTERI ST CS SWO6FQ and --40C <7, <+85C for SWO6GP /GS, unless otherwise noted) SW 06B SW O06F SW 06G Param eter Symbol Conditions Min Typ Max |Min Typ Max |Min Typ Max | Units TEM PERATURE RANGE Ta Operating 55 +125 | -25 +85 |0 70 C ON RESISTANCE Ron Vs=0V,1s= 1.0mA 75 110 75 125 75 175 | Q V5 = +410 V,1s=1.0mA 80 86110 80 125 80 175 ARon MATCH BETWEEN SWITCHES | Ron Match | Vs=0 V,1s= LOO pA! 6 20 6 25 10 %e ANALOG VOLTAGE RANGE Va ls = 1.0 mA* +10 +11 +10 +11 +10 +11 Vv ls = 1.0 mA? -10 -15 -10 -15 -10 -15 ANALOG CURRENT RANGE ls Vs=+410V 7 12 5 11 ll mA ARon WITH APPLIED VOLTAGE ARon -10 VS Vs LOV,Ig=1.0mA 10 12 15 % SOURCE CURRENT IN V5= 10 V, Vp =-l0V OFF CONDITION IsoFF) T4 = Max Operating Temp*? 60 30 60 nA DRAIN CURRENT IN Vs= 10 V, Vp =-10V OFF CONDITION ID.OFF} Ta = Max Operating Temp* 60 30 60 nA LEAKAGE CURRENT IN Iscon + Vs = Vp =+410V 100 30 60 nA ON CONDITION Ipion; Ta = Max Operating Temp* LOGICAL 1 INPUT CURRENT lie Vin = 2.0 Vto 15.0 10 10 15 pA LOGICAL *0" INPUT CURRENT lit Vin = 0.8 V 4 10 4 10 5 15 pA TURN-ON TIME ton See Switching Time +40 900 500 900 1000 | ns Test Circuit TURN-OFF TIME torr See Switching Time 300 500 330 500 500 | ns Test Cirenit* BREAK -BEFORE-MAKE TIME ton-torr Note 7 70 70 50 ns POSITIVE SUPPLY CURRENT lt All Channels OFF, 9.0 13.5 13.5 | mA DIs = "0"? NEGATIVE SUPPLY CURRENT l- All Channels OFF, 75 10.5 10.5 | mA DIs=*0"3 GROUND CURRENT le All Channels ON or 6.0 75 75 mA OFR NOTES Ron + Bows + Bons + Fon 4 Wg =0V, Is = 100 pA. Specified as a percentage of Raverace where: Raysracs = FT "Guaranteed by Ron and leakage tests. For normal operation maximum analog signal voltages should be restricted to less than (V+) 4 V. "Switch being tested ON or OFF as indicated, Viyy, = 2.0 V or Vin, = 0.8 V, per logic truth table. 4Also applies to disable pin. *Current tested at Vj_ = 2.0 V. This is worst case condition. *Sample tested. "Switch is guaranteed by design to provide break-before-make operation. *Guaranteed by design. Parameter tested only at T, = +125C for military grade device. Specifications subject to change without notice. REV. A _3_oW06 WAFER TEST LI MI TS (@ Vt = +15 V, Vee = --15 V, T= +25, unless otherwise noted) SW O6N SW O06G Param eter Sym bol Conditions Limit Limit Units ON RESIST ANCE Ron -lOVsV,s 10V,IsslmA 80 100 QO max Row MATCH BETWEEN SWITCHES Ron Match| Va=0V, Is 100pA 15 20 % max ARon VS. Va ARon -lOV<e Vas 10V,Is2lmA 10 20 % max POSITIVE SUPPLY CURRENT I+ Note 1 6.0 9.0 mA max NEGATIVE SUPPLY CURRENT L- Note 1 5.0 7.0 mA max GROUND CURRENT Ig Note 1 4.0 4.0 mA max ANALOG VOLT AGE RANGE Va Iz=lmA +10.0 +10.0 min LOGIC 1 INPUT VOLTAGE Vinu Note 2 2.0 2.0 min LOGIC 0 INPUT VOLTAGE Vint Note 2 0.8 0.8 V max LOGIC 0 INPUT CURRENT Ip OVS Vy $0.8 V 5.0 5.0 pA max LOGIC 1 INPUT CURRENT Inu 20V<Vysi5sVv 5 5 pA max ANALOG CURRENT RANGE Ta Vs =t10mV 10 7 mA min NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. TYP | CAL ELECTRI CAL CHAR ACTERI STl CS (@ V+ = +15 V, Vee = --15 V, T= + 25C, unless otherwise noted) SW OG6N SW O06G Param eter Sym bol Conditions Typical Typical | Units ON RESIST ANCE Ron -lOV<E Vas 1O0V,Is;2lmA 60 60 Oo TURN-ON TIME ton 340 340 ns TURN-OFF TIME torr 200 200 ns DRAIN CURRENT IN OFF CONDITION TprorF) V5=10V,V,=-10V 0.3 0.3 nA OFF ISOLATION IsocoFF) f= 500 kHz, Ry = 6800 58 58 dB CROSSTALK Cr f= 500 kHz, R; = 6800 70 70 dB NOTES 'Power supply and ground current specified for switch ON or OFF. ?Guaranteed by Ron and leakage tests. 3Current tested at Vzy = 2.0 V. This is worst case condition. REV. AoW06 ABSOLUTE MAXIMUM RATINGS" ORDERING GUIDE Operating Temperature Range ; ; Tem perature Package Package SWO06BQ, BRC ...........-..--06- $5C to +125C M odel Range Description Option SWO06FQ ..... ee e eee 40C to +85C SWO6GP,GS ...............2.0006. 40C to +85C SWO6BQ 55C to+125C_ | Cerdip Q-16 Storage Temperature Range ........... -65C to +150C SWO6BRC 55C to+125C | LCC E-20A Lead Temperature (Soldering, 60 sec) ............ +300C SWO06FQ 40C to +85C Cerdip Q-16 Maximum Junction Temperature ................ +150C SWO06GP 40C to +85C Plastic DIP N-16 V+ Supply to V-Supply .. 0.0.0... cee eee +36 V SW06GS 40C to +85C SOL R-16 V+ Supply to Ground 2.0.0.0... 2.00. +36 V Logic Input Voltage ........... (+4 V or V-) to V+ Supply Analog Input Voltage Range TRUTH TABLE Continuous ...........0. V Supply to V+ Supply +20 V Switch State Maximum Current Through Disable Logie Channels Channels Any Pin Including Switch ..........0......0... 30 mA Input Input 1&2 ah 4 Package T ype 67 fy Units 4 xX OFF OFF 16-Pin Hermetic DIP (Q) 100 16 ecyw Lor NC OFF ON 16-Pin Plastic DIP (P) 82 39 ecyw Lor NC ON OFF 20-Contact LCC (RC) 98 38 C/W 16-Pin SOL (S) 98 30 C/W NOTES Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 76.4 is specified for worst case mounting conditions, i.e., 8), 18 specified for device in socket for Cerdip, P-DIP, and LCC packages; 8), is specified for device soldered to printed circuit board for SO package. DICE CHARACTERISTICS Die Size 0.101 x 0.097 inch, 9797 sq. mils (2.565 x 2.464 mm, 6320 sq. mm) REV. A 5 PIN CONNECTIONS 16-Pin DIP (Q or P-Sufftix) 16-Pin SOL (S- Suffix) ms peg fil me oer, ! we b4 To ee ono [4] [ra] Dis a ES arf oF mis |r IN2 E>! ~<f-T9] ina SW 06B RC /883 LOC Package (RC -Suftix)oW06-- Typical Performance Characteristics NOP Ta = 26C Vi = 15V 100 Fy =-15V Fon (ii 8s eSB a 8 8 = 63 2120: 13 tt 4B Otte O17? ETH EAD POWER SUPPLY VOLTAGE [VOLTS} ON Resistance vs. Power Supply Voltage -10 gg) SWITCH CURRENT (mA} 2 n 2 =1 0 1 Zz Vsp VOLTAGE ACROSS SWITCH (VOLTS) Switch Current vs. Voliage 1D T , ve = 15V Vo =15V Dis - 0 at_4 J a = 5 6 oe Ww < | c 3 + A po | > 4 fe 2 a I- = 2) . ee , ,,. i 85 -35 -15 5 25 #45 #6650 68 O105 1245 TEMPERATURE (C) Supply Current vs. Temperature 75 7 Ve=4+15V W- = -15V 70 F- Ta = 25C Ig mA 65 = 60 Peel a aa = ee) ow 55 50 45 40 10 -5 0 5 10 ANALQG INPUT VOLTAGE-Va (VOLTS} ON Resistance vs. Analog Voltage ~100 SUPPLY = +15V __ Tg = 125C | o Ipton}+'S(ON} LEAKAGE (nl 4 L = o LE POLARITY REVERSES. MAGNITUDE LESS THAN 10 AM -6.01 15 10 5 0 5 10 15 ANALOG VOLTAGE (VOLTS) leakage Current vs. Analog Voltage 10 Ta = 25C Ols = 0 a Zz = BG J Fs = It o nee > ab - ws a o all 5 n on] I- 2 3 6 % 12 15 18 +SUPPLY VOLTAGE {VOLTS} Supply Current vs. Supply Voltage LEAKAGE CURRENT CAPACITANCE [pF] 76 T Ve = 16 V-=-15 70 od 40 55 25 a 25 50 76 100 1265 TEMPERATURE (C! Ron vs. Temperature 100n A V+ = 15V V-=-15V 10nA Tn a ig wor * wd > 100pA 10pa 65 = 25 a 2 SO 75 100 125 TEMPERATURE ("Ch Leakage Current vs. Temperature 32 28 24 20 16 Cs (OFF) 4 Cp (OFFI 0 -1-9 7-5 -3 -1 1 3 5 7 9 1 ANALOG VOLTAGE {VOLTS} Switch Capacitance vs. Analog Voltage REV. ATon/Top Switching Response INSERTION LOSS (dB) Var Mem Rut Kg 5 1M FREQUENCY [Hz] 10M 100M dasertion Loss vs. Frequency REV. A POWER SUPPLY REJECTION (dB) 4+PSAR = 20 Ing Ay PSRR = 20 loy Bp Tas 25C Ventey vas 15 Ry = 1ki2 SWITCH CLOSED 100k FREQUENCY (Hz} dk Wk Power Supply Rejection vs. Frequency 1M 400 Vg = LBV FL = ki a CL = 10pF 350 = Tas2nc 4 ce @ 300 el Z F 250 N 200 T nl OFF 150 =-10 =5 0 4 10 ANALOG INPUT VOLTAGE (VOLTS) Switching Time vs. Analog Voltage 190 T4711 | | | Ta=25C Vt = 1B |] 90 | ' > SY TH 70 OFF ISGLATION AND CROSSTALK (dB) 4S ' iy! "4 4q vO, \ PO 6o + MN ~] / 5 PS MS lly 40 | Ly 100k IM 10M FAEQUENCY (Hz! Crosstalk and OFF Isolation vs. Frequency 500 | Ton 400 a Le | Lae) en T, $m = oo & jae) a 2 Le = 200 oa 1 100 0 35 -2% 0 2 60 7% 100 125 TEMPERATURE CC) Switching Time vs. Temperature Ve=4+ 16 Vo - 16V- Ya> ins Ty = 25C = TOTAL H&RMONIC DISTORTION 1%) 2 0.01 10k FREQUENCY (Hz) 100 100k Total Harmonic Distortion Av+ aVD ANALOG CURRENT=I 4 (mA} 20 -1 DB a 10 2 30 ANALOG VOLTAGE-, (VOLTS) Overvoliage CharacteristicsoW06-- Typical Performance Characteristics (Operating and Single Supply) 200 180 160 140 120 100 30 ON RESISTANCE (23) 6g 40 20 G o 4 8 12 16 20 24 ANALOG VOLTAGE (VOLTSI 28 On Resistance vs. Analog Voltage 1000 0 500 700 Vas 28y 0.1 'DiOFFI IStOFF) FOR Iniarr), Ys" 12 FOR IgigfF), pt 2 'DioN) LEAKAGE CURRENT [nA} Ve =2BV v-=0V GND-OV Ty=25' C i 4 a 12 16 20 24 28 ANALOG VOLTAGE (VOLTS} feakage Current vs. Vanaroc NOTE SUPPLY CURRENT (ma) Supply Current vs. Supply Voltage 10 SUPPLY v--0 GND =0 Ty 25C | I Ve I- r 4 I | i ' : | | | | 0 8 12 16 20024 VOLTAGE (VOLTS) SWITCHING TIME {inser} 600 50D 400 300 200 tore 100 o 4 8 12 16 200 (24 28 ANALOG VOLTAGE (VOLTS) Switching Time vs. Supply Voltage INPUT Ke INy a4 ! mY DIGITAL ai as an D1 Y @ OW Da These single-supply-operation characteristic curves are valid when the negative power supply V is tied to the logic ground reference pin GND. TTL input compatibility is still main- tained when GND is the same potential as the TTL ground. torr is measured from 50% of logic input waveform to 0.9 Vo. The analog voltage range extends from 0 V to V+ -4 V; the switch will no longer respond to logic control when Vy, is within 4 volts of V+. OG D2 SH os ag I { mm ANALOG IN (3) \ | Obs O aino Simplified Schematic Diagram (Typical Switch) _| J10 /- out iD REV. A3 Vout Va SVams AT [- 500kHz s a D T Va 400 cL AL Va 1 OFF ISOLATION - 20 LOG | | Vout Off Isolation Test Circuit +15 +15V RL J Vo" Vs AL + rps (ON) SWITCH SWITCH INPUT bis vad 5 OUTPUT 1 Vg2-5 Of | + Vo i IN1 I [> RL cL Loic me 40 OF co INPUT SND REPEAT TEST FOR IN, INg AND INg. REV. A Va = VRMS AT f = 500kKH7 $1 Nc oO ot D1 CROSSTALK - 20106 Dez ee ee) Ne Va, Yo Crosstalk Test Circuit LOGIC INPUT 3.0V te = 2OnS re 20nd SWITCH LOGIC 0 = SW ON a ae j INPUT = SWITCH OUTPUT } | ton 1 SWITCH QUTPUT WAVEFORM SHOWN FOR Vg = CONSTANT WITH LOGIC INPUT WAVEFORM AS SHOWN. Vo IS THE STEADY STATE OUTPUT WITH SWITCH ON. LOGIC INPUT IS INVERTED FOR SWITCH t& 2 Switching Time Test CircuitoW06 QUAD SPST DPDT 81,54 82,83 IN TIN 2 ane or or 4 b4 a1 Ds D2 DUAL $PDT 1,54 IN TIN 4 r b4 D1 $2,83 IN 2IN t OR Dz GUAL DPST SI 52 IN 1,(N 2 r { I, b., 4 53 5 IN 3.1N 4 f Ds Db. 4 Figure 1. Functional Applications of SW06 APPLICATIONS INFORMATION The single analog switch product configures, by appropriate pin connections, into four switch applications. As shown in Figure 1, the SWO06 connects asa QUAD SPST, a DUAL SPDT, a DUAL DPST, or a DPDT analog switch. This versatility in- creases further when taking advantage of the disable input (DIS) which turns all switches OFF when taken active low. Ion-implantation of the JFET analog switch achieves low ON resistance and tight channel-to-channel matching. Combining the low ON resistance and low leakage currents results in a worst case voltage error figure Verror @ +125C = Ipron; x Rspron; = LOO nA x 100 O = 11 microvolts. This amount of er- ror is negligible considering dissimilar-metal thermally-induced offsets will be in the 5 to 15 microvolt range. LOGIC INPUTS The logic inputs (INx) and disable input (DIS) are referenced to a TTL logic threshold value of two forward diode drops (1.4 V at +25C)} above the GND terminal. These inputs use PNP transistors which draw maximum current at a logic 0 level and drops to a leakage current of a reverse biased diode as the logic input voltage raises above 1.4 volts. Any logic input voltage greater than 2.0 volts becomes logic 1, less than 0.8 volts be- comes logic OQ resulting in full TTL noise immunity not avail- able from similar CMOS input analog switches. The PNP transistor inputs require such low input current that the SW06 approaches fan-ins of CMOS input devices. These bipolar logic inputs exceed any CMOS input circuit in resistance to static voltage and radiation susceptibility. No damage will occur to the SW06 if logic high voltages are present when the SW06 power supplies are OFF. When the V+ and V supplies are OFF, the logic inputs present a reverse bias diode loading to active logic inputs. Input logic thresholds are independent of V+ and V supplies making single V+ supply operation possible by simply connecting GND and V- together to the logic ground supply. ANALOG VOLTAGE AND CURRENT ANALOG VOLTAGE These switches have constant ON resistance for analog voltages from the negative power supply (V) to within 4 volts of the positive power supply. This characteristic shown in the plots re- sults in good total harmonic distortion, especially when com- pared to CMOS analog switches that have a 20 to 30 percent variation in ON resistance versus analog voltage. Positive analog input voltage should be restricted to 4 volts less than V+ assur- ing the switch remains open circuit in the OFF state. No in- crease in switch ON resistance occurs when operating at supply voltages less than +15 volts (see plot). Small signals have a 3 dB down frequency of 70 MHz (see insertion loss versus frequency plot). ANALOG CURRENT The analog switches in the ON state are JFETs biased in their triode region and act as switches for analog current up to the I, specification (see plot of Ips vs Vps). Some applications require pulsed currents exceeding the I, spec. For example, an integra- tor reset switch discharging a shunt capacitor will produce a peak current of Ix;pgaxy = Veap/Rpscons. In this application, it is best to connect the source to the most positive end of the ca- pacitor, thereby achieving the lowest switch resistance and 10- REV. AoW06 fastest reset times. The switch can easily handle any amount of capacitor discharge current subject only to the maximum heat dissipation of the package and the maximum operating junction temperature from which repetition can be established. SWITCHING Switching time toy and tore characteristics are plotted versus VanaLoo and temperature. In all cases, torr is designed faster than ton to ensure a break-before-make interval for SPDT and DPDT applications. The disable input (DIS) has the same switching times (toy and togp) as the logic inputs (INy). Switching transients occurring at the source and drain contacts results from ac coupling of the switching FETs gate-to-source and gate-to-drain coupling capacitance. The switch turn ON will cause a negative going spike to occur and the turn OFF will cause a positive spike to occur. These spikes can be reduced by additional capacitance Loading, lower values of Ri, or switching an additional switch (with its extra contact floating) to the op- posite state connected to the spike sensitive node. Typical Applications d 1/4 SWOB O- Vanarog = Vt -4 3 a 5 VauT a O +BV I o | TTL OR Mi CONTROL _ ems | C _l INPUL v SNO Operation from Single Positive Power Supply 115 DISABLE NODE This TTL compatible node is similar to the logic inputs INy but has an internal 2 WA current source pull-up. If disable is left un- connected, it will assume the logic 1 state, then the state of the switches is controlled only by the logic inputs INx. POWER SUPPLIES This product operates with power supply voltages ranging from +12 to +18 volts; however, the specifications only guarantee device parameters with +15 volt 45% power supplies. The power supply sensitive parameters have plots to indicate effects of supply voltages other than +15 volts. i, +15V |, 15V Swe | a . oa 2 VOUT 13 DISABLE ALL SWITCHES CHANNEL SELECT 4-Channel Sample Hold Amplifier +18 | CONTROL a3 sw 06 Ve rose 15 .- | H Vout | | j | ova! AA O18 -} nc a in v-[-9 -15v i 1,16 INPUT HI-CHANNEL 1 ON LO CHANNEL 2 ON THIS SWITCH ARRANGEMENT IMPROVES OFF ISOLATION BY 20dB High Off Isolation Selector Switch (Shunt-Series Switch) REV. A -ll-oW06 4g LOGIC IN ve (VOLTS) 7,10 u yo - > 0 %o 6] a 1K Vo (VOLTS) pee During the BBM interval the 1kf resistor pulls the output to ground assuring thal no shorting between V, and Vz occurs. Single Pole Double Throw Selector Switch with Break-Be fore-Make Interval OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Terminal Leadless Chip Carrier (RC-Suffix) E-20A 0.100 (2.54) Gon 0.064 (1.63) REF 4 0.358 (9.09) 9.358 ee (9.09) 0.011 (0.28) 0.942 (8.69) ay 0.007 we) sa R TYP Lt 0.075 i a) ht 0.088 (2.24) 0.055 (1.40) 0.054 (1.37) 0.045 (1.14) 0.095 (2.44) 0.075 (1.90) 0.200 (5.08) BSc ry 0.100 (2.54) BSC M7 in 0.150 (3.81} BSC 16-L ead Plastic DIP (P -Sufttix) N-16 0.840 (21.33) 0.745 (18.93) aA A Pt ts 0.280 (7.11) P. |] 9-240 (6.10) w,7 CU ee SF 0.060 (1.52) PIN 1 0.015 (0.38) 0.240 (5.33) MAX 0.130 0.160 (4.06) A IN (3.30) 3915 (12.04 Nui 0.415 (2.09) 0.022 (0.558) 0.014 (0.356} ee 0.100 (2.54) BSC 0.070 (1.77) SEATING 0.095 (4.15) PLANE 0.325 (8.25) 0.300 (7.62) 9-195 (4.95} 0.115 (2.93) 0.015 (0.381) D.008 (0.204} 16-Lead Cerdip (Q-Suffix) Q-16 0.005 (0.13) MIM 0.080 (2.03) MAX PIN 71 p> 0.840 (21.94) MAX 0.320 (8.13) = | 0.200 0.060 (1.52) ($.08) F 0.015 (0.38) MAX 0.450 0.018 (0.38) 0.200 (5.08) (3.81) 025 (3.18) MIM 0.008 (0.20) ~ uw 0.023 (0.58) o.100 0.070 (1.78) o 014 (0.38) (2.54) 030 .76) ae Bsc LAME 16-Lead Wide Body SOL (S- Suttix) R-16/SOL-16 0.4133 (10.50) | 0.3977 (10.00) Pip A i A A 16 9 g| 2/8 ele Fle > ale ol 2 i =|8 = HEHEHE Y | PIN i 0.1043 (2.85) 0.0291 (0.74) | 46 0.0118 (0.30) 0.0926 (2.95) 7 [* o.0098 (0.25) D098 (0.25) 0.0040 (0.10) tA ay hoe et wel [am ge 0.0500 (1.27) 0.0500 0.0192 (0.49) i 0 0.0187 (0.40) ay he (1.27) opraemgs) SEATING 0.0128 (0.22) Bsc PLANE 5.0094 (0.23) REV. A