ICE5AR0680AGXUMA1 - INFINEON TECHNOLOGIES AG

Datasheet Please read the Important Notice and Warnings at the end of this document V 2.2

www.infineon.com page 1 of 42 2018-03-02

ICE5xRxxxxAG

Fixed Frequency 700 V/800 V CoolSET™ - in DSO-

12 Package

Product highlights

 Integrated 700 V/ 800 V avalanche rugged CoolMOS™

 Enhanced Active Burst Mode with selectable entry and exit standby

power to reach the lowest standby power <100 mW

 Digital frequency reduction for better overall system efficiency

 Fast startup achieved with cascode configuration

 Frequency jitter and soft gate driving for low EMI

 Integrated error amplifier

 Comprehensive protection with input line over voltage protection

 Pb-free lead plating, halogen-free mold compound, RoHS compliant

PG-DSO-12

Features

 Integrated 700 V/ 800 V avalanche rugged

CoolMOS™

 Enhanced Active Burst Mode with selectable entry

and exit standby power

 Digital frequency reduction for better overall

system efficiency

 Fast startup achieved with cascode configuration

 DCM and CCM operation with slope compensation

 Frequency jitter and soft gate driving for low EMI

 Built-in digital soft start

 Integrated error amplifier to support direct

feedback in non-isolated flyback

 Comprehensive protection with input line over

voltage protection, VCC over voltage, VCC under

voltage, overload/open loop, over temperature

and Current Sense (CS) short to GND

 All protections are in auto restart mode

 Limited charging current for VCC short to GND

Applications

 Auxiliary power supply for home appliances/white

goods, TV, PC & server

 Blu-ray player, set-top box & LCD/LED monitor

Product validation

Fully qualified according to JEDEC for Industrial

Applications

Description

The ICE5xRxxxxAG is the 5th generation of fixed

frequency integrated power IC (CoolSET™) optimized

for off-line switch mode power supply in cascode

configuration. The CoolSET™ package has 2 separate

chips inside; one is controller chip and the other is a

700 V/ 800 V CoolMOS™ chip. The cascode

configuration helps achieve fast startup. The

frequency reduction with soft gate driving and

frequency jitter operation offers lower EMI and better

efficiency between light load and 50% load. The

selectable entry and exit standby power ABM enables

flexibility and ultra-low power consumption at

standby mode with small and controllable output

voltage ripple. The product has a wide operating

range (10.0 ~ 25.5 V) of IC power supply and lower

power consumption. The numerous protection

functions with adjustable line over voltage protection

support the power supply system in failure situations.

All these make the 5th generation CoolSET™ series an

outstanding integrated power stage fixed frequency

flyback converter in the market.

Datasheet Please read the Important Notice and Warnings at the end of this document V 2.2

www.infineon.com page 2 of 42 2018-03-02

ICE5xRxxxxAG

85 ~ 300 VAC

Snubber

Cbus

Dr1~Dr4

RCS

CVCC DVCC

ICE5xRxxxxAG CoolSETTM

CoolMOSTM

RVCC

DRAIN

Active Burst Mode

Power Management

Cycle-by-Cycle

current limitation

Error Amplifier

PWM controller

Current Mode Control

Digital Control

VCC

Control Unit

VERR

GND

VIN

RI1

RI2

Gate

Driver

Protections

RSTARTUP

GATE

TL431

Optocoupler

Rb1 Rb2

Rc1

Cc1 Cc2

Rovs2

Rovs1

DO1 CO1 Lf1 Cf1 VO1

CPS

DO2 CO2 Lf2 Cf2 VO2

Ws1

Ws2

# RSel

# Optional

RSel (Burst mode detect)

Rovs3

(V02 feedback)

# Rovs3

Figure 1 Typical application in isolated flyback using TL431 and optocoupler

85 ~ 300 VAC

Snubber

Cbus

Dr1~Dr4

RCS

CVCC DVCC

ICE5xRxxxxAG CoolSETTM

CoolMOSTM

RVCC

DRAIN

Active Burst Mode

Power Management

Cycle-by-Cycle

current limitation

Error Amplifier

PWM controller

Current Mode Control

Digital Control

VCC

Control Unit

VERR

GND

VIN

RI1

RI2

Gate

Driver

Protections

RSTARTUP

GATE

RF1

RF2

DO1 CO1 Lf1 Cf1 VO1

CPS

DP1

CP1

LfP1

CfP1

VP1

Ws1

WP1

# RSel

# Optional

RSel (Burst mode detect)

Figure 2 Typical application in non-isolated flyback utilizing integrated error amplifier

Output power of 5th generation Fixed-Frequency CoolSET™

Table 1 Output power of 5th generation Fixed-Frequency CoolSET™

Type

Package

Marking

VDS

Fsw

RDSon1

220 V AC ±20%2

at DCM

85-300 V AC2

at DCM

85-300 V AC2

at CCM

ICE5AR4770AG

PG-DSO-12

5AR4770AG

700 V

100 kHz

4.73 Ω

27 W

15 W

16 W

ICE5GR4780AG

PG-DSO-12

5GR4780AG

800 V

125 kHz

4.13 Ω

27.5 W

15 W

16 W

ICE5GR2280AG

PG-DSO-12

5GR2280AG

800 V

125 kHz

2.13 Ω

41 W

23 W

24 W

ICE5GR1680AG

PG-DSO-12

5GR1680AG

800 V

125 kHz

1.53 Ω

48 W

27 W

28 W

ICE5AR0680AG

PG-DSO-12

5AR0680AG

800 V

100 kHz

0.71 Ω

68 W

40 W

42 W

Typ. at TJ =25 °C (inclusive of low side MOSFET)

Calculated maximum output power rating in an open frame design at Ta=50 °C, TJ=125 °C (integrated high voltage MOSFET) and using

minimum drain pin copper area in a 2 oz copper single sided PCB. The output power figure is for selection purpose only. The actual

power can vary depending on particular designs. Please contact to a technical expert from Infineon for more information.

Datasheet 3 of 42 V 2.2

2018-03-02

Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package

Pin configuration and functionality

Table of contents

Product highlights ................................................................................................................................................. 1

Features ................................................................................................................................................................. 1

Applications ........................................................................................................................................................... 1

Product validation ................................................................................................................................................. 1

Description ............................................................................................................................................................ 1

Output power of 5th generation Fixed-Frequency CoolSET™ ................................................................................. 2

Table of contents ................................................................................................................................................... 3

1 Pin configuration and functionality ............................................................................................................. 5

2 Representative block diagram ..................................................................................................................... 7

3 Functional description ................................................................................................................................. 8

3.1 VCC pre-charging and typical VCC voltage during start-up ....................................................................... 8

3.2 Soft-start .................................................................................................................................................. 9

3.3 Normal operation .................................................................................................................................... 9

3.3.1 PWM operation and peak current mode control .............................................................................. 9

3.3.1.1 Switch-on determination.............................................................................................................. 9

3.3.1.2 Switch-off determination ............................................................................................................. 9

3.3.2 Current sense ................................................................................................................................... 10

3.3.3 Frequency reduction ........................................................................................................................ 11

3.3.4 Slope compensation ........................................................................................................................ 11

3.3.5 Oscillator and frequency jittering .................................................................................................... 12

3.3.6 Modulated gate drive ....................................................................................................................... 12

3.4 Peak current limitation ......................................................................................................................... 12

3.4.1 Propagation delay compensation ................................................................................................... 12

3.5 Active Burst Mode (ABM) with selectable power level ......................................................................... 14

3.5.1 Entering ABM operation ................................................................................................................... 14

3.5.2 During ABM operation ...................................................................................................................... 14

3.5.3 Leaving ABM operation .................................................................................................................... 14

3.5.4 ABM configuration ............................................................................................................................ 16

3.6 Non-isolated/isolated configuration .................................................................................................... 16

3.7 Protection functions ............................................................................................................................. 17

3.7.1 Line over voltage .............................................................................................................................. 17

3.7.2 VCC over/under voltage ..................................................................................................................... 17

3.7.3 Overload/ open loop ........................................................................................................................ 17

3.7.4 Over temperature ............................................................................................................................. 17

3.7.5 CS short to GND ................................................................................................................................ 18

3.7.6 VCC short to GND................................................................................................................................ 18

3.7.7 Protection modes ............................................................................................................................. 18

4 Electrical characteristics ............................................................................................................................ 20

4.1 Absolute maximum ratings ................................................................................................................... 20

4.2 Operating range .................................................................................................................................... 21

4.3 Operating conditions ............................................................................................................................ 21

4.4 Internal voltage reference ..................................................................................................................... 22

4.5 PWM section .......................................................................................................................................... 22

4.6 Error amplifier ....................................................................................................................................... 23

4.7 Current sense ......................................................................................................................................... 23

4.8 Soft start ................................................................................................................................................ 23

Datasheet 4 of 42 V 2.2

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Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package

Pin configuration and functionality

4.9 Active Burst Mode .................................................................................................................................. 24

4.10 Line over voltage protection ................................................................................................................. 24

4.11 VCC over voltage protection ................................................................................................................... 25

4.12 Overload protection .............................................................................................................................. 25

4.13 Thermal protection ............................................................................................................................... 25

4.14 CS short to GND protection ................................................................................................................... 25

4.15 CoolMOS™ section ................................................................................................................................. 26

5 CoolMOS™ performance characteristics .................................................................................................... 27

6 Output power curve ................................................................................................................................... 36

7 Outline dimension ..................................................................................................................................... 39

8 Marking ...................................................................................................................................................... 40

Revision history ................................................................................................................................................... 41

Datasheet 5 of 42 V 2.2

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Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package

Pin configuration and functionality

1 Pin configuration and functionality

The pin configuration is shown in Figure 3 and the functions are described in Table 2.

Figure 3 Pin configuration

Table 2 Pin definitions and functions

Symbol

Function

VIN

Input Line Over Voltage Protection (LOVP)

VIN pin is connected to the bus via resistor divider (see Figure 1) to sense the line voltage.

Internally, it is connected to the line over voltage comparator which will stop the

switching when LOVP condition occurs. To disable LOVP, connect this pin to GND.

VERR

Error amplifier

VERR pin is internally connected to the transconductance error amplifier for non-isolated

flyback application. Connect this pin to GND for isolated flyback application.

Feedback and ABM entry/exit control

FB pin combines the functions of feedback control, selectable burst entry/exit control

and overload/open loop protection.

Current sense

The CS pin is connected to the shunt resistor for the primary current sensing externally

and to the PWM signal generator block for switch-off determination (together with the

feedback voltage) internally. Moreover, CS short to ground protection is sensed via this

pin.

GND

VERR

VIN

VCC

GATE

CS NC

PG-DSO-12

DRAIN DRAIN

Datasheet 6 of 42 V 2.2

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Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package

Pin configuration and functionality

Symbol

Function

5, 6, 7,

DRAIN

DRAIN(Drain of integrated CoolMOS™)

The DRAIN pin is connected to the drain of the integrated CoolMOS™.

No connection

GATE

Gate driver output

The GATE pin is connected to the Gate of the internal CoolMOS™ and additionally, a pull

up resistor is connected from bus voltage to turn on the internal CoolMOS™ for charging

up the VCC capacitor during startup.

VCC

VCC(Positive voltage supply)

The VCC pin is the positive voltage supply to the IC. The operating range is between

VVCC_OFF and VVCC_OVP.

GND

Ground

The GND pin is the common ground of the controller.

Datasheet 7 of 42 V 2.2

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Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package

Representative block diagram

2 Representative block diagram

Gate Driver

Thermal Protection

Slope Compensation/Current Limiting

Line Overvoltage Protection

Active Burst Block

RFB

25kΩ

2pF

tFB_BEB

C10

VFB_BOn

C11

VFB_BOff

fOSC

OSC

Active

Burst Mode

Soft-start

VREF

DRAIN

VCC

Gate

Drive

Current Mode GPWM

PWM OP

PWM

Comparator

VPWM

Power Management

Voltage

Reference

Undervoltage Lockout

16.0V

10.0V

tVCC_OVP_B

Internal

Bias

CoolMOSTM

Overload Protection

C12

VFB_OLP/

VFB_LB

tFB_OLP_B

10kΩ

Leading

Edge

Blanking

tCS_LEB 1pF

C13

C15

Protection and PWM Digital Control

GND

C20

VVCC_OVP

Tj > Tjcon_OTP

C7a

VVIN_LOVP

Autorestart

Protect

Input

OVP

Mode

250 µs

Blanking

time

VIN

GATE

VCS_BLP

VCS_BHP

VFB_EBHP

VFB_EBLP

Autorestart

Protect

Tj < Tjcon_OTP-TjHYS _OTP

OTP

Mode

50 µs

Blanking

time

Gate

Drive

C19 VCS_STG

Delay

tCS_STG

100 ns

Blanking

time

VCS_Nx

CPWM

VERR

Error Amplifier

ERR

VERR_REF

Non-

Isolated

Detector

fOSC_2

OSC with

Jitter and

Frequency

Reduction

Slope

Comp

VREF

Burst Mode

Level Select

Burst

Mode

detect

Peak current

limit

No burst C15a

Figure 4 Representative block diagram

Note: Junction temperature of the controller chip is sensed for over temperature protection. The

CoolMOSTM is a separate chip from the controller chip in the same package. Please refer to the

design guide and/or consult a technical expert for the proper thermal design.

Datasheet 8 of 42 V 2.2

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Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package

Functional description

3 Functional description

3.1 VCC pre-charging and typical VCC voltage during start-up

As shown in Figure 1, once the line input voltage is applied, a rectified voltage appears across the capacitor CBUS.

The pull up resistor RSTARTUP provides a current to charge the Ciss (input capacitance) of CoolMOS™ and gradually

generate one voltage level. If the voltage over Ciss is high enough, CoolMOS™ on and VCC capacitor will be

charged through primary inductance of transformer LP, CoolMOS™ and internal diode D1 with two steps

constant current source IVCC_ Charge1

and IVCC_ Charge31.

A very small constant current source (IVCC_Charge1) is charged to the VCC capacitor till VCC reach VCC_SCP to protect the

controller from VCC pin short to ground during the start up. After this, the second step constant current source

(IVCC_Charge3) is provided to charge the VCC capacitor further, until the VCC voltage exceeds the turned-on threshold

VVCC_ON. As shown in the time phase I in Figure 5, the VCC voltage increase almost linearly with two steps.

VVCC_ON

VVCC

VVCC_OFF

III III

tAtB

VVCC_SCP

IVCC_Charge2/3

IVCC

IVCC_Normal

IVCC_Charge1

-IVCC

Figure 5 VCC voltage and current at startup

The time taking for the VCC pre-charging can then be approximately calculated as:

  

  



󰇛

  

󰇜  



(1)

When the VCC voltage exceeds the VCC turn on threshold VVCC_ON at time t1, the IC begins to operate with soft-start.

Due to power consumption of the IC and the fact that there is still no energy from the auxiliary winding to

charge the VCC capacitor before the output voltage is built up, the VCC voltage drops (Phase II). Once the output

voltage rises close to regulation, the auxiliary winding starts to charge the VCC capacitor from the time t2 onward

and delivering the IVCC_ Normal

to the CoolSET™. The VCC then will reach a constant value depending on output

load.

IVCC_ Charge1/2/3 is charging current from the controller to VCC capacitor during start up

IVCC_ Normal is supply current from VCC capacitor or auxiliary winding to the CoolSET™ during normal operation

Datasheet 9 of 42 V 2.2

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Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package

Functional description

3.2 Soft-start

As shown in Figure 6, the IC begins to operate with a soft-start at time ton. The switching stresses on the power

MOSFET, diode and transformer are minimized during soft-start. The soft-start implemented in ICE5xRxxxxAG is

a digital time-based function. The preset soft-start time is tSS (12 ms) with 4 steps. If not limited by other

functions, the peak voltage on CS pin will increase step by step from 0.3 V to VCS_N (0.8 V) finally. The normal

feedback loop will take over the control when the output voltage reaches its regulated value.

Figure 6 Maximum current sense voltage during soft start

3.3 Normal operation

The PWM controller during normal operation consists of a digital signal processing circuit including regulation

control and an analog circuit including a current measurement unit and a comparator. Details about the full

operation of the CoolSET™ in normal operation are illustrated in the following paragraphs.

3.3.1 PWM operation and peak current mode control

3.3.1.1 Switch-on determination

The power MOSFET turn-on is synchronized with the internal oscillator with a switching frequency fSW that

corresponds to the voltage level VFB (see Figure 8).

3.3.1.2 Switch-off determination

In peak current mode control, the PWM comparator monitors voltage V1 (see Figure 4) which is the

representation of the instantaneous current of the power MOSFET. When V1 exceeds VFB, the PWM comparator

sends a signal to switch off the GATE of the power MOSFET. Therefore, the peak current of the power MOSFET is

controlled by the feedback voltage VFB (see Figure 7).

At switch on transient of the power MOSFET, a voltage spike across RCS can cause V1 to increase and exceed VFB.

To avoid a false switch off, the IC has a blanking time tCS_LEB before detecting the voltage across RCS to mask the

voltage spike. Therefore, the minimum turn on time of the power MOSFET is tCS_LEB.

For some reason that the voltage level at V1 takes long time to exceed VFB, the IC has implemented a maximum

duty cycle control to force the power MOSFET to switch off when DMAX = 0.75 is reached.

Datasheet 10 of 42 V 2.2

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Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package

Functional description

Figure 7 Pulse width modulation

3.3.2 Current sense

The power MOSFET current generates a voltage VCS across the current sense resistor RCS connected between the

CS pin and the GND pin. VCS is amplified with gain GPWM, then, added with an offset VPWM to become V1 as

described below in below equation 3.



   

(2)



 

    



(3)

where, VCS : CS pin voltage

ID : power MOSFET current

RCS : resistance of the current sense resistor

V1 : voltage level compared to VFB as described in section 3.3.1.2

GPWM : PWM-OP gain

VPWM : offset for voltage ramp

Datasheet 11 of 42 V 2.2

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Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package

Functional description

3.3.3 Frequency reduction

Frequency reduction is implemented in ICE5xRxxxxAG to achieve a better efficiency during the light load. At

light load, the reduced switching frequency FSW improves efficiency by reducing the switching loses.

When load decreases, VFB decreases as well. FSW is dependent on the VFB as shown in Figure 8. Therefore, FSW

decreases as the load decreases.

Typically, FSW at high load is 100 kHz/ 125 kHz and starts to decrease at VFB = 1.7V. There is no further frequency

reduction once it reached the fOSCx_MIN even the load is further reduced.

VFB

fSW(VFB)

1.35 V

1.7 V VFB_OLP

2.73 V

fOSC2_MIN / fOSC4_MIN

53 kHz / 43 kHz

fOSC2 / fOSC4

125 kHz / 100 kHz

VCS (VFB)

VCS_N

0.80 V

VFB_EBxP

0.93 / 1.03 V

VCS_BHP / VCS_BLP

0.27 V /0.22 V

fOSC2_ABM / fOSC4_ABM

103 kHz / 83 kHz

0.5 V

No B M

Fsw

Vcs

Figure 8 Frequency reduction curve

3.3.4 Slope compensation

ICE5xRxxxxAG can operate at Continuous Conduction Mode (CCM). At CCM operation, duty cycle greater than

50% may generate a sub-harmonic oscillation. To avoid the sub-harmonic oscillation, slope compensation is

added to VCS pin when the gate of the power MOSFET is turned on for more than 40% of the switching cycle

period. The relationship between VFB and the VCS for CCM operation is described in below equation 4:



  

    

    󰇛   󰇜

(4)

where, TON : gate turn on time of the power MOSFET

MCOMP : slope compensation rate

TPERIOD : switching cycle period

Slope compensation circuit is disabled and no slope compensation is added into the VCS pin during active burst

mode to save the power consumption.

Datasheet 12 of 42 V 2.2

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Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package

Functional description

3.3.5 Oscillator and frequency jittering

The oscillator generates a frequency of 100 kHz/ 125 kHz with frequency jittering of ±4% at a jittering period of

TJITTER (4 ms). The frequency jittering helps to reduce conducted EMI.

A capacitor, a current source and current sink which determine the frequency are integrated. The charging and

discharging current of the implemented oscillator capacitor are internally trimmed in order to achieve a highly

accurate switching frequency.

Once the soft-start period is over and when the IC goes into normal operating mode, the frequency jittering is

enabled. There is also frequency jittering during frequency reduction.

3.3.6 Modulated gate drive

The drive-stage is optimized for EMI consideration. The switch on speed is slowed down before it reaches the

CoolMOS™ turn on threshold. That is a slope control of the rising edge at the output of driver (see Figure 9).

Thus the leading switch spike during turn on is minimized.

Figure 9 Gate rising waveform

3.4 Peak current limitation

There is a cycle by cycle peak current limitation realized by the current limit comparator to provide primary

over-current protection. The primary current generates a voltage VCS across the current sense resistor RCS

connected between the CS pin and the GND pin. If the voltage VCS exceeds an internal voltage limit VCS_N, the

comparator immediately turns off the gate drive.

The primary peak current IPEAK_PRI can be calculated as below:

  

 



(5)

To avoid mistriggering caused by MOSFET switch on transient voltage spikes, a leading edge blanking time

(tCS_LEB) is integrated in the current sensing path.

3.4.1 Propagation delay compensation

In case of overcurrent detection, there is always a propagation delay from sensing the VCS to switching the

power MOSFET off. An overshoot on the peak current Ipeak caused by the delay depends on the ratio of dI/dt of

the primary current (see Figure 10).

Datasheet 13 of 42 V 2.2

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Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package

Functional description

Figure 10 Current limiting

The overshoot of Signal2 is larger than Signal1 due to the steeper rising waveform. This change in the slope is

depending on the AC input voltage. Propagation delay compensation is integrated to reduce the overshoot due

to dI/dt of the rising primary current. Thus the propagation delay time between exceeding the current sense

threshold VCS_N and the switching off of the power MOSFET is compensated over wide bus voltage range.

Current limiting becomes more accurate which will result in a minimum difference of overload protection

triggering power between low and high AC line input voltage.

Under CCM operation, the same VCS do not result in the same power. In order to achieve a close overload

triggering level for CCM, ICE5xRxxxxAG has implemented a 2 compensation curve as shown Figure 11. One of

the curve is used for TON greater than 0.40 duty cycle and the other is for lower than 0.40 duty cycle.

Figure 11 Dynamic voltage threshold VCS_N

Similarly, the same concept of propagation delay compensation is also implemented in ABM with reduced

level. With this implementation, the entry and exit burst mode power can be close between low and high AC

line input voltage.

Datasheet 14 of 42 V 2.2

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Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package

Functional description

3.5 Active Burst Mode (ABM) with selectable power level

At light load condition, the IC enters ABM operation to minimize the power consumption. Details about ABM

operation are explained in the following paragraphs.

3.5.1 Entering ABM operation

The sytem will enter into ABM operation when two conditions below are met:

 the FB voltage is lower than the threshold of VFB_EBLP/VFB_EBHP depending on burst configuration option setup

 and a certain blanking time tFB_BEB

Once all of these conditions are fulfilled, the ABM flip-flop is set and the controller enters ABM operation. This

multi-condition determination for entering ABM operation prevents mis-triggering of entering ABM operation,

so that the controller enters ABM operation only when the output power is really low.

3.5.2 During ABM operation

After entering ABM, the PWM section will be inactive making the VOUT start todecrease. As the VOUT decreases, VFB

rises. Once VFB exceeded VFB_BOn, the internal circuit is again activated by the internal bias to start with the

switching.

If the PWM is still operating and the output load is still low, VOUT increases and VFB signal starts to decrease.

When VFB reaches the low threshold VFB_BOff, the internal bias is reset again and the PWM section is disabled with

no switching until VFB increases back to exceed VFB_BOn threshold.

In ABM, VFB is like a sawtooth waveform swinging between VFB_BOff and VFB_BOn shown in Figure 12.

During ABM, the switching frequency fOSCx_ABM is 83 kHz for 100 kHz version and 103 kHz for 125 kHz version IC.

The peak current IPEAK_ABMof the power MOSFET is defined by:

   

 



(6)

where VCS_BxP is the peak current limitation in ABM

3.5.3 Leaving ABM operation

The FB voltage immediately increases if there is a sudden increase in the output load. When VFB exceeds VFB_LB, it

will leave ABM and the peak current limitation trhreshold voltage will return back to VCS_N immediately.

Datasheet 15 of 42 V 2.2

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Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package

Functional description

Figure 12 Signals in Active Burst Mode

VFB_EBHP/VFB_EBLP

VFB_BOn

VFB_LB

VFB

VCS_BHP/VCS_BLP

VCS_N

VCS

VVCC_off

VVC C

VFB_BOff

Current limit level during Active Burst Mode

Blanking Window (tFB_BEB)

Leaving Active Burst Mode

Entering Active Burst Mode

Burst Mode Operation

Max. Ripple < 1%

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Functional description

3.5.4 ABM configuration

The burst mode entry level can be selected by changing the different resistance RSel at FB pin. There are 3

configuration options depending on RSel which corresponds to the options of no ABM (Option 1), low range of

ABM power (Option 2) and high range of ABM power (Option 3). The table below shows the control logic for the

entry and exit level with the FB voltage.

Table 3 ABM configuration option setup

Option

RSel

VFB

VCS_BxP

Entry level

Exit level

VFB_EBxP

VFB_LB

<470 kΩ

VFB < VFB_P_BIAS1

No ABM

720 kΩ ~ 790 kΩ

VFB_P_BIAS1<VFB<VFB_P_BIAS2

0.22V

0.93 V

2.73 V

3(Default)

>1210 kΩ

VFB > VFB_P_BIAS2

0.27V

1.03 V

2.73 V

During IC first startup, the controller preset the ABM selection to Option 3, the FB resistor (RFB) is turned off by

internal switch S2 (see Figure 13)and a current source Isel is turned on instead.From VCC= 4.44 V to VCC on

threshold, the FB pin will start to charge resistor RSel with current ISel to a certain voltage level. When VCC reaches

VCC on threshold, the FB voltage is sensed. The burst mode option is then chosen according to the FB voltage

level. After finishing the selection, any change on the FB level will not change the burst mode option and the

current source (Isel) is turned off while the FB resistor (RFB) is connected back to the circuit (Figure 13).

Figure 13 ABM detect and adjust

3.6 Non-isolated/isolated configuration

ICE5xRxxxxAG has a VERR Pin, which is connected to the input of an integrated error amplifier to support non-

isolated flyback application (see Figure 2). When VCC is charging and before reaching the VCC on threshold, a

current source IERR_P_BIAS from VERR pin together with RF1 and RF2 will generate a voltage across it. If VERR voltage

is more than VERR_P_BIAS (0.2 V), non-isolated configuration is selected, otherwise, isolated configuration is

selected. In isolated configuration, the error amplifier output is disconnected from the FB pin.

In case of non-isolated configuration, the voltage divider RF1 and RF2 is used to sense the output voltage and

compared with the internal reference voltage VERR_REF. The difference between the sensed voltage and the

reference voltage is converted as an output current by the error amplifier. The output current will

charge/discharge the resistor and capacitor network connected at the FB pin for the loop compensation.

Datasheet 17 of 42 V 2.2

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Functional description

3.7 Protection functions

The ICE5xRxxxxAG provides numerous protection functions which considerably improve the power supply

system robustness, safety and reliability. The following table summarizes these protection functions and the

corresponding protection mode whether as a non switch auto restart, auto restart or odd skip auto restart

mode. Refer to Figure 14, Figure 15 and Figure 16 for the waveform illustration of protection modes.

Table 4 Protection functions

Protection Functions

Normal Mode

Burst Mode

Protection Mode

Burst ON

Burst OFF

Line over voltage

√

Non switch auto restart

VCC over voltage

√

NA1

Odd skip auto restart

VCC under voltage

√

Auto restart

Overload/ open loop

√

NA1

Odd skip auto restart

Over temperature

√

Non switch auto restart

CS short to GND

√

NA1

Odd skip auto restart

VCC short to GND

√

No startup

3.7.1 Line over voltage

The AC Line Over Voltage Protection (LOVP) is detected by sensing bus capacitor voltage through VIN pin via

voltage divider resistors, Rl1 and Rl2 (Figure 1). Once VVIN voltage is higher than the line over voltage threshold

(VVIN_LOVP), the controller enters into protection mode until VVIN is lower than VVIN_LOVP. This protection can be

disabled by connecting VIN pin to GND.

3.7.2 VCC over/under voltage

During operation, the VCC voltage is continuously monitored. If VCC is either below VVCC_OFF for 50 µs (tVCC_OFF_B) or

above VVCC_OVP for 55 µs (tVCC_OVP_B), the power MOSFET is kept switch off. After the VCC voltage falls below the

threshold VVCCoff, the new start up sequence is activated. The VCC capacitor is then charged up. Once the voltage

exceeds the threshold VVCC_ON, the IC begins to operate with a new soft-start.

3.7.3 Overload/ open loop

In case of open control loop or output overload, the FB voltage will be pulled up. When VFB exceeds VFB_OLP after

a blanking time of tFB_OLP_B, the IC enters odd skip auto restart mode. The blanking time enables the converter to

provide a peak power in case the increase in VFB is due to a sudden load increase.

3.7.4 Over temperature

If the junction temperature of controller exceeds Tjcon_OTP, the IC enters into Over Temperature Protection (OTP)

auto restart mode. The IC has also implemented with a 40 °C hysteresis. That means the IC can only be recovered

from OTP when the controller junction temperature is dropped 40 °C lower than the over temperature trigger

point.

Not Applicable

Datasheet 18 of 42 V 2.2

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Functional description

3.7.5 CS short to GND

If the voltage at the current sense pin is lower than the preset threshold VCS_STG with certain blanking time

tCS_STG_B for three consecutive pulses during on-time of the power switch, the IC enters CS short to GND

protection.

3.7.6 VCC short to GND

To limit the power dissipation of the startup circuit at VCC short to GND condition, the VCC charging current is

limited to a minimum level of IVCC_ Charge1. With such low current, the power loss of the IC is limited to prevent

overheating.

3.7.7 Protection modes

All the protections are in auto restart mode with a new soft start sequence. The three auto restart modes are

illustrated in the following figures.

VCC_OFF

VCS

VVCC

No switching

Fault

detected

Fault released

Switching start at the

following restart cycle

VCC_ON

Start up and detect at

every charging cycle

Figure 14 Non switch auto restart mode

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Functional description

VCC_OFF

VCS

VVCC

Fault

detected

Fault released

Switching start at the

following restart cycle

VCC_ON

Start up and detect at every

charging cycle

Figure 15 Auto restart mode

VCC_OFF

VCS

VVCC

Fault

detected

Fault released

Switching start at the

following even restart

cycle

VCC_ON

Start up and detect at

every even charging

cycle

No detect No detect

Figure 16 Odd skip auto restart

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Electrical characteristics

4 Electrical characteristics

Attention: All voltages are measured with respect to ground (Pin 12). The voltage levels are valid if other

ratings are not violated.

4.1 Absolute maximum ratings

Attention: Stresses above the maximum values listed here may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device

reliability. Maximum ratings are absolute ratings; exceeding any one of these values may cause

irreversible damage to the integrated circuit. For the same reason, make sure that any capacitor

that will be connected to pin 11 (VCC) is discharged before assembling the application circuit.

Ta=25 °C unless otherwise specified.

Table 5 Absolute maximum ratings

Parameter

Symbol

Limit Values

Unit

Note / Test Condition

Min.

Max.

Drain Voltage

ICE5xRxx70AG

ICE5xRxx80AG

VDRAIN

700

800

Tj = 25 °C

Pulse drain current

ICE5AR4770AG

ICE5GR4780AG

ICE5GR2280AG

ICE5GR1680AG

ICE5AR0680AG

ID,Pulse

2.21

2.61

5.82

Avalanche energy, repetitive, tAR limited

by max. TJ=150 °C and TJ,Start = 25 °C

ICE5AR4770AG

ICE5GR4780AG

ICE5GR2280AG

ICE5GR1680AG

ICE5AR0680AG

EAR

0.02

0.05

0.07

0.22

ID=0.14 A, VDD=50 V

ID=0.20 A, VDD=50 V

ID=0.40 A, VDD=50 V

ID=0.60 A, VDD=50 V

ID=1.80 A, VDD=50 V

Avalanche current, repetitive,tAR limited

by max. TJ=150 °C and TJ,Start = 25 °C

ICE5AR4770AG

ICE5GR4780AG

ICE5GR2280AG

ICE5GR1680AG

ICE5AR0680AG

IAR

0.14

0.20

0.40

0.60

1.80

VCC Supply Voltage

VCC

-0.3

27.0

GATE Voltage

VGATE

-0.3

27.0

Pulse width tP limited by Tj,max

Pulse width tP = 20 µs and limited by Tj,max

Datasheet 21 of 42 V 2.2

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Electrical characteristics

FB Voltage

VFB

-0.3

3.6

VERR Voltage

VERR

-0.3

3.6

CS Voltage

VCS

-0.3

3.6

VIN Voltage

VIN

-0.3

3.6

Maximum DC current on any pin

-10.0

10.0

Except DRAIN and CS pin

ESD robustness HBM

VESD_HBM

2000

According to EIA/JESD22

ESD robustness CDM

VESD_CDM

500

Junction temperature range

-40

150

°C

Controller & CoolMOS

Storage Temperature

TSTORE

-55

150

°C

Thermal Resistance (Junction- Ambient)

ICE5AR4770AG

ICE5GR4780AG

ICE5GR2280AG

ICE5GR1680AG

ICE5AR0680AG

RthJA

104

105

K/W

Setup according to the JEDEC

standard JESD51 and using

minimum drain pin copper

area in a 2 oz copper single

sided PCB

4.2 Operating range

Note: Within the operating range, the IC operates as described in the functional description.

Table 6 Operating range

Parameter

Symbol

Limit Values

Unit

Remark

Min.

Max.

VCC Supply Voltage

VVCC

VVCC_OFF

VVCC_OVP

Junction Temperature of

controller

TjCon_op

-40

TjCon_OTP

˚C

Max value limited due to OTP

of controller chip

Junction Temperature of CoolMOS

TjCoolMOS_op

-40

150

˚C

4.3 Operating conditions

Note: The electrical characteristics involve the spread of values within the specified supply voltage and

junction temperature range TJ from – 40 °C to 125 °C. Typical values represent the median values,

which are related to 25 °C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed.

Table 7 Operating conditions

Parameter

Symbol

Limit Values

Unit

Note / Test Condition

Min.

Typ.

Max.

VCC Charge Current

IVCC_Charge1

-0.35

-0.20

-0.09

VVCC=0 V, RStartUp=50 MΩ and

VDRAIN=90 V

IVCC_Charge2

-3.2

VVCC=3 V, RStartUp=50 MΩ and

VDRAIN=90 V

IVCC_Charge3

-5

-3

-1

VVCC=15 V, RStartUp=50 MΩ

and VDRAIN=90 V

Current Consumption, Startup Current

IVCC_Startup

0.25

VVCC=15 V

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Electrical characteristics

Current Consumption, Normal

IVCC_Normal

0.9

IFB=0 A (No gate switching)

Current Consumption, Auto Restart

IVCC_AR

410

µA

Current Consumption, Burst Mode –

Isolated

IVCC_Burst

Mode_ISO

0.54

Current Consumption, Burst Mode –

Non-Isolated

IVCC_Burst

Mode_NISO

0.61

VCC Turn-on Threshold Voltage

VVCC_ON

15.3

16.0

16.5

VCC Turn-off Threshold Voltage

VVCC_OFF

9.4

10.0

10.4

VCC Short Circuit Protection

VVCC_SCP

1.1

1.9

VCC Turn-off blanking

tVCC_OFF_B

µs

4.4 Internal voltage reference

Table 8 Internal voltage reference

Parameter

Symbol

Limit Values

Unit

Note / Test Condition

Min.

Typ.

Max.

Internal Reference Voltage

VREF

3.20

3.30

3.39

Measured at pin FB IFB=0 A

4.5 PWM section

Table 9 PWM section

Parameter

Symbol

Limit Values

Unit

Note / Test

Condition

Min.

Typ.

Max.

Fixed Oscillator Frequency –

125 kHz

fOSC1

117

125

133

k H z

fOSC2

119

125

131

k H z

Tj = 25 °C

Fixed Oscillator Frequency –

100 kHz

fOSC3

100

108

k H z

fOSC4

100

106

k H z

Tj = 25 °C

Fixed Oscillator Frequency –

125 kHz (Active Burst Mode)

fOSC2_ABM

103

114

k H z

Tj = 25 °C

Fixed Oscillator Frequency –

100 kHz (Active Burst Mode)

fOSC4_ABM

k H z

Tj = 25 °C

Fixed Oscillator Frequency –

125 kHz (Minimum Fsw)

fOSC2_MIN

k H z

Tj = 25 °C

Fixed Oscillator Frequency –

100 kHz (Minimum Fsw)

fOSC4_MIN

k H z

Tj = 25 °C

Frequency Jittering Range

FJITTER

+/- 4

Tj = 25 °C

Frequency Jittering period

TJITTER

Tj = 25 °C

Maximum Duty Cycle

DMAX

Feedback Pull-Up Resistor

RFB

kΩ

PWM-OP Gain

GPWM

1.91

2.03

2.16

Offset for Voltage Ramp

VPWM

0.42

0.50

0.58

Slope Compensation rate –

125 kHz

MCOMP

52.5

61.0

68.0

m V / μ s

VCS=0 V

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Electrical characteristics

Slope Compensation rate -

100 kHz

MCOMP

m V / μ s

Vcs=0 V

4.6 Error amplifier

Table 10 Error amplifier

Parameter

Symbol

Values

Unit

Note / Test Condition

Min.

Typ.

Max.

Transconductance

GERR_M

2.14

2.80

3.44

m A / V

Transconductance – Burst Mode

GERR_BM

6.9

9.2

11.6

m A / V

Error Amplifier Source Current

IERR_SOURCE

150

223

μA

Error Amplifier Sink Current

IERR_SINK

150

223

μA

Error Amplifier Reference Voltage

VERR_REF

1.76

1.80

1.84

Error Amplifier Output Dynamic

Range of Transconductance

VERR_DYN

0.05

3.15

Error Amplifier Mode Bias Current

IERR_P_BIAS

9.5

14.0

18.5

μA

Error Amplifier Mode Threshold

VERR_P_BIAS

0.16

0.20

0.24

4.7 Current sense

Table 11 Current sense

Parameter

Symbol

Limit Values

Unit

Note / Test Condition

Min.

Typ.

Max.

Peak current limitation in normal

operation

VCS_N

0.72

0.80

0.88

dvsense/dt = 0.41V/ μs

Peak current limitation in normal

operation, 15% of TON

VCS_N15

0.74

0.79

0.84

Leading Edge Blanking time

tCS_LEB

220

365

Peak Current Limitation in Active

Burst Mode - High Power

VCS_BHP

0.23

0.27

0.31

Peak Current Limitation in Active

Burst Mode - Low Power

VCS_BLP

0.18

0.22

0.26

4.8 Soft start

Table 12 Soft start

Parameter

Symbol

Limit Values

Unit

Note / Test Condition

Min.

Typ.

Max.

Soft-Start time

tSS

7.3

12.0

Soft-start time step

tSS_S1

CS peak voltage at first step of soft

start

VSS11

0.30

CS peak voltage

The parameter is not subjected to production test - verified by design/characterization

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Electrical characteristics

Step increment of CS peak voltage

in soft start

VSS_S1

0.15

CS peak voltage

4.9 Active Burst Mode

Table 13 Active Burst Mode

Parameter

Symbol

Limit Values

Unit

Note / Test Condition

Min.

Typ.

Max.

Charging current to select burst

mode

Isel

2.5

3.0

3.5

µA

Burst mode selection reference

voltage Threshold

VFB_P_BIAS1

1.65

1.73

1.80

Burst mode selection reference

voltage Threshold

VFB_P_BIAS2

2.76

2.89

3.01

Feedback voltage for entering

ABM for high power

VFB_EBHP

0.98

1.03

1.08

Feedback voltage for entering

ABM for low power

VFB_EBLP

0.88

0.93

0.98

Blanking time for entering

Active Burst Mode

tFB_BEB

Feedback voltage for leaving

Active Burst Mode

VFB_LB

2.63

2.73

2.83

Feedback voltage for burst-on

– Isolated Case

VFB_Bon_ISO

2.26

2.35

2.45

Feedback voltage for burst-off

– Isolated Case

VFB_BOff_ISO

1.88

2.00

2.05

Feedback voltage for burst-on

– Non-Isolated Case

VFB_Bon_NISO

1.88

1.95

2.05

Feedback voltage for burst-off

– Non-Isolated Case

VFB_BOff_NISO

1.50

1.55

1.64

4.10 Line over voltage protection

Table 14 Line OVP

Parameter

Symbol

Limit Values

Unit

Note / Test Condition

Min.

Typ.

Max.

Line Over Voltage threshold

VVIN_LOVP

2.75

2.85

2.95

Line Over Voltage Blanking

tVIN_LOVP_B

250

µs

The parameter is not subjected to production test - verified by design/characterization

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Electrical characteristics

4.11 VCC over voltage protection

Table 15 VCC over voltage protection

Parameter

Symbol

Limit Values

Unit

Note / Test Condition

Min.

Typ.

Max.

VCC Over Voltage threshold

VVCC_OVP

24.0

25.5

27.0

VCC Over Voltage blanking

tVCC_OVP_B

µs

4.12 Overload protection

Table 16 Overload protection

Parameter

Symbol

Limit Values

Unit

Note / Test Condition

Min.

Typ.

Max.

Over Load Detection threshold for

OLP protection at FB pin

VFB_OLP

2.63

2.73

2.83

Over Load Protection Blanking

Time

tFB_OLP_B

4.13 Thermal protection

Table 17 Thermal protection

Parameter

Symbol

Limit Values

Unit

Note / Test Condition

Min.

Typ.

Max.

Over temperature protection

Tjcon_OTP1

129

140

150

°C

Junction temperature of

the controller chip (not the

CoolMOS™ chip)

Over temperature Hysteresis

TjHYS_OTP

°C

Over temperature Blanking Time

Tjcon_OTP_B

µs

4.14 CS short to GND protection

Table 18 CS short to GND protection

Parameter

Symbol

Limit Values

Unit

Note / Test Condition

Min.

Typ.

Max.

CS Short to Gnd Protection

VCS_STG

0.06

0.10

0.15

CS Short to Gnd Consecutive

Trigger

PCS_STG

cycle

CS Short to Gnd Sample period

tCS_STG_SAM

tPERIOD *

0.36

tPERIOD *

0.4

tPERIOD *

0.44

µs

The parameter is not subjected to production test - verified by design/characterization

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Electrical characteristics

4.15 CoolMOS™ section

Table 19 ICE5xRxxxxAG

Parameter

Symbol

Limit Values

Unit

Note / Test Condition

Min.

Typ.

Max.

Drain Source Breakdown Voltage

ICE5xRxx70AG

ICE5xRxx80AG

V(BR)DSS

700

800

Tj = 25°C

Drain Source On-Resistance (inclusive of low

side MOSFET)

ICE5AR4770AG

ICE5GR4780AG

ICE5GR2280AG

ICE5GR1680AG

ICE5AR0680AG

RDSon

4.73

8.731

4.13

8.691

2.13

4.311

1.53

3.011

0.71

1.271

5.18

4.85

2.35

1.75

0.80

Ω

Tj = 25°C

Tj=125°C at ID =0.4A

Tj = 25°C

Tj=125°C at ID =0.4A

Tj = 25°C

Tj=125°C at ID =1A

Tj = 25°C

Tj=125°C at ID =1.4A

Tj = 25°C

Tj=125°C at ID =2A

Effective output capacitance, energy related1

ICE5AR4770AG

ICE5GR4780AG

ICE5GR2280AG

ICE5GR1680AG

ICE5AR0680AG

Co(er)

3.4

VGS=0V, VDS=0~480V

VGS=0V, VDS=0~500V

Rise Time

trise2

Fall Time

tfall2

The parameter is not subjected to production test - verified by design/characterization

Measured in a typical flyback converter application

Datasheet 27 of 42 V 2.2

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CoolMOS™ performance characteristics

5 CoolMOS™ performance characteristics

Figure 17 Safe Operating Area (SOA) curve for ICE5AR4770AG

Figure 18 Safe Operating Area (SOA) curve for ICE5GR4780AG

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CoolMOS™ performance characteristics

Figure 19 Safe Operating Area (SOA) curve for ICE5GR2280AG

Figure 20 Safe Operating Area (SOA) curve for ICE5GR1680AG

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CoolMOS™ performance characteristics

Figure 21 Safe Operating Area (SOA) curve for ICE5AR0680AG

Figure 22 Power dissipation of ICE5AR4770AG; Ptot=f(Ta), (Maximum ratings as given in section 4.1 must

not be exceeded)

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CoolMOS™ performance characteristics

Figure 23 Power dissipation of ICE5GR4780AG; Ptot=f(Ta), (Maximum ratings as given in section 4.1 must

not be exceeded)

Figure 24 Power dissipation of ICE5GR2280AG; Ptot=f(Ta), (Maximum ratings as given in section 4.1 must

not be exceeded)

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CoolMOS™ performance characteristics

Figure 25 Power dissipation of ICE5GR1680AG; Ptot=f(Ta), (Maximum ratings as given in section 4.1 must

not be exceeded)

Figure 26 Power dissipation of ICE5AR0680AG; Ptot=f(Ta), (Maximum ratings as given in section 4.1 must

not be exceeded)

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CoolMOS™ performance characteristics

Figure 27 Drain-source breakdown voltage ICE5xRxx70AG; VBR(DSS)=f(TJ), ID=1 mA

Figure 28 Drain-source breakdown voltage ICE5xRxx80AG; VBR(DSS)=f(TJ), ID=1 mA

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CoolMOS™ performance characteristics

Figure 29 Typical CoolMOS™ capacitances of ICE5AR4770AG (C=f(VDS);VGS=0 V; f=1 MHz)

Figure 30 Typical CoolMOS™ capacitances of ICE5GR4780AG (C=f(VDS);VGS=0 V; f=250 kHz)

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CoolMOS™ performance characteristics

Figure 31 Typical CoolMOS™ capacitances of ICE5GR2280AG (C=f(VDS);VGS=0 V; f=250 kHz)

Figure 32 Typical CoolMOS™ capacitances of ICE5GR1680AG (C=f(VDS);VGS=0 V; f=250 kHz)

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CoolMOS™ performance characteristics

Figure 33 Typical CoolMOS™ capacitances of ICE5AR0680AG (C=f(VDS);VGS=0 V; f=250 kHz)

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Output power curve

6 Output power curve

The calculated output power curves versus ambient temperature are shown below. The curves are derived

based on a typical DCM/CCM flyback in an open frame design setting the maximum TJ of the integrated

CoolMOS™ at 125 °C, using minimum drain pin copper area in a 2 oz copper single sided PCB and steady state

operation only (no design margins for abnormal operation modes are included).

The output power figure is for selection purpose only. The actual power can vary depending on a particular

design. In a power supply system, appropriate thermal design margins must be considered to make sure that

the operation of the device is within the maximum ratings given in section 4.1.

Figure 34 Output power curve of ICE5AR4770AG

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Output power curve

Figure 35 Output power curve of ICE5GR4780AG

Figure 36 Output power curve of ICE5GR2280AG

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Output power curve

Figure 37 Output power curve of ICE5GR1680AG

Figure 38 Output power curve of ICE5AR0680AG

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Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package

Outline dimension

7 Outline dimension

Figure 39 PG-DSO-12

Datasheet 40 of 42 V 2.2

2018-03-02

Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package

Marking

8 Marking

Figure 40 Marking of PG-DSO-12

Datasheet 41 of 42 V 2.2

2018-03-02

Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package

Revision history

Document

version

Date of release

Description of changes

V 2.0

21 Nov 2017

First release

V 2.1

27 Feb 2018

Page 1

Product validation text content revised

V 2.2

2 Mar 2018

Page 21, Table 5

The symbol of parameter VIN voltage changed from VCS to VIN

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

Edition 2018-03-02

ICE5xRxxxxAG

Published by

Infineon Technologies AG

81726 Munich, Germany

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document?

Email: erratum@infineon.com

Document reference

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