General Description
The MAX5360/MAX5361/MAX5362 are low-cost, 6-bit
digital-to-analog converters (DACs) in miniature 5-pin
SOT23 packages with a simple 2-wire serial interface
that allows communication with multiple devices. The
MAX5360 has an internal +2V reference and operates
from a +2.7V to +3.6V supply. The MAX5361 has an
internal +4V reference and operates from a +4.5V to
+5.5V supply. The MAX5362 operates over the full
+2.7V to +5.5V supply range and has an internal refer-
ence equal to 0.9 VDD.
The fast-mode I2C-compatible serial interface allows
communication at data rates up to 400kbps, minimizing
board space and reducing interconnect complexity in
many applications. Each device is available with one of
four factory-preset addresses (see
Selector Guide
).
The MAX5360/MAX5361/MAX5362 also include an out-
put buffer, a low-power shutdown mode, and a power-
on reset that ensures the DAC outputs are at zero when
power is initially applied. In shutdown mode, the supply
current is reduced to less than 1µA and the output is
pulled down with a 10kΩresistor to GND.
The MAX5360/MAX5361/MAX5362 are available in
miniature 5-pin SOT23 packages.
Applications
Automatic Tuning (VCO)
Power Amplifier Bias Control
Programmable Threshold Levels
Automatic Gain Control
Automatic Offset Adjustment
Features
6-Bit Accuracy in a Tiny 5-Pin SOT23 Package
Wide +2.7V to +5.5V Supply Range (MAX5362)
1µA Shutdown Mode
Buffered Output Drives Resistive Loads
Low Glitch Power-On-Reset to Zero DAC Output
Fast I2C-Compatible Serial Interface
≤-5% Full-Scale Error (MAX5362)
≤1LSB (max) INL/DNL
Low 230µA max Supply Current
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
________________________________________________________________
Maxim Integrated Products
1
GND
SDAVDD
15SCLOUT
MAX5360
MAX5361
MAX5362
SOT23-5
TOP VIEW
2
34
PX.1/SCL
+2.7V TO +5.5V
PX.0/SDA
GND
μC
VDD
SCL
SDA
OUT
GND
VDD
MAX5362
Typical Operating Circuit
19-1785; Rev 2; 3/11
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
*See Selector Guide for address options.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration
Ordering Information
PART
MAX5360LEUK
MAX5360MEUK
MAX5360NEUK 0x64
0x62
0x60
ADDRESS REFERENCE
+2.0V
+2.0V
+2.0V ADNE
ADMY
ADMM
TOP
MARK
MAX5360PEUK 0x66 +2.0V ADMO
MAX5361LEUK 0x60 +4.0V ADMU
MAX5361MEUK 0x62 +4.0V ADNA
MAX5361NEUK 0x64 +4.0V ADNG
MAX5361PEUK 0x66 +4.0V ADMQ
MAX5362MEUK 0x62 0.9 x VDD ADNC
MAX5362NEUK 0x64 0.9 x VDD ADNI
MAX5362PEUK 0x66 0.9 x VDD ADMS
MAX5362LEUK 0x60 0.9 x VDD ADMW
Selector Guide
PART TEMP RANGE PIN-PACKAGE
MAX5360_EUK_ +T* -40°C to +85°C5 S OT23- 5
MAX5361_EUK_ +T* -40°C to +85°C5 S OT23- 5
MAX5362_EUK_ +T* -40°C to +85°C5 S OT23- 5
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 3.6V (MAX5360); VDD = 4.5V to 5.5V (MAX5361); VDD = 2.7V to 5.5V (MAX5362); RL=10kΩ, CL= 50pF, TA= TMIN to
TMAX, unless otherwise noted. Typical values are TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND..............................................................-0.3V to +6V
OUT to GND ...............................................-0.3V to (VDD + 0.3V)
SCL, SDA to GND.....................................................-0.3V to +6V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
5-Pin SOT23 (derate 7.1mW/°C above +70°C)...........571mW
Operating Temperature Range
MAX536__EUK-T ............................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Code = 0, all digital inputs from 0 to VDD
To 1/2LSB, 50kΩand 50pF load (Note 6)
Positive and negative
(Note 1)
VOUT = 0 to VDD, power-down mode
Code = 0, 0 to -100µA
MAX5360
Code = 63, MAX5360/MAX5361 (Note 4)
Code = 63
Guaranteed monotonic (Note 2)
Guaranteed monotonic (Note 2)
MAX5362 (Notes 2, 3)
Code = 63
CONDITIONS
nVs
2
Digital Feedthrough
µs20Output Settling Time
V/µs0.4Voltage Output Slew Rate
kΩ10Output Resistance
LSB
0.5
Output Load Regulation
1.8 2 2.2
ppm/°C
±10
Full-Scale Error Temperature
Coefficient
LSB±1INLIntegral Linearity Error
Bits6Resolution
±40
dB60Full-Scale Error Supply Rejection
% of Ideal
FS
5
Full-Scale Error 10
LSB±1DNLDifferential Linearity Error
mV±1 ±25VOS
Offset Error
dB60Offset Error Supply Rejection
3
UNITSMIN TYP MAXSYMBOLPARAMETER
From software shutdown
Code 31 to 32
µs50Wake-Up Time
nVs
40
Digital-Analog Glitch Impulse
(Note 2) ppm/°C
1
Offset Error Temperature
Coefficient
MAX5360/MAX5361
MAX5362
MAX5360/MAX5361
MAX5362
MAX5360/MAX5361
MAX5362
Code = 63, 0 to 100µA 0.5
MAX5361 3.6 4 4.4
MAX5362
V
0.850.90.95
VDD VDD VDD
REFInternal Reference (Note 5)
STATIC ACCURACY
DAC OUTPUT
DYNAMIC PERFORMANCE
MAX5360/MAX5361/MAX5362
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX5360); VDD = 4.5V to 5.5V (MAX5361); VDD = 2.7V to 5.5V (MAX5362); RL=10kΩ, CL= 50pF, TA= TMIN to
TMAX, unless otherwise noted. Typical values are TA= +25°C.)
MAX5361
MAX5360
VIH min to VIL max,
bus capacitance
10pF to 400pF
ISINK = 6mA
(Note 7)
ISINK = 3mA
MAX5362
No load, all digital inputs at 0 or VDD, code = 63
Shutdown mode
CONDITIONS
ns
250
tof
Output Fall Time
V
0 0.6
VOL
Output Low Voltage 0 0.4
ns050tSP
Pulse Width of Spike Suppressed
µA±10Ii
Input Leakage Current
4.5 5.5
2.7 3.6
pF10CIN
Input Capacitance
V0.05 VDD
Vhys
Input Hysteresis
V0.7 VDD
VIH
Input High Voltage
V0.3 VDD
VIL
Input Low Voltage
V
2.7 5.5
VDD
Supply Voltage
150 230 µA
1
IDD
Supply Current
UNITSMIN TYP MAXSYMBOLPARAMETER
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
_______________________________________________________________________________________ 3
ISINK = 3mA
ISINK = 6mA 250
POWER REQUIREMENTS
DIGITAL INPUTS (SCL, SDA)
DIGITAL OUTPUT (SDA) (open drain)
CONDITIONS
µs0.6tHIGH
High Period of the SCL Clock
µs1.3tLOW
Low Period of the SCL Clock
kHz
0 400
fSCL
SCL Clock Frequency
µs0.6tHD, STA
Hold Time (Repeated)
START Condition
µs1.3tBUF
Bus-Free Time Between a
STOP and a START Condition
UNITSMIN TYP MAXSYMBOLPARAMETER
TIMING CHARACTERISTICS
(VDD = 2.7V to 3.6V (MAX5360); VDD = 4.5V to 5.5V (MAX5361); VDD = 2.7V to 5.5V (MAX5362); RL=10kΩ, CL= 50pF, TA= TMAX to
TMIN, Figure 3, unless otherwise noted. Typical values are TA= +25°C.)
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX5360); VDD = 4.5V to 5.5V (MAX5361); VDD = 2.7V to 5.5V (MAX5362); RL=10kΩ, CL= 50pF, TA= TMAX to
TMIN, Figure 3, unless otherwise noted. Typical values are TA= +25°C.)
Data Hold Time tHD, DAT 0 0.9 µs
Data Setup Time tSU, DAT 100 ns
Rise Time of Both SDA and
SCL Signals tr300 ns
Fall Time of Both SDA and
SCL Signals tf
CONDITIONS
300 ns
Setup Time for STOP Condition tSU, STO 0.6 µs
Capacitive Load for Each
Bus Line Cb400 pF
µs0.6tSU, STA
Setup Time for a Repeated
START Condition
UNITSMIN TYP MAXSYMBOLPARAMETER
Note 1: Guaranteed from code 1 to code 63.
Note 2: The offset value extrapolated from the range over which the INL is guaranteed.
Note 3: MAX5362, tested at VDD = 5V ±10%.
Note 4: MAX5360, tested at VDD = 3V ±10%; MAX5361, tested at VDD = 5V ±10%.
Note 5: Actual output voltage at full scale is 63/64 VREF.
Note 6: Output settling time is measured by taking the code from code 1 to code 63, and from code 63 to code 1.
Note 7: Guaranteed by design.
-0.045
-0.020
-0.030
-0.025
-0.035
-0.040
-0.015
-0.010
-0.005
0
0.005
0.010
0.015
0.020
0.025
0.030
0 255075
INTEGRAL NONLINEARITY vs. CODE
MAX5360/1/2-01
CODE
INL (LSB)
0
-0.025
-0.050
2.5 4.03.0 3.5 4.5 5.0 5.5
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX5360/1/2-02
SUPPLY VOLTAGE (V)
INL (LSB)
0
-0.025
-0.050
-40 20-20 0 40 60 80 100
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX5360/1/2-03
TEMPERATURE (°C)
INL (LSB)
Typical Operating Characteristics
(VDD = 3V (MAX5360), VDD = 5V (MAX5361/MAX5362), TA= +25°C, unless otherwise noted.)
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
_______________________________________________________________________________________
5
-0.020
-0.010
-0.015
-0.005
0
0.005
0.010
0 255075
DIFFERENTIAL NONLINEARITY vs. CODE
MAX5360/1/2-04
CODE
DNL (LSB)
0
-0.015
-0.020
-0.010
-0.005
-0.025
2.5 4.03.0 3.5 4.5 5.0 5.5
DIFFERENTIAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX5360/1/2-05
SUPPLY VOLTAGE (V)
DNL (LSB)
0
-0.010
-0.015
-0.020
-0.005
-0.025
-40 20-20 0 40 60 80 100
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
MAX5360/1/2-06
TEMPERATURE
(
°C
)
DNL (LSB)
-0.20
-0.10
-0.15
-0.05
0
0.05
0.10
0.15
0 255075
TOTAL UNADJUSTED ERROR vs. CODE
MAX5360/1/2-07
CODE
TUE (LSB)
0
-0.25
-0.50
2.5 4.03.0 3.5 4.5 5.0 5.5
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX5360/1/2-08
SUPPLY VOLTAGE (V)
VOS (mV)
0
-0.25
-0.50
-40 20-20 0 40 60 80 100
OFFSET ERROR vs. TEMPERATURE
MAX5360/1/2-09
TEMPERATURE (°C)
VOS
Typical Operating Characteristics (continued)
(VDD = 3V (MAX5360), VDD = 5V (MAX5361/MAX5362), TA= +25°C, unless otherwise noted.)
0.75
0.25
0
-0.25
-0.50
0.50
-0.75
2.5 4.03.0 3.5 4.5 5.0 5.5
FULL-SCALE ERROR vs. TEMPERATURE
MAX5360/1/2-10
SUPPLY VOLTAGE (V)
FULL-SCALE ERROR (LSB)
1.2
0.4
0
-0.4
-0.8
0.8
-1.2
SC O ( )
MAX5361
MAX5360
MAX5362
NO LOAD
0.75
0.25
0
-0.25
-0.50
0.50
-0.75
1.2
0.4
0
-0.4
-0.8
0.8
-1.2
-40 20-20 0 40 60 80 100
FULL-SCALE ERROR vs. TEMPERATURE
MAX5360/1/2-11
TEMPERATURE (°C)
FULL-SCALE ERROR (LSB)
FULL-SCALE ERROR (%)
MAX5362
MAX5360
MAX5361
200
140
120
100
60
80
20
40
160
180
0
2.5 4.03.0 3.5 4.5 5.0 5.5
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5360/1/2-12
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (μA)
MAX5360
MAX5361
MAX5362
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
6 _______________________________________________________________________________________
160
150
145
140
135
155
130
-40 20-20 0 40 60 80 100
SUPPLY CURRENT vs. TEMPERATURE
MAX5360/1/2-13
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
MAX5361
MAX5362
MAX5360
160
150
145
140
135
155
130
024816 3240485664
SUPPLY CURRENT vs. CODE
MAX5360/1/2-14
CODE
SUPPLY CURRENT (μA)
MAX5361
VDD = 5V MAX5362
VDD = 5V
MAX5360
VDD = 3V
MAX5360
VDD = 5V
1.0
0.4
0.2
0.6
08
0
2.5 4.03.0 3.5 4.5 5.0 5.5
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5360/1/2-15
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (μA)
1.0
0.6
0.4
0.2
0.8
0
-40 20-20 0 40 60 80 100
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX5360/1/2-16
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
VDD = 5V
VDD = 3V
2.0
1.5
2.5
3.0
4.0
3.5
4.5
0
0.1
0.2
021436589710
OUTPUT LOAD REGULATION
MAX5360/1/2-17
LOAD CURRENT (mA)
A: MAX5361/MAX5362, VDD = 4.5V, FULL-SCALE OR SOURCI
B: MAX5360, FULL-SCALE, VDD = 2.7V SINKING, VDD = 5V S
C: MAX5360, FULL-SCALE, VDD = 2.7V, SOURCING
D: ZERO CODE, VDD = 2.7V, SINKING
E: ZERO CODE, VDD = 5.5V SINKING
VOUT FULL SCALE (V)
VOUT ZERO CODE (V)
A
B
C
D
E
4μs/div
OUTPUT VOLTAGE ON POWER-UP
MAX5360/1/2-18
OUT
50mV/div
VDD
2V/div
Typical Operating Characteristics (continued)
(VDD = 3V (MAX5360), VDD = 5V (MAX5361/MAX5362), TA= +25°C, unless otherwise noted.)
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
_______________________________________________________________________________________
7
Pin Description
NAME FUNCTION
1OUT DAC Voltage Output
2GND Ground
PIN
3 VDD Power-Supply Input
4SDA Serial Data Input
5SCL Serial Clock Input
10μs/div
MAX5360
OUTPUT VOLTAGE
EXITING SHUTDOWN
MAX5360/1/2-19
OUT
500mV/div
SDA
3V/div
1μs/div
MAX5360
OUTPUT VOLTAGE
ENTERING SHUTDOWN
MAX5360/1/2-20
OUT
500mV/div
SDA
3V/div
1μs/div
MAX5360
OUTPUT SETTLING FROM
1/4 FS TO 3/4 FS
MAX5360/1/2-21
OUT
0.5V/div
SDA
3V/div
1μs/div
MAX5360
OUTPUT SETTLING FROM
3/4 FS TO 1/4 FS
MAX5360/1/2-22
OUT
0.5V/div
SDA
3V/div
2μs/div
MAX5360
OUTPUT SETTLING
1/4LSB STEP-UP
MAX5360/1/2-23
OUT
20mV/div
AC-COUPLED
SDA
3V/div
0 x 7F TO 0 x 80
01111111 TO 10000000
MAX5360
OUTPUT SETTLING
1/4LSB STEP-DOWN
MAX5360/1/2-24
OUT
20mV/div
AC-COUPLED
SDA
3V/div
2μs/div
0 x 80 TO 0 x 7F
10000000 TO 01111111
Typical Operating Characteristics (continued)
(VDD = 3V (MAX5360), VDD = 5V (MAX5361/MAX5362), TA= +25°C, unless otherwise noted.)
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
8 _______________________________________________________________________________________
Detailed Description
The MAX5360/MAX5361/MAX5362 voltage-output, 6-bit
DACs offer full 6-bit performance with less than 1LSB
integral nonlinearity (INL) error and less than 1LSB dif-
ferential nonlinearity (DNL) error ensuring monotonic
performance. The devices use a simple two-wire, fast-
mode I2C-compatible serial interface that operates up
to 400kHz. The MAX5360/MAX5361/MAX5362 include
an internal reference, an output buffer, and low-current
shutdown mode, making them ideal for low-power,
highly integrated applications. Figure 1 shows the
devices’ functional diagram.
Analog Section
The MAX5360/MAX5361/MAX5362 employ a current-
steering DAC topology as shown in Figure 2. At the
core of the DAC is a reference voltage-to-current con-
verter (V/I) that generates a reference current. This cur-
rent is mirrored to 255 equally weighted current
sources. DAC switches control the outputs of these cur-
rent mirrors, so only the desired fraction of the total cur-
rent-mirror currents is steered to the DAC output. The
current is then converted to a voltage across a resistor,
and this voltage is buffered by the output buffer amplifier.
Output Voltage
Table 1 shows the relationship between the DAC code
and the analog output voltage. The 6-bit DAC code is
binary unipolar with 1LSB = (VREF / 64). The MAX5360/
MAX5361 have a full-scale output voltage of (+2V -
1LSB) and (+4V - 1LSB), respectively, set by the inter-
nal references. The MAX5362 has a full-scale output
voltage of (0.9 VDD - 1LSB). Each device accepts 8-bit
DAC codes, but the accuracy is guaranteed only for
6 bits.
Output Buffer
The DAC voltage output is an internally buffered unity-
gain follower that typically slews at ±0.4V/µs. The out-
put can swing from 0 to full scale. With a 1/4 FS to 3/4
FS output transition, the amplifier outputs typically settle
to 1/2LSB in less than 5µs when loaded with 10kΩin
parallel with 50pF. The buffer amplifiers are stable with
any combination of resistive loads >10kΩand capaci-
tive loads <50pF.
VREF
OUT
SW1 SW2 SW255
Figure 2. Current-Steering Topology
VDD
OUT
10k
GND
SDA
SCL
255
6 + 2
CURRENT-
STEERING
DAC
DATA LATCH
SERIAL INPUT
REGISTER
CONTROL
LOGIC
MAX5360
MAX5361
MAX5362
REF
Figure 1. Functional Diagram
Table 1. Unipolar Code Current
000001 (00) 0.9 VDD / 6462mV31mV
000000 (00) 000
100000 (00) 0.9 VDD / 22V1V
111111 (00) 0.9 VDD (63/64)4V (63/64)2V (63/64)
MAX5362
MAX5361
MAX5360
DAC CODE
6 BITS + 2 SUBBITS
OUTPUT VOLTAGE
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
_______________________________________________________________________________________ 9
Power-On Reset
The MAX5360/MAX5361/MAX5362 have a power-on
reset circuit to set the DAC’s output to 0 when VDD is
first applied or when VDD dips below 1.7V. This ensures
that unwanted DAC output voltages will not occur
immediately following a system startup, such as after a
loss of power. The output glitch on startup is typically
<50mV.
Shutdown Mode
The MAX5360/MAX5361/MAX5362 include a software-
controlled shutdown mode that reduces the supply cur-
rent to <1µA. All internal circuitry is disabled and an
internal 10kΩresistor is placed from OUT to GND to
ensure 0V at OUT while in shutdown. The device enters
shutdown in less than 5µs and exits shutdown in less
than 50µs.
Digital Section
Serial interface
The MAX5360/MAX5361/MAX5362 use a simple two-
wire serial interface requiring only two I/O lines (two-
wire bus) of a standard microprocessor (µP) port.
Figure 3 shows the timing diagram for signals on the 2-
wire bus.
The two bus lines (SDA and SCL) must be high when
the bus is not in use. The MAX5360/MAX5361/
MAX5362 are receive-only devices (slaves) and must
be controlled by a bus master device. Figure 4 shows a
typical application where multiple devices can be con-
nected to the bus provided they have different address
settings. External pullup resistors are not necessary on
these lines (when driven by push-pull drivers), though
the MAX5360/MAX5361/MAX5362 can be used in
applications where pullup resistors are required (such
as in I2C systems) to maintain compatibility with exist-
ing circuitry. The serial interface operates at SCL rates
up to 400kHz. The SDA state is allowed to change only
while SCL is low, with the exception of START and
STOP conditions as shown in Figure 5. Each transmis-
sion consists of a START condition sent by the bus
master device, followed by the MAX5360/MAX5361/
MAX5362’s preset slave address, a power-mode bit,
the DAC data (6 bits + 2 subbits), and finally, a STOP
SCL
SDA
tLOW
tHIGH
tF
tR
tHD, STA
tHD, DAT
tHD, STA
tSU, DAT tSU, STA
tBUF
tSU, STO
START CONDITIONSTOP CONDITIONREPEATED START CONDITIONSTART CONDITION
Figure 3. Two-Wire Serial Interface Timing Diagram
μC
SDA SCL
RS*
VDD
OFFSET ADJUSTMENT
THRESHOLD ADJUSTMENT
GAIN ADJUSTMENT
RS* IS OPTIONAL.
SCL
SDA
VDD
OUT
MAX5360M
2V REFERENCE
SCL
SDA
VDD
OUT
MAX5361N
4V REFERENCE
SCL
SDA
VDD
OUT
MAX5362P
VDD REFERENCE
Figure 4. Typical Application Circuit
MAX5360/MAX5361/MAX5362
condition (Figure 6). The bus is then free for another
transmission.
SDA’s state is sampled, and therefore must remain sta-
ble while SCL is high. Data is transmitted in 8-bit bytes.
Nine clock cycles are required to transfer each byte to
the MAX5360/MAX5361/MAX5362. Release SDA during
the 9th clock cycle as the selected device acknowl-
edges the receipt of the byte, by pulling SDA low dur-
ing this time. A series resistor on the SDA line may be
needed if the master’s output is forced high while the
selected device acknowledges (Figure 4).
Slave Address
The MAX5360/MAX5361/MAX5362 are available with
one of four preset slave addresses. Each address
option is identified by the suffix L, M, N, or P added to
the part number. The address is defined as the 7 most
significant bits (MSBs) sent by the master after a
START condition. The address options are 0x60, 0x62,
0x64, and 0x66 (left justified with LSB set to 0). The 8th
bit, typically used to define a write or read protocol,
sets the device’s power mode (SHDN); the device is
powered down when SHDN is set to 1. During a device
search routine, the MAX5360/MAX5361/MAX5362
acknowledge both options (SHDN = 0 or SHDN = 1)
but does not change its power state if a stop condition
(or restart) is issued immediately. The second byte
(DAC data) must be sent/received for the device to
update both power mode and DAC output.
DAC Data
The 6-bit DAC data is decoded as straight binary MSB
first with 1LSB = (VREF / 64) and converted into the cor-
responding analog voltage as shown in Table 1. Two
subbits complete the data byte; these 2 bits should be
set to zero since they are not tested to guaranteed-
monotonic performance.
After receiving the data byte, the MAX5360/MAX5361/
MAX5362 acknowledge its receipt and expect a STOP
condition, at which point the DAC output is updated.
The devices update the output and the power mode
only if the second byte is clocked in (SHDN = 0) or out
(SHDN = 1) of the device. When SHDN = 1, the master
will read all ones when clocking out a data byte. The
MAX5360/MAX5361/MAX5362 do not drive SDA except
for the acknowledge bit.
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
10 ______________________________________________________________________________________
SCL
SDA
START
CONDITION
STOP
CONDITION
132 465 798 10 1211 13 1514 16 1817
ACK
LSBMSBLSBMSB
011 0X0 XACKSHDN D6 D3D4 D2 D0D1 S1 S0
SLAVE ADDRESS BYTE DAC CODE
Figure 6. Complete Serial Transmission
SCL
SDA
START CONDITION STOP CONDITION
Figure 5. Start and Stop Conditions
I2C Compatibility
The MAX5360/MAX5361/MAX5362 are compatible with
existing I2C systems. SCL and SDA are high-imped-
ance inputs; SDA has an open drain that pulls the data
line low during the 9th clock pulse. Figure 7 shows a
typical I2C application. The communication protocol
supports the standard I2C 8-bit communications. The
general call address is ignored, and CBUS formats are
not supported. The MAX5360/MAX5361/MAX5362
address is compatible with the 7-bit I2C addressing
protocol only. No 10-bit formats are supported.
RESTART protocol is supported, but an immediate
STOP condition is necessary to update the DAC.
Applications Information
Digital Inputs and Interface Logic
The serial 2-wire interface has logic levels defined as
VOL = 0.3 x VDD and VOH = 0.7 x VDD. All of the inputs
include Schmitt-trigger buffers to accept slow-transition
interfaces. This means that optocouplers can interface
directly to the MAX5360/MAX5361/MAX5362 without
additional external logic. The digital inputs are compati-
ble with CMOS logic levels and must not be driven with
voltages higher than VDD.
Power-Supply Bypassing and Layout
Careful PC board layout is important for best system
performance. To reduce crosstalk and noise injection,
keep analog and digital signals separate. Ensure that
the ground return from GND to the supply ground is
short and low impedance; a ground plane is recom-
mended. Bypass VDD with a 0.1µF to ground as close
as possible to the device. If the supply is excessively
noisy, connect a 10Ωresistor in series with the supply
and VDD, and add additional capacitance
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
______________________________________________________________________________________ 11
μC
SDA SCL
VDD
OFFSET ADJUSTMENT
THRESHOLD ADJUSTMENT
GAIN ADJUSTMENT
SCL
SDA
VDD
OUT
MAX5360L
2V REFERENCE
SCL
SDA
VDD
OUT
MAX5361M
4V REFERENCE
SCL
SDA
VDD
OUT
MAX5362P
VDD REFERENCE
Figure 7. I2C Typical Application
PROCESS: BiCMOS
Chip Information
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
12 ______________________________________________________________________________________
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND
PATTERN NO.
5 SOT23 U5+1 21-0057 90-0174
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
13
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
2 3/11 Corrected offset error specification in Electrical Characteristics table 2