MP28265
21V, 5A, 1.1MHz
Synchronous Step-down Converter
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The Future of Analog IC Technology
DESCRIPTION
The MP28265 is a high frequency synchronous
rectified step-down switch mode converter with
built in internal power MOSFETs. It offers a
very compact solution to achieve 5A continuous
output current over a wide input supply range
with excellent load and line regulation. The
MP28265 operates at high efficiency over a
wide output current load range.
Current mode operation provides fast transient
response and eases loop stabilization.
Full protection features include OCP and thermal
shut down.
The MP28265 requires a minimum number of
readily available standard external components
and is available in a space saving 3mm x 4mm
14-pin QFN package.
FEATURES
• Wide 4.5V to 21V Operating Input Range
• 5A Output Current
• Low RDS(ON) Internal Power MOSFETs
• Proprietary Switching Loss Reduction
Technique
• Fixed 1.1MHz Switching Frequency
• Sync from 400kHz to 2MHz External Clock
• Internal Compensation
• OCP Protection and Thermal Shutdown
• Output Adjustable from 0.8V
• Available in 14-pin QFN3x4 Package
APPLICATIONS
• Notebook Systems and I/O Power
• Networking Systems
• Digital Set Top Boxes
• Personal Video Recorders
• Flat Panel Television and Monitors
• Distributed Power Systems
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
The information in this datasheet about the product and its associated
technologies are proprietary and intellectual property of Monolithic Powe
r
Systems and are protected by copyright and pending patent applications
TYPICAL APPLICATION （FOR NOTEBOOK）
MP28265
SW
GNDNC AGND
FB
EN/SYNC
IN BST
VCC
PG
PG
R2
10K
Rt
24.9K
R1
4.99K
R3
100K
VIN
ON/OFF
8
10
6
2,3,4,5
1
11
9
7
12,13
4.5V-21V
14
Efficiency
V
OUT
=1.2V
0
10
20
30
40
50
60
70
80
90
100
0123456
OUTPUT CURRENT(A)
EFFICIENCY(%)
V
IN
=12V
V
IN
=21V
V
IN
=5V
MP28265 – 5A, 21V, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS
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ORDERING INFORMATION
Part Number* Package Top Marking Free Air Temperature (TA)
MP28265EL 3x4 QFN14 28265 –20°C to +85°C
* For Tape & Reel, add suffix –Z (e.g. MP28265EL–Z).
For RoHS compliant packaging, add suffix –LF (e.g. MP28265EL–LF–Z)
PACKAGE REFERENCE
NC
VCC
GND
AGND
GND
PG
FB
IN
SW
SW
SW
SW
BST
EN/SYNC
TOP VIEW
PIN 1 ID
EXPOSED PAD
ON BACKSIDE
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VIN ....................................... 22V
VSW .........................–0.3V (-5V for<10ns) to 23V
VBS ....................................................... VSW + 6V
All Other Pins.................................–0.3V to +6V
Operating Temperature.............. -20°C to +85°C
Continuous Power Dissipation (TA = +25°C) (2)
…………………………………..…………....2.6W
Junction Temperature...............................150°C
Lead Temperature ....................................260°C
Storage Temperature.............. –65°C to +150°C
Recommended Operating Conditions (3)
Supply Voltage VIN ...........................4.5V to 21V
Operating Junct. Temp (TJ) .....–20°C to +125°C
Thermal Resistance (4) θJA θJC
3x4 QFN14 ............................. 48 ...... 11... °C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-to-
ambient thermal resistance JA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
TA)/JA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
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ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameters Symbol Condition Min Typ Max Units
Supply Current (Shutdown) IIN V
EN = 0V 0 A
Supply Current (Quiescent) IIN V
EN = 2V, VFB = 1V 0.7 mA
HS Switch On Resistance HSRDS-ON 120 m
LS Switch On Resistance LSRDS-ON 20 m
Switch Leakage SWLKG VEN = 0V, VSW = 0V or
12V 0 10 A
Current Limit (5) I
LIMIT 6 A
Oscillator Frequency FSW V
FB = 0.75V 0.9 1.1 1.3 MHz
Fold-back Frequency FFB V
FB = 300mV 0.25 fSW
Maximum Duty Cycle DMAX V
FB = 700mV 85 90 %
Sync Frequency Range FSYNC 0.4 2 MHz
Feedback Voltage VFB TA = -20°C to + 85°C 789 805 821 mV
Feedback Current IFB V
FB = 800mV 10 50 nA
EN Rising Threshold VEN_RISING 1.1 1.3 1.6 V
EN Threshold Hysteresis VEN_HYS 0.4 V
VEN = 2V 2 A
EN Input Current IEN VEN = 0V 0
EN Turn Off Delay ENTd-Off 5 s
Power Good Rising Threshold PGVth-Hi 0.9 VFB
Power Good Falling Threshold PGVth-Lo 0.7 VFB
Power Good Delay PGTd 20 s
Power Good Sink Current
Capability VPG Sink 4mA 0.4 V
Power Good Leakage Current IPG_LEAK V
PG = 3.3V 10 nA
VIN Under Voltage Lockout
Threshold Rising INUVVth 3.8 4.0 4.2 V
VIN Under Voltage Lockout
Threshold Hysteresis INUVHYS 880 mV
VCC Regulator VCC 5 V
VCC Load Regulation Icc=5mA 5 %
Soft-Start Period 2 4 6.5 ms
Thermal Shutdown TSD 150 °C
Note:
5) Guaranteed by design.
MP28265 – 5A, 21V, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS
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PIN FUNCTIONS
Pin # Name Description
1 IN
Supply Voltage. The MP28265 operates from a +4.5V to +21V input rail. C1 is
needed to decouple the input rail. Use wide PCB traces and multiple vias to make
the connection.
2,3,4,5 SW Switch Output. Use wide PCB traces and multiple vias to make the connection.
6 BST
Bootstrap. A capacitor connected between SW and BS pins is required to form a
floating supply across the high-side switch driver.
7 EN/SYNC
EN=1 to enable the chip. External clock can be applied to EN pin for changing
switching frequency. For automatic start-up, connect EN pin to VIN by proper EN
resistor divider as Figure 2 shows.
8 FB
Feedback. An external resistor divider from the output to GND, tapped to the FB
pin, sets the output voltage. To prevent current limit run away during a short circuit
fault condition the frequency fold-back comparator lowers the oscillator frequency
when the FB voltage is below 500mV.
9 PG
Power Good Output, the output of this pin is open drain. Power good threshold is
90% low to high and 70% high to low of regulation value.
10,
Exposed Pad NC No Internal Connection.
11 VCC
Bias Supply. Decouple with 0.1uF~0.22uF cap. And the capacitance should be no
more than 0.22uF.
12,13 GND
System Ground. This pin is the reference ground of the regulated output voltage.
For this reason care must be taken in PCB layout.
14 AGND
Signal Ground. AGND is not internally connected to System Ground, make sure
AGND connected to system Ground in PCB layout.
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TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 1.2V, L = 0.95µH, TA = +25ºC, unless otherwise noted.
Load Regulation
ENABLE SUPPLY CURRENT (uA)
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Enable Supply Current
vs. Input Voltage
V
FB
=1V
Disable Supply Current
vs. Input Voltage
V
EN
=0V
500
550
600
650
700
750
800
850
900
950
1000
0 5 10 15 20 25 -0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0 5 10 15 20 25
DISABLE SUPPLY CURRENT (uA)
V
CC
(V)
VCC Regulator Line Regulation
3.5
4
4.5
5
5.5
6
0 5 10 15 20 25
Peak Current vs. Duty Cycle
5
5.2
5.4
5.6
5.8
6
6.2
6.4
6.6
6.8
7
0 102030405060708090100
DUTY CYCLE (%)
PEAK CURRENT (A)
Operating Range
0.1
1
10
100
0 5 10 15 20 25
OUTPUT VOLTAGE (V)
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
012345
LOA D CURRENT(A)
NORMALIZED OUTPUT VOLTAGE (%)
VIN=4.5V
VIN=21V
VIN=12V
Line Regulation
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 5 10 15 20 25
NORMALIZED OUTPUT VOLTAGE (%)
IOUT=0A
IOUT=2.5A
IOUT=5A
Case Temperature Rise
vs.Output Current
0
10
20
30
40
50
60
012345
OUTPUT CURRENT (A)
Dmax Limit
Minimum on Time Limit
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1.2V, L = 0.95µH, TA = +25ºC, unless otherwise noted.
Efficiency
VOUT=1.2V
Efficiency
VOUT=1.8V
Efficiency
VOUT=2.5V
0
10
20
30
40
50
60
70
80
90
100
0123456
OUTPUT CURRENT(A) OUTPUT CURRENT(A) OUTPUT CURRENT(A)
EFFICIENCY(%)
EFFICIENCY(%)
EFFICIENCY(%)
VIN=12V
VIN=21V
VIN=5V
0
10
20
30
40
50
60
70
80
90
100
0123456
VIN=12V
VIN=21V
VIN=5V
0
10
20
30
40
50
60
70
80
90
100
0123456
VIN=12V
VIN=21V
VIN=5V
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1.2V, L = 0.95µH, TA = +25ºC, unless otherwise noted.
Enable Startup
with 5A Load
Enable Startup
without Load
Power Up without Load
Power up with 5A Load
VOUT
1V/div
VSW
10V/div
IINDUCTOR
5A/div
VOUT
1V/div
VEN
5V/div
VSW
10V/div
IINDUCTOR
5A/div
IINDUCTOR
5A/div
VOUT
1V/div
VEN
5V/div
VSW
10V/div
IINDUCTOR
5A/div
VOUT
1V/div
VIN
10V/div
VSW
10V/div
IINDUCTOR
5A/div
2ms/div
4ms/div
400ns/div
4ms/div
4ms/div
Short Entry Short Recovery
2ms/div
Output Ripple Voltage
IOUT=5A
Input Ripple Voltage
IOUT=5A
VOUT
1V/div
VIN
10V/div
VSW
10V/div
IINDUCTOR
5A/div
VOUT
1V/div
VSW
10V/div
IINDUCTOR
5A/div
4ms/div
VSW
10V/div
VSW
5V/div
VOUT/AC
20mV/div
VIN/AC
100mV/div
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BLOCK DIAGRAM
Reference
Oscillator
VCC
Regulator
-
+
-
+
HS
Driver
-
+
FB
EN/SYNC
IN
Current Sense
Amplifer
Current Limit
Comparator
Error Amplifier
SW
BST
GND
LS
Driver
VCC
+
BOOST
Regulator
Comparator
On Time Control
Logic Control
400K1MEG 50pF
RSEN
1pF
VCC
PG
PG
Comparator
--
+
Figure 1—Functional Block Diagram
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OPERATION
The MP28265 is a high frequency synchronous
rectified step-down switch mode converter with
built in internal power MOSFETs. It offers a very
compact solution to achieve 5A continuous
output current over a wide input supply range
with excellent load and line regulation.
The MP28265 operates in a fixed frequency,
peak current control mode to regulate the output
voltage. A PWM cycle is initiated by the internal
clock. The integrated high-side power MOSFET
is turned on and remains on until its current
reaches the value set by the COMP voltage.
When the power switch is off, it remains off until
the next clock cycle starts. If, in 90% of one PWM
period, the current in the power MOSFET does
not reach the COMP set current value, the power
MOSFET will be forced to turn off
Power Good Indicator
When the FB is below 0.85VFB, the PG pin will be
internally pulled low. When the FB is above
0.9VFB , the PG becomes an open-drain output.
Internal Regulator
Most of the internal circuitries are powered from
the 5V internal regulator. This regulator takes the
VIN input and operates in the full VIN range.
When VIN is greater than 5.0V, the output of the
regulator is in full regulation. When VIN is lower
than 5.0V, the output decreases, 0.1uF ceramic
capacitor for decoupling purpose is required.
Error Amplifier
The error amplifier compares the FB pin voltage
with the internal FB reference (VFB) and outputs a
current proportional to the difference between the
two. This output current is then used to charge or
discharge the internal compensation network to
form the COMP voltage, which is used to control
the power MOSFET current. The optimized
internal compensation network minimizes the
external component counts and simplifies the
control loop design.
Enable/Sync Control
EN/Sync is a digital control pin that turns the
regulator on and off. Drive EN high to turn on the
regulator, drive it low to turn it off. There is an
internal 1MEG resistor from EN/Sync to GND
thus EN/Sync can be floated to shut down the
chip.
1) Enabled by external logic H/L signal
The chip starts up once the enable signal goes
higher than EN/SYNC input high voltage (2V),
and is shut down when the signal is lower than
EN/SYNC input low voltage (0.4V). To disable
the chip, EN must be pulled low for at least 5µs.
The input is compatible with both CMOS and TTL.
2) Enabled by Vin through voltage divider.
Connect EN with VIN through a resistive voltage
divider for automatic startup as the figure 2
shows.
EN
V
IN
R
EN1
R
EN2
Figure 2—Enable Divider Circuit
Choose the value of the pull-up resistor REN1 and
pull-down resistor REN2 to reset the automatic
start-up voltage:
R
R(R
VV
EN2
EN2EN1
EN_RISINGIN_START Ω
Ω
+
⋅= MM
1|| )1||
Ω
Ω
+
⋅
=MM
1|| )1||
EN2
EN2EN1
FALLING-ENIN_STOP R
R(R
VV
Figure 3—Startup Sequence Using EN Divider
3) Synchronized by External Sync Clock Signal
The chip can be synchronized to external clock
range from 400kHz up to 2MHz through this pin
2ms right after output voltage is set, with the
internal clock rising edge synchronized to the
external clock rising edge.
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Vin
EN/Sync
Vcc
Vout
CLK
5us
Foldback
1.1MHz
External CLK
0.625*Vout_set
2ms1ms
VCC_Rising
Vout_set
Figure 4—Startup Sequence Using External
Sync Clock Signal
Under-Voltage Lockout (UVLO)
Under-voltage lockout (UVLO) is implemented to
protect the chip from operating at insufficient
supply voltage. The MP28265 UVLO comparator
monitors the output voltage of the internal
regulator, VCC. The UVLO rising threshold is
about 4.0V while its falling threshold is a
consistent 3.2V.
Internal Soft-Start
The soft-start is implemented to prevent the
converter output voltage from overshooting
during startup. When the chip starts, the internal
circuitry generates a soft-start voltage (SS)
ramping up from 0V to 1.2V. When it is lower
than the internal reference (REF), SS overrides
REF so the error amplifier uses SS as the
reference. When SS is higher than REF, REF
regains control. The SS time is internally fixed to
4ms.
Over-Current-Protection and Hiccup
The MP28265 has cycle-by-cycle over current
limit when the inductor current peak value
exceeds the set current limit threshold.
Meanwhile, output voltage starts to drop until FB
is below the Under-Voltage (UV) threshold,
typically 30% below the reference. Once a UV is
triggered, the MP28265 enters hiccup mode to
periodically restart the part. This protection mode
is especially useful when the output is dead-short
to ground. The average short circuit current is
greatly reduced to alleviate the thermal issue and
to protect the regulator. The MP28265 exits the
hiccup mode once the over current condition is
removed.
Thermal Shutdown
Thermal shutdown is implemented to prevent the
chip from operating at exceedingly high
temperatures. When the silicon die temperature
is higher than 150°C, it shuts down the whole
chip. When the temperature is lower than its
lower threshold, typically 140°C, the chip is
enabled again.
Floating Driver and Bootstrap Charging
The floating power MOSFET driver is powered by
an external bootstrap capacitor. This floating
driver has its own UVLO protection. This UVLO’s
rising threshold is 2.2V with a hysteresis of
150mV. The bootstrap capacitor voltage is
regulated internally by VIN through D1, M3, C4,
L1 and C2 (Figure 5). If (VIN-VSW) is more than
5V, U2 will regulate M3 to maintain a 5V BST
voltage across C4.
SW
Figure 5—Internal Bootstrap Charging Circuit
Startup and Shutdown
If both VIN and EN are higher than their
appropriate thresholds, the chip starts. The
reference block starts first, generating stable
reference voltage and currents, and then the
internal regulator is enabled. The regulator
provides stable supply for the remaining
circuitries.
Three events can shut down the chip: EN low,
VIN low and thermal shutdown. In the shutdown
procedure, the signaling path is first blocked to
avoid any fault triggering. The COMP voltage and
the internal supply rail are then pulled down. The
floating driver is not subject to this shutdown
command.
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APPLICATION INFORMATION
Setting the Output Voltage
The external resistor divider is used to set the
output voltage (see Typical Application on page
1). The feedback resistor R1 also sets the
feedback loop bandwidth with the internal
compensation capacitor (see Typical Application
on page 1). Choose R1 to be around 40.2k for
optimal transient response. R2 is then given by:
1
V
VR1
R2
FB
OUT −
=
The T-type network is highly recommended when
Vo is low, as Figure 6 shows.
FB 1
R2
R1
Rt
VOUT
Figure 6— T-type Network
Table 1 lists the recommended T-type resistors
value for common output voltages.
Table 1—Resistor Selection for Common
Output Voltages
VOUT (V) R1 (kΩ) R2 (kΩ) Rt (kΩ)
1.05 4.99(1%) 16.5(1%) 24.9(1%)
1.2 4.99(1%) 10.2(1%) 24.9(1%)
1.5 4.99(1%) 5.76(1%) 24.9(1%)
1.8 4.99(1%) 4.02(1%) 24.9(1%)
2.5 40.2 (1%) 19.1(1%) 0
3.3 40.2(1%) 13(1%) 0
5 40.2 (1%) 7.68(1%) 0
Selecting the Inductor
A 1µH to 10µH inductor with a DC current rating
of at least 25% percent higher than the maximum
load current is recommended for most
applications. For highest efficiency, the inductor
DC resistance should be less than 15m. For
most designs, the inductance value can be
derived from the following equation.
OSCLIN
OUTINOUT
fIV
)VV(V
L×Δ×
−×
=
Where IL is the inductor ripple current.
Choose inductor ripple current to be
approximately 30% if the maximum load current,
5A. The maximum inductor peak current is:
2
I
II L
LOAD)MAX(L
Δ
+=
Under light load conditions below 100mA, larger
inductance is recommended for improved
efficiency.
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous, therefore a capacitor is required to
supply the AC current to the step-down converter
while maintaining the DC input voltage. Use low ESR
capacitors for the best performance. Ceramic
capacitors with X5R or X7R dielectrics are highly
recommended because of their low ESR and
small temperature coefficients. For most
applications, a 22µF capacitor is sufficient.
Since the input capacitor (C1) absorbs the input
switching current it requires an adequate ripple
current rating. The RMS current in the input capacitor
can be estimated by:
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
×−×=
IN
OUT
IN
OUT
LOAD1C V
V
1
V
V
II
The worse case condition occurs at VIN = 2VOUT,
where:
2
I
ILOAD
1C =
For simplification, choose the input capacitor
whose RMS current rating greater than half of the
maximum load current.
The input capacitor can be electrolytic, tantalum
or ceramic. When using electrolytic or tantalum
capacitors, a small, high quality ceramic
capacitor, i.e. 0.1F, should be placed as close
to the IC as possible. When using ceramic
capacitors, make sure that they have enough
capacitance to provide sufficient charge to
prevent excessive voltage ripple at input. The
input voltage ripple caused by capacitance can
be estimated by:
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−××
×
=Δ
IN
OUT
IN
OUT
S
LOAD
IN V
V
1
V
V
1Cf
I
V
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Selecting the Output Capacitor
The output capacitor (C2) is required to
maintain the DC output voltage. Ceramic,
tantalum, or low ESR electrolytic capacitors are
recommended. Low ESR capacitors are
preferred to keep the output voltage ripple low.
The output voltage ripple can be estimated by:
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
××
+×
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−×
×
=Δ 2Cf8
1
R
V
V
1
Lf
V
V
S
ESR
IN
OUT
S
OUT
OUT
Where L is the inductor value and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
In the case of ceramic capacitors, the
impedance at the switching frequency is
dominated by the capacitance. The output
voltage ripple is mainly caused by the
capacitance. For simplification, the output
voltage ripple can be estimated by:
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−×
×××
=
IN
OUT
2
S
OUT
OUT V
V
1
2CLf8
V
V
In the case of tantalum or electrolytic capacitors,
the ESR dominates the impedance at the
switching frequency. For simplification, the
output ripple can be approximated to:
ESR
IN
OUT
S
OUT
OUT R
V
V
1
Lf
V
V×
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−×
×
=
The characteristics of the output capacitor also
affect the stability of the regulation system. The
MP28265 can be optimized for a wide range of
capacitance and ESR values.
PCB Layout
PCB layout is very important to achieve stable
operation. Please follow these guidelines and
take Figure 7 for references.
1) Keep the connection of input ground and
GND pin as short and wide as possible.
2) Keep the connection of input capacitor and
IN pin as short and wide as possible.
3) Ensure all feedback connections are short
and direct. Place the feedback resistors
and compensation components as close to
the chip as possible.
4) Route SW away from sensitive analog
areas such as FB.
5) Connect IN, SW, and especially GND
respectively to a large copper area to cool
the chip to improve thermal performance
and long-term reliability.
6) Adding RC snubber circuit from IN pin to
SW pin can reduce SW spikes.
C4
Top Layer
Bottom Layer
Figure 7—PCB Layout
MP28265 – 5A, 21V, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS
MP28265 Rev. 0.92 www.MonolithicPower.com 13
12/2/2009 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
External Bootstrap Diode
An external bootstrap diode may enhance the
efficiency of the regulator, the applicable
conditions of external BST diode is:
z Duty cycle is high: D=
IN
OUT
V
V>65%
In this case, an external BST diode is
recommended from the VCC pin to BST pin, as
shown in Figure 8
SW
BST
MP28265 C
L
BST
C
OUT
External BST Diode
VCC
IN4148
Figure 8—Add Optional External Bootstrap
Diode to Enhance Efficiency
The recommended external BST diode is
IN4148, and the BST cap is 0.1~1µF.
MP28265 – 5A, 21V, SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP28265 Rev. 0.92 www.MonolithicPower.com 14
12/2/2009 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
PACKAGE INFORMATION
3mm x 4mm QFN14
SIDE VIEW
TOP VIEW
1
14
87
BOTTOM VIEW
2.90
3.10
1.60
1.80
3.90
4.10
3.20
3.40
0.50
BSC
0.18
0.30
0.80
1.00
0.00
0.05
0.20 REF
PIN 1 ID
MARKING
1.70
0.50
0.25
RECOMMENDED LAND PATTERN
2.90 NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) JEDEC REFERENCE IS MO-229, VARIATION VGED-3.
5) DRAWING IS NOT TO SCALE.
PIN 1 ID
SEE DETAIL A
3.30
0.70
PIN 1 ID OPTION B
R0.20 TYP.
PIN 1 ID OPTION A
0.30x45º TYP.
DETAIL A
0.30
0.50
PIN 1 ID
INDEX AREA
Mouser Electronics
Authorized Distributor
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