SONY CXA2069Q $2-Compatible 7-Input 3-Output Audio/Video Switch Description The CXA20690 is a 7-input, 3-output audio/video switch featuring l2@C bus compatibility for TVs. This IC has input pins that are compatible with S2 protocol. Features 4 inputs that are compatible with S2 protocol * Serial control with I2C bus 7 inputs, 3 outputs The desired inputs can be selected independently for each of the 3 outputs Wide band video amplifier (20 MHz, 3 dB) Y/C MIX circuit * Slave address can be changed (S0H/92H) * Audio muting from external pin * High impedance maintained by I2C bus lines (SDA, SCL) even when power is OFF * Wide audio dynamic range (3 Vrms typ.} Applications Audio/video switch featuring l2@C bus compatibility for TVs Structure Bipolar silicon monolithic IC 64 pin QFP (Plastic) Absolute Maximum Ratings (Ta=25 C} Supply voltage = Vec Operating temperature Topr * Storage temperature Tstg Allowable power dissipation Pp Operating Conditions Supply voltage 12 -20 to +75 65 to +150 1300 9+0.5 C C mW Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. { E96YO05D1YSONY CXA2069Q Block Diagram T v1 53) VOUT (48) YIN1 (56) YOUT1 55) TRAP1 v2 va V4 VS V6 (58) courTi (51) CIN1 1 Y2 VNOUT2 3 v4 TRAP2 COUT2 cl VOUTS C2 ca C4 YOUT3 COUTS VGND BIAS Veo LTV AGND LVI LOUT1 Lye AOLUTt LV3 LOUT2 Lv4 ov RGUT. LV5 oure LV6 LOUTS ATY ROUT3 RV1 RV2 OC OUT AV3 SCL AVa SDA RV5 ADR RV6 S-1 8-2 -3 S-4 $2-1 $2.2 Audio system is attenuated by 6dB at input, and a total gain is OdB (LOUT1 and ROUT1 can be changed to ~6dB). 32-3 82-4 MUTESONY CXAZ069Q Pin Configuration o >] oO a << x OSONY CXA2069Q Pin Description Pin Symbol Pin Equivalent circuit DB ipti ui No. y voltage q esoriplion 63 TV Vee 1 V1 8 V2 ; . ; 1s V3 4.0V nowt, corse vieo signal 22 v4 pureomp gna's- 30 V5 60 V6 3 1 Y/G separation signal inputs. 10 Y2 Input luminance signals. 17 3 4.0V The YIN1 pin inputs the signal 24 4 obtained by /C separating the 49 YIN1 VOUT1 pin output. TT 5 C1 /C separation signal inputs. 12 C2 Input chrominance signals. 19 C3 45V The CIN1 pin inputs the signal 26 C4 obtained by Y/C separating the 51 CIN1 VOUT1 pin output. 62,2 | LTV, LV1 9,16 | LV2,LV3 23, 29| LV4,LV5 59, 64| LV6,RTV | 4.5V Audio signal inputs. 4,11 | RV1, RV2 18, 25|) AV3, RV4 31,61) RAV5, RV6 53 VOUT1 3.9V Video signal outputs. 41 VOUT3 Output composite video signals.SONY CXA20690Q Pin Symbol Pin Equivalent circuit D ipti ircui ripti No. y voltage q eseripnon Voc Voc Vcc Veco Video signal output. 44 | vNouT2 | 38V Either composite video signal output or iuminance signal output can be selected by I2C bus control. Vcc Veco Vcc Vcc 56 YOUT1 3.3 V Ch) Video signal outputs. (8) cf Output luminance signals. 39 | YOUT3 | 3.8V ) C) Vec Vcc Vcc Vec 58 | COUT1 (58) Y Video signal outputs. 47 COUT2 | 45V (47) fo out at shrominanoe signals 37 COUT3 (37) cof P gras: Vcc Vcc 52 LOUT1 43 LOUT2 38 LOUTS3 4.5V Audio signal outputs. 54 ROUT1 , Z0=50 Q (within DC +2 mA) 45 ROUT2 40 ROUT3 Detects the S2-compatible DC superimposed onto the C signal. 4:3 video signa! at 1.3 V or less 6 $2-1 4 : 3 letter-box signal at 1.3 V or more 13 2-2 to 2.5 V or less 20 $2-3 16: 9 picture squeezed signal at 2.5 V 27 $2-4 or more This pin is pulled down to GND by a 100 k&2 resistor, so the 4 : 3 video signal is selected when open.SONY CXA20690 Pin No. Symbol Pin voltage Equivalent circuit Description 14 21 28 S-1 8-2 8-3 8-4 Composite video/S selector. The detection results are written to the status register. S signal at 3.5 V or less Compcsite video signal at 3.5 V or more This pin is pulled up to 5 V by a 100 kQ resistor, so the composite video signal is selected when open. 32 ADR 147 72k 28k Selects the slave address for the l2C bus. 90H at 1.5 V or less 92H at 2.5 V or more 90H when open. 33 SCL 10.5k l2C bus signal input Vi_max=1.5 V Vinmin=3.0 V 34 SDA I2C bus signal input Vitmax=1.5 V Vinmin=3.0 V Votmax=0.4 VSONY CXA20690 Pin Symbol Pin Equivalent circuit D ipti escription No. y voltage q pio Outputs the $2-compatible DC superimposed onto the COUTS output. The DC is superimposed by connecting this pin to the COUTS3 cutput via a capacitor. Control is performed by the l2C bus. When 0 V is output, Q1 is ON and the 4k 1k impedance is 5 kQ. 36 DC_OUT 7 (26) . $2 protocol output impedance of 28k 10 +3 kQ is realized by attaching external resistance of 4.7 kQ. DC_OUT (bus) Output DC 0 45V 1 OV 2 1.9V 3 4.5V 55 | TRAP1 100 3.8 V Connects trap circuit for subcarrier. 46 | TRAP2 P 3X8) ik o Audio signal output mute. 1470 72k Mute OFF at 1.5 V or less Mute ON at 2.5 V or more 28k Mute OFF when open. 4g | MUTE (48) Vcc Vee Voc internal reference bias (Vcc/2). Connect to GND via a capacitor. 50 BIAS 45VSONY CXA20690 Electrical Characteristics (Ta=25 C Vcc=9 V) Item Symbol Conditions Min. | Typ. | Max. | Unit Current consumption Icc No signal, no load 49 55 72 mA Video system (Measurement circuit ; Fig. 1) Gain GVv_ | f=100 kHz, 0.3 Vp-p input 5.9 6.4 6.9 dB Freque a cto. FBWv1 | f=100 kHz, input frequency where output 15 20 MHz charactensic: ee amplitude is -3 dB with 0.3 Vp-p output ri nse equency Tespo FBWv2 | serving as 0 dB 10 | 15 | | MHz characteristics (Y/C mix) Input dynamic range Ddv F100 kHz, maximum with 1.4 V purey g distortion < 1.0 % PP Cross talk Vetv | f=4.43 MHz, 1 Vp-p input _ 50 dB Audio system (Measurement circuits ; Fig. 2 to Fig. 5) f=1 kHz, 1 Vp-p input, 5.7 kQ Gain GVA KHz, 1 VP-P Inpu 1 | 0 1 | oB resistor inserted to input Frequency response f=1 kHz, input frequency where output quency resp FBWa | amplitude is -3 dB with 1 Vp-p output 50 | | | kHz characteristics ; serving as 0 dB Total harmonic f=1 kHz, 2.2 Vp-p input, where 400 Hz THD 0.03 05 % distortion HPF+80 kHz LPF are inserted Input dynamic range Dda | f=1 kHz, maximum with distortion < 0.3%] 2.8 3.0 _ Vrms Cross talk Veta | f=1 kHz, 1 Vp-p input _ -90 -80 dB Ripple rejection ratio Veta | f=100 Hz, 0.3 Vp-p applied to Vcc ~55 40 dB Output DC offset Voff | Offset voltage between input and output -30 _ 30 mv . . When 400 Hz HPF+30 kHz LPF Residual noise VNa . 0 20 30 | uVrms are inserted f=1 kHz, 1 Vrms input i S/N -1 90 B SIN ratio fot=400 Hz, fcH=30kHz 00 qSONY CXA2069Q Logic system Item Symbol Conditions Min. | Typ. | Max. | Unit righ level Vin 30 | | 50 | v input voltage Low level VIL 0 _ 1.5 Vv input voltage Low level Vo. | With SDA 3 mA current supplied 0 0.4 Vv output voltage High level 9 te Vin=4,5V 0 10 pA input current Low level row ln | Vu=0.4V o | | 1 | pA input current Maximum clock fseL 0 _ 100 kHz frequency Minimum waiting time tBUF 4.7 _ ys for data change Minimum waiting time tHD-STA 40 5 for data transfer start , H Low level clock t 47 LOW . _ S pulse width H High level clock tic 40 HIGH . s pulse width H Minimum waiting time . tSU:STA 4.7 _ = ps for start preparation Minimum data tuD-DaT 300 hold time ~ | "8 Minimum data oo. tSU:DAT 250 _ ns preparation time Rise time tr _ _ 1 Us Fall time tF 300 ns Minimum waiting time . tsu;sToO 4.7 _ _ Us for stop preparationCXA20690 SONY =e Measurement point isp) fetal lpia CXA20690 Signal is input from one of the following pins: 1, 3, 5,8, 10, 12, 15, 17, 19, 22, 24, 26, 30, 60 and 62. Output signal is measured from one of the following pins: 37, 39, 41, 44, 47, 53, 56 and 58. Fig. 1 Video system (gain, frequency response characteristics, input dynamic range, cross talk} measurement circuit > = 7 $ Measurement paint $4 : i: : 2 i S a . Ee 3 g (Input signal 10k 10 101 5 Ses ce _ pean _ = ae SOee a = a = o 10p 10u 10u Q o 4736) g zt & ~w bE > Q 3 O47y 75 H oo E 2 Q o 3 ~s * (38) oS) 2 3 8 (87) van St Ca) CXA2069Q oa CC A Input signal Signal is input from one of the following pins: 2, 4, 9, 11, 16, 18, 23, 25, 29, 31, 59, 61, 62 and 64. Output signal is measured from ona of the following pins: 38, 40, 43, 45, 52 and 54. Fig. 2 Audio system (gain, frequency response characteristics, total harmonic distortion, input dynamic range, cross talk) measurement circuit 10SONY CXA20690 100HZ, 0.3Vp-p 0 CXA2069Q = = or Ge 5 4 a 4 gi ai 8s Ss ga od a oem o - 3 ort a 7 3 o 3 k= 8= fe 8S & ks B= k= SF 2 oe At=1O0Hz, 0.3Vp-p signal is applied ta Vcc and tha output signals from Pins 38, 40, 43, 45, 52 and 54 are measured. Fig. 3 Audio system (ripple rejection ratio) measurement circuit a Measurement paint oo v A ous ein ze $ 28/38 23) | Fed 8 28 oe z 4 = . of pon = = s avews{idedsvavads +f 3 z 2 Tere ro Te re ye Ts Ss OHO-BLM OBO) (49) 439) (38) i 2:8 & 8 Bee: 2 SRS a> 2 3 Z 82 2 g @) 1g s * ~ 7 57k 1 00 st avs (31) cxAz0690 ca OIC ARS Measurement point Fig. 4 Audio system (output DC offset voltage) measurement circuit -1{SONY CXA20690 A006 Measurement point 10k 10p verout2() CXA2069Q ca (28) Rf Fig. 5 Audio system (residual noise) measurement circuitCXA20690 SONY ales O} @Np WYHy JeUJO pue yueyed Ayed purul jo jusWeBuLyU Aue JO) JO S}INDUID @SeL] JO ASN Sy Jo yNo HulsuB siysjqoid Aue Joy Aijigisucdsa awwinsse JouUBd Auog sealAep ay) jo UOyeado ay) Buneysn|! sajdwexe jeoidA, aye UmOYs s}NoWIO UORoyddy ab sz Indu OIA a indu! OFQIA ny ud siq] 10) 4/2} $so29 JUBAaad 0} _ Saouepeduy Mo] UNM Indu SI} aAg Ajaanoadsay seiq jeuonde sey waysds olpne pue waysds oapia jo indjno yoee aouls sioyoedes ay) jo sanuefod eu) oF UONUaE AY tht f 89 IsNwW sounes jeudis ompne ayy yo souRepedwy jndyno au) JaWseoqns ZHWES'E JO ale (SS PUE OF SUld) SdWHL SUL BIOL 10 ASE Ol gp Ulg Bunas Aq payAW 9q UBS INd\no oIpNe ayy e He 0} 31 BU) JO SSauppe aaeys oy Buges UeyM 22/4, 0} ZE Ud JIGUUO Aeagoedsal AS pue AL Ajoyeuyxosdde $1.9 PUP GP SUId 18 SBIQ Ol) BOUIS SIOWOedES ay) jo soE|od UL 0) UOQUEe Aed si9yy Guide eu) jo SEIG INdjno aL UG BLipuaded yndui OAIA (8) ino 20 o+4 (5 )einoo indino O30IA indul Z OAIA a ve SZ lee 82 lo : So a 2 n AAA = x Wy | _ oS 2 : ws fo Ma MoMs : = c DE90CVXO doi nog. 029 indno Z OAAIA yndul 1 OFGIA bel HL Gs) Linod (es) g3L1s +, __ nh = 4(e 3 itp 5 t L + C_+ < nh a 4] (#_ Oo nero a ic 2 yi 5 oz9 dog: dar o indine | OFQIA gWOD yns19 uoVea|ddy i3gSONY CXA2069Q ?C BUS Control Signal PU PAS I tA <'F ' ' ' 1 THDISTA TLOW THD;DAT THIGH ~ tSU;DAT {SUISTA 1 tSU;STO _s! -P! Fig. 6 l2C BUS Control Signal Timing Chart Description of Operation The CXA2069Q is a TV I?C bus-compatible AV switch IC. The video system and the stereo audio system both have 7 inputs and 3 outputs each. 4 of the 7 video system inputs support $2 and S protocols. The desired inputs can be independently assigned to each output (in the audio system, the left and right channels are processed as one unit) by l2C bus control. However, the same input is assigned to both the video and audio system output 3. 2C BUS Registers 1) 20 BUS The I?C bus (inter-IC bus) is an inter-IC bus system developed by Philips. Two lines (SDA-serial data, SCL-serial clock) provide control over start, stop, data transfer, synchronization, and collision avoidance. The IC outputs are either open collector or open drain, forming a bus line in the wired OR format. | MSB LSB MSB S| 1 2 3 4 5 6 7 8 9 1 2 $: Start condition ; SDA is set Low when SCL is High P: Stop condition ; SDA is set High when SCL is High A: Acknowledge ; signal sent from the slave Data is transmitted by MSB-first. One data unit consists of 8 bits, to which the acknowledge signal, which indicates that the data has been accepted by the slave, is attached at the end. Normally, the slave*1 IC receives data at the rising edge of SCL and the master*2 IC changes data at the falling edge of SCL. *1 Slave : An IC that is placed under the control of the master. In a normal system, all devices excluding the central microcomputer are slaves. *2 Master: A central microcomputer or other controlling IC. 14SONY CXA2069Q 2) Control Registers The CXA2068Q control is exercised by writing 3-byte data into the three 8-bit control registers which control the output selector circuits for the 3 outputs. | S| Slave address [A] DATA [| A} DATA2 | A[ DATA3 [A|P | S; Start condition A; Acknowledge P; Stop condition O Control register structure (DATA1 to DATA3) * All registers are set to O during IC power on. e x indicates undefined. b?7 b6 b5 b4 b3 b2 b1 bO Slave add. 1 0 oO | 1 | @ 0 | ADR | RAW DATA1 A-GAIN |S/COMP1 V-IN1 A-IN1 DATA2 VANOUT |S/COMP2 V-IN2 A-IN2 DATA3 * _ |S/COMP3 AV-IN3 DCOUT| R/W (1) : Read/write mode 0 : Control data write 1: Status register read ADR (1): This bit sets the slave address set by the address pin. 0: 90H 1: 92H A-GAIN (1): LOUT1/ROUT1 output gain selector 0: 0 dB output 1 :-6 dB output S/COMP1 to S/COMPS (1 each) : S terminal input/composite signal input selectors By setting S/COMP1 to 0, when composite signal input is selected, YOUT1/COUT1 output the inputs from YIN1/GIN1 during video 1 output. 0 : Composite signal inputs (TV, V1 to V6 inputs) 1: terminal inputs (1/C1 to Y4/C4 inputs) V/AYOUT (1): This bit selects the output to Pin 44 (VAYYOUT2). 0: VOUT (composite signal) output 1: YOUT (luminance signal) output V-IN1 to V-IN2 (3 each) : These bits select the input signals output to each video output. V-IN1 corresponds to the VOUT1 and YOUT1/COUT1 outputs, and V-IN2 to the VOUT2 and YOUT2/COUT?2 outputs. 0: Mute 4: Selects the V3 and Y3/C3 inputs 1: Selects the TV input 5: Selects the V4 and Y4/C4 inputs 2: Selects the V1 and Y1/C1 inputs 6 : Selects the V5 input 3: Selects the V2 and Y2/C2 inputs 7 : Selects the V6 inputSONY CXA2069Q A-IN1 to A-IN2 (3 each) : These bits select the input signals output to each audio output. A-IN1 corresponds to the LOUT1/ROUT1 outputs, and A-IN2 to the LOUT2/ROUT?2 outputs. 0: Mute 4: Selects the LV3/RV3 inputs 1: Selects the LTV/RTV inputs 5 : Selects the LV4/RV4 inputs 2: Selects the LV1/RV1 inputs 6: Selects the LV5/RV5 inputs 3: Selects the LV2/RV2 inputs : Selects the LV6/RV6 inputs AV-IN3 (3) : This bit selects the input signals output to output 3. Both the video output and the audio output are selected at the same time only for AV-IN3. 0: Mute 4: Selects the V3, Y3/C3 and LV3/RV3 inputs 1: Selects the TV and LTV/RTV inputs 5 : Selects the V4, Y4/C4 and LV4/RV4 inputs 2: Selects the V1, Y1/C1 and LV1/RV1 inputs 6: Selects the V5 and LV5/RV5 inputs 3: Selects the V2, Y2/C2 and LV2/RV2 inputs 7 : Selects the V6 and LV6/RV6 inputs DC OUT (2) : These bits set the DC voltage output from Pin 35 (DC OUT). 0:4.5V 1:0V 2:1.9V 3:4.5V 3) Status Registers e When reading two bytes | S| Slaveaddress [| A| DATA | A| DATA2 [NA| P | When reading one byte | S| Slaveaddress | A| DATA [NA| P | S; Start condition A; Acknowledge NA; No acknowledge P; Stop condition When communication is to be terminated in the status register reading mode, the no-acknowledge signal is needed to assure that the master does not issue the acknowledge signal to the slave. It is possible to read only DATA1 of the status register by sending the no-acknowledge signal after DATA. O Status register structure (DATA1 to DATA2) b7 b6 b5 b4 b3 b2 b1 bo Slave add. 1 tf) 0 1 0 0 ADR | 1 DATA1 S1SEL S2SEL SS3SEL S4SEL $-C1 S-C2 DATA2 S1SEL S2SEL S3SEL S4SEL 3-C3 -C4 i5SONY CXA2069Q S1SEL to S4SEL (1 each) : S-1 to S-4 pin status 0; S-1 to S-4 pins are not grounded. 3.5 V or more 0 1; S-1 to S-4 pins are grounded. 35 V or less 1 S1SEL to S4SEL are actually determined by comparing the S-1 to S-4 pin DC voltages with 3.5 V. -C1, 8-C2, S-C3, $-C4 (2 each) : $2-1, S2-2, S2-3 and S2-4 pin status 0; 4:3 video signal $2-1 to $2-4 pin DC voltage] S-C1 to S-C4 1; 4:3 letter-box signal 1.3V orless 0 2; 16: 9 video squeezed signal 1.3 V or more to 2.5 V or less 1 3; No signal 2.5 V of more 2 S-C1 to S-C4 are actually determined by S-1 to S-4 OPEN 3 comparing the S2-1 to S2-4 pin DC voltages 8-1 to S-4 pin DC voltage S1SEL to S4SEL with two threshold. However, when the S-1 to 5-4 pins are open, the outputs are fixed to 3. 4) Power-on Reset The CXA2069Q has an internal power-on reset function that sets each control register to O during IC power ON. The power-on reset VtH has hysteresis. Power-onreset |... released Power-on reset 4.5V Veco 5.6VSONY CXA20690 Video system frequency response characteristics = 8 TV, V1 to V6 VOUT1 to VOUTS 3. Y1 to 4 > YOUTI to YOUTS c 6 J C1 to C4 > COUT1 to COUT3 a m eT 5 a \ g 4 Y1IC1 to 4/C4 N g VOUT1 to VOUT3 2 wo = a) Gc 2 > | -2 100k 1M 10M 100M Frequency [Hz] Audio system frequency response characteristics a L/RTV, L/R1 to L/R6 > LOUT1 (0dB) zZ, URTV, L/A1 to L/R6 > LOUT2 to LOUTS1 o g / m Ss a o Ss -2 g 2 oa = 4 E - o LAATV, L/R1 to LIR6 LOUTI (-6dB) J o h o ~ 2 a3 = -8 ik 10k 100k 1M Frequency [Hz] Audio system distortion vs. Input amplitude 10 fe1kHz 400Hz HPF, 80kHz LPF = 1 & c 2 c 2 2 Ta 2 5 0.1 z 3 LOUT1 output (0dB gain 2 of LOUT2 and 0. LOUT 3 outputs 0.002 0 1 2 3 4 Input amplitude [Vrms] 18SONY CXAZO69Q Package Outline PEC Ass'y Unit: mm 64PIN QFP (PLASTIC} 2390.4 +04 +01 200-0) epee WIE = 0.05 INPAWEANAEAAAAA RARE ae 52 Fao) az om bn) oD Fos cm Ir od Em -) oF fo | 6 a oo C) C) Eos * S| oo fo3 zp on 7 ao FE oo Eo coy Ir om oO Eo om Fr 20 +02 HHHHHRER ERS HH Oe 3 1 18 ' 0.15 + 0.35) 4 ae 4264 275-0715). | 4 a | a beg te eto 3| PACKAGE STRUCTURE PACKAGE MATERIAL | EPOXY RESIN SONY CODE OFP-64P-L01 LEAD TREATMENT SOLDER PLATING ElAs CODE P-OFPEA-14<20-1 0 LEAD MATERIAL 4B/COPPEA ALLOY JEDEG CODE PACKAGE MASS 15 64PIN QFP(PLASTIC) ww P88 AOA +04 +0) 20.0-0.1 pay 215 0.08 JARAR RAAA RAR ARAB ADA O Oo Q z (NRBHERABERAY ~ O to 7 4 1 + 414.0 = 8 SEBRBERBHBBE g BHT EHE OH DEBHEBEH 04-01 78 = 0. | | is! $0.95 + 0.35) a =o. al 4 | - 0 toi 0 a {BL 02 ) - A] 015 16.3 PACKAGE STRUCTURE PACKAGE MATEFIAL | EPOXY RESIN ~TSOLDERPALLAGIUM SONY CODE OFP-64P.LOt _LEAD TREATMENT OLDERPA LL AGM EIAJ CODE OFPos4-P-1420 {EAD MATERIAL 42/COPPER ALLOY JEDEC CODE PACKAGE MASS 15g LEAD PLATING SPECIFICATIONS ITEM SPEC, LEAD MATERIAL 42. ALLOY SOLDER COMPOSITION Sn-Bi Bit awit PLATING THICKNESS Staum 19 Sony Corporation