Features
•Fast Read Access Time – 55 ns
•Low Power CMOS Operation
– 100 µA Maximum Standby
– 35 mA Maximum Active at 5 MHz
•JEDEC Standard Packages
– 40-lead PDIP
– 44-lead PLCC
– 40-lead VSOP
•Direct Upgrade from 512-Kbit and 1-Mbit (AT27C516 and AT27C1024) EPROMs
•5V ± 10% Power Supply
•High Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
•Rapid Programming Algorithm – 50 µs/Word (Typical)
•CMOS and TTL Compatible Inputs and Outputs
•Integrated Product Identification Code
•Industrial Temperature Range
1. Description
The AT27C2048 is a low-power, high-performance 2,097,152-bit one-time program-
mable read-only memory (OTP EPROM) organized 128K by 16 bits. It requires a
single 5V power supply in normal read mode operation. Any word can be accessed in
less than 55 ns, eliminating the need for speed-reducing WAIT states. The by-16
organization makes this part ideal for high-performance 16 and 32 bit microprocessor
systems.
In read mode, the AT27C2048 typically consumes 15 mA. Standby mode supply cur-
rent is typically less than 10 µA.
The AT27C2048 is available in industry-standard JEDEC-approved one-time pro-
grammable (OTP) plastic PDIP, PLCC, and VSOP packages. The device features
two-line control (CE, OE) to eliminate bus contention in high-speed systems.
With high density 128K word storage capability, the AT27C2048 allows firmware to be
stored reliably and to be accessed by the system without the delays of mass storage
media.
Atmel’s AT27C2048 has additional features that ensure high quality and efficient pro-
duction use. The Rapid Programming Algorithm reduces the time required to program
the part and guarantees reliable programming. Programming time is typically only
50 µs/word. The Integrated Product Identification Code electronically identifies the
device and manufacturer. This feature is used by industry-standard programming
equipment to select the proper programming algorithms and voltages.
2-Megabit
(128K x 16)
OTP EPROM
AT27C2048
0632F–EPROM–12/07
2
0632F–EPROM–12/07
AT27C2048
2. Pin Configurations
Note: Both GND pins must be connected.
2.1 40-lead PDIP Top View
Pin Name Function
A0 - A16 Addresses
O0 - O15 Outputs
CE Chip Enable
OE Output Enable
PGM Program Strobe
NC No Connect
DC Don’t Connect
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VPP
CE
O15
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
O5
O4
O3
O2
O1
O0
OE
VCC
PGM
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
2.2 40-lead VSOP (Type 1) Top View
2.3 44-lead PLCC Top View
Note: Note: PLCC package pins 1 and 23 are Don’t Connect.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A9
A10
A11
A12
A13
A14
A15
A16
PGM
VCC
VPP
CE
O15
O14
O13
O12
O11
O10
O9
O8
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
O0
O1
O2
O3
O4
O5
O6
O7
GND
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
O12
O11
O10
O9
O8
GND
NC
O7
O6
O5
O4
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
O3
O2
O1
O0
OE
DC
A0
A1
A2
A3
A4
O13
O14
O15
CE
VPP
DC
VCC
PGM
A16
A15
A14
3
0632F–EPROM–12/07
AT27C2048
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce transient
voltage excursions. Unless accommodated by the system design, these transients may exceed
datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency,
low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor
should be connected between the VCC and Ground terminals of the device, as close to the
device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards
with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again con-
nected between the VCC and Ground terminals. This capacitor should be positioned as close as
possible to the point where the power supply is connected to the array.
4. Block Diagram
Note: 1. Maximum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is
VCC + 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns.
5. Absolute Maximum Ratings*
Temperature Under Bias............................... -55°C to +125°C
Storage Temperature .................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on A9 with
Respect to Ground ......................................-2.0V to +14.0V(1)
VPP Supply Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
GND
VPP
VCC DATA OUTPUTS
O0 - O15
OE, CE AND
PROGRAM LOGIC
Y DECODER
X DECODER
OUTPUT
BUFFERS
Y-GATING
CELL MATRIX
IDENTIFICATION
A0 - A17
ADDRESS
INPUTS
OE
CE
4
0632F–EPROM–12/07
AT27C2048
Notes: 1. X can be VIL or VIH.
2. Refer to the Programming characteristics.
3. VH = 12.0 ± 0.5V.
4. Two identifier words may be selected. All Ai inputs are held low (VIL), except A9, which is set to VH, and A0, which is toggled
low (VIL) to select the Manufacturer’s Identification word and high (VIH) to select the Device Code word.
5. Standby VCC current (ISB) is specified with VPP = VCC. VCC > VPP will cause a slight increase in ISB.
Notes: 1. VCC must be applied simultaneously or before VPP
, and removed simultaneously or after VPP
.
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP
.
6. Operating Modes
Mode/Pin CE OE PGM Ai VPP Outputs
Read VIL VIL X(1) Ai X(1) DOUT
Output Disable X VIH X X X High Z
Standby VIH XX X X
(5) High Z
Rapid Program(2) VIL VIH VIL Ai VPP DIN
PGM Verify VIL VIL VIH Ai VPP DOUT
PGM Inhibit VIH XX X V
PP High Z
Product Identification(4) VIL VIL X
A9 = VH(3)
A0 = VIH or VIL
A1 - A16 = VIL
VCC Identification Code
7. DC and AC Operating Conditions for Read Operation
AT27C2048
-55 -90
Industrial Operating Temperature (Case) -40°C - 85°C-40°C - 85°C
VCC Power Supply 5V ± 10% 5V ± 10%
8. DC and Operating Characteristics for Read Operation
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC ± 1µA
ILO Output Leakage Current VOUT = 0V to VCC ± 5µA
IPP1(2) VPP(1) Read/Standby Current VPP = VCC 10 µA
ISB VCC(1) Standby Current
ISB1 (CMOS)
CE = VCC ± 0.3V 100 µA
ISB2 (TTL)
CE = 2.0 to VCC + 0.5V 1mA
ICC VCC Active Current f = 5 MHz, IOUT = 0 mA, CE = VIL 35 mA
VIL Input Low Voltage -0.6 0.8 V
VIH Input High Voltage 2.0 VCC + 0.5 V
VOL Output Low Voltage IOL = 2.1 mA 0.4 V
VOH Output High Voltage IOH = -400 µA 2.4 V
5
0632F–EPROM–12/07
AT27C2048
Note: 2, 3, 4, 5. See the AC Waveforms for Read Operation diagram.
10. AC Waveforms for Read Operation(1)
Notes: 1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.
3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
9. AC Characteristics for Read Operation
Symbol Parameter Condition
AT27C2048
Units
-55 -90
Min Max Min Max
tACC(3) Address to Output Delay CE = OE
= VIL
55 90 ns
tCE(2) CE to Output Delay OE = VIL 55 90 ns
tOE(2)(3) OE to Output Delay CE = VIL 20 35 ns
tDF(4)(5) OE or CE High to Output Float, Whichever Occurred First 20 20 ns
tOH(4) Output Hold from Address, CE or OE, Whichever
Occurred First 70 ns
6
0632F–EPROM–12/07
AT27C2048
11. Input Test Waveforms and Measurement Levels
For -55 devices only:
tR, tF < 5 ns (10% to 90%)
For -90 devices:
tR, tF < 20 ns (10% to 90%)
12. Output Test Load
Note: CL = 100 pF including jig capacitance, except for the -55 devices, where CL = 30 pF.
13. Pin Capacitance
Note: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Symbol Typ Max Units Conditions
CIN 410pFV
IN = 0V
COUT 812pFV
OUT = 0V
7
0632F–EPROM–12/07
AT27C2048
14. Programming Waveforms(1)
Notes: 1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.
2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the AT27C2048, a 0.1 µF capacitor is required across VPP and ground to suppress spurious voltage
transients.
15. DC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Symbol Parameter Test Conditions
Limits
UnitsMin Max
ILI Input Load Current VIN = VIL, VIH ±10 µA
VIL Input Low Level -0.6 0.8 V
VIH Input High Level 2.0 VCC + 0.5 V
VOL Output Low Voltage IOL = 2.1 mA 0.4 V
VOH Output High Voltage IOH = -400 µA 2.4 V
ICC2 VCC Supply Current (Program and Verify) 50 mA
IPP2 VPP Supply Current CE = VIL 30 mA
VID A9 Product Identification Voltage 11.5 12.5 V
8
0632F–EPROM–12/07
AT27C2048
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP
.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven –
see timing diagram.
3. Program Pulse width tolerance is 50 µsec ± 5%.
16. AC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Symbol Parameter Test Conditions(1)
Limits
UnitsMin Max
tAS Address Setup Time
Input Rise and Fall Times
(10% to 90%) 20 ns
Input Pulse Levels
0.45V to 2.4V
Input Timing Reference Level
0.8V to 2.0V
Output Timing Reference Level
0.8V to 2.0V
2µs
tOES OE Setup Time 2 µs
tDS Data Setup Time 2 µs
tAH Address Hold Time 0 µs
tDH Data Hold Time 2 µs
tDFP OE High to Output Float Delay(2) 0130ns
tVPS VPP Setup Time 2 µs
tVCS VCC Setup Time 2 µs
tPW PGM Program Pulse Width(3) 47.5 52.5 µs
tOE Data Valid from OE 150 ns
tPRT
VPP Pulse Rise Time During
Programming 50 ns
17. Atmel’s 27C2048 Intergrated Product Identification Code
Codes
Pins
Hex DataA0 O15-O8 O7 O6 O5 O4 O3 O2 O1 O0
Manufacturer 0 0 00011110 001E
Device Type 1 0 11110111 00F7
9
0632F–EPROM–12/07
AT27C2048
18. Rapid Programming Algorithm
A 50 µs CE pulse width is used to program. The address is set to the first location. VCC is raised
to 6.5V and VPP is raised to 13.0V. Each address is first programmed with one 50 µs CE pulse
without verification. Then a verification/reprogramming loop is executed for each address. In the
event a word fails to pass verification, up to 10 successive 50 µs pulses are applied with a verifi-
cation after each pulse. If the word fails to verify after 10 pulses have been applied, the part is
considered failed. After the word verifies properly, the next address is selected until all have
been checked. VPP is then lowered to 5.0V and VCC to 5.0V. All words are read again and com-
pared with the original data to determine if the device passes or fails.
10
0632F–EPROM–12/07
AT27C2048
19. Ordering Information
Note: 1. The 40-lead VSOP package is not recommended for new designs.
19.1 Standard Package
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
55 35 0.1 AT27C2048-55JI
AT27C2048-55PI
AT27C2048-55VI
44J
40P6
40V(1)
Industrial
(-40°C to 85°C)
90 35 0.1 AT27C2048-90JI
AT27C2048-90PI
AT27C2048-90VI
44J
40P6
40V(1)
Industrial
(-40°C to 85°C)
Note: Not recommended for new designs. Use Green package option.
19.2 Green Package (Pb/Halide-free)
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
55 35 0.1 AT27C2048-55JU
AT27C2048-55PU
44J
40P6
Industrial
(-40°C to 85°C)
90 35 0.1 AT27C2048-90JU
AT27C2048-90PU
44J
40P6
Industrial
(-40°C to 85°C)
Package Type
44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)
40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
40V 40-lead, Plastic Thin Small Outline Package (VSOP)
11
0632F–EPROM–12/07
AT27C2048
20. Packaging Information
20.1 44J – PLCC
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 4.191 – 4.572
A1 2.286 – 3.048
A2 0.508 – –
D 17.399 – 17.653
D1 16.510 – 16.662 Note 2
E 17.399 – 17.653
E1 16.510 – 16.662 Note 2
D2/E2 14.986 – 16.002
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
1.14(0.045) X 45˚ PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1 D2/E2
B
e
E1 E
D1
D
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) B
44J
10/04/01
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
12
0632F–EPROM–12/07
AT27C2048
20.2 40P6 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP) B
40P6
09/28/01
PIN
1
E1
A1
B
REF
E
B1
C
L
SEATING PLANE
A
0º ~ 15º
D
e
eB
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 4.826
A1 0.381 – –
D 52.070 – 52.578 Note 2
E 15.240 – 15.875
E1 13.462 – 13.970 Note 2
B 0.356 – 0.559
B1 1.041 – 1.651
L 3.048 – 3.556
C 0.203 – 0.381
eB 15.494 – 17.526
e 2.540 TYP
Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
13
0632F–EPROM–12/07
AT27C2048
20.3 40V – VSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
40V, 40-lead (10 x 14 mm Package) Plastic Thin Small Outline
Package, Type I (VSOP) B
40V
10/18/01
PIN 1
D1 D
Pin 1 Identifier
b
e
EA
A1
A2 SEATING PLANE
0º ~ 8º c
L
L1
GAGE PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MO-142, Variation CA.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 13.80 14.00 14.20
D1 12.30 12.40 12.50 Note 2
E 9.90 10.00 10.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC
0632F–EPROM–12/07
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