HX6408
512k x 8 STATIC RAM
The 512K x 8 Radiation Hardened Static RAM is a
high performance 524,288 word x 8-bit static random
access memory with optional industry-standard
functionality. It is fabricated with Honeywell’s radiation
hardened Silicon On Insulator (SOI) technology, and
is designed for use in low voltage systems operating
in radiation environments. The RAM operates over the
full military temperature range and requires only a
single 3.3 V ± 0.3V power supply. Power consumption
is typically <30 mW @ 1MHz in write mode, <14 mW
@ 1MHz in read mode, and is less than 5 mW when
in standby mode.
Honeywell’s enhanced SOI V technology is radiation
hardened through the use of advanced and
proprietary design, layout and process hardening
techniques.
The SOI V low power process is a SOI CMOS
technology with an 80 Å gate oxide and a minimum
drawn feature size of 0.35 µm. Additional features
include tungsten via and contact plugs, Honeywell’s
proprietary SHARP planarization process and a lightly
doped drain (LDD) structure for improved short
channel reliability. A seven transistor (7T) memory cell
is used for superior single event upset hardening,
while three layer metal power busing and the low
collection volume SOI substrate provide improved
dose rate hardening.
FEATURES
Fabricated with SOI V
Silicon On Insulator
0.35 mm Process (Leff = 0.28 µm)
Total Dose ≥ 3x105 and 1X106 rad(Si)
Neutron ≥1x1014 cm-2
Dynamic and Static Transient Upset
≥1x1010 rad(Si O2)/s (3.3 V)
Dose Rate Survivability ≥1x1012 rad(Si O2)/s
Soft Error Rate
≤1x10-10 Upsets/bit-day (3.3 V)
No Latchup
Read/Write Cycle Times
≤20 ns, (3.3 V), -55 to 125°C
Typical Operating Power (3.3 V)
<14 mW @ 1MHz Read
<30 mW @ 1MHz Write
<5 mW Standby mode
Asynchronous Operation
CMOS Compatible I/O
Single Power Supply,
3.3 V ± 0.3 V
Operating Range is
-55°C to +125°C
36-Lead Flat Pack Package
Optional Low Power Sleep
Mode
HX6408
2 www.honeywell.com
FUNCTIONAL DIAGRAM 36 LEAD FLAT PACK PINOUT
SIGNAL DEFINITIONS
A: 0-18 Address input pins, which select a particular eight-bit word within the memory array.
DQ: 0-7 Bidirectional data pins, which serve as data outputs during a read operation and as data inputs
during a write operation.
NCS Negative chip select, when at a low level allows normal read or write operation. When at a high level
NCS forces the SRAM to a precharge condition, holds the data output drivers in a high impedance
state. If this signal is not used it must be connected to VSS.
NWE Negative write enable, when at a low level activates a write operation and holds the data output
drivers in a high impedance state. When at a high level NWE allows normal read operation.
NOE Negative output enable, when at a high level holds the data output drivers in a high impedance
state. When at a low level, the data output driver state is defined by NCS, NWE and NSL. This
signal is asynchronous.
NSL Not sleep, when at a high level allows normal operation. When at a low level NSL forces the SRAM
to a precharge condition, holds the data output drivers in a high impedance state and disables all the
input buffers except the NCS and NOE input buffers. If this signal is not used it must be connected
to VDD. This signal is asynchronous. The HX6408 may be ordered without the sleep mode option
and pin 36 is then a NC.
All controls must be enabled
for signal to pass.
# = number of buffers,
Default = 1
Signal Signal
1 = enabled
#
Address
Decoder
Memory
Arra
y
DQ(0:7)
WE • CS
NOE
NCS
NSL
NWE
An
Timing \ Control
NWE • CS
A0 1
A1 2
A2 3
A3 4
A4 5
NCS 6
D0 7
D1 8
VDD 9
VSS 10
D2 11
D3 12
NWE 13
A5 14
A6 15
A7 16
A8 17
A9 18
36 (NSL)
35 A18
34 A17
33 A16
32 A15
31 NOE
30 D4
29 D5
28 VSS
27 VDD
26 D6
25 D7
24 A14
23 A13
22 A12
21 A11
20 A10
19 NC*
* = No Connect
HX6408
Top View
HX6408
3 www.honeywell.com
TRUTH TABLE
NCS NSL NWE NOE Mode DQ
L H H L Read Data Out
L H L X Write Data In
H X X X Deselected High Z
X L X X Sleep High Z
X: VI = VIH or VIL,
NOE=H: High Z output state maintained for NCS=X, NWE=X
RADIATION
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature
range after the specified total ionizing radiation dose.
All electrical and timing performance parameters will
remain within specifications. Total dose hardness is
assured by wafer level testing of process monitor
transistors and RAM product using 10 KeV X-ray.
Transistor gate threshold shift correlations have been
made between 10 KeV X-rays applied at a dose rate of
1x105 rad(SiO2)/min at T= 25°C and gamma rays
(Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse, up to the specified transient
dose rate upset specification, when applied under
recommended operating conditions. It is recommended
to provide external power supply decoupling capacitors
to maintain VDD voltage levels during transient events.
The SRAM will meet any functional or electrical
specification after exposure to a radiation pulse up to
the transient dose rate survivability specification, when
applied under recommended operating conditions.
Note that the current conducted during the pulse by the
RAM inputs, outputs, and power supply may
significantly exceed the normal operating levels. The
application design must accommodate these effects.
Neutron Radiation
The SRAM will meet any functional or timing
specification after exposure to the specified neutron
fluence under recommended operating or storage
conditions. This assumes an equivalent neutron energy
of 1 MeV.
Soft Error Rate
The SRAM is capable of meeting the specified Soft
Error Rate (SER), under recommended operating
conditions.
This hardness level is defined by the Adams 90%
worst case cosmic ray environment for
geosynchronous orbits.
Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under
recommended operating conditions. Fabrication with
the SOI substrate material provides oxide isolation
between adjacent PMOS and NMOS transistors and
eliminates any potential SCR latchup structures.
Sufficient transistor body tie connections to the p- and
n-channel substrates are made to ensure no
source/drain snapback occurs.
HX6408
4 www.honeywell.com
RADIATION HARDNESS RATINGS (1)
Parameter Limits (2) Units Test Conditions
Total Dose ≥3X105
≥1X106
rad(Si) TA=25°C
Cobalt 60
Transient Dose Rate Upset ≥1X1010 rad(Si O2)/s Pulse width ≤50 ns
VDD=3.6V, TA=25°C, x-
ray
Transient Dose Rate Survivability ≥1X1012 rad(Si O2)/s Pulse width ≤50 ns, X-
ray,VDD=3.6V,
TA=25°C
Soft Error Rate <1X10-10 Upsets/bit-day TA= 85°C, Adams 90%
worst case environment
Neutron Fluence ≥1X1014 N/cm2 1MeV equivalent
energy, Unbiased,
TA=25°C
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=3.0V to 3.6V, TA=-55oC to 125oC
ABSOLUTE MAXIMUM RATINGS (1)
Rating Symbol Parameter
Min Max
Units
VDD Supply Voltage Range (2) -0.5 4.6 V
VPIN Voltage on Any Pin (2) -0.5 VDD+0.5 V
TSTORE Storage Temperature (Zero Bias) -65 150 °C
TSOLDER Soldering Temperature (5 seconds) 270 °C
PD Maximum Power Dissipation (3) 2.5 W
IOUT DC or Average Output Current 25 mA
VPROT ESD Input Protection Voltage (4) 2000 V
36 Pin FP 2 ΘJC Thermal Resistance (Jct-to-Case)
°C/W
TJ Junction Temperature 175 °C
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is
not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this
specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DSEC certified lab.
RECOMMENDED OPERATING CONDITIONS
Description Symbol Parameter Min Typ Max Units
VDD Supply Voltage (referenced to VSS) 3.0 3.3 3.6 V
TA Ambient Temperature -55 25 125 °C
VPIN Voltage on Any Pin (referenced to VSS) -0.3 VDD+0.3 V
VDDRAMP VDD Turn on ramp time 50 ms
HX6408
5 www.honeywell.com
DC ELECTRICAL CHARACTERISTICS
Worst Case (1) Symbol Parameter Min Max Units Test Conditions
IDDSB Static Supply Current
TA=25°C
TA=125°C
5
10
mA
VDD=max, Iout=0mA,
Inputs Stable
IDDOP3 Static Supply Current
Deselected
24 mA VDD=max, Iout=0mA,
f=fmax, NSL=NCS=VIH (2)
(3)
IDDOPW Dynamic Supply Current,
Selected (Write)
1 MHz
2 MHz
10 MHz
25 MHz
40 MHz
9
18
89
160
260
mA
VDD=max, Iout=0mA,
NSL=VIH, NCS=VIL (1) (3)
IDDOPR Dynamic Supply Current,
Selected (Read)
1 MHz
2 MHz
10 MHz
25 MHz
40 MHz
4
8
40
100
160
mA
VDD=max, Iout=0mA,
NSL=VIH, NCS=VIL (1) (3)
IDDOP1 Dynamic Supply Current,
Deselected
1.5 mA VDD=max, Iout=0mA,
f=1MHz, NSL=VIH (2) (3)
IDDOP2 Dynamic Supply Current,
Sleep
0.2 mA VDD=max, Iout=0mA,
f=1MHz, NSL=VIL (2) (3)
II Input Leakage Current -5 5 µA Vss VI VDD
IOZ Output Leakage Current -10 10 µA Vss VIO
VDD output = high Z
VIL Low-Level Input Voltage 0.3xVDD V VDD=3.0V
VIH High-Level Input Voltage 0.7xVDD V VDD=3.6V
VOL Low-Level Output Voltage 0.4 V VDD=3.0V, IOL = 8mA
VOH High-Level Output Voltage 2.7 V VDD=3.0V, IOH = 4mA
(1) Worst case operating conditions: VDD=3.0V to 3.6V, -55°C to +125°C, post total dose at 25°C.
(2) All inputs switching. DC average current.
(3) All dynamic operating mode current measurements (IDDOPx) exclude standby mode current (IDDSB)
CAPACITANCE (1)
Worst Case (1) Symbol Parameter Min Max Units Test Conditions
CI Input Capacitance 9 pF VI=VDD or VSS, f=1 MHz
CO Output Capacitance 8 pF VIO=VDD or VSS, f=1 MHz
(1) This parameter is tested during initial design characterization only.
HX6408
6 www.honeywell.com
DATA RETENTION CHARACTERISTICS
Worst Case (2) Symbol Parameter Typical
(1) Min Max Units Test Conditions
VDR Data Retention Voltage 2.0 V NCS=VDR
VI=VDR or VSS
IDR Data Retention Current 3 mA NCS=VDD=VDR
VI=VRD or VSS
(1) Typical operating conditions: TA=25°C, pre-radiation.
(2) Worst case operating conditions: TA=-55°C to +125°C, post dose at 25°C
TESTER EQUIVALENT LOAD CIRCUIT
* CL = 5pf for TWQZ, TSHQZ, TPLQZ, and TGHQZ
Tester AC Timing Characteristics
Input Levels *
V
DD
V
SS
Output Sense
Levels
V
DD/2
VDD – 0.4V
0.4V
High Z
High Z
(
VDD/2
)
+ 0.2V
(VDD/2) - 0.2V
High Z = VDD/2
* Input rise and fall times <5 ns.
DUT
Output
Valid Low
Output
Valid High
Output
1.9V
249
V1
V2
CL < 50 pf *
HX6408
7 www.honeywell.com
ASYCHRONOUS READ CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
-55 to 125°C
Symbol
Parameter
Typical
(2) Min Max
Units
TAVAVR Address Read Cycle Time 300KRad
300kRad and 1MRad
20
25
ns
TAVQV Address Access Time 300KRad
300kRad and 1MRad
20
25
ns
TAXQX Address Change to Output Invalid Time (4) 5 ns
TSLQV Chip Select Access Time 300KRad
300kRad and 1MRad
20
25
ns
TSLQX Chip Select Output Enable Time (4) 4 ns
TSHQZ Chip Select Output Disable Time (4) 4 ns
TPHQV Sleep Enable Access Time 25 ns
TPHQX Sleep Enable Output Enable Time 5 ns
TPLQZ Sleep Enable Output Disable Time 10 ns
TGLQV Output Enable Access Time 5 ns
TGLQX Output Enable Output Enable Time (4) 0.5 ns
TGHQZ Output Enable Output Disable Time (4) 3 ns
(1) Test conditions: input switching levels, VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels shown in
the Tester AC Timing Characteristics table, capacitive output loading CL≥50 pF, or equivalent capacitive output loading CL=5 pF for
TSHQZ, TPLQZ TGHQZ. For CL>50 pF, derate access times by 0.02 ns/pF (typical).
(2) Typical operating conditions: VDD=3.3V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=3.0V to 3.6V, TA=-55°C to 125°C, post total dose at 25°C.
(4) These parameters can be tested as pass/fail.
ADDRESS
NCS
DATA OUT
NSL
NOE
DATA VALID
HIGH
IMPEDANCE
TAVAVR
TSLQV
TPHQX
TPHQV
TGLQV
TAXQX
TSLQX
TGLQX
TAV
Q
V
TSHQZ
TPLQZ
TGHQZ
HX6408
8 www.honeywell.com
Precharge Pulse on Data Outputs
Precharge Pulses are narrow pulses on the data
output pins when a user may expect it to be a “low”
logic condition during a READ cycle. During the start
of each Read operation, two actions take place: the
internal data bus is pre-charged to a high state
(regardless of the previous value) and then the output
latch is opened. Since the latch is opened at the start
of the Read operation, the internal “high” pre-charge
value will show up at the output. This will only be
apparent on Reads of two “low” values (low to low).
Please read the Application Note AN312 Data Output
Precharge Pulse Condition for detailed timing
information and mitigation actions.
Pre-Charge Pulses on the Data Output pins - Memory Data is all “0s”.
Precharge Pulses on Data Outputs after Address bits transition when NOE is kept low for entire cycle.
ASYNCHRONOUS WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
-55 to 125°C
Symbol
Parameter
Typical
(2) Min Max
Units
TAVAVW Write Cycle Time (4) 300KRad
300kRad and 1MRad
20
25
ns
TWLWH Write Enable Write Pulse Width 300KRad
300kRad and 1MRad
15
25
ns
TSLWH Chip Select to End of Write Time 300KRad
1MRad
16
20
ns
TDVWH Data Valid to End of Write Time 300KRad
1MRad
12
15
ns
TAVWH Address Valid to End of Write Time 300KRad
1MRad
20
25
ns
TWHDX Data Hold after End of Write Time (6) 0.5 ns
TAVWL Address Valid Setup to Start of Write Time (6) 1.5 ns
TWHAX Address Valid Hold after End of Write Time (6) 3 ns
TWLQZ Write Enable to Output Disable Time (6) 6 ns
TWHQX Write Disable to Output Enable Time (6) 6 ns
TWHWL Write Disable to Write Enable Pulse Width (5) 5 ns
TPHWH Sleep Disable to Write Disable Time 25 ns
(1) Test conditions: input switching levels, VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels shown in
the Tester AC Timing Characteristics table, capacitive output loading ≥50 pF, or equivalent capacitive load 5 pF for TWLQZ.
(2) Typical operating conditions: VDD=3.3V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=3.0V to 3.6V, -55°C to 125°C, post total dose 25°C
(4) TAVAVW = TWLWH + TWHWL
(5) Guaranteed but not tested.
(6) These parameters can be tested as pass/fail.
HX6408
9 www.honeywell.com
DYNAMIC ELECTRICAL CHARACTERISTICS
Asynchronous Operation
The RAM is asynchronous in operation. Read and
Write cycles are controlled by NWE, NCS, NSL, and
Address signals.
Read Operation
To perform a valid read operation, both chip select
and output enable (NOE) must be low and not sleep
(NSL) and write enable (NWE) must be high. The
output drivers can be controlled independently by the
NOE signal.
To perform consecutive read operations, NCS is
required to be held continuously low, NSL held
continuously high, and the toggling of the addresses
will start the new read cycle.
It is important to have the address bus free of noise
and glitches, which can cause inadvertent read
operations. The control and address signals should
have rising and falling edges that are fast (<5 ns) and
have good signal integrity (free of noise, ringing or
steps associated reflections).
For an address activated read cycle, NCS and NSL
must be valid prior to or coincident with the address
edge transition(s). Any amount of toggling or skew
between address edge transitions is permissible;
however, data outputs will become valid TAVQV time
following the latest occurring address edge transition.
The minimum address activated read cycle time is
TAVAV. When the RAM is operated at the minimum
address activated read cycle time, the data outputs
will remain valid on the RAM I/O until TAXQX time
following the next sequential address transition.
To control a read cycle with NCS, all addresses and
NSL must be valid prior to or coincident with the
enabling NCS edge transition. Address or NSL edge
transitions can occur later than the specified setup
times to NCS; however, the valid data access time will
be delayed. Any address edge transition, which
occurs during the time when NCS is low, will initiate a
new read access, and data outputs will not become
valid until TAVQV time following the address edge
transition. Data outputs will enter a high impedance
state TSHQZ time following a disabling NCS edge
transition.
To control a read cycle with NSL, all addresses and
NCS must be valid prior to or coincident with the
enabling NSL edge transition. Address or NCS edge
ADDRESS
NCS
DATA OUT
NSL
HIGH
IMPEDANCE
TAVAVW
TSLWH
T
WLWH
TPHWH
T
WHWL
T
WHDX
TWHAX
NWE
TAVWL
TAVWH
DATA IN DATA VALID
TWL
Q
Z TWHQX
TDVWH
HX6408
10 www.honeywell.com
transitions can occur later than the specified setup
times to NSL; however, the valid data access time will
be delayed. Any address edge transition, which
occurs during the time when NSL is high will initiate a
new read access, and data outputs will not become
valid until TAVQV time following the address edge
transition. Data outputs will enter a high impedance
state TPLQZ time following a disabling NSL edge
transition.
Write Operation
To perform a write operation, both NWE and NCS
must be low, and NSL must be high.
Consecutive write cycles can be performed by
toggling one of the control signals while the other
remains in their “write” state (NWE or NCS held
continuously low, or NSL held continuously high). At
least one of the control signals must transition to the
opposite state between consecutive write operations.
The write mode can be controlled via three different
control signals: NWE, NCS, and NSL. All three modes
of control are similar, except the NCS and NSL
controlled modes actually disable the RAM during the
write recovery pulse. NSL fully disables the RAM
decode logic and input buffers for power savings.
Only the NWE controlled mode is shown in the table
and diagram on the previous page for simplicity;
however, each mode of control provides the same
write cycle timing characteristics. Thus, some of the
parameter names referenced below are not shown in
the write cycle table or diagram, but indicate which
control pin is in control as it switches high or low. To
write data into the RAM, NWE and NCS must be held
low and NSL must be held high for at least
WLWH/TSLSH/TPHPH time. Any amount of edge
skew between the signals can be tolerated, and any
one of the control signals can initiate or terminate the
write operation. The DATA IN must be valid TDVWH
time prior to switching high.
For consecutive write operations, write pulses (NWE)
must be separated by the minimum specified
WHWL/TSHSL/TPLPL time. Address inputs must be
valid at least TAVWL/TAVSL/TAVPH time before the
enabling NWE/NCS/NSL edge transition, and must
remain valid during the entire write time. A valid data
overlap of write pulse width time of TDVWH/TDVSH/
TDVPL, and an address valid to end of write time of
TAVWH/TAVSH/TAVPL also must be provided for
during the write operation. Hold times for address
inputs and data inputs with respect to the disabling
NWE/NCS/NSL edge transition must be a minimum of
TWHAX/TSHAX/TPLPX time and TWHDX/TSHDX
/TPLDX time, respectively. The minimum write cycle
time is TAVAV.
QUALITY AND RADIATION HARDNESS ASSURANCE
Honeywell maintains a high level of product integrity through process control, utilizing statistical process
control, a complete “Total Quality Assurance System,” a computer data base process performance
tracking system and a radiation-hardness assurance strategy.
The radiation hardness assurance strategy starts with a technology that is resistant to the effects of
radiation. Radiation hardness is assured on every wafer by irradiating test structures as well as SRAM
product, and then monitoring key parameters, which are sensitive to ionizing radiation. Conventional MIL-
STD-883 TM 5005 Group E testing, which includes total dose exposure with Cobalt 60, may also be
performed as required. This Total Quality approach ensures our customers of a reliable product. It starts
with process development and continuing through product qualification and screening.
SCREENING LEVELS
Honeywell offers several levels of device screening to meet your system needs. “Engineering Devices” are
available with limited performance and screening for operational evaluation testing. As a QML supplier,
Honeywell also offers QML Class Q and V devices per MIL-PRF-38535 and are available per the
applicable Standard Microcircuit Drawing (SMD). QML devices offer ease of procurement by eliminating
the need to create detailed specifications and offer benefits of improved quality and cost savings through
standardization. The HX6408 is available per Standard Microcircuit Drawing (SMD) 5962-06203.
HX6408
11 www.honeywell.com
RELIABILITY
Honeywell understands the stringent reliability
requirements for space and defense systems and has
extensive experience in reliability testing on programs
of this nature. This experience is derived from
comprehensive testing of VLSI processes. Reliability
attributes of the SOI process were characterized by
testing specially designed irradiated and non-
irradiated test structures from which specific failure
mechanisms were evaluated. These specific
mechanisms included, but were not limited to, hot
carriers, electromigration and time dependent
dielectric breakdown. This data was then used to
make changes to the design models and process to
ensure more reliable products.
In addition, the reliability of the SOI process and
product in a military environment is monitored by
testing irradiated and non-irradiated circuits in
accelerated dynamic life test conditions. Packages
were qualified for product use after undergoing
Groups B & D testing as outlined in MIL-STD-883, TM
5005, Class S. Quality conformance testing is
performed as an option on all production lots to
ensure the ongoing reliability of the product.
PACKAGING
The 512K x 8 SRAM is offered in a commercially
compatible 36-lead flat pack. This package is
constructed of multi-layer ceramic (Al2O3) and
contains internal power and ground planes.
Parentheses denote pin options. These pins are
available as NC to conform to commercial
standards. All NC (no connect) pins should be
connected to VSS to prevent charge build up in
the radiation environment.
This SRAM is also offered as a Known Good Die
(KGD). These parts are fully tested and
screened and delivered in die form. KGD are
often stacked or integrated with other chips into
multi-chip modules to reduce the overall size of
the electronics.
KGD may contain stub bonds and require
compound wire bonding.
PACKAGE OUTLINE
COMMON DIMENSIONS
SYM
MIN.
NOM.
MAX.
A .102 .113 .125
A1 .085 .095 .105
B .016 .018 .020
C .004 .006 .008
D .910 .920 .930
E .045 .050 .055
E1 .832 .840 .848
L ----- .450 -----
Q ----- .104 -----
HX6408
www.honeywell.com
12
ORDERING INFORMATION (1) (4)
(1) Orders may be faxed to 763-954-2051. Please contact our Customer Service Representative at 1-800-323-8295 for further information.
(2) Engineering Device Description: Parameters are tested -55°C to 125°C, 24 hour burn-in, no radiation Guaranteed.
(3) With the Non-Sleep Mode option, Pin 36 is a no-connect (NC), and is not wirebonded to the chip. With the Sleep Mode, Pin 36 has the NSL
function.
(4) The HX6408 is available per Standard Microcircuit Drawing (SMD) 5962-06203.
(5) Total Dose Hardness Level H can only be procured with a 25ns Access Time.
FIND OUT MORE
For more information visit us online at www.honeywell.com/radhard.com or contact us at 800-323-8295 (763-954-2474
internationally).
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others.
H X 6408 S H X
Source
H = Honeywell
PROCESS
X = SOI
PACKAGE DESIGNAT ION
X = 36 Lead FP
K = Known Good Die
PART NUMBER
SCREEN LEVEL
V = QML Class V
Q = QML Class Q
Z = Class V Equivalent
E = Eng. Model (2)
TOTAL DOSE HARDNESS
F = 3x105 rad (Si)
H = 1x106 rad (Si) (5)
N = No Level Guaranteed (2)
N
MODE (3)
N = Non-Sleep Mode
M = Sleep Mode
Form #900918
August 2006
©2006 Honeywell International Inc.
20
ACCESS TIME
20 ns (5)
25 ns
Honeywell
12001 Highway 55
Plymouth, MN 55441
Tel: 800-323-8295
www.honeywell.com/radhard
