TIP122TUF129 - FAIRCHILD SEMICONDUCTOR

November 2012

SG1577 • Rev. 1.0.6

SG1577 — Dual Synchronous DC/DC Controller

SG1577

Dual Synchronous DC/DC Controller

Features

 Integrated Two Sets of MOSFET Drivers

 Two Independent PWM Controllers

 Constant Frequency Operation: Free-running Fixed

Frequency Oscillator Programmable: 60 kHz to

320 kHz

 Wide Range Input Supply Voltage: 8~15 V

 Programmable Output as Low as 0.7 V

 Internal Error Amplifier Reference Voltage:

0.7 V ±1.5%

 Two Soft-Start / EN Functions

 Programmable Over-Current Protection (OCP)

 30 V HIGH Voltage Pin for Bootstrap Voltage

 Output Over-Voltage Protection (OVP)

 SOP 20-Pin

Applications

 CPU and GPU Vcore Power Supply

 Power Supply Requiring Two Independent Outputs

Description

The SG1577 is a high-efficiency, voltage-mode, dual-

channel, synchronous DC/DC PWM controller for two

independent outputs. The two channels are operated

out of phase. The internal reference voltage is trimmed

to 0.7 V ±1.5%. It is connected to the error amplifier’s

positive terminal for voltage feedback regulation. The

soft-start circuit ensures the output voltage can be

gradually and smoothly increased from zero to its final

regulated value. The soft-start pin can also be used for

chip-enable function. When two soft-start pins are

grounded, the chip is disabled and the total operation

current can be reduced to under 0.55 mA. The fixed-

frequency is programmable from 60 kHz to 320 kHz.

The Over-Current Protection (OCP) level can be

programmed by an external current sense resistor. It

has two integrated sets of internal MOSFET drivers.

SG1577 is available in the 20-pin SOP package.

Ordering Information

Part Number Operating

Temperature Range Package Packing

Method

SG1577SY -40°C to +85°C 20-Lead, Small Outline Package (SOP-20) Tape & Reel

SG1577 • Rev. 1.0.6 2

SG1577 — Dual Synchronous DC/DC Controller

Application Diagram

Figure 1. Typical Application

Internal Block Diagram

Figure 2. Functional Block Diagram

SG1577 • Rev. 1.0.6 3

SG1577 — Dual Synchronous DC/DC Controller

Marking Diagram

Figure 3. Top Mark

F ZXYTT

SG1577

TPM

F: Fairchild Logo

Z: Plant Code

X: 1-Digit Year Code for SOP

Y: 1-Digit Week Code for SOP

TT: 2-Digit Die Run Code

T: Package Type (S = SOP)

P: Z=Lead Free + ROHS

Compatible

Y=Green Package

M: Manufacture Flow Code

SG1577 • Rev. 1.0.6 4

SG1577 — Dual Synchronous DC/DC Controller

Pin Configuration

Figure 4. SOP-20 Pin Configuration (Top View)

Pin Definitions

Name Pin # Type Description

RT 1 Frequency Select

Switching frequency programming pin. An external resistor connecting from

this pin to GND can program the switching frequency. The switching

frequency would be 60 kHz when RT is open and become 320 kHz when a

30 kΩ RT resistor is connected.

IN1 2 Feedback

Inverting input of the error amplifier. It is normally connected to the

switching power supply output through a resistor divider.

COMP1 3 Compensation

Output of the error amplifier and input to the PWM comparator. It is used

for feedback loop compensation.

SS1/ENB 4 Soft Start/Enable

A 10 µA internal current source charging an external capacitor for soft start.

Pull down this pin and pin 17 can disable the chip.

CLP1 5 Over Current

Protection

Over-current protection for high-side MOSFET. Connect a resistor from this

pin to the high-side supply voltage to program the OCP level.

BST1 6 Boost Supply Supply for high-side driver. Connect to the internal bootstrap circuit.

DH1 7 High-Side Drive Channel 1, high-side MOSFET gate driver pin.

CLN1 8 Switch Node

Switch-node connection to inductor. For channel 1 high-side driver’s

reference ground.

DL1 9 Low-Side Drive Low-side MOSFET gate driver pin.

PGND 10 Driver Ground Driver circuit GND supply. Connect to low-side MOSFET GND.

VCC 11 Power Supply Supply voltage input.

DL2 12 Low-Side Drive Low-side MOSFET gate driver pin.

CLN2 13 Switch Node

Switch-node connection to inductor. For channel 2, high-side driver’s

reference ground.

DH2 14 High-Side Drive Channel 2 high-side MOSFET gate driver pin.

BST2 15 Boost Supply Supply for high-side driver. Connect to the internal bootstrap circuit.

CLP2 16 Over-Current

Protection

Over-current protection for the high-side MOSFET. Connect a resistor from

this pin to the high-side supply voltage to program the OCP level.

SS2/ENB 17 Soft-Start/Enable

A 10 µA internal current source charging an external capacitor for soft start.

Pull down this pin and pin 4 can disable the chip.

COMP2 18 Compensation

Output of the error amplifier and input to the PWM comparator. It is used

for feedback-loop compensation.

IN2 19 Feedback

Inverting input of the error amplifier. It is normally connected to the

switching power supply output through a resistor divider.

GND 20 Control Ground Control circuit GND supply.

SG1577 • Rev. 1.0.6 5

SG1577 — Dual Synchronous DC/DC Controller

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are given with

respect to the network ground terminal. Stresses beyond those listed under "absolute maximum ratings" may cause

permanent damage to the device.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage, VCC to GND 16 V

BST1(or 2) - CLN1(or 2) BST1(2) to CLN1(2) 16 V

CLN1(or 2) -GND CLN1(2) to GND for 100 ns Transient -4 18 V

BST1(or 2) - GND BST1(2) to GND for 100 ns Transient 30 V

DH1(or 2) - CLN1(or 2) 16 V

CLN1(or 2), DL1(or 2) -0.3 VCC+0.3 V

PGND PGND to GND ±1 V

ΘJA Thermal Resistance, Junction-to-Air 90 °C/W

TJ Operating Junction Temperature -40 +125 °C

TSTG Storage Temperature Range -65 +150 °C

ESD Human Body Model, JESD22-A114 2.5 kV

Charged Device Model, JESD22-C101 750 V

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage +8 +15 V

TA Operating Ambient Temperature -40 +85 °C

SG1577 • Rev. 1.0.6 6

SG1577 — Dual Synchronous DC/DC Controller

Electrical Characteristics

VCC=12 V, TA =25°C, unless otherwise noted.

Symbol Parameter Conditions Min. Typ. Max. Unit

Oscillator

fosc Oscillator Frequency RRT=OPEN 54 60 66

KHz

RRT=GND 288 320 352

fosc,rt Total Accuracy 20 kΩ＜RRT -10 10 %

DON_MAX Maximum Duty Cycle 85 90 95 %

Error Amplifier

VREF Internal Reference Voltage VCC=8 V, VCC=15 V 0.6895 0.7000 0.7105 V

△VREF Temperature Coefficient(1) T

A=0~85°C 0.03 mV/°C

AVOL Open-Loop Voltage Gain 77 dB

BW Unity Gain Bandwidth 3.5 MHz

PSRR Power Supply Rejection Ratio 50 dB

ISOURCE Output Source Current IN1=IN2=0.6 V 60 80 100 µA

ISINK Output Sink Current IN1=IN2=0.8 V 500 µA

VH COMP Output Voltage IN1=IN2=0.6 V 5 V

VL COMP Output Voltage IN1=IN2=0.8 V 100 mV

Soft Start

ISOURCE Soft-Start Charge Current VCLP＜VCLN 8 10 12 µA

ISINK Soft-Start Discharge Current VCLP＞VCLN 0.8 1.0 1.2 µA

Protections

IOSCET OC Sink Current VCC=12 V 90 120 150 µA

TOT Over-Temperature 150 °C

TOT_hys Over-Temperature Hysteresis 20 °C

VOVP Over-Voltage Protection of IN VOVP/VIN 112 125 %

Output

IDH High-Side Current Source VBST - VCLN=12 V,VDH -

VCLN=6 V 1.0 1.7 A

RDH High-Side Sink Resistor VBST - VCLN=12 V 3.3 4.0 Ω

IDL Low-Side Current Source VCC=12 V,VDL=6 V 1.0 1.7 A

RDL Low-Side Sink Resistor VCC=12 V 3.1 4 Ω

tDT Dead Time(2) V

CC=12 V, DH and DL=1000 pF 10 40 70 ns

Total Operating Current

ICC_OP Operating Supply Current VCC=12 V, No Load 3.3 4.3 5.3 mA

ICC_SBY Standby Current (Disabled) SS1/ENB=SS2/ENB=0 V 0.55 1.00 mA

Notes:

1. Not test in production, 30 pcs sample.

2. When VDL falls less than 2 V relative to VDH rising to 2 V.

SG1577 • Rev. 1.0.6 7

SG1577 — Dual Synchronous DC/DC Controller

Typical Performance Characteristics

Unless otherwise noted, values are for VCC=12 V, TA=+25°C, and according to Figure 1.

Figure 5. V5p0 Power On with 1.6 A Load Figure 6. V3p3 Power On with 3 A Load

Figure 7. V5p0 Power On with 15 A Load Figure 8. V3p3 Power On with 8 A Load

Figure 9. V5p0 Power Off with 15 A Load Figure 10. V3p3 Power Off with 8 A Load

SG1577 • Rev. 1.0.6 8

SG1577 — Dual Synchronous DC/DC Controller

Typical Performance Characteristics (Continued)

Unless otherwise noted, values are for VCC=12 V, TA=+25°C, and according to Figure 1.

Figure 11. 3p3 and V5p0 Phase Shift with L ight Load Figure 12. V3p3 and V5p0 Phase Shift

with Heavy Load

Figure 13. Dead Time with Light Load (Rise Edge) Figure 14. Dead Time with Light Load (Fall Edge)

Figure 15. Dead Time with Heavy Load (Rise Edge) Figure 16. Dead Time with Heavy Load (Fall Edge)

SG1577 • Rev. 1.0.6 9

SG1577 — Dual Synchronous DC/DC Controller

Typical Performance Characteristics (Continued)

Unless otherwise noted, values are for VCC=12 V, TA=+25°C, and according to Figure 1.

Figure 17. Load Transient Response (Step-Up)

20k Ω/22 nF in Compensation Loop Figure 18. Load Transient Response (Step-Down)

20 kΩ/22 nF in Compensation Loop

Figure 19. Over-Current Protection (OCP) Figure 20. Over-Current Protection (Hiccup Mode)

100

110

120

130

140

150

-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃

Temperature (oC)

Iocset (uA)

Iocset 1

Iocset 2

Figure 21. Over-Voltage Protection (OVP) Figure 22. IOCSET vs. Temperature

SG1577 • Rev. 1.0.6 10

SG1577 — Dual Synchronous DC/DC Controller

Functional Description

The SG1577 is a dual-channel voltage-mode PWM

controller. It has two sets of synchronous MOSFET

driving circuits. The two channels are running 180-

degrees out of phase. The following descriptions

highlight the advantages of the SG1577 design.

Soft-Start

An internal startup current (10 µA) flows out of SS/EN

pin to charge an external capacitor. During the startup

sequence, SG1577 isn’t enabled until the SS/ENB pin is

higher than 1.2 V. From 1.2 V to (1.2 + 1.6 x DON /

DON_MAX) V, PWM duty cycle gradually increases

following SS/ENB pin voltage to bring output rising. After

(1.2 + 1.6 x DON / DON_MAX) V, the soft-start period ends

and SS/ENB pin continually goes up to 4.8 V. When

input power is abnormal, the external capacitor on SS

pin is shorted to ground and the chip is disabled.

TSOFTSTART = CSS/ENB x 1.6 x DON / DON_MAX / ISOURCE (1)

Over-Current Protection (OCP)

Over-current protection is implemented by sensing the

voltage drop across the drain and the source of

external high-side MOSFET. Over-current protection is

triggered when the voltage drop on external high-side

MOSFET’s RDS(ON) is greater than the programmable

current limit voltage threshold. 120 µA flowing through

an external resistor between input voltage and the CLP

pin sets the threshold of current limit voltage. When

over-current condition is true, the system is protected

against the cycle-by-cycle current limit. A counter

counts a series of over-current peak values to eight

cycles; the soft-start capacitor is discharged by a 1 µA

current until the voltage on SS pin reaches 1.2 V.

During the discharge period, the high-side driver is

turned off and the low-side driver is turned on. Once

the voltage on SS/ENB pin is under 1.2 V, the normal

soft-start sequence is initiated and the 10 µA current

charges the soft-start capacitor again.

IL(OCP)= [(RSENSE x IOCSET + VOFFSET) / RDS(ON) -

(VIN - VOUT) x VOUT / (fOSC x LOUT x VIN x 2) ] (2)

where, VOFFSET (=10 mV) is the offset voltage

contributed by the internal OCP comparator.

Design Notes

VCC noise/spike affects the offset voltage of the OCP

comparator Figure 23 shows the VOFFSET1/2 vs. VCC

variation curve, which is a simulation result by IC

internal circuitry. Calculate the OCP variation between

VCC=12 V and VCC=4 V. For Ch1 or Ch2, VOFFSET /

RDS(ON) = 172 mV / 9 mΩ = 19 A is affected. VCC>10 V is

the recommended range; lower, and the comparator’s

offset voltage is large.

Prevent CLN Noise in SG1577

To prevent noise/spike on CLN from affecting OCP

judgment, SG1577 internal has a 500 ns blanking time

to filter out this noise/spike on CLN at each turn-on

cycle and counts for eight cycles of CLP>CLN, then

OCP is asserted.

OFFSET

of OCP Comparator

100

120

140

160

180

200

220

240

4 6 8 10 12 14 16

V CC (V )

OFFSET

(m V )

Figure 23. VOFFSET1/2 vs. VCC

Error Amplifier

The IN1 and IN2 pins are connected to the

corresponding internal error amplifier’s inverting input

and the outputs of the error amplifiers are connected to

the corresponding COMP1 and COMP2 pins. The

COMP1 and COMP2 pins are available for control-loop

compensation externally. Non-inverting inputs are

internally tied to a fixed 0.7 V ±1.5% reference voltage.

Oscillator Operation

The SG1577 has a frequency-programmable oscillator.

The oscillator is running at 60 kHz when the RT pin is

floating. The oscillator frequency can be adjusted from

60 kHz up to 320 kHz by an external resistor RRT

between RT pin and the ground. The oscillator

generates a sawtooth wave that has 90% rising duty.

Sawtooth wave voltage threshold is from 1.2 V to 2.8 V.

The frequency of oscillator can be programmed by the

following equation:

fOSC, RT(kHz) = 60kHz + 8522 / RRT(kΩ) (3)

Output Driver

The high-side gate drivers need an external

bootstrapping circuit to provide the required boost

voltage. The highest gate driver’s output (15 V is the

allowed) on high-side and low-side MOSFETs forces

external MOSFETs to have the lowest RDS(ON), which

results in higher efficiency.

Over-Temperature Protection (OTP)

The device is over-temperature protected. When chip

temperature is over 150°C, the chip enters tri-state

(high-side driver is turned off). The hysteresis is 20°C.

SG1577 • Rev. 1.0.6 11

SG1577 — Dual Synchronous DC/DC Controller

Type II Compensation Design

(for Output Capacitors with High ESR)

SG1577 is a voltage-mode controller; the control loop is

a single voltage feedback path, including an error

amplifier and PWM comparator, as shown in Figure 24.

To achieve fast transient response and accurate output

regulation, an adequate compensator design is

necessary. A stable control loop has a 0 dB gain

crossing with -20 dB/decade slope and a phase margin

greater than 45°.

Figure 24. Closed Loop

1. Modulator Frequency Equations

The modulator transfer function is the small-signal

transfer function of VOUT/VE/A. This transfer function is

dominated by a DC gain and the output filter (LO and CO)

with a double-pole frequency at fLC and a zero at FESR.

The DC gain of the modulator is the input voltage (VIN)

divided by the peak-to-peak oscillator voltage

VRAMP(=1.6 V). The first step is to calculate the complex

conjugate poles contributed by the LC output filter. The

output LC filter introduces a double pole,

-40 dB / decade gain slope above its corner resonant

frequency, and a total phase lag of 180°. The resonant

frequency of the LC filter expressed as:

P(LC) CLπ2

××

= (4)

The next step of compensation design is to calculate the

ESR zero. The ESR zero is contributed by the ESR

associated with the output capacitance. Note that this

requires that the output capacitor should have enough

ESR to satisfy stability requirements. The ESR zero of

the output capacitor is expressed as:

ESRC2

)ESR(Z ××

(5)

2. Compensation Frequency Equations

The compensation network consists of the error

amplifier and the impedance networks ZC and Zf, as

Figure 24 shows.

Figure 25. Compensation Loop

)C//C(R2

CR2

212

××

(6)

Figure 26 shows the DC-DC converter gain vs.

frequency. The compensation gain uses external

impedance networks ZC and Zf to provide a stable,

high-bandwidth loop.

High crossover frequency is desirable for fast transient

response, but often jeopardizes the system stability. To

cancel one of the LC filter poles, place the zero before

the LC filter resonant frequency. Place the zero at 75%

of the LC filter resonant frequency. Crossover frequency

should be higher than the ESR zero, but less than 1/5 of

the switching frequency. The second pole should be

placed at half the switching frequency.

Figure 26. Bode Plot

SG1577 • Rev. 1.0.6 12

SG1577 — Dual Synchronous DC/DC Controller

Layout Considerations

Layout is important in high-frequency switching converter

design. If designed improperly, PCB can radiate

excessive noise and contribute to converter instability.

Place the PWM power stage components first. Mount all

the power components and connections in the top layer

with wide copper areas. The MOSFETs of buck,

inductor, and output capacitor should be as close to

each other as possible to reduce the radiation of EMI

due to the high-frequency current loop. If the output

capacitors are placed in parallel to reduce the ESR of

capacitor, equal sharing ripple current should be

considered. Place the input capacitor near the drain of

high-side MOSFET. In multi-layer PCB, use one layer as

power ground and have a separate control signal ground

as the reference for all signals. To avoid the signal

ground being affected by noise and have best load

regulation, it should be connected to the ground terminal

of output.

Follow the below guidelines for best performance:

1 A two-layer printed circuit board is recommended.

2 Use the bottom layer of the PCB as a ground plane

and make all critical component ground connections

through vias to this layer.

3 Keep the metal running from the CLNx terminal to

the output inductor short.

4 Use copper-filled polygons on the top (and bottom,

if two-layer PCB) circuit layers for the CLN node.

5 The small-signal wiring traces from the DLx and

DHx pins to the MOSFET gates should be kept

short and wide enough to easily handle the several

amps of drive current.

6 The critical, small-signal components include any

bypass capacitors (SMD-type of capacitors applied

at VCC and SSx/ENB pins), feedback components

(resistor divider), and compensation components

(between INx and COMPx pins). Position those

components close to their pins with a local, clear

GND connection or directly to the ground plane.

7 Place the bootstrap capacitor near the BSTx and

CLNx pins.

8 The resistor on the RT pin should be near this pin

and the GND return should be short and kept away

from the noisy MOSFET’s GND (which is short

together with IC’s PGND pin to GND plane on back

side of PCB).

9 Place the compensation components close to the

INx and COMPx pins.

10 The feedback resistors for both regulators should

be located as close as possible to the relevant INx

pin with vias tied straight to the ground plane as

required.

11 Minimize the length of the connections between the

input capacitors, CIN, and the power switchers

(MOSFETs) by placing them nearby.

12 Position both the ceramic and bulk input capacitors

as close to the upper MOSFET drain as possible

and make the GND returns (from the source of

lower MOSFET to VIN capacitor GND) short.

13 Position the output inductor and output capacitors

between the upper MOSFET and lower MOSFET

and the load.

14 AGND should be on the clearer plane and kept

away from the noisy MOSFET GND.

15 PGND should be short, together with MOSFET

GND, then through vias to GND plane on the

bottom of PCB.

16 Prevent spike happen on CLN pin a proper snubber

circuit for CLN and GND is recommend.

SG1577 • Rev. 1.0.6 13

SG1577 — Dual Synchronous DC/DC Controller

Physical Dimensions

2.65 MAX

0.20±0.10

0.10 C

12.80±0.20 A

SEE DETAIL A

0.33

0.20

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC MS-013.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN RECOMMENDATION IS FSC DESIGN

PIN ONE

INDICATOR

0.25

1.27

0.51

0.35

BCA

10.325

20 11

11.430

7.50±0.10

X 45°

0.75

0.25

(R0.10)

0.40~1.27

8°

0°

SEATING PLANE

(1.40)

0.25

GAGE PLANE

DETAIL A

SCALE: 2:1

SEATING PLANE

1.27 TYP

0.50 TYP

LAND PATTERN RECOMMENDATION

1.25 TYP

11.930

11.430

8.422

10.922

PIN #1

INDICATOR

PIN #1

INDICATOR 1

OPTION 1 OPTION 2 OPTION 3

PIN #1

INDICATOR

PIN#1 IDENTIFICATION OPTIONS

HALF MOON & PIN 1 HALF MOON ONLY PIN 1 ONLY

E) FILENAME AND REVISION: M20BREV4

Figure 27. 20-Lead, Small Outline Package (SOP)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide term s and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

SG1577 • Rev. 1.0.6 14

SG1577 — Dual Synchronous DC/DC Controller