Standard Products UT8SDMQ64M40 2.5-Gigabit SDRAM MCM UT8SDMQ64M48 3.0-Gigabit SDRAM MCM Preliminary Datasheet October 25, 2011 INTRODUCTION FEATURES Organized as 64M x 40 (16Meg x 40 x 4 banks) and 64Meg x 48 (16Meg x 48 x 4 banks) Single JEDEC standard 3.3V power supply PC100-compliant The UT8SDMQ64M40 and UT8SDMQ64M48 are high performance, highly integrated Synchronous Dynamic Random Access Memory (SDRAM) multi-chip modules (MCMs). Total module density is 2,684,354,560 bits for the 2.5G device and 3,221,225,472 bits for the 3G device. Each bit bank is organized as 8192 rows by 2048 columns. Operation -40oC to +105oC LVTTL compatible with multiplexed address Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Programmable burst lengths: 1,2,4,8, or full page Auto-precharge, includes concurrent auto precharge, and auto-refresh mode 32ms, 8,192-cycle refresh Operational environment: - Total dose: 100 krad(Si) Read and write accesses to the DRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. The programmable READ and WRITE burst lengths (BL) are 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. Aeroflex's SDRAMs are designed to operate at 3.3V. An autorefresh mode is provided, along with a power-saving, powerdown mode. All inputs and outputs are LVTTL compatible. SDRAMs offer significant advances in DRAM operating execution, including the capability to synchronously burst data at a high data rate with automatic column-address generation, to interleave between internal banks to mask precharging time, and to randomly change column addresses on each clock cycle during a burst access. - SEL Immune 111 MeV-cm2/mg Package options: 128-lead Ceramic Quad Flatpack Standard Microcircuit Drawing TBD - UT8SDMQ64M40: 5962-10229 - UT8SDMQ64M48: 5962-10230 - QML Q and Q+ pending 48 40 DQM5 DQM4 U4 DQM3 DQ[7:0](4) 8 DQ[7:0](3) U2 DQM1 8 DQ[7:0](2) U1 DQM0 A[12:0] BA[1:0] CLK CKE RAS# CAS# WE# CS# 8 U3 DQM2 15 U0 SDRAM U5 DQM4 8 DQ[7:0](1) 8 DQ[7:0](0) DQ[39:32] DQ[15:8] DQ[7:0] 16Meg x 8 x4 2.5Gigabit (64Mx40) DQ[7:0](3) 8 DQ[7:0](2) U1 DQM0 15 Figure 1. Block Diagrams 1 DQ[7:0](4) 8 U2 DQM1 A[12:0] BA[1:0] CLK CKE RAS# CAS# WE# CS# 8 U3 DQM2 DQ[23:16] DQ[7:0](5) U4 DQM3 DQ[31:24] 8 U0 8 DQ[7:0](1) 8 DQ[7:0](0) DQ[47:40] DQ[39:32] DQ[31:24] DQ[23:16] DQ[15:8] DQ[7:0] SDRAM 16Meg x 8 x4 3.0Gigabit (64Mx48) Table of Contents Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..11 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Burst Length (BL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Burst Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 WRITE Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..16 COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 LOAD MODE REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 17 BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..20 WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Clock Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...32 Burst READ/Single WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..34 READ wth Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...36 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Operational Environment Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 DC Electrical Characteritics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 IDD Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . ..... .43 Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 AC Characteristics and Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .44 AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ....45 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . 46 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..47 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .65 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .66 List of Figures Figure 1: Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .1 Figure 2: 128-lead package 2.5G SDRAM Module Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Figure 3: 128-lead package 3.0G SDRAM Module Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 4: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Figure 5: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 6: Activating a Specific Row In a Specific Bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .19 Figure 7: Example Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Figure 8: READ Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 20 Figure 9: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 21 Figure 10: Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .22 Figure 11: Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 22 Figure 12: READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .23 Figure 13: READ-to-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .24 Figure 14: READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .25 Figure 15: Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .25 Figure 16: WRITE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . ..26 Figure 17: WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .27 Figure 18: WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .27 Figure 19: Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .28 Figure 20: WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .28 Figure 21: WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .29 Figure 22: Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .30 Figure 23: PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .31 Figure 24: Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .32 Figure 25: CLOCK SUSPEND During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .33 Figure 26: CLOCK SUSPEND During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .33 Figure 27: READ with Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . .34 Figure 28: READ with Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .35 Figure 29: WRITE with Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .36 Figure 30: WRITE with Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . .37 Figure 31: Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . .47 Figure 32: Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . .48 Figure 33: Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . .49 Figure 34: Auto-Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . .50 Figure 35: READ - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . .. . . . . .51 Figure 36: READ - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . ..52 Figure 37: Single READ - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . .53 Figure 38: Single READ - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . .54 Figure 39: Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . .55 Figure 40: READ - Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . .56 Figure 41: READ DQM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . ..57 Figure 42: WRITE - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . .. . . . . .58 Figure 43: WRITE - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . ..59 Figure 44: Single WRITE - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . .60 Figure 45: Single WRITE with Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . ..61 Figure 46: Alternating Bank WRITE Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .62 Figure 47: WRITE - Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . ..63 Figure 48: WRITE - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . ..64 Figure 49: 128 - CQFP Package Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . 65 3 List of Tables Table 1: 2.5G SDRAM Module Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .6 Table 2: 3.0G SDRAM Module Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 9 Table 3: Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . .14 Table 4: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . .. . . . . .15 Table 5: Truth Table 1 - Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ... . . . .. . . . . . .16 Table 6: Truth Table 2 - CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ... . . . .. . . . 38 Table 7: Truth Table 3 - Current State Bank n, Command to Bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . .. . . . . .38 Table 8: Truth Table 4 - Current State Bank n, Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . .. . . . . .40 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 DQ7(0) DQ7(1) DQ0(0) DQ0(1) DQ6(0) DQ6(1) DQ1(0) DQ1(1) DQ5(0) DQ5(1) DQ2(0) DQ2(1) DQ4(0) DQ4(1) DQ3(0) DQ3(1) DQM0 DQM1 VDD VSS VSSQ VDDQ VSSQ VDDQ VSSQ VSS VDD VDDQ VSSQ VSS VDD VDDQ VSSQ VSS VDD VDDQ VSSQ VDDQ DQM3 VSS DQ3(3) VSS DQ4(3) VSS DQ2(3) VSS DQ5(3) VSS DQ1(3) VSS DQ6(3) VSS DQ0(3) VSS DQ7(3) VSS VDDQ VSSQ VSS VDD VDDQ VSSQ VSS VDD 128 127 126 125 124 123 122 121 120 1119 118 117 116 115 114 113 112 111 110 109 108 107 106 DQ7(4) DQ7(2) DQ0(4) DQ0(2) DQ6(4) DQ6(2) DQ1(4) DQ1(2) DQ5(4) DQ5(2) DQ2(4) DQ2(2) DQ4(4) DQ4(2) DQ3(4) DQ3(2) DQM4 DQM2 NC VSSQ VDDQ VDD VSS DEVICE PACKAGE PINOUT DRAWING Figure 2: 128-lead Package 2.5G (512Mb x 5) SDRAM Module 5 VSSQ VDDQ VDD VSS VSSQ VDDQ VDD VSS VSSQ VDDQ A4 A3 A5 A2 A6 A1 A7 A0 A8 A10/AP A9 BA1 A11 BA0 A12 CS# CKE RAS# CLK CAS# WE# VDDQ VSSQ VSS VDD VDDQ VSSQ VSS VDD VDDQ VSSQ 2.5G (512Mb x 5) SDRAM Module Table 1. Pin Descriptions Pin Numbers Symbols Type 77 CLK Input 79 CKE Input 80 CS# Input 78, 76, 75 RAS#, CAS#, WE# Input Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. 112, 16, 111, 59, 58 DQM(4:0) Input 84 ,82 BA (1:0) Input 81, 83, 86, 85, 87, 89, 91, 93, 95, 94, 92, 90, 88 A(12:0) Input 42, 46, 50, 54, 56, 52, 48, 44 DQ[7.0](0) Data I/O Input/output mask: DQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle. Bank address inputs: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address inputs: A0-A12 are sampled during the ACTIVE command (row-address A0-A12) and READ/WRITE command (column-address A0-A9, A11); with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether all banks are to be precharged (A10[HIGH]) or bank selected by (A10 [LOW]). The address inputs also provide the opcode during a LOAD MODE REGISTER command. Data input/output 43, 47, 51, 55, 57, 53, 49, 45 DQ[7:0](1) Data I/O Data input/output 127, 123, 119, 115, 113, 117, 121, 125 DQ[7:0](2) Data I/O Data input/output 32, 28, 24, 20, 18, 22, 26, 30 DQ[7:0](3) Data I/O Data input/output Description Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE power-down, ACTIVE power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down providing low standby power. CKE may be tied HIGH. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. 6 Table 1. Pin Descriptions Pin Numbers Description Symbols Type 128, 124, 120, 116, 114, 118, 122, 126 DQ[7:0](4) Data I/O 110 NC 1, 5, 9, 13, 15, 34, 38, 63, 66, 70, 74, 96, 100, 104, 108 VDDQ Supply DQ power: Isolated DQ power to the die for improved noise immunity. 2, 6, 10, 14, 35, 39, 62, 64, 65, 69, 73, 97, 101, 105, 109 VSSQ Supply DQ ground: Isolated DQ ground to the die for improved noise immunity. 4, 8, 12, 37, 41, 60, 67, 71, 99, 103, 107 VDD Supply Power supply: +3.3V +0.3V 3, 7, 11, 17, 19, 21, 23, 25, 27, 29, 31, 33, 36, 40, 61, 68, 72, 98, 102, 106 VSS Supply Ground Data input/output No connect: This pin should be left unconnected. 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VSSQ VDDQ VDD VSS VSSQ VDDQ VDD VSS VSSQ VDDQ A4 A3 A5 A2 A6 A1 A7 A0 A8 A10/AP A9 BA1 A11 BA0 A12 CS# CKE RAS# CLK CAS# WE# VDDQ VSSQ VSS VDD VDDQ VSSQ VSS VDD VDDQ VSSQ DQ7(0) DQ7(1) DQ0(0) DQ0(1) DQ6(0) DQ6(1) DQ1(0) DQ1(1) DQ5(0) DQ5(1) DQ2(0) DQ2(1) DQ4(0) DQ4(1) DQ3(0) DQ3(1) DQM0 DQM1 VDD VSS VSSQ VDDQ VSSQ VDDQ VSSQ VSS VDD VDDQ VSSQ VSS VDD VDDQ VSSQ VSS VDD VDDQ VSSQ VDDQ DQM3 DQM5 DQ3(3) DQ3(5) DQ4(3) DQ4(5) DQ2(3) DQ2(5) DQ5(3) DQ5(5) DQ1(3) DQ1(5) DQ6(3) DQ6(5) DQ0(3) DQ0(5) DQ7(3) DQ7(5) VDDQ VSSQ VSS VDD VDDQ VSSQ VSS VDD 128 127 126 125 124 123 122 121 120 1119 118 117 116 115 114 113 112 111 110 109 108 107 106 DQ7(4) DQ7(2) DQ0(4) DQ0(2) DQ6(4) DQ6(2) DQ1(4) DQ1(2) DQ5(4) DQ5(2) DQ2(4) DQ2(2) DQ4(4) DQ4(2) DQ3(4) DQ3(2) DQM4 DQM2 NC VSSQ VDDQ VDD VSS PACKAGE DRAWING Figure 3: 128-lead Package 3.0G (512Mb x 6) SDRAM Module 8 3.0G (512Mb x 6) SDRAM Module Table 2. Pin Descriptions Description Pin Numbers Symbols Type 77 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. 79 CKE Input 80 CS# Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE power-down, ACTIVE power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down providing low standby power. CKE may be tied HIGH. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. 75, 76, 78 RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. 16, 17, 58, 59, 111, 112 DQM(5:0) Input 82 ,84 BA(1:0) Input Input/output mask: DQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle. Bank address inputs: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. 81, 83, 85, 86, 87, 88, 89, 90, 91,92, 93, 94, 95 A(12:0) Input 42, 44, 46, 48, 50, 52, 54, 56 DQ(7:0)(0) Data I/O Data input/output 43, 45, 47, 49, 51, 53, 55, 57 DQ[7:0](1) Data I/O Data input/output 113, 115, 117, 119, 121, 123, 125, 127 DQ[7:0](2) Data I/O Data input/output 18, 20, 22, 24, 26, 28, 30, 32 DQ[7:0](3) Data I/O Data input/output Address inputs: A0-A12 are sampled during the ACTIVE command (row-address A0-A12) and READ/WRITE command (address A0-A9, A11 with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether all banks are to be precharged (A10[HIGH]) or bank selected by (A10 [LOW]). The address inputs also provide the opcode during a LOAD MODE REGISTER command. 9 Table 2. Pin Descriptions Description Pin Numbers Symbols Type 114, 116, 118,120, 122, 124,126, 128 DQ[7:0](4) Data I/O Data input/output 19, 21, 23, 25, 27, 29, 31, 33 DQ[7:0](5) Data I/O Data input/output 110 NC 1, 5, 9, 13, 15, 34, 38, 63, 66, 70, 74, 96, 100, 104, 108 VDDQ Supply DQ power: Isolated DQ power to the die for improved noise immunity. 2, 6, 10, 14, 35, 39, 62, 64, 65, 69, 73, 97, 101, 105, 109 VSSQ Supply DQ ground: Isolated DQ ground to the die for improved noise immunity. 4, 8, 12, 37, 41, 60, 67, 71, 99, 103, 107 VDD Supply Power supply: +3.3V 0.3V. 3, 7, 11, 36, 40, 61, 68, 72, 98, 102, 106 VSS Supply Ground No connect: This pin should be left unconnected. 10 FUNCTIONAL DESCRIPTION The 2.5G and 3.0G SDRAMs are organized as 16M x 40 x 4 banks and 16M x 48 x 4 banks that operate on 3.3V using a synchronous interface (signals are registered on the positive CLK edge). Read and write accesses to the SDRAM are burst oriented. Accesses start at address locations selected and continue for programmed number of locations in a programmed sequence. Device accesses start with the registration of the ACTIVE command followed by a READ or WRITE command. Some address and both bank bits are registered coincident to the ACTIVE command registration and are used to select the row and bank locations, while column location to initiate burst access address bits A0-A9 are registered at time of READ/WRITE command. Previous to normal operation the device must initialized properly. Initialization The SDRAMs must be powered up and initialized in a certain manner. Failure to initial devices may result in unpredictable behavior. Once stable power is applied to VDD and VDDQ (simultaneously), and the clock is running and stable (cycling within specified parameters) the device requires a minimum 100s delay prior to issuing any command other than NOP or COMMAND INHIBIT. At some time during this period the COMMAND INHIBIT or NOP can be issued and should continue through the end of the 100s period. After the delay has been completed with at least one COMMAND INHIBIT or NOP command, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing all banks in the device into the idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register powers up in an unknown state, it should be loaded prior to applying any operational command. The recommended power-up sequence for SDRAMs: 1. Simultaneously apply power to VDD and VDDQ. 2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-compatible. 3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing constraints specified for the clock pin. 4. Wait at least 100s prior to issuing any command other than a COMMAND INHIBIT or NOP. 5. Starting at some point during this 100s period, bring CKE HIGH. Continuing at least through the end of this period, one or more COMMAND INHIBIT or NOP commands must be applied. 6. Perform a PRECHARGE ALL command. 7. Wait at least tRP time; during this time, NOPs or DESELECT commands must be given. All banks will complete their precharge, thereby placing the device in the all banks idle state. 8. Issue an AUTO REFRESH command. 9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands are allowed. 10. Issue an AUTO REFRESH command. 11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands are allowed. 12. The SDRAM is now ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded with desired bit values prior to applying any operational command. Using the LMR command, program the mode register. The mode register is programmed via the MODE REGISTER SET command with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again or the device loses power. Not programming the mode register upon initialization will result in default settings which may not be desired. Outputs are guaranteed High-Z after the LMR command is issued. Outputs should be High-Z already before the LMR command is issued. 13. Wait at least tMRD time, during which only NOP or DESELECT commands are allowed. At this point, the DRAM is ready for any valid command. Note: If desired, more than two AUTO REFRESH commands can be issued in the sequence. After steps 9 and 10 are complete, repeat them until the desired number of AUTO REFRESCH + tRFC loops is achieved. REGISTER DEFINITION Mode Register The mode register is used to set a specific mode of operation for the SDRAM. These definitions include Burst length (BL), the CAS latency (CL), and the write burst mode as shown in Figure 4. The mode register is programmed using the LOAD MODE REGISTER command and retains the stored setting information until either reprogrammed or device power is lost. Mode register bits M0-M2 11 specifies the BL, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CL, M7 and M8 specifies the operation mode, M9 specifies the write burst mode, M10 and M11 are reserved. Address M12 is undefined, but should be driven low during mode register programming. All references to bit(s) Mx in this document affect the mode register. Burst Length (BL) All read and write activity to the SDRAMs are burst oriented. The burst mode is selected by programming BL as described above. Burst length of 1, 2, 4, and 8 locations are available for both sequential and interleaved burst types. A full page burst is also available in sequential mode only and is used in conjunction with BURST TERMINATE command to generate arbitrary burst lengths. Reserved states for BL should not be used as they may result in undefined operations. Whenever a read or write command is issued a block of columns is selected that is equal to the BL. All access for that burst takes place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1A9, and A11when BL = 2, A2-A9, and A11when BL = 4, A3-A9, and A11when BL = 8. The remaining least significant address bits are used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved: this is referred to as the burst type and is selected via bit M3. The ordering of the accesses with the burst is determined by BL1, the burst type and the staring column address, as shown in Table 3. 12 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 12 11 10 9 8 7 6 5 4 3 2 1 0 WB Reserved1 M9 0 1 Op Mode CAS Latency BT Address Bus Mode Register (Mx) Burst Length Burst Length Write Burst Mode Programmed burst length Single location access M2 M1 M0 M8 M7 M6-M0 Operating Mode 0 0 Defined Standard Operation - - - All other states reserved M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved M6 M5 M4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 M8 Burst Type 0 1 1 3 0 Sequential 1 0 0 Reserved 1 Interleaved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Notes: 1. Program M12, M11, M10 = "0, 0, 0" to ensure compatibility with future devices. Figure 4: Mode Register Definition 13 Table 3. Burst Definition Burst Length 2 4 8 Full page (y) Order of Accesses Within a Burst Starting Column Address Type = Sequential Type = Interleaved - - A0 - - 0 0-1 0-1 - - 1 1-0 1-0 - A1 A0 - 0 0 0-1-2-3 0-1-2-3 - 0 1 1-2-3-0 1-0-3-2 - 1 0 2-3-0-1 2-3-0-1 - 1 1 3-0-1-2 3-2-1-0 A2 A1 A0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Cn, Cn + 1, Cn + 2 Cn + 3 Cn + 4... ...Cn - 1 Cn... Not Supported n = A0-A12/11/9 (location 0-y) Notes: 1. For full-page accesses: y = 2,048 2. For BL = 2, A1-A9, A11 select the block-of-two burst; A0 selects the starting column within the block. 3. For BL = 4, A2-A9, A11 select the block-of-four burst; A0-A1 select the starting column within the block. 4. For BL = 8, A3-A9, A-11 select the block-of-eight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0-A9, A11 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For BL = 1, A0-A9, A11 select the unique column to be accessed, and mode register bit M3 is ignored. 14 CAS Latency (CL) CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, as shown in Figure 5, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs start driving after T1 and the data will be valid by T2. Table 4 indicates the operating frequencies at which each CL setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. T0 T2 T1 T3 CLK Command READ NOP tLZ NOP tAC tOH DQ Data CL = 2 T0 T1 T2 T3 CLK Command READ NOP NOP tLZ NOP tAC DQ tOH Data CL = 3 Don't Care Undefined Figure 5: CAS Latency Table 4. CAS Latency Allowable Operating Frequency (MHz) Frequency Latency < 100 CL = 2 15 Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. WRITE Burst Mode When M9 = 0, BL programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ burst, but write accesses are single-location (nonburst) accesses. COMMANDS Table 5 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear in the Operations section; these tables provide current state/next state information. Table 5: Truth Table 1 Commands and DQM Operation Name (Function) CS# RAS# CAS# WE# DQM Address DQs Notes COMMAND INHIBIT (NOP) H X X X X X X NO OPERATION (NOP) L H H H X X X ACTIVE (Select bank and activate row) L L H H X Bank/ row X 3 READ (Select bank and column, and start READ burst) L H L H L/H8 Bank/ col X 4 WRITE (Select bank and column, and start WRITE burst) L H L L L/H8 Bank/ col Valid 4 BURST TERMINATE L H H L X X Active PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5 AUTO REFRESH L L L H X X X 6, 7 LOAD MODE REGISTER L L L L X Op-code X 4 Write enable/output enable -- -- -- -- L -- Active 8 Write inhibit/output High-Z -- -- -- -- H -- High-Z 8 Notes: 1. CKE is HIGH for all commands shown. 2. A0-A11 define the op-code written to the mode register, and A12 should be driven LOW. 3. A0-A12 provide row address, and BA0, BA1 determine which bank is made active. 4. A0-A9, A11 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. 5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are "Don't Care." 6. This command is AUTO REFRESH if CKE is HIGH. 7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM that is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. 16 LOAD MODE REGISTER The mode register is loaded via inputs A0-A11 (A12 should be driven LOW). See "Mode Register" on page 13. The LOAD MODE REGISTER command can only be issued when all banks are idle and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank and the address provided on inputs; A0-A9, A11 selects the starting column location. The value on input A10 determines whether auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row remains open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs provides valid data. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A9, A11 selects the starting column location. The value on input A10 determines whether auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row remains open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access at a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." After a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. Auto Precharge Auto precharge is a feature that performs the same individual-bank PRECHARGE function described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge is non-persistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operations section. BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the "Operations" section on page 17. The BURST TERMINATE command does not precharge the row; the row will remain open until a PRECHARGE 17 command is issued. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command as shown in the Operations section. The addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. The 512Mb SDRAM requires 8,192 AUTO REFRESH cycles every 32ms (tREF). Providing a distributed AUTO REFRESH command every 3.9s will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRC), once every 32ms. OPERATIONS Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command which selects both the bank and the row to be activated (see Figure 6). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 7, which covers any case where 2 < tRCD (MIN)/tCK 3 (the same procedure is used to convert other specification limits from time units to clock cycles). A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. 18 T0 CLK CKE CS# RAS# CAS# WE# Address Row Address BA Bank Address Don't Care Figure 6: Activating a Specific Row in a Specific Bank T0 T1 T3 T2 CLK Command Active NOP NOP Read or Write tRCD Don't Care Figure 7: Example Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK < 3 19 READs READ bursts are initiated with a READ command, as shown in Figure 8. The starting column and bank addresses are provided with the READ command, and auto precharge either is enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following CL after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 9 on page 20 shows general timing for each possible CL setting. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. CLK CKE CS# RAS# CAS# WE# A0-A9, A11 Column Address A12 Enable Auto Precharge A10 Disable Auto Precharge BA(0,1) Bank Address Don't Care Figure 8: READ Command 20 T0 T2 T1 T3 CLK Command READ NOP tLZ NOP tAC tOH DQ Data CL = 2 T0 T1 T2 T3 CLK Command READ NOP NOP tLZ NOP tAC DQ tOH Data CL = 3 Don't Care Undefined Figure 9: CAS Latency Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated (at the end of the page, it wraps to the start address and continue). Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst either follows the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid where x = CL - 1. This is shown in Figure 9 for CL = 2 and CL = 3; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The SDRAM uses a pipelined architecture and, therefore, does not require the 2n rule associated with a pre-fetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Figure 11, or each subsequent READ may be performed to a different bank. 21 T0 T1 T2 T3 T4 T5 T6 T7 CLK Command READ Address BANK COL n NOP NOP NOP READ NOP NOP BANK COL b CL = 2 DQ(CL=2) Dout n n+1 n+2 n+3 Dout b Dout n n+1 n+2 n+3 CL = 3 DQ(CL=3) Notes: 1. Each READ Command may be to any bank. DQM is Low. Dout b Don't Care Transitioning Data Figure 10: Consecutive READ Bursts T0 T1 T2 T3 T4 T5 T6 READ NOP NOP NOP READ NOP NOP BANK COL n BANK COL a BANK COL x BANK COL m CLK Command Address CL = 2 DQ(CL=2) Dout n Dout a Dout x Dout m Dout n Dout a Dout x CL = 3 DQ(CL=3) Notes: 1. Each READ Command may be to any bank. DQM is Low. Dout m Don't Care Transitioning Data Figure 11: Random READ Accesses 22 Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. The DQM input is used to avoid I/O contention, as shown in Figure 12 and Figure 13. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress dataout from the READ. After the WRITE command is registered, the DQs go High-Z (or remain High-Z), regardless of the state of the DQM signal, provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 13, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 12 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 13 shows the case where the additional NOP is needed. T0 T1 T2 T3 T4 T5 tCK CLK DQM Command Address READ NOP NOP NOP WRITE BANK COL b BANK COL n tHZ DQ Dout n tDS Din b Don't Care Transitioning Data Notes: 1. CL = 3 is used for illustration. The READ or WRITE Command may be to any bank. If a burst of one is used, DQM is not required. Figure 12: READ-to-WRITE 23 T0 T1 T2 T3 T4 T5 tCK CLK DQM Command Address READ NOP NOP NOP NOP BANK COL n WRITE BANK COL b tDS tHZ DQ Dout n Din b Don't Care Transitioning Data Notes: 1. CL = 3 is used for illustration. The READ or WRITE Command may be to any bank. If a burst of one is used, DQM is not required Figure 13: READ-to-WRITE with Extra Clock Cycle A fixed-length READ burst may be followed by, or truncated with, a PRECHARGEcommand to the same bank (provided that auto precharge was not activated), and a full page burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 14 for each possible CL; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note: Part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires the command and address buses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is it can be used to truncate fixed-length or full-page bursts. Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 15 for each possible CL; data element n + 3 is the last desired data element of a longer burst. 24 T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Address READ NOP NOP NOP PRECHARGE Bank a, Col n NOP NOP ACTIVE Bank (a or all) Bank a, ROW CL = 2 Dout n DQ(CL = 2) n+1 n+2 n+3 Dout n n+1 n+2 CL = 3 DQ(CL = 3) n+3 Don't Care Notes: 1. DQM is Low. Transitioning Data Figure 14: READ-to-PRECHARGE T0 T1 T2 T3 T4 T5 T6 CLK Command Address READ NOP NOP BURST TERMINATE NOP NOP NOP BANK COL n CL = 2 Dout n DQ(CL=2) n+1 n+2 n+3 Dout n n+1 n+2 CL = 3 DQ(CL=3) n+3 Don't Care Notes: 1. DQM is Low. Transitioning Data Figure 15: Terminating a READ Burst 25 WRITES WRITE bursts are initiated with a WRITE command, as shown in Figure 16. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs remains High-Z and any additional input data will be ignored (see Figure 17 on page 26). A full-page burst will continue until terminated (at the end of the page, it will wrap to the start address and continue). Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 18. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. The 512Mb SDRAM uses a pipelined architecture and, therefore, does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 19, or each subsequent WRITE may be performed to a different bank. T0 CLK CKE CS# RAS# CAS# WE# A[0-9], A11 Column Address A12 Enable Auto Precharge A10 Disable Auto Precharge BA(0,1) Bank Address Don't Care Figure 16: Write Command 26 T0 T1 T2 T3 WRITE NOP NOP NOP CLK Command A DQ BANK COL n Din n Din n+1 Notes: 1. BL = 2. DQM is Low. Don't Care Transitioning Data Figure 17: WRITE Burst T0 T1 T2 CLK Command Address DQ WRITE NOP BANK COL n Din n WRITE BANK COL b Din n+1 Notes: 1. DQM is LOW. Each WRITE command may bo to any bank. Figure 18: WRITE-TO-WRITE 27 Din b Don't Care Transitioning Data T0 T1 T3 T2 CLK WRITE WRITE WRITE WRITE Bank Col. n Bank Col. a Bank Col. x Bank Col. m Din n Din a Din x Din m Command A DQ Notes: 1. DQM is LOW. Each WRITE command may be to any bank. Transitioning Data Figure 19: Random WRITE Cycles T0 T1 T2 T3 T4 T5 T6 tCK CLK Command WRITE Address Bank Col. n DQ Din n NOP READ NOP NOP NOP Dout b Dout b+1 Bank Col. b Din n+1 Notes: The WRITE or READ command may be to any bank. DQM is LOW Don't Care Transitioning Data Figure 20: WRITE-to-READ 28 Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a tWR of at least one clock plus time, regardless of frequency. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 21. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. The precharge can be issued coincident with the first coincident second clock (Figure 21). In the case of a fixedlength burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Fixed-length or fullpage WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 22, where data n is the last desired data element of a longer burst. T0 T1 T2 T3 T4 tWR T5 T6 tRP CLK tWR = tCLK >= 15 ns DQM COMMAND WRITE ADDRESS Bank a, Col n DQ Din n NOP PRECHARGE NOP NOP ACTIVE Bank (a or all) NOP Bank a, ROW Din n+1 tWR = tCLK < 15 ns tWR tRP DQM COMMAND WRITE ADDRESS Bank a, Col n DQ Din n NOP NOP PRECHARGE NOP NOP Bank (a or all) ACTIVE Bank a, ROW Din n+1 Don't Care Transitioning Data Notes: 1. DQM could remain low in this example if the write burst is a fixed length of two. Figure 21: WRITE-to-PRECHARGE 29 T1 T0 T2 CLK Command A DQ WRITE BURST TERMINATE Bank Col. n Next Command Address Din n (Data) Note: DQMs are LOW. Don't Care Transitioning Data Figure 22: Terminating a WRITE Burst 30 Precharge The PRECHARGE command shown in Figure 23 is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access at the specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." After a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. CLK CKE CS# RAS# CAS# WE# A(0-9,11,12) All Banks A10 Bank Selected BA(0,1) Bank Address Don't Care Figure 23: PRECHARGE Command 31 Power-Down Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximumpower savings while in standby. The device may not remain in the power-down state longer than the refresh period (32ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS). See Figure 24. CLK tCKS tCKS CKE Command NOP All Banks Idle NOP Input Buffers Gated Off Enter Power-Down Mode Exit Power-Down Mode ACTIVE tRCD tRAS tRC Don't Care Figure 24: POWER-DOWN Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, "freezing" the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven. Burst counters are not incremented, as long as the clock is suspended (see examples in Figures 25 and 26). Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation resumes on the subsequent positive clock edge. The device may not remain in clock suspend state longer than the refresh period (32ms) since no refresh operations are performed in this mode. 32 T0 T1 T2 T3 T4 T5 CLK CKE INTERNAL CLOCK COMMAND ADDRESS DQ NOP Bank Col. n Din n NOP NOP Dout b Dout b+1 WRITE Bank Col. b Din n+1 Note: 1. BL = 4 or greater. DM is LOW. Don't Care Transitioning Data Figure 25: CLOCK SUSPEND During WRITE Burst T0 T1 T2 T3 COMMAND READ NOP NOP ADDRESS Bank Col. n T4 T5 T6 NOP NOP NOP CLK SYSCLK CKE DQ Dout n Dout n+1 Notes: 1. For this example CL = 2, BL = 4 or greater, and DQM is LOW. Figure 26: CLOCK SUSPEND During READ Burst 33 Dout n+2 Dout n+3 Don't Care Transitioning Data Burst READ/Single WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0). Concurrent Auto Precharge An access command to (READ or WRITE) another bank, while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports concurrent auto precharge. SDRAMs support concurrent auto precharge. Four cases where concurrent auto precharge occurs are defined below. READ with Auto Precharge Interrupted by a READ (with or without auto precharge): A READ to bank m interrupts a READ on bank n, CL later. The PRECHARGE to bank n begins when the READ to bank m is registered (see Figure 28). Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m interrupts a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begins when the WRITE to bank m is registered (see Figure 29). T0 T1 T2 T3 T4 T5 T6 T7 NOP NOP NOP NOP CLK COMMAND NOP READ AP BANK n NOP READ AP BANK m BANKn Read with burst of 4 Page Active Read with burst of 4 BANK m COL d BANK n COL a ADDRESS Idle Interrupt Burst, Precharge Page Active BANKm tRP BANK m tRP BANK n Internal States Precharge CL = 3 (Bank m) CL = 3 (Bank n) DQ(CL=3) Dout a Dout a+1 Dout d Dout d+1 Don't Care Notes: 1. DQM is LOW. Transitioning Data Figure 27: READ with Auto Precharge Interrupted by a READ 34 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK CCOMMAND READ AP BANK n NOP NOP READ AP BANK m NOP Internal States NOP Read with burst of 4 BANKm Page Active NOP tWR BANK m tRP BANK n Page BANKn Active ADDRESS NOP Interrupt Burst, Precharge Idle Write with burst of 4 Write Back BANK m COL d BANK n COL a DQM DQ(CL=3) Dout a Din d Din d+1 Din d+2 Din d+3 CL = 3 (bank n) Don't Care Notes: 1. DQM is High at T2 to prevent Dout a+1 from contending with Din d at T4. Figure 28: READ with Auto Precharge Interrupted by a WRITE 35 Transitioning Data Data for any WRITE burst may be truncated with a subsequent READ comment, and data for a fixed-length WRITE burst may be immediately followed by a READ command. After the READ command is registered, the data inputs will be ignored, and WRITEs will not be executed. An example is shown. Data n+1 is either the last of a burst of two or the latest desired of a longer burst. WRITE with Auto Precharge Interrupted by a READ (with or without auto precharge): A READ to bank m interrupts a WRITE on bank n when registered, with the data-out appearing CL later. The PRECHARGE to bank n begins after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (see Figure 29). Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m interrupts a WRITE on bank n when registered. The PRECHARGE to bank n begins after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (see Figure 30). T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND NOP WRITE AP BANK n NOP READ AP BANK m NOP Internal States BANKn ADDRESS DQ(CL=3) Read with burst of 4 NOP tWR BANK m Interrupt Burst, write-back Page Active Precharge Read with burst of 4 bank n col a Din a NOP tRP BANK n tWR BANK n Page Active BANKm NOP bank m cl d a+1 Dout d d+1 Don't Care Notes: 1. DQM is Low. Transitioning Data Figure 29: WRITE with Auto Precharge Interrupted by a READ 36 T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND NOP WRITE AP BANK n NOP WRITE AP BANK m NOP Internal States BANKn Write with burst of 4 tWR BANK m Precharge Write with burst of 4 BANK n COL a Din a NOP tRP BANK n Interrupt Burst, write-back Page Active BANKm DQ(CL=3) NOP tWR BANK n Page Active ADDRESS NOP Write-Back BANK m COL d a+1 a+2 Din d d+1 d+2 d+3 Don't Care Notes: 1. DQM is Low. Transitioning Data Figure 30: WRITE with Auto Precharge Interrupted by a WRITE 37 Table 6: Truth Table 2 - CKE Notes 1-4 apply to entire table; Notes appear below. CKEn-1 CKEn Current State COMMANDn ACTIONn L L Power-down X Maintain power-down Clock suspend X Maintain clock suspend Power-down COMMAND INHIBIT or NOP Exit power-down 5 Clock suspend X Exit clock suspend 6 All banks idle COMMAND INHIBIT or NOP Power-down entry All banks idle AUTO REFRESH Reading or writing VALID L H H H L Notes Clock suspend entry See Table 7 H Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn - 1 was the state of CKE at the previous clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tCKS is met). 6. After exiting clock suspend at clock edge n, the device resumes operation and recognize the next command at clock edge n + 1. Table 7: Truth Table 3 - Current State Bank n, Command to Bank n Current State CS# Any H X X X COMMAND INHIBIT (NOP/continue previous operation) L H H H NO OPERATION (NOP/continue previous operation) L L H H ACTIVE (Select and activiate row) L L L H AUTO REFRESH 7 L L L L LOAD MODE REGISTER 7 L L H L PRECHARGE 11 L H L H READ (Select column and start READ burst) 10 L H L L WRITE (Select column and start WRITE burst) 10 L L H L PRECHARGE (Deactivate row in bank or banks) 8 L H L H READ (Select column and start new READ burst) 10 L H L L WRITE (Select column and start WRITE burst) 10 L L H L PRECHARGE (Truncate READ burst, start PRECHARGE) 8 L H H L BURST TERMINATE 9 Idle Row active Read (auto precharge disabled) RAS# CAS# WE# Command (Action) 38 Notes Table 7: Truth Table 3 - Current State Bank n, Command to Bank n Write (auto precharge disabled) L H L H READ (Select column and start READ burst) 10 L H L L WRITE (Select column and start new WRITE burst) 10 L L H L PRECHARGE (Truncate WRITE burst, start PRECHARGE) 8 L H H L BURST TERMINATE 9 Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Table 7) and after tXSR has been met. 2. This table is bank-specific (except where noted) the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Table 7 and according to Table 8. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. After tRP is met, the bank will be in the idle state. Row activating: Starts with registration of an ACTIVE command and ends when tRCD is met. After tRCD is met, the bank will be in the row active state. Read with auto Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. After tRP is met, the bank precharge enabled: will be in the idle state. Write w/auto: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. After tRP is met, the bank precharge enabled: will be in the idle state. 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. After tRC is met, the SDRAM will be in the al banks idle state. Accessing mode Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. After tMRD is met, the SDRAM register: will be in the all banks idle state. Precharging all: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. After tRP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank. 10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 11. Does not affect the state of the bank and acts as a NOP to that bank. 39 Table 8: Truth Table 4 - Current State Bank n, Command to Bank m Current State CS# Any H X X X COMMAND INHIBIT (NOP/continue previous operation) L H H H NO OPERATION (NOP/continue previous operation) Idle X X X X Any Command Otherwise Allowed to Bank m Row activating, active, or precharging L L H H ACTIVE (Select and activate row) L H L H READ (Select column and start READ burst) 7 L H L L WRITE (Select column and start WRITE burst) 7 L L H L PRECHARGE L L H H ACTIVE (Select and activate row) L H L H READ (Select column and start new READ burst) 7, 10 L H L L WRITE (Select column and start WRITE burst) 7, 11 L L H L PRECHARGE L L H H ACTIVE (Select and activate row) L H L H READ (Select column and start READ burst) 7, 12 L H L L WRITE (Select column and start new WRITE burst) 7, 13 L L H L PRECHARGE L L H H ACTIVE (Select and activate row) L H L H READ (Select column and start new READ burst) 7, 8, 14 L H L L WRITE (Select column and start WRITE burst) 7, 8, 15 L L H L PRECHARGE L L H H ACTIVE (Select and activate row) L H L H READ (Select column and start READ burst) 7, 8, 16 L H L L WRITE (Select column and start new WRITE burst) 7, 8, 17 L L H L PRECHARGE Read (auto precharge disabled) Write (auto precharge disabled) Read (with auto precharge) Write (with auto precharge) RAS# CAS# WE# Command (Action) Notes 9 9 9 9 Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Table 6) and after tXSR has been met. 2. This table describes alternate bank operation, except where noted; that is, the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminate Read with auto Starts with registration of a READ command with auto precharge enabled, and ends when tRP has been met. After tRP is met, the precharge enabled: bank will be in the idle state. Write with autoStarts with registration of a WRITE command with auto precharge enabled, and ends when tRP has been met. After tRP is met, the precharge enabled: bank will be in the idle state. 40 4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. Concurrent auto precharge: Bank n initiates the auto precharge command when its burst has been interrupted by bank m's burst. 9. Burst in bank n continues as initiated. 10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m interrupts the READ on bank n, CL later (Figure 10). 11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m interrupts the READ on bank n when registered (Figure 12 and Figure 13). DQM should be used one clock prior to the WRITE command to prevent bus contention. 12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank minterrupst the WRITE on bank n when registered (Figure 20), with the data-out appearing CL later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m interrupts the WRITE on bank n when registered (Figure 18). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank minterrupts the READ on bank n, CL later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 27). 15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m interrupts the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 28). 16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank minterrupts the WRITE on bank n when registered, with the data-out appearing CL later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be datain registered one clock prior to the READ to bank m (Figure 29). 17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank minterrups the WRITE on bank n when registered. The PRECHARGE to bank n begins after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure30). 41 Electrical Specifications ABSOLUTE MAXIMUM RATINGS (Referenced to VSS) SYMBOL VDD and VDDQ VIN, VOUT TSTG PARAMETER DC supply voltage Voltage on any pin relative to VSS Storage temperature PD Maximum power dissipation TJ Maximum junction temperature JC Thermal resistance, junction-to-case LIMITS -1.0 to +4.3V -0.3 to VDD +0.3V -65 to +150C 5W +125oC TBDoC/W Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. RECOMMENDED OPERATING CONDITIONS (Referenced to VSS) SYMBOL PARAMETER LIMITS VDD and VDDQ Positive supply voltage 3.0 to 3.6V TC Case temperature range -40 to 105oC VIN DC input voltage 0V to VDDQ OPERATIONAL ENVIRONMENT SPECIFICATIONS TOTAL DOSE Heavy Ion Event Rate2 100K 1.1 E-10 RAD(SI) Events/Bit-Day 42 DC Electrical Characteristics and Operating Conditions (Pre/Post-Radiation)* Notes 1, 4, and 5 apply to entire table. (VDD, VDDQ = +3.3V +/-0.3V; Unless otherwise noted, Tc is per temperature range ordered.) Parameter/Condition Symbol Min Input high voltage: Logic 1; All inputs VIH 2 Input low voltage: Logic 0; All inputs VIL Input leakage current: Any input 0V< VIN < VDD (All other pins not under test = 0V) Max Units Notes V 0.8 V II -5 5 A Output leakage current: DQs are disabled; 0V < VOUT < VDDQ IOZ -5 5 A Output levels: Output high voltage (IOUT = -4mA) VOH 2.4 -- V Output low voltage (IOUT = 4mA) VOL -- 0.4 V IDD Specifications and Conditions (Pre/Post-Radiation)* Notes 1, 4, 5, 9, and 11 apply to entire table. (VDD, VDDQ = +3.3V +/-0.3V; Unless otherwise noted, Tc is per temperature range ordered.) Max Parameter/Condition Symbol x40 x48 Units Notes Operating current: active mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) IDD1 600 720 mA 3, 12, 13, 15 Standby current: power-down mode; CKE = LOW; All banks idle IDD2 17.5 21 mA 15 Standby current: active mode; CS# = HIGH CKE = HIGH; All banks active after tRCD met; No accesses in progress IDD3 225 270 mA 3, 10,13, 15 Operating current: Burst mode; Page burst; READ or WRITE; All banks active IDD4 625 750 mA 3, 12, 13, 15 tRFC = tRFC (MIN) IDD5 1300 1300 mA tRFC =3.9 s IDD6 30 36 mA 3, 12, 13, 15, 16 Auto refresh current: CS# = HIGH; CKE = HIGH Capacitance Notes 2 apply to entire table Parameter Condition Symbol Max Units Input capacitance: All other input-only pins f=1MHz @ 0V CIN Cl1 TBD pF Input/output capacitance: DQs f=1MHz @ 0V CIO Cl1 TBD pF 43 AC CHARACTERISTICS and RECOMMENDED OPERATING CONDITIONS (Pre/Post-Radiation)* Notes 4, 5, 6, 7, 8 and 9 apply to entire table. (VDD, VDDQ = +3.3V +/-0.3V; Unless otherwise noted, Tc is per temperature range ordered.) SYMBOL PARAMETER MIN MAX UNIT ns tAC(3) Access time from CLK (positive edge) CL=3 5.4 tAC(2) Access time from CLK (positive edge) CL=2 6 tAH Address hold time 0.8 ns tAS Address setup time 1.5 ns tCH CLK high-level width 2.5 ns tCL CLK low-level width 2.5 ns tCK3 Clock cycle time CL=3 7.5 ns tCK2 Clock cycle time CL = 2 10 ns tCKH CKE hold time 0.8 ns tCKS CKE setup time 1.5 ns tCMH CS#, RS#, CAS#, WE#, DQM hold time 0.8 ns tCMS CS#, RS#, CAS#, WE#, DQM setup time 1.5 ns tDH Data-in hold time 0.8 ns tDS Data-in setup time 1.5 ns tHZ3 Data-out High-Z time CL = 3 5.4 ns tHZ2 Data-out High-Z time CL = 2 6.0 ns tLZ Data-out Low-Z time tOH 1 ns Data-out Hold time (load) 2.7 ns tOHN Data-out hold time (no load) 1.8 ns tRAS ACTIVE-to-PRECHARGE command 44 tRC ACTIVE-to-ACTIVE command period 66 tRCD ACTIVE-to-READ or WRITE delay 20 ns tREF Refresh period (8,192 rows) 32 ms tRFC AUTO REFRESH period 66 ns tRP PRECHARGE command period 20 ns ACTIVE bank a-to-ACTIVE bank b command 15 ns Transition time 0.3 tRRD tT tWR WRITE recovery time 120,000 AC Functional Characteristics (Pre/Post-Radiation)* 44 14 ns ns 1.2 ns 1 CLK + 7ns 15 NOTES ns 6 Notes 4, 5, 6, 7, 8, and 9apply to entire table. (VDD, VDDQ = +3.3V +/-0.3V; Unless otherwise noted, Tc is per temperature range ordered.) PARAMETER Symbol x40 x48 Units READ/WRITE command-to-READ/WRITE command tCCD 1 1 tCK CKE to clock disable or power-down entry mode tCKED 1 1 tCK CKE to clock enable or power-down exit setup mode tPED 1 1 tCK DQM input data delay tDQD 0 0 tCK DQM to data mask during WRITEs tDQM 0 0 tCK DQM to data High-Z during READs tDQZ 2 2 tCK WRITE command to input data delay tDWD 0 0 tCK Data-in to ACTIVE command tDAL 5 5 tCK Data-in to PRECHARGE command tDPL 2 2 tCK Last data-in to burst STOP command tBDL 1 1 tCK Last data-in to new READ/WRITE command tCDL 1 1 tCK Last data-in to PRECHARGE command tRDL 2 2 tCK LOAD MODE REGISTER command to ACTIVE or REFRESH command tMRD 2 2 tCK tROH(3) 3 3 tCK tROH(2) 2 2 tCK Dataout to High-Z form PRECHARGE command 45 Notes Notes: * For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured. 1. All voltages referenced to VSS. 2. Measured only for initial qualification and after process or design change that could affect this parameter. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-40C TC 105C) is ensured. 5. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 6. AC characteristics assume tT = 1ns, supplied as a design limit, neither tested nor guaranteed. 7. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 8. Outputs measured at 1.5V with equivalent load: V DD V DD R TERM 100-ohm s C L = 40pF DUT Test Point Zo = 50-ohm s R TERM 100-ohm s Equivalent Test Load Circuit 9. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5Vcrossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. 10. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 11. IDD specifications are tested after the device is properly initialized. 12. The IDD current will increase or decrease in a proportional amount by the amount the frequency is altered for the test condition. 13. Address transitions average one transition every two clocks. 14. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 15. CL = 2, tCK = 7.5ns. 16. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 46 TIMING DIAGRAMS T0 To +1 Tn + 1 T1 tCH tCK Tp + 2 Tp + 1 Tp + 3 tCL CLK tCKH tCKS CKE tCMH tCMS COMMAND NOP AUTO REFRESH PRE CHARGE NOP NOP AUTO REFRESH NOP LOAD MODE REGISTER NOP NOP ACTIVE DQM tAH tAS A(0:9,11:12) CODE tAS ALL BANKS A(10) ROW tAH ROW CODE SINGLE BANK BA(0,1) DQ BANK ALL BANKS High-Z tRP Power-up: Vdd and CLK stable Precharge all banks tRFC tRFC AUTO REFRESH AUTO REFRESH tMRD Program mode register 2, 3, 4 Don't Care Notes: 1. If CS is HIGH at clock HIGH time, all commands applied are NOP. 2. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired. 3. JEDEC and PC100 specify three clocks. 4. Outputs are guaranteed High-Z after command is issued. 5. A12 should be a LOW at Tp+1. Figure 31: Initialize and Load Mode Register 47 T2 T1 T0 tCK tCH Tn + 1 Tn + 2 tCL CLK tCKS tCKH tCKS tCKS CKE tCMH tCMS PRE CHARGE COMMAND NOP NOP NOP ACTIVE DQM A(0:9,11:12) ROW ALL BANKS A(10) ROW SINGLE BANK tAH tAS BA(0,1) DQ BANK BANK(s) High-Z Two clock cycles Precharge all active banks Input buffers gated off while in power-down mode All banks idle, enter power-down mode All banks idle Exit power-down mode Note: Violating refresh requirements during power down may result in a loss of data. Figure 32: Power-Down Mode 48 Don't Care T0 T2 T1 tCK T4 T3 tCL tCH T5 T6 NOP NOP T8 T7 T9 CLK tCKH tCKS CKE tCMH tCMS COMMAND READ NOP tCMS NOP NOP WRITE NOP tCMH DQM tAH tAS column COLUMN A(0:9,11:12) m2 e2 tAH tAS A(10) tAH tAS BA(0,1) BANK Bank tLZ DQ High-Z tAC tOH tAC Dout m tHZ Dout m+1 Notes: 1. For this example, BL=2, CL=3 and auto precharge is disabled. 2. A12 = "Dont Care." Figure 33: Clock Suspend Mode 49 tDS tDH Din e Din + 1 Don't Care Undefined T0 T1 tCK Tn+1 Tn+1 T2 tCH tCL CLK tCKH tCKS CKE tCMH tCMS PRE CHARGE COMMAND NOP AUTO REFRESH NOP NOP AUTO REFRESH NOP NOP ACTIVE DQM A(0:9,11:12) ROW Row ALL BANKS A(10) SINGLE BANK tAS BA(0,1) DQ ROW tAH BANK(s) BANK High-Z tRP tRFC tRFC Don't Care Precharge all active banks Figure 34: Auto-Refresh Mode 50 T0 T2 T1 T3 tCH tCK T4 T5 T6 NOP NOP T7 T8 tCL CLK tCKH tCKS CKE tCMH tCMS COMMAND NOP ACTIVE NOP READ NOP PRE CHARGE NOP ACTIVE tCMH tCMS DQM tAS A(0:9,11:12) ROW tAH ALL BANKS ROW ROW tAS BA(0,1) column m2 ROW tAS A(10) tAH tAH BANK BANK BANK tLZ DQ SINGLE BANK DISABLE AUTO PRECHARGE High-Z tAC tAC tOH Dout m tRCD tAC tOH m+1 BANK tAC tOH m+2 CAS Latency tRAS tRC tHZ tOH m+3 tRP Don't Care Undefined Notes: 1. For this example BL = 4, CL = 2, and the read burst is followed by a "manual" PRECHARGE 2. A12 = "Don't Care" Figure 35: READ - Without Auto Precharge 51 T0 T2 T1 T3 tCK T4 T5 T6 NOP NOP NOP tCH tCL T7 T8 T9 T10 NOP NOP ACTIVE CLK tCKH tCKS CKE tCMH tCMS COMMAND ACTIVE NOP NOP READ NOP tCMH tCMS DQM tAH A(0:9,11:12) tAS ROW A(10) tAS ROW tAS BA(0,1) column m2 tAH ROW ENABLE AUTO PRECHARGE ROW tAH BANK BANK BANK tLZ DQ tAC tAC High-Z tOH Dout m tOH m+1 CAS Latency tRCD tHZ tAC tAC tOH m+2 tOH m+3 tRP tRAS tRC Notes: 1. For this example BL=4, and CL = 2. 2. A12 = "Dont Care." Don't Care Undefined Figure 36: READ - With Auto Precharge 52 T0 T1 T2 T3 T4 tCH tCK T5 T6 T7 T8 T9 tCL CLK tCKH tCKS CKE tCMH tCMS COMMAND NOP ACTIVE NOP READ NOP NOP NOP PRE CHARGE NOP ACTIVE tCMH tCMS DQM tAS A(0:9,11:12) A(10) column m2 ROW tAS ROW tAS BA(0,1) tAH ROW tAH ALL BANKS ROW tAH BANK BANK BANK(S) tLZ DQ SINGLE BANK DISABLE AUTO PRECHARGE High-Z tAC BANK tHZ tOH Dout m tRCD tRAS tRC Notes: 1. For this example, BL = 1, CL = 2, and the READ burst is followed by a manual PRECHARGE. 2. A12 = "Dont Care." Figure 37: Single READ - Without Auto Precharge 53 Don't Care Transitioning Data T0 T1 T2 T4 T3 tCH tCK T5 T6 NOP NOP T7 T8 T9 tCL CLK tCKH tCKS CKE tCMH tCMS COMMAND NOP ACTIVE NOP3 NOP3 READ ACTIVE NOP DQM tAS A(0:9,11:12) ROW tAH ENABLE AUTO PRECHARGE ROW tAS BA(0,1) column m2 ROW tAS A(10) tAH ROW tAH BANK BANK BANK tLZ DQ High-Z tHZ tOH tAC Dout m CAS Latency tRCD tRAS tRP tRC Don't Care Notes: 1. For this example, BL=1, and CL = 2. 2. A12 = "Dont Care." 3. READ command not allowed (would violate tRAS). Undefined Figure 38: Single READ - With Auto Precharge 54 T0 T1 tCK T2 tCH T4 T5 T6 T7 T8 NOP NOP NOP READ NOP T3 T9 tCL CLK tCKH tCKS CKE COMMAND tCMH tCMS ACTIVE NOP NOP READ ACTIVE tCMH tCMS DQM tAS A(0:9,11:12) A(10) DQ column m3 ROW tAS ROW tAS BA(0,1) tAH column b3 ROW ROW tAH ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE ROW ROW tAH BANK 0 BANK BANK 3 tAC tOH tLZ tAC High-Z Dout m tAC tOH m+1 BANK 0 BANK 3 tAC tOH m+2 tAC tOH m+3 tAC tOH Dout b CAS Latency - Bank 0 tRCD - Bank 0 tRP- Bank 0 tRAS - Bank 0 tRC - Bank 0 tRRD CAS Latency - Bank 3 tRCD - Bank 3 Don't Care Notes: 1. For this example, BL=4, CL = 2. 2. A12 = "Dont Care." Undefined Figure 39: Alternating Bank Read Accesses 55 T0 T1 T2 T4 T3 T5 tCH tCK T6 T7 T8 NOP NOP NOP T9 tCL CLK tCKH tCKS CKE tCMH tCMS COMMAND NOP ACTIVE NOP READ NOP NOP BURST TERM NOP tCMH tCMS DQM tAS tAH column m2 ROW tAS A(10) BA(0,1) tAH ROW tAH tAS BANK BANK tAC tOH tLZ tAC DQ Dout m tRCD CAS Latency tAC tOH m+1 tAC tOH m+2 tAC tOH m-1 tAC tOH Dout m tHZ tOH m+1 1024 locations within same row Notes: 1. For this example, CL = 2. 2. A12 = "Dont Care" 3. Page left open; no tRP Don't Care Undefined Figure 40: READ - Full-Page Burst 56 NOP T1 T0 T2 T4 T5 T6 T7 T8 T9 NOP NOP NOP NOP NOP NOP T3 tCH tCK tCL CLK tCKH tCKS CKE tCMH tCMS COMMAND NOP ACTIVE NOP READ tCMH tCMS DQM A(0:9,11:12) tAS ROW tAS A(10) column m tAH ENABLE AUTO PRECHARGE ROW tAS BA(0,1) tAH DISABLE AUTO PRECHARGE tAH BANK BANK tLZ DQ tAC tAC High-Z tOH Dout m tRCD tLZ tAC tAC tOH m+2 tHZ tOH m+3 CAS Latency Don't Care Notes: 1. For this example, BL=4, and CL = 2 2. A12 = "Dont Care" Undefined Figure 41: READ DQM Operation 57 T0 tCK T1 T2 T3 T4 tCH tCL T5 T6 T7 NOP NOP NOP T8 T9 CLK tCKH tCKS CKE tCMH tCMS COMMAND ACTIVE NOP NOP WRITE NOP PRE CHARGE NOP NOP NOP ACTIVE tCMH tCMS DQM A(0:9,11:12) tAH tAS ROW A(10) tAH tAS ROW column m3 ALL BANKS ROW SINGLE BANK DISABLE AUTO PRECHARGE tAH tAS BA(0,1) ROW BANK BANK tDH tDS Din m DQ BANK tDS tDH m+1 tDH tDS tDS m+2 BANK tDH m+3 tRCD tWR3 tRP tRAS tRC Don't Care Notes: 1. For this example, BL= 4, and the WRITE burst is followed by a manual PRECHARGE. 2. 14ns to 15 ns is required between <Din m+3 > and the PRECHARGE command, regardless of frequency. 3. A12 = "Dont Care." Figure 42: WRITE - Without Auto Precharge 58 T0 tCK T1 T2 T3 T4 tCH tCL T5 T6 T7 NOP NOP NOP T8 T9 NOP NOP CLK tCKH tCKS CKE tCMH tCMS ACTIVE NOP NOP WRITE NOP NOP NOP ACTIVE tCMH tCMS DQM tAH tAS ROW A(10) column m2 tAH tAS ROW ROW ENABLE AUTO PRECHARGE tAH tAS BA(0,1) ROW BANK BANK tDH tDS Din m DQ BANK tDS tDH m+1 tDH tDS m+2 tDS tDH m+3 tRCD tWR tRP tRAS tRC Notes: 1. For this example, BL= 4. 2. A12 = "Dont Care." Don't Care Figure 43: WRITE - With Auto Precharge 59 T0 tCK T1 T2 T3 T4 tCH tCL T5 T6 T7 NOP NOP NOP T8 T9 CLK tCKH tCKS CKE tCMH tCMS COMMAND ACTIVE NOP NOP WRITE NOP NOP PRE CHARGE NOP NOP ACTIVE tCMH tCMS DQM A(0:9,11:12) tAH tAS ROW A(10) tAH tAS ROW column m3 ALL BANKS ROW SINGLE BANK DISABLE AUTO PRECHARGE tAH tAS BA(0,1) ROW BANK BANK BANK tDS tDH tDH tDS Din m m+1 DQ BANK tDH tDS m+2 tDS tDH m+3 tRCD tWR2 tRP tRAS tRC Don't Care Notes: 1. For this example, BL= 1, and the WRITE burst is followed by a manual PRECHARGE. 2. 14ns to 15ns is required between <Din m > and the PRECHARGE command, regardless of frequency. 3. A12 = "Dont Care." 4. PRECHARGE command not allowed else tRAS would be violated. Figure 44: Single WRITE - Without Auto Precharge 60 T0 T1 T2 T3 T4 tCH tCK T5 T6 T7 T8 NOP NOP NOP NOP T9 tCL CLK CKE COMMAND tCKH tCKS tCMH tCMS ACTIVE NOP4 NOP4 NOP4 WRITE ACTIVE DQM tAS A(0:9,11:12) ROW tAH ENABLE AUTO PRECHARGE ROW ROW tAS BA(0,1) column m3 ROW tAS A(10) tAH tAH BANK BANK BANK tDH tDS DQ Din m tRCD3 tWR2 CAS Latency tRAS tRC tRP Don't Care Notes: 1. For this example, BL = 1, and the WRITE burst is followed by a manual PRECHARGE. 2. 14 to 15 ns is required between <Din m > and the PRECHARGE command, regardless of the frequency. 3. A12 = "Dont Care." 4. PRECHARGE command not allowed (would violate tRAS). Figure 45: Single WRITE - With Auto Precharge 61 T0 T1 tCK T2 tCH T4 T3 T5 T6 T7 T8 T9 tCL CLK tCKH tCKS CKE tCMH tCMS ACTIVE NOP COMMAND NOP WRITE NOP ACTIVE NOP WRITE NOP ACTIVE tCMH tCMS DQM A(0:9,11:12) tAS ROW A(10) tAS ROW tAS BA(0,1) tAH column m3 column b3 ROW ROW tAH ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE ROW ROW tAH BANK 0 BANK 0 BANK 1 BANK 0 BANK 1 tDH tDS DQ Din m m+1 m+2 CAS Latency - Bank 0 tRCD - Bank 0 m+3 Din b b+1 b+2 tRP - Bank 0 tWR - Bank 0 tRAS - Bank 0 tRC - Bank 0 tRRD CAS Latency - Bank 1 tRCD - Bank 1 Don't Care Notes: 1. For this example, BL=4, CL=2. 2. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14 to 15ns with PRECHARGE. 3. A12 = "Dont Care." Figure 46: Alternating Bank WRITE Accesses 62 T0 T1 T2 tCK T3 tCH Tn+1 T4 T5 T6 NOP NOP NOP NOP m+1 m+2 m+3 Din m-1 tCL Tn+3 Tn+2 CLK tCKH tCKS CKE tCMH tCMS COMMAND NOP ACTIVE NOP WRITE BURST TERMINATE NOP tCMH tCMS DQM tAH A(0:9,11:12) tAS ROW A(10) tAS ROW BA(0,1) tAS BANK column m1 tAH tAH BANK tDS DQ Din m tDH 2048 locations within same row tRCD Full page completed Notes: 1. A12 = "Dont Care." 2. tWR must be satisfied prior to PRECHARGE command. 3. Page left open; no tRP. Figure 47: WRITE Full-Page Burst 63 Full-Page Burst does not self-terminate. Can use BURST TERMINATE command to stop. Don't Care T0 T1 T3 T2 tCK tCH T4 T5 T6 NOP NOP m+2 m+3 T7 T8 tCL CLK tCKH tCKS CKE tCMH tCMS COMMAND NOP ACTIVE NOP NOP WRITE NOP NOP tCMH tCMS DQM tAH tAS A(0:9,11:12) column m2 ROW tAH tAS A(10) ENABLE AUTO PRECHARGE ROW DISABLE AUTO PRECHARGE tAH tAS BA(0,1) BANK BANK tDH tDS DQ Din m tRCD Don't Care Undefined Notes: 1. For this example, BL=4. 2. A12 = "Dont Care." Figure 48: WRITE - DQM Operation 64 Packaging Prototypes Only Figure 49: 128-lead Ceramic, Extended Side-Braze, Dual Sided Quad Flatpack (Datasheet Case Outline: X) 65 Packaging Production Figure 50: 128-lead Ceramic, Shallow Side-Braze, Dual Sided Quad Flatpack (Datasheet Case Outline: Y / SMD Case Outline: X) 66 Recommended Universal Footprint and Lead Forming Guidelines LEAD FORMING GUIDELINES: APPLY THE FOLLOWING LEAD FORMING GUIDELINES TO ENSURE THE 128 LEAD CERAMIC QFP WILL FIT THIS FOOTPRINT. 1) FIRST LEAD BEND IS 1.14 +/- 0.13 (0.045 +/- 0.13) FROM THE BODY. 2) SECOND LEAD BEND IS MADE 2.67 -0/+0.51 (0.105 -0/+0.020) TO ALLOW PWB TO COMPONENT BODY CLEARANCE. 3) THE FOOT OF THE LEAD IS 1.14 +/- 0.13 (0.045 +/- 0.005) THESE LEAD FORMING GUIDELINES ARE COMPATABLE WITH IPC/EIA J-STD001C FOR NOMINAL SOLDER FILLETS AND IPC-SM-782 FOR LAND PATTERN DESIGN PAD SIZE = 0.356 X 3.81 (0.014 X 0.150) Figure 51: Recommended Footprint for Combination of Aeroflex UT8SDMQ64 Prototype and Production Packages 67 ORDERING INFORMATION 64Meg x 40 SDRAM 64Meg x 48 SDRAM UT ********** - ** * * * Lead Finish: (Note 1) (C) = Gold Screening: (Notes 2 and 3) (E) = HiRel Flow (Temperature Range: -40oC to +1050C) (P) = Prototype flow (Temperature Range: 25oC only) Package Type: (X) = 128-lead ceramic, extended side-braze, dual sided, quad flatpack (Prototypes only - Figure 49) (Y) = 128-lead ceramic, shallow side-braze, dual sided, quad flatpack (HiRel & Prototype - Figure 50) Access Time: (75) = 7.5ns cycle time @ CL=3 (PCI33) (10) = 10ns cycle time @ CL=3 (PC100) Device Type: (8SDMQ64M40) = 64Meg x 40 (8SDMQ64M48) = 64Meg x 48 Notes: 1. Lead finish is "C" (Gold) only, and must be specified. 2. Prototype Flow per Aeroflex Manufacturing Flows Document. Devices are tested at 25oC only. Radiation is neither tested nor guaranteed. 3. HiRel flow per Aeroflex Manufacturing Flows Document. Radiation is neither tested nor guaranteed. 68 64Meg x 40 SDRAM: SMD 64Meg x 48 SDRAM: SMD 5962 - ***** ** * * * Lead Finish: NOTE 1 (C) = Gold Case Outline: (X) = 128-lead ceramic, shallow side-braze, dual sided, quad flatpack (Figure 50) Class Designator: (Q) = QML Class Q Device Type (NOTE 2) (01) = SDRAM (-40oC to +105oC) (02) = SDRAM assembled to Aeroflex Q+ Flow (-40oC to +105oC) Drawing Number: 10229: 2.5G SDRAM (64 meg x 40) 10230: 3.0G SDRAM (64 meg x 48) Total Dose (-) = none (D) = 1E4 (10krad(Si)) (P) = 3E4 (30krad(Si)) (L) = 5E4 (50krad(Si)) (R) = 1E5 (100krad(Si)) Federal Stock Class Designator: No Options Notes: 1. Lead finish is "C" (Gold) only. 2. Aeroflex's Q+ assembly flow, as defined in section 4.2.2.d of the SMD, provides QML Q product through the SMD that is manufactured with Aeroflex's standard QML V flow. 69 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com Aeroflex Colorado Springs (Aeroflex) reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused 70