1
FEATURES
APPLICATIONS
DESCRIPTION
DAC5670-SP
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............................................................................................................................................................................................... SGLS386 – JANUARY 2009
14-BIT 2.4-GSPS DIGITAL-TO-ANALOG CONVERTER
•Differential Scalable Current Outputs:5 mA to 30 mA2
•14-Bit Resolution
•On-Chip 1.2-V Reference•2.4-GSPS Maximum Update Rate Digital toAnalog Converter •3.3-V Analog Supply Operation•Dual Differential Input Ports •Power Dissipation: 2 W– Even/Odd Demultiplexed Data •192-Ball CBGA (GEM) Package– Maximum 1.2 GSPS Each Port, 2.4 GSPS •QML-V Qualified, SMD 5962-07247Total
•Military Temperature Range– Dual 14-Bit Inputs + 1 Reference Bit (-55 ° C to 125 ° C T
case
)– DDR Output Clock– DLL Optimized Clock Timing Synchronized
•Cable Modem Termination System Directto Reference Bit
Synthesis– LVDS and HyperTransport™ Voltage Level
•Cellular Base Transceiver Station TransmitCompatible
Channels– Internal 100- ΩTerminations for Data and
– CDMA: W-CDMA, CDMA2000, TD-SCDMAReference Bit Inputs
– 800 to 900-MHz Direct Synthesis•Selectable 2 Times Interpolation With Fs/2
•Point-to-Point MicrowaveMixing
•Radar
•Satellite Communications
The DAC5670 is a 14-bit 2.4-GSPS digital-to-analog converter (DAC) with dual demultiplexed differential inputports. The DAC5670 is clocked at the DAC sample rate and the two input ports run at a maximum of 1.2 GSPS.An additional reference bit input sequence is used to adjust the output clock delay to the data source, optimizingthe internal data latching clock relative to this reference bit with a delay lock loop (DLL).
The DAC5670 also can accept data up to 1.2 GSPS on one input port the same clock configuration. In the singleport mode, repeating the input sample (A_ONLY mode), 2 times interpolation by zero stuff (A_ONLY_ZS mode),or 2 times interpolation by repeating and inverting the input sample (A_ONLY_INV) are used to double the inputsample rate up to 2.4 GSPS.
The DAC5670 operates with a single 3-V to 3.6-V supply voltage. Power dissipation is 2 W at maximumoperating conditions. The DAC5670 provides a nominal full-scale differential current-output of 20 mA, supportingboth single-ended and differential applications. An on-chip 1.2-V temperature-compensated bandgap referenceand control amplifier allows the user to adjust the full-scale output current from the nominal 20 mA to as low as 5mA or as high as 30 mA. The output current can be directly fed to the load with no additional external outputbuffer required. The device has been specifically designed for a differential transformer coupled output with a50- Ωdoubly-terminated load.
The DAC5670 is available in a 192-ball CBGA package. The device is characterized for operation over themilitary temperature range ( – 55 ° C to 125 ° C T
case
).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
100
Phase
Detector
Loop
Filter
Variable
Delay
÷2 ÷2
14bit
2.4Gsps
DAC
100
100
Input
Registers
Demux
and
Format
DA_P[13:0]
DA_N[13:0]
DB_P[13:0]
DB_N[13:0]
DLYCLK_P
DLYCLK_N
DTCLK_P
DTCLK_N
DACCLK_P
DACCLK_N
Bandgap
Ref
REFIO_IN
REFIO
RBIASOUT
RBIASIN
CSBIAS
CSBIAS_IN
IOUT_P
IOUT_N
LVDS_HTB
INV_CLK
ModeControls
NORMAL
A_ONLY
A_ONLY_INV
A_ONLY_ZS
RESTART
LOCK
SLEEP
100
Phase
Detector
Loop
Filter
Variable
Delay
÷2 ÷2
14bit
2.4Gsps
DAC
100
100
Input
Registers
Demux
and
Format
DA_P[13:0]
DA_N[13:0]
DB_P[13:0]
DB_N[13:0]
DLYCLK_P
DLYCLK_N
DTCLK_P
DTCLK_N
DACCLK_P
DACCLK_N
Bandgap
Ref
REFIO_IN
REFIO
RBIASOUT
RBIASIN
CSBIAS
CSBIAS_IN
IOUT_P
IOUT_N
LVDS_HTB
INV_CLK
ModeControls
NORMAL
A_ONLY
A_ONLY_INV
A_ONLY_ZS
RESTART
SLEEP
DAC5670-SP
SGLS386 – JANUARY 2009 ...............................................................................................................................................................................................
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AVAILABLE OPTIONS
TEMPERATURE PACKAGE
(1)
TOP SIDE SYMBOL
5962-0724701VXA– 55 ° C to 125 ° C T
case
192-GEM
DAC5670MGEM-V
(1) For the most current package and ordering information, see the Package Option Addendum at the endof this document, or see the TI website at www.ti.com.
Figure 1. Functional Block Diagram DAC5670
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Table 1. Terminal Assignments (Top View)1 2 3 4 5 6 7 8 9 10 11 12 13 14
ADB10_N DB10_P DB12_P DB12_N DLYCLK DLYCLK DTCLK_N DTCLK_P DA2_N DA2_P DA3_N DA3_P_N _P
BDB9_P GND GND DB11_P DB11_N DB13_N DB13_P DA0_P DA0_N DA1_P DA1_N GND GND DA4_P
CDB9_N DB8_P AVDD AVDD AVDD GND GND GND GND AVDD DA7_N DA7_P DA5_P DA4_N
DDB7_N DB8_N DB6_P DB6_N AVDD AVDD AVDD AVDD AVDD AVDD DA6_N DA6_P DA5_N DA8_N
EDB7_P DB5_N AVDD AVDD GND GND GND GND GND GND AVDD AVDD DA9_N DA8_P
FDB3_N DB5_P GND AVDD GND GND GND GND GND GND AVDD GND DA9_P DA10_N
GDB3_P AVDD GND AVDD GND GND AVDD AVDD GND GND AVDD GND DA11_N DA10_P
HDB4_N AVDD GND AVDD GND GND AVDD AVDD GND GND AVDD GND DA11_P DA12_N
JDB4_P DB2_P GND AVDD GND GND GND GND GND GND AVDD GND DA13_P DA12_P
KDB1_P DB2_N AVDD AVDD GND GND GND GND GND GND AVDD AVDD DA13_N Dacclk_P
LDB1_N AVDD REFIO REFIO_I AVDD AVDD AVDD AVDD AVDD AVDD GND Inv_clk AVDD Dacclk_NN
MDB0_P GND AVDD AVDD AVDD IOUT_N IOUT_P GND GND AVDD GND Restart GND GND
NDB0_N GND GND AVDD GND GND GND GND GND A_only A_only_z GND
PCSCap CSCap RBIAS_IN RBIAS GND GND LVDS AVDD Sleep A_only M_IN _OUT _htb _inv _Normal
Table 2. Terminal Assignments (Bottom View)A B C D E F G H J K L M N P
1DB9_P DB9_N DB7_N DB7_P DB3_N DB3_P DB4_N DB4_P DB1_P DB1_N DB0_P DB0_N
2DB10_N GND DB8_P DB8_N DB5_N DB5_P AVDD AVDD DB2_P DB2_N AVDD GND GND CSCap
_IN
3DB10_P GND AVDD DB6_P AVDD GND GND GND GND AVDD REFIO AVDD GND CSCap
4DB12_P DB11_P AVDD DB6_N AVDD AVDD AVDD AVDD AVDD AVDD REFIO_I AVDD AVDD RBIAS_INN
5DB12_N DB11_N AVDD AVDD GND GND GND GND GND GND AVDD AVDD GND RBIAS_O
UT
6DLYCLK DB13_N GND AVDD GND GND GND GND GND GND AVDD IOUT_N GND_N
7DLYCLK DB13_P GND AVDD GND GND AVDD AVDD GND GND AVDD IOUT_P GND GND_P
8DTCLK_N DA0_P GND AVDD GND GND AVDD AVDD GND GND AVDD GND GND GND
9DTCLK_P DA0_N GND AVDD GND GND GND GND GND GND AVDD GND GND LVDS_htb
10 DA2_N DA1_P AVDD AVDD GND GND GND GND GND GND AVDD AVDD A_only AVDD
11 DA2_P DA1_N DA7_N DA6_N AVDD AVDD AVDD AVDD AVDD AVDD GND GND Sleep
12 DA3_N GND DA7_P DA6_P AVDD GND GND GND GND AVDD Inv_clk Restart A_only_in
v
13 DA3_P GND DA5_P DA5_N DA9_N DA9_P DA11_N DA11_P DA13_P DA13_N AVDD GND A_only_z M_Norma
l
1 4 DA4_P DA4_N DA8_N DA8_P DA10_N DA10_P DA12_N DA12_P Dacclk_P Dacclk_N GND GND
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TERMINAL FUNCTIONS
TERMINAL
Type DESCRIPTIONNAME BALL NO.
DACCLK_P K14 I External clock, sample clock for the DACDACCLK_N L14 I Complementary external clock, sample clock for the DACDLYCLK_P A7 O DDR type data clock to data sourceDLYCLK_N A6 O DDR type data clock to data source complementary signalDTCLK_P A9 I Input data toggling reference bitDTCLK_N A8 I Input data toggling reference bit, complementary signal
xxx
DA_P[13] J13 I Port A data bit 13 (MSB)DA_N[13] K13 I Port A data bit 13 complement (MSB)DA_P[12] J14 I Port A data bit 12DA_N[12] H14 I Port A data bit 12 complementDA_P[11] H13 I Port A data bit 11DA_N[11] G13 I Port A data bit 11 complementDA_P[10] G14 I Port A data bit 10DA_N[10] F14 I Port A data bit 10 complementDA_P[9] F13 I Port A data bit 9DA_N[9] E13 I Port A data bit 9 complementDA_P[8] E14 I Port A data bit 8DA_N[8] D14 I Port A data bit 8 complementDA_P[7] C12 I Port A data bit 7DA_N[7] C11 I Port A data bit 7 complementDA_P[6] D12 I Port A data bit 6DA_N[6] D11 I Port A data bit 6 complementDA_P[5] C13 I Port A data bit 5DA_N[5] D13 I Port A data bit 5 complementDA_P[4] B14 I Port A data bit 4DA_N[4] C14 I Port A data bit 4 complementDA_P[3] A13 I Port A data bit 3DA_N[3] A12 I Port A data bit 3 complementDA_P[2] A11 I Port A data bit 2DA_N[2] A10 I Port A data bit 2 complementDA_P[1] B10 I Port A data bit 1DA_N[1] B11 I Port A data bit 1 complementDA_P[0] B8 I Port A data bit 0 (LSB)DA_N[0] B9 I Port A data bit 0 complement (LSB)
xxx
DB_P[13] B7 Port B data bit 13 (MSB)DB_N[13] B6 I Port B data bit 13 complement (MSB)DB_P[12] A4 I Port B data bit 12DB_N[12] A5 I Port B data bit 12 complementDB_P[11] B4 I Port B data bit 11DB_N[11] B5 I Port B data bit 11 complementDB_P[10] A3 I Port B data bit 10DB_N[10] A2 I Port B data bit 10 complementDB_P[9] B1 I Port B data bit 9DB_N[9] C1 I Port B data bit 9 complement
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TERMINAL FUNCTIONS (continued)
TERMINAL
Type DESCRIPTIONNAME BALL NO.
DB_P[8] C2 I Port B data bit 8DB_N[8] D2 I Port B data bit 8 complementDB_P[7] E1 I Port B data bit 7DB_N[7] D1 I Port B data bit 7 complementDB_P[6] D3 I Port B data bit 6DB_N[6] D4 I Port B data bit 6 complementDB_P[5] F2 I Port B data bit 5DB_N[5] E2 I Port B data bit 5 complementDB_P[4] J1 I Port B data bit 4DB_N[4] H1 I Port B data bit 4 complementDB_P[3] G1 I Port B data bit 3DB_N[3] F1 I Port B data bit 3 complementDB_P[2] J2 I Port B data bit 2DB_N[2] K2 I Port B data bit 2 complementDB_P[1] K1 I Port B data bit 1DB_N[1] L1 I Port B data bit 1 complementDB_P[0] M1 I Port B data bit 0 (LSB)DB_N[0] N1 I Port B data bit 0 complement (LSB)
xxx
IOUT_P M7 O DAC current output. Full scale when all input bits are set 1.IOUT_N M6 O DAC complementary current output. Full scale when all input bits are 0.
xxx
RBIASOUT P5 O Rbias resistor current outputRBIASIN P4 I Rbias resistor sense inputCSCAP P3 O Current source bias voltageCSCAP_IN P2 I Current source bias voltage sense inputREFIO L3 O Bandgap reference outputREFIO_IN L4 I Bandgap reference sense input
xxx
RESTART M12 I Resets DLL when high. Low for normal DLL operation.LVDS_HTB P9 I DLYCLK_P/N control, lvds mode when high, ht mode when lowINV_CLK L12 I Inverts the DLL target clocking relationship when high. Low for normal DLL operation.
xxx
SLEEP P11 I Active-high sleepNORMAL P13 I High for {a0,b0,a1,b1,a2,b2, … } normal modeA_ONLY N10 I High for {a0,a0,a1,a1,a2,a2, … } A_only modeA_ONLY_INV P12 I High for {a0,-a0, a1,-a1,a2,-a2, ...} A_only_inv modeA_ONLY_ZS N13 I High for {a0,0,a1,0,a2,0, … } A_only_zs mode
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Absolute Maximum Ratings
(1)
DAC5670-SP
SGLS386 – JANUARY 2009 ...............................................................................................................................................................................................
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over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage AVDD to GND 5.0 VDA_P[13..0], DA_N[13..0],
Measured with respect to GND -0.3 AVDD + 0.3 VDB_P[13..0], DB_N[13..0]NORMAL, A_ONLY,
Measured with respect to GND -0.3 AVDD + 0.3 VA_ONLY_INV, A_ONLY_ZSDTCLK_P, DTCLK_N,
Measured with respect to GND -0.3 AVDD + 0.3 VDACCLK_P, DACCLK_NLVDS_HTB, INV_CLK,
Measured with respect to GND -0.3 AVDD + 0.3 VRESTART
IOUT_P, IOUT_N Measured with respect to GND AVDD – 0.5 AVDD + 1.5 VCSCAP_IN, REFIO_IN,
Measured with respect to GND -0.3 AVDD + 0.3 VRBIAS_IN
Peak input current (any input) 20 mAStorage temperature range – 65 150 ° CMaximum Junction Temperature 150 ° CLead temperature 1,6 mm (1/16 in) from the case for 10 s 260 ° C
(1) Stresses above those listed under " absolute maximum ratings " may cause permanent damage to the device. Exposure to absolutemaximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of thedevice at these or any other conditions beyond those indicated under " recommended operating conditions " is not implied. Exposure toabsolute-maximum-rated conditions for extended periods may affect device reliability.
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............................................................................................................................................................................................... SGLS386 – JANUARY 2009
T
C,MIN
= – 55 ° C to T
C,MAX
= 125 ° C, typical values at 25 ° C, AVDD = 3 V to 3.6 V, IoutFS = 20 mA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
Resolution 14 Bits
DC Accuracy
INL Integral nonlinearity – 7.5 ± 1.5 7.5T
C,MIN
to T
C,MAX
, f
DAC
= 640 KHz,
LSBf
OUT
= 10 KHzDNL Differential nonlinearity – 0.98 ± 0.8 1.75
Monotonocity 14 Bits
Analog Output
Offset error Mid code offset – 0.45 ± 0.09 0.45 %FSRGain error With external reference – 6.0 ± 1.6 6.0 %FSRGain error With internal reference – 6.0 ± 1.6 6.0 %FSRFull-scale output current 30 mAI
O(FS)
= 20 mA, AV
DD
= 3.15 V toOutput compliance range AVDD – 0.5 AVDD + 0.5 V3.45 VOutput resistance 300
(2)
kΩ
Output capacitance IOUT_P and IOUT_N single ended 13.7
(2)
pF
Reference Output
Reference voltage 1.14 1.2 1.26 VReference output current 100 nA
Reference Input
V
REFIO
Input voltage range 1.14 1.2 1.26 VInput resistance 1
(2)
MΩ
Small-signal bandwidth 1.4 MHzInput capacitance 3.2
(2)
pF
Temperature Coefficients
Offset drift 75 ppm of FSR/ ° CGain drift With external reference 75 ppm of FSR/ ° CGain drift With internal reference 75 ppm of FSR/ ° CReference voltage drift 35 ppm/ ° C
Power Supply
AVDD Analog supply voltage 3 3.3 3.6 Vf
DAC
= 2.4 GHz, NORMAL inputI
AVDD
Analog supply current 560 650 mAmodeSleep mode, AVDD supplyI
AVDD
Sleep mode (SLEEP pin high) 150 180 mAcurrent
f
DAC
= 2.4 GHz, NORMAL inputP Power dissipation 1800 2350 mWmodePSRR Power-supply rejection ratio AV
DD
= 3.15V to 3.45V 0.4 1.3 %FSR/V
(1) Typicals are characterization values at 25C and AVDD = 3.3V. These parameters are characterized but not production tested.(2) Specified by design
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AC Electrical Characteristics
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T
C,MIN
= – 55 ° C to T
C,MAX
= 125 ° C, typical values at 25 ° C, AVDD = 3 V to 3.6 V, IoutFS = 20 mA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
Analog Output
f
DAC
Maximum output update
2.4 GSPSratet
s(DAC)
Output setting time to
Mid-scale transition 3.5 ns0.1%t
pd
7 DACCLKOutput propagation delay
+ 1.5 nst
r(IOUT)
Output rise time, 10% to
280 ps90%t
f(IOUT)
Output fall time, 90% to
280 ps10%
AC Performance
f
DAC
= 2.4 GSPS, f
OUT
= 100 MHz, Dual-port
46 55mode, 0 dBFSf
DAC
= 2.4 GSPS, f
OUT
= 200 MHz, Dual-port
51mode, 0 dBFSSpurious-free dynamic f
DAC
= 2.4 GSPS, f
OUT
= 300 MHz, Dual-portSFDR 31 36 dBcrange mode, 0 dBFSf
DAC
= 2.4 GSPS, f
OUT
= 500 MHz, Dual-port
35 43mode, 0 dBFSf
DAC
= 2.4 GSPS, f
OUT
= 500 MHz, Dual-port
47mode, – 6 dBFSf
DAC
= 2.4 GSPS, f
OUT
= 100 MHz, Dual-port
58 60mode, 0 dBFSf
DAC
= 2.4 GSPS, f
OUT
= 200 MHz, Dual-port
60mode, 0 dBFSf
DAC
= 2.4 GSPS, f
OUT
= 300 MHz, Dual-portSNR Signal-to-noise ratio 56 62 dBcmode, 0 dBFSf
DAC
= 2.4 GSPS, f
OUT
= 500 MHz, Dual-port
51 58mode, 0 dBFSf
DAC
= 2.4 GSPS, f
OUT
= 500 MHz, Dual-port
52mode, – 6 dBFSf
DAC
= 2.4 GSPS, f
OUT
= 100 MHz, Dual-port
45 52mode, 0 dBFSf
DAC
= 2.4 GSPS, f
OUT
= 200 MHz, Dual-port
50mode, 0 dBFSf
DAC
= 2.4 GSPS, f
OUT
= 300 MHz, Dual-portTHD Total harmonic distortion 31 36 dBcmode, 0 dBFSf
DAC
= 2.4 GSPS, f
OUT
= 500 MHz, Dual-port
35 46mode, 0 dBFSf
DAC
= 2.4 GSPS, f
OUT
= 500 MHz, Dual-port
44mode, – 6 dBFSf
DAC
= 2.4 GSPS, f
OUT
= 99 MHz and 102 MHz,
70 dBcEach tone at – 6 dBFS, Dual-port mode.f
DAC
= 2.4 GSPS, f
OUT
= 200 MHz and 202 MHz,
68 dBcEach tone at – 6 dBFS, Dual-port mode.Third-order two-toneIMD3
intermodulation
f
DAC
= 2.4 GSPS, f
OUT
= 253 Mhz and 257 MHz,
47 57 dBcEach tone at – 6 dBFS, Dual-port mode.f
DAC
= 2.4 GSPS, f
OUT
= 299 Mhz and 302 MHz,
35 55 dBcEach tone at – 6 dBFS, Dual-port mode.f
DAC
= 2.4 GSPS, f
OUT
= 298 MHz, 299 MHz,IMD Four-tone intermodulation 300 MHz, and 301 MHz, Each tone at – 12 47 62.5 dBcdBFS, Dual-port mode.
(1) Typicals are characterization values at 25C and AVDD = 3.3V. These parameters are characterized but not production tested
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............................................................................................................................................................................................... SGLS386 – JANUARY 2009
T
C,MIN
= – 55 ° C to T
C,MAX
= 125 ° C, typical values at 25 ° C, AVDD = 3 V to 3.6 V, IoutFS = 20 mA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
CMOS Interface (SLEEP, RESTART, INV_CLK, NORMAL, A_ONLY, A_ONLY_INV, A_ONLY_ZS)
V
IH
High-level input voltage 2 3 VV
IL
Low-level input voltage 0 0 0.8 VI
IH
High-level input current 0.2 10 µAI
IL
Low-level input current -10 -0.2 µAInput capacitance 2.5
(2)
pF
Differential Data Interface (DA_P[13:0], DA_N[13:0], DB_P[13:0], DB_N[13:0], DTCLK_P, DTCLK_N)
V
ITH
Differential input threshold – 100 100 mVZ
T
Internal termination impedance 80 100 125 Ω
V
ICOM
Input common mode 0.6 1.4 VC
i
Input capacitance 2.6
(2)
pF
Clock Inputs (DACCLK_P, DACCLK_N)
|DACCLK_P -
Clock differential input voltage 200 1000 mVDACCLK_N|
Clock duty cycle 40 60 %VCLKCM Clock common mode 1.0 1.4 V
(1) Typicals are characterization values at 25C and AVDD = 3.3V. These parameters are characterized but not production tested(2) Specified by design
Thermal Information
Parameter TEST CONDITIONS TYPICAL UNIT
Non-thermally enhanced JEDEC standardR
θJA
Junction-to-free-air thermal resistance 41.3 ° C/WPCB, per JESD-51, 51-3RθJC Junction-to-case thermal resistance MIL-STD-883 test method 1012 3.8 ° C/W
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1
10
100
100 110 120 130 140 150 160
Continuous TJ(°C)
Estimated Life (Years)
Electromigration Fail Mode
DAC5670-SP
SGLS386 – JANUARY 2009 ...............................................................................................................................................................................................
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A. See data sheet for absolute maximum and minimum recommended operating conditions.B. Silicon operating life design goal is 10 years at 105 ° C junction temperture (does not include package interconnectlife).
Figure 2. DAC5670MGEM-V - 192/GEM PackageOperating LIfe Derating Chart
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TYPICAL CHARACTERISTICS
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............................................................................................................................................................................................... SGLS386 – JANUARY 2009
Single-Tone Spectrum PowervsFrequency
Figure 3.
Two-Tone IMD (Power)
vsFrequency
Figure 4.
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TYPICAL CHARACTERISTICS (continued)W-CDMA TM1 Single Carrier PowervsFrequency
Figure 5.
W-CDMA TM1 Single Carrier PowervsFrequency
Figure 6.
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TYPICAL CHARACTERISTICS (continued)W-CDMA TM1 Dual Carrier PowervsFrequency
Figure 7.
W-CDMA TM1 Three Carrier PowervsFrequency
Figure 8.
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TYPICAL CHARACTERISTICS (continued)W-CDMA TM1 Four Carrier PowervsFrequency
Figure 9.
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APPLICATION INFORMATION
Detailed Description
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............................................................................................................................................................................................... SGLS386 – JANUARY 2009
Figure 10 shows a simplified block diagram of the current steering DAC5670. The DAC5670 consists of asegmented array of NPN-transistor current sinks, capable of delivering a full-scale output current up to 30mA.Differential current switches direct the current of each current sink to either one of the complementary outputnodes IOUT_P or IOUT_N. The complementary current output enables differential operation, canceling outcommon-mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, and even-order distortioncomponents, and doubling signal output power.
The full-scale output current is set using an external resistor (RBIAS) in combination with an on-chip bandgapvoltage reference source (1.2V) and control amplifier. The current (IBIAS) through resistor RBIAS is mirroredinternally to provide a full-scale output current equal to 32 times IBIAS. The full-scale current is adjustable from30mA down to 5mA by using the appropriate bias resistor value.
Figure 10. Current Steering DAC5670
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Digital Inputs
DAC5670-SP
SGLS386 – JANUARY 2009 ...............................................................................................................................................................................................
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The DAC5670 differential digital inputs are compatible with LVDS and HyperTransport voltage levels.
Figure 11. Digital Input Voltage Options
The DAC5670 uses low voltage differential signaling (LVDS and Hyper-Transport) for the bus input interface. TheLVDS and Hyper-Transport input modes feature a low differential voltage swing. The differential characteristic ofLVDS and Hyper-Transport modes allow for high-speed data transmission with low electromagnetic interference(EMI) levels. Figure 12 shows the equivalent complementary digital input interface for the DAC5670, valid forpins DA_P[13:0], DA_N[13:0], DB_P[13:0], and DB_N[13:0].
Figure 12.
16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC5670-SP
DACCLK_P DACCLK_N
DA_P[13:0]
DA_N[13:0]
DB_P[13:0]
DB_N[13:0]
DLYCLK_P
DLYCLK_N
DTCLK_P
DTCLK_N
DataSource
Input
Registers
Delay
Locked
Loop
(DLL)
÷2 ÷2
DAC5670
DACCLK_P DACCLK_N
DA_P[13:0]
DA_N[13:0]
DB_P[13:0]
DB_N[13:0]
DLYCLK_P
DLYCLK_N
DTCLK_P
DTCLK_N
DataSource
Input
Registers
Delay
Locked
Loop
(DLL)
÷2 ÷2
DAC5670
DAC5670-SP
www.ti.com
............................................................................................................................................................................................... SGLS386 – JANUARY 2009
Figure 13 shows a schematic of the equivalent CMOS/TTL-compatible digital inputs of the DAC5670, valid for thefollowing pins: RESTART, LVDS_HTB, INV_CLK, SLEEP, NORMAL, A_ONLY, A_ONLY_INV, and A_ONLY_ZS.
Figure 13.
The DAC5670 is clocked at the DAC sample rate. Each input port runs at a maximum of 1.2 GSPS. TheDAC5670 provides an output clock at one-half the input port data rate (DACCLK/4), monitors an additionalreference bit input sequence, and adjusts the output clock delay to optimize the data latch relative to thereference bit with a DLL. The DLL delay automatically adjusts for drift over temperature and time.
Figure 14. DLL Input Loop Simplified Block Diagram
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Product Folder Link(s): DAC5670-SP
DACCLK_P/N
DACCLK/2internal
toDAC5670
DLYCLKisDACCLK/4delayedbytheDAC5670DLL tobeusedasthe DDRclockforthedatasourcedigitalchip
DTCLKisatogglingbit,alignedwithDA andDBdatafromdigita lchip,usedbytheDAC5670DLL feedbackpath
DA_P/N[13:0]
b0
a0
b1
a1
b2
a2
b3
a3
sourcedigitalchip’sclocktodataoutputtime
DLYCLK_P/N
DTCLK_P/N
DB_P/N[13:0]
internaldatato
theDACcorein
NORMAL mode a0 b0 a1 b1
TBDpipelinedelay
ThisinternalDACCLK/2isusedtoclocktheinputdataDA andDB intotheDAC5670
DACCLK_P/N
DACCLK/2internal
toDAC5670
DLYCLKisDACCLK/4delayedbytheDAC5670DLL tobeusedasthe DDRclockforthedatasourcedigitalchip
DTCLKisatogglingbit,alignedwithDA andDBdatafromdigita lchip,usedbytheDAC5670DLL feedbackpath
DA_P/N[13:0]
b0
a0
b1
a1
b2
a2
b3
a3
sourcedigitalchip’sclocktodataoutputtime
DLYCLK_P/N
DTCLK_P/N
DB_P/N[13:0]
internaldatato
theDACcorein
NORMAL mode a0 b0 a1 b1
TBDpipelinedelay
ThisinternalDACCLK/2isusedtoclocktheinputdataDA andDB intotheDAC5670
Input Format
DAC5670-SP
SGLS386 – JANUARY 2009 ...............................................................................................................................................................................................
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Figure 15. DLL Input Loop Functional Timing
The DAC5670 has four input modes selected by the four mutually exclusive configuration pins: NORMAL,A_ONLY, A_ONLY_INV, and A_ONLY_ZS. Table 3 lists the input modes, the input sample rates, the maximumDAC sample rate (CLK input) and resulting DAC output sequence for each configuration. For all configurations,the DLYCLK_P/N outputs and DTCLK_P/N inputs are DACCLK_P/N frequency divided by four.
Table 3. DAC5670 Input Formats
DLYCLK_P/N
ANDf
DAC
MAX DAC OUTPUTNORMAL A_ONLY A_ONLY_INV A_ONLY_ZS FinA/Fdac FinB/Fdac DTCLK_P/N
(MHz) SEQUENCEFREQ
(MHz)
A0, B0, A1, B1,1 0 0 0 1/2 1/2 2400 Fdac/4
A2, B2, . . .A0, A0, A1, A1,0 1 0 0 1/2 Off 2400 Fdac/4
A2, A2, . . .A0, – A0, A1, – A1,0 0 1 0 1/2 Off 2400 Fdac/4
A2, – A2, . .A0, 0, A1, 0,0 0 0 1 1/2 Off 2400 Fdac/4
A2, 0, . . .
18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC5670-SP
Clock Input
DAC5670-SP
www.ti.com
............................................................................................................................................................................................... SGLS386 – JANUARY 2009
The DAC5670 features differential, LVPECL compatible clock inputs (DACCLK_P, DACCLK_N). Figure 16 showsthe equivalent schematic of the clock input buffer. The internal biasing resistors set the input common-modevoltage to AVDD/2, while the input resistance is typically 1 k Ω. A variety of clock sources can be ac-coupled tothe device, including a sine wave source (see Figure 17 ).
Figure 16. Clock Equivalent Input
Figure 17. Driving the DAC5670 with a Single-Ended Clock Source Using a Transformer
To obtain best ac performance the DAC5670 clock input should be driven with a differential LVPECL or sinewave source as shown in Figure 18 and Figure 19 . Here, the potential of VTT should be set to the terminationvoltage required by the driver along with the proper termination resistors (RT). The DAC5670 clock input can alsobe driven single-ended for slower clock rates using TTL/CMOS levels; this is shown in Figure 20 .
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DAC5670-SP
SGLS386 – JANUARY 2009 ...............................................................................................................................................................................................
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Figure 18. Driving the DAC5670 with a Single-Ended ECL/PECL Clock Source
Figure 19. Driving the DAC5670 with a Differential ECL/PECL Clock Source
Figure 20. Driving the DAC5670 with a Single-Ended TTL/CMOS Clock Source
20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC5670-SP
DAC Transfer Function
DAC5670-SP
www.ti.com
............................................................................................................................................................................................... SGLS386 – JANUARY 2009
The DAC5670 has a current sink output. The current flow through IOUT_P and IOUT_N is controlled byDx_P[13:0] and Dx_N[13:0]. For ease of use, we denote D[13:0] as the logical bit equivalent of Dx_P[13:0] andits complement Dx_N[13:0]. The DAC5670 supports straight binary coding with D13 being the MSB and D0 theLSB. Full-scale current flows through IOUTP when all D[13:0] inputs are set high and through IOUTN when allD[13:0] inputs are set low. The relationship between IOUT_P and IOUT_N can be expressed as Equation 1 :IOUT_N = IO
(FS)
- IOUT_P (1)
IO
(FS)
is the full-scale output current sink (5 mA to 30 mA). Since the output stage is a current sink, the currentcan only flow from AVDD through the load resistors R
L
into the IOUT_N and IOUT_P pins.
The output current flow in each pin driving a resistive load can be expressed as shown in Figure 21 , as well as inEquation 2 and Equation 3 .
Figure 21. Relationship between D[13:0], IOUT_N and IOUT_P
IOUT_N = (IOUT
(FS)
x (16383 - CODE)) / 16384 (2)
IOUT_P = (IOUT
(FS)
x CODE) / 16384 (3)
where CODE is the decimal representation of the DAC input word. This would translate into single-endedvoltages at IOUT_N and IOUT_P, as shown in Equation 4 and Equation 5 :VOUTN = AVDD - IOUT_N x R
L
(4)
VOUTP = AVDD - IOUT_P x R
L
(5)
For example, assuming that D[13:0] = 1 and that R
L
is 50 Ω, the differential voltage between pins IOUT_N andIOUT_P can be expressed as shown in Equation 6 through Equation 8 where IO
(FS)
= 20 mA:VOUTN = 3.3 V - 0 mA x 50 Ω= 3.3 V (6)
VOUTP = 3.3 V - 20 mA x 50 Ω= 2.3 V (7)
VDIFF = VOUTN - VOUTP = 1 V (8)
If D[13:0] = 0, then IOUT_P = 0 mA and IOUT_N = 20 mA and the differential voltage VDIFF = – 1 V.
The output currents and voltages in IOUT_N and IOUT_P are complementary. The voltage, when measureddifferentially, will be doubled compared to measuring each output individually. Care must be taken not to exceedthe compliance voltages at the IOUT_N and IOUT_P pins in order to keep signal distortion low.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): DAC5670-SP
Reference Operation
Bandgap
Reference
REFIO_IN
REFIO
RBIASOUT
RBIASIN
1.2VReference
External
REFIO
Filter
Capacitor
External
REFIO
Filter
Capacitor
External
RBIAS
Resistor
External
RBIAS
Resistor
+
-
DAC5670-SP
SGLS386 – JANUARY 2009 ...............................................................................................................................................................................................
www.ti.com
Figure 22. Reference Circuit
The DAC5670 comprises a bandgap reference and control amplifier for biasing the full-scale output current. Thefull-scale output current is set by applying an external resistor R
BIAS
to pins RBIASOUT and RBIASIN. The biascurrent I
BIAS
through resistor R
BIAS
is defined by the on-chip bandgap reference voltage and control amplifier. Thefull-scale output current equals 32 times this bias current. The full-scale output current IOUT
FS
can thus beexpressed as:IOUT
FS
= 32 × I
BIAS
= 32 × V
REFIO
/R
BIAS
(9)
Where:
V
REFIO
Voltage at terminals REFIO and REFIO_IN
The bandgap reference voltage delivers an accurate voltage of 1.2 V. An external REFIO filter capacitor of 0.1µF should be connected externally to the terminals REFIO and REFIO_IN for compensation.
The full-scale output current can be adjusted from 30 mA down to 5 mA by varying external resistor R
BIAS
.
22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC5670-SP
Analog Current Outputs
sw_p(0) sw_n(0) sw_n(1)sw_p(1) sw_n(N)sw_p(N)
CSBIAS
External
CSBIAS
Filter
Capacitor
RLOADRLOAD
AVDD(3.3V)
IOUT_N IOUT_P
sw_p(0) sw_n(0) sw_n(1)sw_p(1) sw_n(N)sw_p(N)
CSBIAS_INCSBIAS
External
CSBIAS
Filter
Capacitor
CurrentSink Array
DAC5670-SP
www.ti.com
............................................................................................................................................................................................... SGLS386 – JANUARY 2009
Figure 23 is a simplified schematic of the current sink array output with corresponding switches. Differential NPNswitches direct the current of each individual NPN current sink to either the positive output node IOUT_P or itscomplementary negative output node IOUT_N. The input data presented at the DA_P[13:0], DA_N[13:0],DB_P[13:0] and DB_N[13:0] is decoded to control the sw_p(N) and sw_n(N) current switches.
Figure 23. Current Sink Array
The external output resistors R
LOAD
are connected to the positive supply, AVDD.
The DAC5670 can easily be configured to drive a doubly-terminated 50 Ωcable using a properly selectedtransformer. Figure 24 and Figure 25 show the 1:1 and 4:1 impedance ratio configuration, respectively. Theseconfigurations provide maximum rejection of common-mode noise sources and even-order distortioncomponents, thereby doubling the power of the DAC to the output. The center tap on the primary side of thetransformer is terminated to AVDD, enabling a dc current flow for both IOUT_N and IOUT_P.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): DAC5670-SP
Sleep Mode
DAC5670-SP
SGLS386 – JANUARY 2009 ...............................................................................................................................................................................................
www.ti.com
Figure 24.
Figure 25.
When the SLEEP pin is asserted (high), the DAC5670 enters a lower-power mode.
24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC5670-SP
Definitions of Specifications and Terminology
DAC5670-SP
www.ti.com
............................................................................................................................................................................................... SGLS386 – JANUARY 2009
Differential Nonlinearity (DNL): Defined as the variation in analog output associated with an ideal 1 LSBchange in the digital input code.
Gain Drift: Defined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per ° C, from thevalue at 25 ° C to values over the full operating temperature range.
Gain Error: Defined as the percentage error in the ratio between the measured full-scale output current and thevalue of the ideal full-scale output (32 x V
REFIO
/R
BIAS
). A V
REFIO
of 1.2V is used to measure the gain error with anexternal reference voltage applied. With an internal reference, this error includes the deviation of V
REFIO
(internalbandgap reference voltage) from the typical value of 1.2V.
Integral Nonlinearity (INL): Defined as the maximum deviation of the actual analog output from the ideal output,determined by a straight line drawn from zero scale to full scale.
Intermodulation Distortion (IMD3, IMD): The two-tone IMD3 or four-tone IMD is defined as the ratio (in dBc) ofthe worst 3rd-order (or higher) intermodulation distortion product to either fundamental output tone.
Offset Drift: Defined as the maximum change in DC offset, in terms of ppm of full-scale range (FSR) per ° C,from the value at 25 ° C to values over the full operating temperature range.
Offset Error: Defined as the percentage error in the ratio of the differential output current (IOUT_P – IOUT_N) tohalf of the full-scale output current for input code 8192.
Output Compliance Range: Defined as the minimum and maximum allowable voltage at the output of thecurrent-output DAC. Exceeding this limit may result in reduced reliability of the device or adversely affectingdistortion performance.
Power Supply Rejection Ratio (PSSR): Defined as the percentage error in the ratio of the delta IOUT and deltasupply voltage normalized with respect to the ideal IOUT current.
Reference Voltage Drift: Defined as the maximum change of the reference voltage in ppm per degree Celsiusfrom value at ambient (25 ° C) to values over the full operating temperature range.
Spurious Free Dynamic Range (SFDR): Defined as the difference (in dBc) between the peak amplitude of theoutput signal and the peak spurious signal.
Signal to Noise Ratio (SNR): Defined as the ratio of the RMS value of the fundamental output signal to theRMS sum of all other spectral components below the Nyquist frequency, including noise, but excluding the firstsix harmonics and dc.
Total Harmonic Distortion (THD): Defined as the ratio of the rms sum of the first six harmonic components tothe rms value of the fundamental output signal.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): DAC5670-SP
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-0724701VXA ACTIVE CBGA GEM 192 1 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 22-Apr-2009
Addendum-Page 1
IMPORTANT NOTICE
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