MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DLow Supply-Voltage Range: 1.8 V to 3.6 V
DUltralow Power Consumption
-- Active Mode: 350 Aat1MHz,2.2V
-- Standby Mode: 1.1 A
-- Off Mode (RAM Retention): 0.2 A
DFive Power-Saving Modes
DWake-Up From Standby Mode in Less
Than 6 s
D16-Bit RISC Architecture,
62.5-ns Instruction Cycle Time
DThree-Channel Internal DMA
DThree, Six or Seven 16-Bit Sigma-Delta
Analog-to-Digital (A/D) Converters With
Differential PGA Inputs
D16-Bit Timer_B With Three
Capture/Compare-With-Shadow Registers
D16-Bit Timer_A With Three
Capture/Compare Registers
DOn-Chip Comparator
DFour Universal Serial Communication
Interface (USCI) Modules
-- USCI_A0 and USCI_A1
-- Enhanced UART Supporting
Auto-Baudrate Detection
-- IrDA Encoder and Decoder
-- Synchronous SPI
-- USCI_B0 and USCI_B1
-- I 2 C
-- Synchronous SPI
DIntegrated LCD Driver With Contrast
Control for Up to 160 Segments
DBasic Timer With Real-Time Clock Feature
D32-Bit Hardware Multiplier
DBrownout Detector
DSupply Voltage Supervisor/Monitor With
Programmable Level Detection
DSerial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
DBootstrap Loader
DOn-Chip Emulation Module
DFamily Members Include
MSP430F47163: 92KB Flash, 4KB RAM
3 Sigma-Delta ADCs
MSP430F47173: 92KB Flash, 8KB RAM
3 Sigma-Delta ADCs
MSP430F47183: 116KB Flash, 8KB RAM
3 Sigma-Delta ADCs
MSP430F47193: 120KB Flash, 4KB RAM
3 Sigma-Delta ADCs
MSP430F47126: 56KB Flash, 4KB RAM
6 Sigma-Delta ADCs
MSP430F47166: 92KB Flash, 4KB RAM
6 Sigma-Delta ADCs
MSP430F47176: 92KB Flash, 8KB RAM
6 Sigma-Delta ADCs
MSP430F47186: 116KB Flash, 8KB RAM
6 Sigma-Delta ADCs
MSP430F47196: 120KB Flash, 4KB RAM
6 Sigma-Delta ADCs
MSP430F47127: 56KB Flash, 4KB RAM
7 Sigma-Delta ADCs
MSP430F47167: 92KB Flash, 4KB RAM
7 Sigma-Delta ADCs
MSP430F47177: 92KB Flash, 8KB RAM
7 Sigma-Delta ADCs
MSP430F47187: 116KB Flash, 8KB RAM
7 Sigma-Delta ADCs
MSP430F47197: 120KB Flash, 4KB RAM
7 Sigma-Delta ADCs
DAvailable in a 100-Pin Plastic Quad
Flatpack (QFP) Package
DFor Complete Module Descriptions, See the
MSP430x4xx Family User’s Guide,
Literature Number SLAU056
DFor E-Meter Reference Design and
Software, See Implementation of a
Three-Phase Electronic Watt-Hour Meter
using the MSP430F471xx, Literature
Number SLAA409
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Copyright 2011, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The devices feature
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency.The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6s.
The MSP430F471xx series are microcontroller configurations targeted to single-phase and poly-phase
electricity meters with three, six, or seven 16-bit sigma-delta A/D converters. Each channel has a differential
input pair and programmable input gain. Also integrated are two 16-bit timers, four universal serial
communication interfaces (USCI), DMA, 68 I/O pins, and a liquid crystal driver (LCD) with integrated contrast
control.
AVAILABLE OPTIONS{
T
PACKAGED DEVICES}
TAPLASTIC 100-PIN QFP (PZ)
MSP430F47127IPZ
MSP430F47167IPZ
MSP430F47177IPZ
MSP430F47187IPZ
MSP430F47197IPZ
-- 4 0 Cto85C
MSP430F47126IPZ
MSP430F47166IPZ
MSP430F47176IPZ
MSP430F47186IPZ
MSP430F47196IPZ
MSP430F47163IPZ
MSP430F47173IPZ
MSP430F47183IPZ
MSP430F47193IPZ
†For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see the
TI web site at www.ti.com.
‡Package drawings, thermal data, and symbolization are available at
www.ti.com/packaging.
DEVELOPMENT TOOL SUPPORT
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging
and programming through easy to use development tools. Recommended hardware options include the
following:
DDebugging and Programming Interface
-- MSP-FET430UIF (USB)
-- MSP-FET430PIF (Parallel Port)
DDebugging and Programming Interface with Target Board
-- MSP-FET430U100
DStand-Alone Target Board
-- MSP-TS430PZ100
DProduction Programmer
-- MSP-GANG430
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
functional block diagram, MSP430F471x7
Oscillators
FLL+
RAM
Brownout
Protection
SVS/SVM
RST/NMI
DVCC1/2 DVSS1/2
MCLK
Watchdog
WDT+
15/16--Bit
Timer_A3
3CC
Registers
16MHz
CPU
incl. 16
Registers
EEM
(L: 8 + 2)
Basic Timer
&
Real--Time
Clock
JTAG
Interface
LCD_A
160
Segments
1,2,3,4 Mux
Ports P1/P2
2x8 I/O
Interrupt
capability &
pull--up/down
Resistors
USCI_A0
(UART/LIN,
IrDA, SPI)
USCI_B0
(SPI, I2C)
Comparator
_A
Flash
Hardware
Multiplier
(32x32)
MPY,
MPYS,
MAC,
MACS
Timer_B3
3CC
Registers,
Shadow
Reg
USCI_A1
(UART/LIN,
IrDA, SPI)
USCI_B1
(SPI, I2C)
AVCC AVSS P1.x/P2.x
2x8
SMCLK
ACLK
MDB
MAB
Ports
P3/P4
P5
3x8 I/O with
pull--up/down
Resistors
Ports
P7/P8
P9/P10
4x8/2x16 I/O
pull--up/down
Resistors
P3.x/P4.x
P5.x
3x8
P7.x/P8.x
P9.x/P10.x
3x8+1x4
XOUT
XT2OUT
XIN
XT2IN
22
DMA
Controller
3 Channels
SD16_A
(w/o BUF)
7
Sigma--
Delta A/D
Converter
120kB
116kB
92kB
92kB
56kB
4kB
8kB
4kB
8kB
4kB
functional block diagram, MSP430F471x6
Oscillators
FLL+
RAM
4kB
8kB
4kB
8kB
Brownout
Protection
SVS/SVM
RST/NMI
DVCC1/2 DVSS1/2
MCLK
Watchdog
WDT+
15/16--Bit
Timer_A3
3CC
Registers
16MHz
CPU
incl. 16
Registers
EEM
(L: 8 + 2)
Basic Timer
&
Real--Time
Clock
JTAG
Interface
LCD_A
160
Segments
1,2,3,4 Mux
Ports P1/P2
2x8 I/O
Interrupt
capability &
pull--up/down
Resistors
USCI_A0
(UART/LIN,
IrDA, SPI)
USCI_B0
(SPI, I2C)
Comparator
_A
Flash
120kB
116kB
92kB
92kB
Hardware
Multiplier
(32x32)
MPY,
MPYS,
MAC,
MACS
Timer_B3
3CC
Registers,
Shadow
Reg
USCI_A1
(UART/LIN,
IrDA, SPI)
USCI_B1
(SPI, I2C)
AVCC AVSS P1.x/P2.x
2x8
SMCLK
ACLK
MDB
MAB
Ports
P3/P4
P5
3x8 I/O with
pull--up/down
Resistors
Ports
P7/P8
P9/P10
4x8/2x16 I/O
pull--up/down
Resistors
P3.x/P4.x
P5.x
3x8
P7.x/P8.x
P9.x/P10.x
3x8+1x4
XOUT
XT2OUT
XIN
XT2IN
22
DMA
Controller
3 Channels
SD16_A
(w/o BUF)
6
Sigma--
Delta A/D
Converter
RAMFlash
120kB
116kB
92kB
92kB
56kB
4kB
8kB
4kB
8kB
4kB
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
functional block diagram, MSP430F471x3
Oscillators
FLL+
RAM
4kB
8kB
4kB
8kB
Brownout
Protection
SVS/SVM
RST/NMI
DVCC1/2 DVSS1/2
MCLK
Watchdog
WDT+
15/16--Bit
Timer_A3
3CC
Registers
16MHz
CPU
incl. 16
Registers
EEM
(L: 8 + 2)
Basic Timer
&
Real--Time
Clock
JTAG
Interface
LCD_A
160
Segments
1,2,3,4 Mux
Ports P1/P2
2x8 I/O
Interrupt
capability &
pull--up/down
Resistors
USCI_A0
(UART/LIN,
IrDA, SPI)
USCI_B0
(SPI, I2C)
Comparator
_A
Flash
120kB
116kB
92kB
92kB
Hardware
Multiplier
(32x32)
MPY,
MPYS,
MAC,
MACS
Timer_B3
3CC
Registers,
Shadow
Reg
USCI_A1
(UART/LIN,
IrDA, SPI)
USCI_B1
(SPI, I2C)
AVCC AVSS P1.x/P2.x
2x8
SMCLK
ACLK
MDB
MAB
Ports
P3/P4
P5
3x8 I/O with
pull--up/down
Resistors
Ports
P7/P8
P9/P10
4x8/2x16 I/O
pull--up/down
Resistors
P3.x/P4.x
P5.x
3x8
P7.x/P8.x
P9.x/P10.x
3x8+1x4
XOUT
XT2OUT
XIN
XT2IN
22
DMA
Controller
3 Channels
SD16_A
(w/o BUF)
3
Sigma--
Delta A/D
Converter
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
pin designation, MSP430F471x7IPZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P2.1/UCB1SIMO/UCB1SDA
TMS
TDI/TCLK
TDO/TDI
P1.0/TA0
P1.1/TA0/MCLK
P1.5/TACLK/ACLK
P1.6/UCA1TXD/UCA1SIMO
P1.7/UCA1RXD/UCA1SOMI
P2.0/UCB1STE/UCA1CLK
P2.5/UCA0RXD/UCA0SOMI
P9.4/S7
P9.3/S8
P9.2/S9
P9.1/S10
P9.0/S11
P8.6/S13
P8.1/S18
P8.0/S19
P7.7/S20
P7.6/S21
P7.5/S22
P7.3/S24
P7.0/S27
P7.4/S23
PZ PACKAGE
(TOP VIEW)
P1.2/TA1
DVCC1
P8.5/S14 XT2OUT
TCK
P1.4/TBCLK/SMCLK
P8.2/S17
P4.7/S28
A0.0+†
A0.0--†
A1.0+†
A1.0--†
A2.0+†
A2.0--†
AVSS
AVCC
VREF
A3.0+†
A3.0--†
A4.0+†
A4.0--†
A5.0+†
A5.0--†
A6.0+†
A6.0--†
AVSS
P10.3/S0
P10.2/S1
P10.1/S2
P10.0/S3
P9.7/S4
P9.6/S5
P9.5/S6
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/TA2/S39
P3.5/TB0/S38
P3.6/TB1/S37
P3.7/TB2/S36
DVSS2
XOUT
XIN
DVCC2
LCDCAP/R33
P5.7/R23
P5.6/LCDREF/R13
P5.5/R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
P5.1/COM0
P5.0/SVSIN
P4.0/CAOUT/S35
P4.1/DMAE0/S34
P4.2/S33
P4.3/S32
P8.7/S12
P8.4/S15
P8.3/S16
P7.1/S26
P7.2/S25
P4.6/S29
P4.5/S30
P4.4/S31
XT2IN
RST/NMI
DVSS1
P1.3/TBOUTH/SVSOUT
P2.2/UCB1SOMI/UCB1SCL
P2.3/UCB1CLK/UCA1STE
P2.4/UCA0TXD/UCA0SIMO
MSP430F471x7IPZ
P2.7/CA1
P2.6/CA0
†It is recommended to short unused analog input pairs and connect them to analog ground (AVSS).
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
pin designation, MSP430F471x6IPZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P2.1/UCB1SIMO/UCB1SDA
TMS
TDI/TCLK
TDO/TDI
P1.0/TA0
P1.1/TA0/MCLK
P1.5/TACLK/ACLK
P1.6/UCA1TXD/UCA1SIMO
P1.7/UCA1RXD/UCA1SOMI
P2.0/UCB1STE/UCA1CLK
P2.5/UCA0RXD/UCA0SOMI
P9.4/S7
P9.3/S8
P9.2/S9
P9.1/S10
P9.0/S11
P8.6/S13
P8.1/S18
P8.0/S19
P7.7/S20
P7.6/S21
P7.5/S22
P7.3/S24
P7.0/S27
P7.4/S23
PZ PACKAGE
(TOP VIEW)
P1.2/TA1
DVCC1
P8.5/S14 XT2OUT
TCK
P1.4/TBCLK/SMCLK
P8.2/S17
P4.7/S28
A0.0+†
A0.0--†
A1.0+†
A1.0--†
A2.0+†
A2.0--†
AVSS
AVCC
VREF
A3.0+†
A3.0--†
A4.0+†
A4.0--†
A5.0+†
A5.0--†
NC‡
NC‡
AVSS
P10.3/S0
P10.2/S1
P10.1/S2
P10.0/S3
P9.7/S4
P9.6/S5
P9.5/S6
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/TA2/S39
P3.5/TB0/S38
P3.6/TB1/S37
P3.7/TB2/S36
DVSS2
XOUT
XIN
DVCC2
LCDCAP/R33
P5.7/R23
P5.6/LCDREF/R13
P5.5/R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
P5.1/COM0
P5.0/SVSIN
P4.0/CAOUT/S35
P4.1/DMAE0/S34
P4.2/S33
P4.3/S32
P8.7/S12
P8.4/S15
P8.3/S16
P7.1/S26
P7.2/S25
P4.6/S29
P4.5/S30
P4.4/S31
XT2IN
RST/NMI
DVSS1
P1.3/TBOUTH/SVSOUT
P2.2/UCB1SOMI/UCB1SCL
P2.3/UCB1CLK/UCA1STE
P2.4/UCA0TXD/UCA0SIMO
MSP430F471x6IPZ
P2.7/CA1
P2.6/CA0
†It is recommended to short unused analog input pairs and connect them to analog ground (AVSS).
‡Connect pin to analog ground (AVSS).
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
pin designation, MSP430F471x3IPZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P2.1/UCB1SIMO/UCB1SDA
TMS
TDI/TCLK
TDO/TDI
P1.0/TA0
P1.1/TA0/MCLK
P1.5/TACLK/ACLK
P1.6/UCA1TXD/UCA1SIMO
P1.7/UCA1RXD/UCA1SOMI
P2.0/UCB1STE/UCA1CLK
P2.5/UCA0RXD/UCA0SOMI
P9.4/S7
P9.3/S8
P9.2/S9
P9.1/S10
P9.0/S11
P8.6/S13
P8.1/S18
P8.0/S19
P7.7/S20
P7.6/S21
P7.5/S22
P7.3/S24
P7.0/S27
P7.4/S23
PZ PACKAGE
(TOP VIEW)
P1.2/TA1
DVCC1
P8.5/S14 XT2OUT
TCK
P1.4/TBCLK/SMCLK
P8.2/S17
P4.7/S28
A0.0+†
A0.0--†
A1.0+†
A1.0--†
A2.0+†
A2.0--†
AVSS
AVCC
VREF
NC‡
NC‡
NC‡
NC‡
NC‡
NC‡
NC‡
NC‡
AVSS
P10.3/S0
P10.2/S1
P10.1/S2
P10.0/S3
P9.7/S4
P9.6/S5
P9.5/S6
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/TA2/S39
P3.5/TB0/S38
P3.6/TB1/S37
P3.7/TB2/S36
DVSS2
XOUT
XIN
DVCC2
LCDCAP/R33
P5.7/R23
P5.6/LCDREF/R13
P5.5/R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
P5.1/COM0
P5.0/SVSIN
P4.0/CAOUT/S35
P4.1/DMAE0/S34
P4.2/S33
P4.3/S32
P8.7/S12
P8.4/S15
P8.3/S16
P7.1/S26
P7.2/S25
P4.6/S29
P4.5/S30
P4.4/S31
XT2IN
RST/NMI
DVSS1
P1.3/TBOUTH/SVSOUT
P2.2/UCB1SOMI/UCB1SCL
P2.3/UCB1CLK/UCA1STE
P2.4/UCA0TXD/UCA0SIMO
MSP430F471x3IPZ
P2.7/CA1
P2.6/CA0
†It is recommended to short unused analog input pairs and connect them to analog ground (AVSS).
‡Connect pin to analog ground (AVSS).
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I
/
O
D
E
S
C
R
I
P
T
I
O
N
NAME NO. I
/
ODESCRIPTION
A0.0+ 1 I SD16_A positive analog input A0.0 (see Note 1)
A0.0-- 2 I SD16_A negative analog input A0.0 (see Note 1)
A1.0+ 3 I SD16_A positive analog input A1.0 (see Note 1)
A1.0-- 4 I SD16_A negative analog input A1.0 (see Note 1)
A2.0+ 5 I SD16_A positive analog input A2.0 (see Note 1)
A2.0-- 6 I SD16_A negative analog input A2.0 (see Note 1)
AVSS 7Analog supply voltage, negative terminal.
AVCC 8Analog supply voltage, positive terminal. Must not power up prior to DVCC1/DVCC2.
VREF 9I/O Input for an external reference voltage /
internal reference voltage output (can be used as mid-voltage)
A3.0+
(MSP430F471x6/7 only) 10 ISD16_A positive analog input A3.0 (see Note 1) --
Not connected in MSP430F471x3, connect pin to analog ground (AVSS).
A3.0--
(MSP430F471x6/7 only) 11 ISD16_A negative analog input A3.0 (see Note 1) --
Not connected in MSP430F471x3, connect pin to analog ground (AVSS).
A4.0+
(MSP430F471x6/7 only) 12 ISD16_A positive analog input A4.0 (see Note 1) --
Not connected in MSP430F471x3, connect pin to analog ground (AVSS).
A4.0--
(MSP430F471x6/7 only) 13 ISD16_A negative analog input A4.0 (see Note 1) --
Not connected in MSP430F471x3, connect pin to analog ground (AVSS).
A5.0+
(MSP430F471x6/7 only) 14 ISD16_A positive analog input A5.0 (see Note 1) --
Not connected in MSP430F471x3, connect pin to analog ground (AVSS).
A5.0--
(MSP430F471x6/7 only) 15 ISD16_A negative analog input A5.0 (see Note 1) --
Not connected in MSP430F471x3, connect pin to analog ground (AVSS).
A6.0+
(MSP430F471x7 only) 16 ISD16_A positive analog input A6.0 (see Note 1) --
Not connected in MSP430F471x6, connect pin to analog ground (AVSS).
A6.0--
(MSP430F471x7 only) 17 ISD16_A negative analog input A6.0 (see Note 1) --
Not connected in MSP430F471x6, connect pin to analog ground (AVSS).
AVSS 18 Analog supply voltage, negative terminal.
P10.3/S0 19 I/O General-purpose digital I/O / LCD segment output 0
P10.2/S1 20 I/O General-purpose digital I/O / LCD segment output 1
P10.1/S2 21 I/O General-purpose digital I/O / LCD segment output 2
P10.0/S3 22 I/O General-purpose digital I/O / LCD segment output 3
P9.7/S4 23 I/O General-purpose digital I/O / LCD segment output 4
P9.6/S5 24 I/O General-purpose digital I/O / LCD segment output 5
P9.5/S6 25 I/O General-purpose digital I/O / LCD segment output 6
P9.4/S7 26 I/O General-purpose digital I/O / LCD segment output 7
P9.3/S8 27 I/O General-purpose digital I/O / LCD segment output 8
P9.2/S9 28 I/O General-purpose digital I/O / LCD segment output 9
P9.1/S10 29 I/O General-purpose digital I/O / LCD segment output 10
P9.0/S11 30 I/O General-purpose digital I/O / LCD segment output 11
P8.7/S12 31 I/O General-purpose digital I/O / LCD segment output 12
P8.6/S13 32 I/O General-purpose digital I/O / LCD segment output 13
P8.5/S14 33 I/O General-purpose digital I/O / LCD segment output 14
P8.4/S15 34 I/O General-purpose digital I/O / LCD segment output 15
P8.3/S16 35 I/O General-purpose digital I/O / LCD segment output 16
P8.2/S17 36 I/O General-purpose digital I/O / LCD segment output 17
P8.1/S18 37 I/O General-purpose digital I/O / LCD segment output 18
NOTES: 1. It is recommended to short unused analog input pairs and connect them to analog ground.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
I
/
O
D
E
S
C
R
I
P
T
I
O
N
NAME NO. I
/
ODESCRIPTION
P8.0/S19 38 I/O General-purpose digital I/O / LCD segment output 19
P7.7/S20 39 I/O General-purpose digital I/O / LCD segment output 20
P7.6/S21 40 I/O General-purpose digital I/O / LCD segment output 21
P7.5/S22 41 I/O General-purpose digital I/O / LCD segment output 22
P7.4/S23 42 I/O General-purpose digital I/O / LCD segment output 23
P7.3/S24 43 I/O General-purpose digital I/O / LCD segment output 24
P7.2/S25 44 I/O General-purpose digital I/O / LCD segment output 25
P7.1/S26 45 I/O General-purpose digital I/O / LCD segment output 26
P7.0/S27 46 I/O General-purpose digital I/O / LCD segment output 27
P4.7/S28 47 I/O General-purpose digital I/O / LCD segment output 28
P4.6/S29 48 I/O General-purpose digital I/O / LCD segment output 29
P4.5/S30 49 I/O General-purpose digital I/O / LCD segment output 30
P4.4/S31 50 I/O General-purpose digital I/O / LCD segment output 31
P4.3/S32 51 I/O General-purpose digital I/O / LCD segment output 32
P4.2/S33 52 I/O General-purpose digital I/O / LCD segment output 33
P4.1/DMAE0/S34 53 I/O General-purpose digital I/O / DMA Channel 0 external trigger / LCD segment output 34
P4.0/CAOUT/S35 54 I/O General-purpose digital I/O / Comparator_A output / LCD segment output 35
P5.0/SVSIN 55 I/O General-purpose digital I/O / analog input to supply voltage supervisor
P5.1/COM0 56 I/O General-purpose digital I/O / common output, COM0--3 are used for LCD backplanes.
P5.2/COM1 57 I/O General-purpose digital I/O / common output, COM0--3 are used for LCD backplanes.
P5.3/COM2 58 I/O General-purpose digital I/O / common output, COM0--3 are used for LCD backplanes.
P5.4/COM3 59 I/O General-purpose digital I/O / common output, COM0--3 are used for LCD backplanes.
P5.5/R03 60 I/O General-purpose digital I/O / Input port of lowest analog LCD level (V5)
P5.6/LCDREF/R13 61 I/O General-purpose digital I/O / External reference voltage input for regulated LCD voltage / Input port
of third most positive analog LCD level (V4 or V3)
P5.7/R23 62 I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
LCDCAP/R33 63 ILCD Capacitor connection / Input/output port of most positive analog LCD level (V1)
DVCC2 64 Digital supply voltage, positive terminal.
XIN 65 IInput port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 66 OOutput terminal of crystal oscillator XT1
DVSS2 67 Digital supply voltage, negative terminal.
P3.7/TB2/S36 68 I/O General-purpose digital I/O / Timer_B3 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
/ LCD segment output 36
P3.6/TB1/S37 69 I/O General-purpose digital I/O / Timer_B3 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
/ LCD segment output 37
P3.5/TB0/S38 70 I/O General-purpose digital I/O / Timer_B3 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
/ LCD segment output 38
P3.4/TA2/S39 71 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output
/ LCD segment output 39
P3.3/
UCB0CLK/UCA0STE 72 I/O General-purpose digital I/O /
USCI_B0 clock input/output / USCI_A0 slave transmit enable
P3.2/
UCB0SOMI/UCB0SCL 73 I/O General-purpose digital I/O /
USCI_B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode
P3.1/
UCB0SIMO/UCB0SDA 74 I/O General-purpose digital I/O /
USCI_B0 slave in/master out in SPI mode, SDA I2CdatainI
2C mode
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL I/O DESCRIPTION
NAME NO. I/O DESCRIPTION
P3.0/
UCB0STE/UCA0CLK 75 I/O General-purpose digital I/O /
USCI_B0 slave transmit enable / USCI_A0 clock input/output
P2.7/CA1 76 I/O General-purpose digital I/O / Comparator_A input
P2.6/CA0 77 I/O General-purpose digital I/O / Comparator_A input
P2.5/
UCA0RXD/UCA0SOMI 78 I/O General-purpose digital I/O / USCI_A0 receive data input in UART mode, slave out/master in in SPI
mode
P2.4/
UCA0TXD/UCA0SIMO 79 I/O General-purpose digital I/O / USCI_A0 transmit data output in UART mode, slave in/master out in
SPI mode
P2.3/
UCB1CLK/UCA1STE 80 I/O General-purpose digital I/O /
USCI_B1 clock input/output / USCI_A1 slave transmit enable
P2.2/
UCB1SOMI/UCB1SCL 81 I/O General-purpose digital I/O /
USCI_B1 slave out/master in in SPI mode, SCL I2C clock in I2C mode
P2.1/
UCB1SIMO/UCB1SDA 82 I/O General-purpose digital I/O /
USCI_B1 slave in/master out in SPI mode, SDA I2CdatainI
2C mode
P2.0/
UCB1STE/UCA1CLK 83 I/O General-purpose digital I/O /
USCI_B1 slave transmit enable / USCI_A1 clock input/output
P1.7/
UCA1RXD/UCA1SOMI 84 I/O General-purpose digital I/O /
USCI_A1 receive data input in UART mode, slave out/master in in SPI mode
P1.6/
UCA1TXD/UCA1SIMO 85 I/O General-purpose digital I/O /
USCI_A1 transmit data output in UART mode, slave in/master out in SPI mode
P1.5/TACLK/ACLK 86 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/SMCLK 87 I/O General-purpose digital I/O / input clock TBCLK—Timer_B3 /
submain system clock SMCLK output
P1.3/TBOUTH/SVSOUT 88 I/O General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B3 TB0
to TB2 / SVS: output of SVS comparator
P1.2/TA1 89 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output
P1.1/TA0/MCLK 90 I/O General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0 91 I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit
DVCC1 92 Digital supply voltage, positive terminal.
XT2OUT 93 OOutput terminal of crystal oscillator XT2
XT2IN 94 IInput port for crystal oscillator XT2. Only standard crystals can be connected.
DVSS1 95 Digital supply voltage, negative terminal.
TDO/TDI 96 I/O Test data output port. TDO/TDI data output or programming data input terminal
TDI/TCLK 97 ITest data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS 98 ITest mode select. TMS is used as an input port for device programming and test.
TCK 99 ITest clock. TCK is the clock input port for device programming and test.
RST/NMI 100 IReset input or nonmaskable interrupt input port
General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
11
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator, respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; Table 2 shows the address
modes.
Table 1. Instruction Word Formats
Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5
Single operands, destination only e.g., CALL R8 PC ---->(TOS), R8----> PC
Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register DDMOV Rs,Rd MOV R10,R11 R10 ----> R11
Indexed D D MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)----> M(6+R6)
Symbolic (PC relative) D D MOV EDE,TONI M(EDE) ----> M(TONI)
Absolute D D MOV &MEM,&TCDAT M(MEM) ----> M(TCDAT)
Indirect DMOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) ----> M(Tab+R6)
Indirect
autoincrement DMOV @Rn+,Rm MOV @R10+,R11 M(R10) ----> R11
R10 + 2----> R10
Immediate DMOV #X,TONI MOV #45,TONI #45 ----> M(TONI)
NOTE: S = source, D = destination
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
operating modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
DActive mode AM
-- All clocks are active
DLow-power mode 0 (LPM0)
-- CPU is disabled
-- ACLK and SMCLK remain active. MCLK is disabled.
-- FLL+ loop control remains active
DLow-power mode 1 (LPM1)
-- CPU is disabled
-- FLL+ loop control is disabled
-- ACLK and SMCLK remain active. MCLK is disabled.
DLow-power mode 2 (LPM2)
-- CPU is disabled
-- MCLK and FLL+ loop control and DCOCLK are disabled
-- DCO’s dc generator remains enabled
-- ACLK remains active
DLow-power mode 3 (LPM3)
-- CPU is disabled
-- MCLK, FLL+ loop control, and DCOCLK are disabled
-- DCO’s dc generator is disabled
-- ACLK remains active
DLow-power mode 4 (LPM4)
-- CPU is disabled
-- ACLK is disabled
-- MCLK, FLL+ loop control, and DCOCLK are disabled
-- DCO’s dc generator is disabled
-- Crystal oscillator is stopped
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
13
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset
vector (at 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU enters LPM4 after power-up.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD
ADDRESS PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
PC Out-of-Range (see Note 4)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 1)
Reset 0FFFEh 31, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh 30
Timer_B3 TBCCR0 CCIFG (see Note 2) Maskable 0FFFAh 29
Timer_B3 TBCCR1 to TBCCR2 CCIFGs
TBIFG (see Notes 1 and 2) Maskable 0FFF8h 28
Comparator_A CAIFG Maskable 0FFF6h 27
Watchdog Timer WDTIFG Maskable 0FFF4h 26
USCI_A0/B0 Receive
USCI_B0 I2C Status
UCA0RXIFG, UCB0RXIFG
(see Notes 1 and 5)
Maskable 0FFF2h 25
USCI_A0/B0 Transmit
USCI_B0 I2C Receive/Transmit
UCA0TXIFG, UCB0TXIFG
(see Notes 1 and 6)
Maskable 0FFF0h 24
SD16_A SD16CCTLx SD16OVIFG, SD16CCTLx SD16IFG
(see Notes 1 and 2)
Maskable 0FFEEh 23
Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 22
Timer_A3 TACCR1 and TACCR2 CCIFGs,
TAIFG (see Notes 1 and 2) Maskable 0FFEAh 21
I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0FFE8h 20
USCI_A1/B1 Receive
USCI_B1 I2C Status
UCA1RXIFG, UCB1RXIFG
(see Notes 1 and 5)
Maskable 0FFE6h 19
USCI_A1/B1 Transmit
USCI_B1 I2C Receive/Transmit
UCA1TXIFG, UCB1TXIFG
(see Notes 1 and 6)
Maskable 0FFE4h 18
I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0FFE2h 17
Basic Timer1/RTC BTIFG Maskable 0FFE0h 16
DMA DMA0IFG, DMA1IFG, DMA2IFG
(see Notes 1 and 2)
Maskable 0FFDEh 15
R
e
s
e
r
v
e
d
R
e
s
e
r
v
e
d
(
s
e
e
N
o
t
e
8
)
0FFDCh to 14 to
Reserved Reserved (see Note 8) 0FFC0h 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable
it.
4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or
from within unused address ranges.
5. USCI_B in SPI mode: UCBxRXIFG. USCI_B in I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG
6. USCI_B in SPI mode: UCBxTXIFG. USCI_B in I2C mode: UCBxRXIFG, UCBxTXIFG
7. The address 0x0FFBE is used as bootstrap loader security key (BSLSKEY).
A 0x0AA55 at this location disables the BSL completely.
A zero disables the erasure of the flash if an invalid password is supplied.
8. The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
14 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
special function registers
The MSP430 special function registers (SFR) are located in the lowest address space and are organized as
byte mode registers. SFRs should be accessed with byte instructions.
interrupt enable 1 and 2
Address76543210
00h ACCVIE NMIIE OFIE WDTIE
rw--0 rw--0 rw--0 rw--0
WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE Oscillator fault enable
NMIIE (Non)maskable interrupt enable
ACCVIE Flash access violation interrupt enable
Address76543210
01h BTIE UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
rw--0 rw--0 rw--0 rw--0 rw--0
UCA0RXIE USCI_A0 receive interrupt enable
UCA0TXIE USCI_A0 transmit interrupt enable
UCB0RXIE USCI_B0 receive interrupt enable
UCB0TXIE USCI_B0 transmit interrupt enable
BTIE Basic timer interrupt enable
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
15
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
interrupt flag register 1 and 2
Address76543210
02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG
rw--0 rw--(0) rw--(1) rw--1 rw--(0)
WDTIFG Set on watchdog timer overflow or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG Flag set on oscillator fault
RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset
on VCC power-up
PORIFG Power-on interrupt flag. Set on VCC power-up.
NMIIFG Set via RST/NMI-pin
Address76543210
03h BTIFG UCB0
TXIFG
UCB0
RXIFG
UCA0
TXIFG
UCA0
RXIFG
rw--0 rw--1 rw--0 rw--1 rw--0
UCA0RXIFG USCI_A0 receive interrupt flag
UCA0TXIFG USCI_A0 transmit interrupt flag
UCB0RXIFG USCI_B0 receive interrupt flag
UCB0TXIFG USCI_B0 transmit interrupt flag
BTIFG Basic Timer1 interrupt flag
Legend rw:
rw-0,1:
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
rw-(0,1):
SFR bit is not present in device
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
16 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
memory organization
MSP430F47126/
MSP430F47127
MSP430F47163/
MSP430F47166/
MSP430F47167
MSP430F47173/
MSP430F47176/
MSP430F47177
MSP430F47183/
MSP430F47186/
MSP430F47187
MSP430F47193/
MSP430F47196/
MSP430F47197
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
56KB
0FFFFh -- 0FFC0h
0FFFFh--002100h
92KB
0FFFFh -- 0FFC0h
018FFFh--
002100h
92KB
0FFFFh -- 0FFC0h
019FFFh--
003100h
116KB
0FFFFh -- 0FFC0h
01FFFFh--
003100h
120KB
0FFFFh -- 0FFC0h
01FFFFh--
002100h
RAM (Total) Size 4KB
020FFh--01100h
4KB
020FFh--01100h
8KB
030FFh--01100h
8KB
030FFh--01100h
4KB
020FFh--01100h
Extended Size 2KB
020FFh--01900h
2KB
020FFh--01900h
6KB
030FFh--01900h
6KB
030FFh--01900h
2KB
020FFh--01900h
Mirrored Size 2KB
018FFh--01100h
2KB
018FFh--01100h
2KB
018FFh--01100h
2KB
018FFh--01100h
2KB
018FFh--01100h
Information memory Size
Flash
256 Byte
010FFh--01000h
256 Byte
010FFh--01000h
256 Byte
010FFh--01000h
256 Byte
010FFh--01000h
256 Byte
010FFh--01000h
Boot memory Size
ROM
1KB
0FFFh--0C00h
1KB
0FFFh--0C00h
1KB
0FFFh -- 0C00h
1KB
0FFFh--0C00h
1KB
0FFFh--0C00h
RAM
(mirrored at
018FFh -- 01100h)
Size 2KB
09FFh--0200h
2KB
09FFh--0200h
2KB
09FFh--0200h
2KB
09FFh--0200h
2KB
09FFh--0200h
Peripherals 16-bit
8-bit
8-bit SFR
01FFh--0100h
0FFh--010h
0Fh--00h
01FFh--0100h
0FFh--010h
0Fh--00h
01FFh--0100h
0FFh--010h
0Fh--00h
01FFh--0100h
0FFh--010h
0Fh--00h
01FFh--0100h
0FFh--010h
0Fh--00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the MSP430 Memory Programming User’s
Guide, literature number SLAU265.
BSL FUNCTION PZ PACKAGE PINS
Data Transmit 91 - P1.0
Data Receive 90 - P1.1
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
DFlash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
DSegments 0 to n may be erased in one step, or each segment may be individually erased.
DSegments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
DSegment A might contain calibration data. After reset segment A is protected against programming or
erasing. It can be unlocked but care should be taken not to erase this segment if the calibration data is
required.
DFlash content integrity check with marginal read modes.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number
SLAU056.
oscillator and system clock
The clock system is supported by the FLL+ module that includes support for a 32768-Hz watch crystal oscillator,
an internal digitally-controlled oscillator (DCO) and an 8-MHz high-frequency crystal oscillator (XT1) plus a
16-MHz high-frequency crystal oscillator (XT2). The FLL+ clock module is designed to meet the requirements
of both low system cost and low power consumption. The FLL+ features a digital frequency locked loop (FLL)
hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple
of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than
6s. The FLL+ module provides the following clock signals:
DAuxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
DMain clock (MCLK), the system clock used by the CPU
DSub-Main clock (SMCLK), the sub-system clock used by the peripheral modules
DACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
brownout, supply voltage supervisor (SVS)
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The SVS circuitry detects if the supply voltage drops below a user selectable level and supports
both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the
device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are nine 8-bit I/O ports implemented—ports P1 through P5 and P7 through P10.
DAll individual I/O bits are independently programmable.
DAny combination of input, output, and interrupt conditions is possible.
DEdge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
DRead/write access to port-control registers is supported by all instructions.
DPorts P7/P8 and P9/P10 can be accessed word-wise as ports PA and PB respectively.
DEach I/O has an individually programmable pullup/pulldown resistor.
Note: Only four bits of port P10 (P10.0 to P10.3) are available on external pins, but all control and data bits for port P10 are implemented.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
18 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from a USCI module to RAM. Using the DMA
controller can increase the throughput of peripheral modules. The DMA controller reduces system power
consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from
a peripheral.
DMA TRIGGER SELECT DMAXTSELX DESCRIPTION
0000 DMAREQ bit (software trigger)
0001 TACCR2 CCIFG bit
0010 TBCCR2 CCIFG bit
0011 UCA0RXIFG bit
0100 UCA0TXIFG bit
0101 N/A
0110 SD16IFG bit
0111 TACCR0 CCIFG bit
1000 TBCCR0 CCIFG bit
1001 UCA1RXIFG bit
1010 UCA1TXIFG bit
1011 Multiplier ready
1100 UCB0RXIFG bit
1101 UCB0TXIFG bit
1110
DMA0IFG bit triggers DMA channel 1
DMA1IFG bit triggers DMA channel 2
DMA2IFG bit triggers DMA channel 0
1111 External trigger DMAE0
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs operations
with 32-bit, 24-bit, 16-bit and 8-bit operands. The module is capable of supporting signed and unsigned
multiplication as well as signed and unsigned multiply and accumulate operations.
watchdog timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
Basic Timer1 and Real-Time Clock (RTC)
The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 is extended to provide an integrated real-time
clock (RTC). An internal calendar compensates for months with less than 31 days and includes leap year
correction.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
universal serial communication interfaces (USCIs) (USCI_A0, USCI_B0, USCI_A1, USCI_B1)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3-pin or 4-pin) and I2C and asynchronous communication protocolssuch
as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI_A0 and USCI_A1 provides support for SPI (3-pin or 4-pin), UART, enhanced UART, and IrDA.
USCI_B0 and USCI_B1 provides support for SPI (3-pin or 4-pin) and I2C.
Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A3 SIGNAL CONNECTIONS
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME MODULE BLOCK MODULE OUTPUT
SIGNAL
OUTPUT PIN
NUMBER
86 - P1.5 TACLK TACLK
ACLK ACLK
T
i
m
e
r
N
A
SMCLK SMCLK Timer N
A
86 - P1.5 TACLK INCLK
91 - P1.0 TA0 CCI0A 91 - P1.0
90 - P1.1 TA0 CCI0B
C
C
R
0
T
A
0
DVSS GND CCR0 T
A
0
DVCC VCC
89 - P1.2 TA1 CCI1A 89 - P1.2
CAOUT (internal) CCI1B
C
C
R
1
T
A
1
DVSS GND CCR1 T
A
1
DVCC VCC
71 - P3.4 TA2 CCI2A 71 - P3.4
ACLK (internal) CCI2B
C
C
R
2
T
A
2
DVSS GND CCR2 T
A
2
DVCC VCC
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
20 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_B3 SIGNAL CONNECTIONS
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME MODULE BLOCK MODULE OUTPUT
SIGNAL
OUTPUT PIN
NUMBER
87 - P1.4 TBCLK TBCLK
ACLK ACLK
T
i
m
e
r
N
A
SMCLK SMCLK Timer N
A
87 - P1.4 TBCLK INCLK
70 -- P3.5 TB0 CCI0A 70 - P3.5
70 -- P3.5 TB0 CCI0B
C
C
R
0
T
B
0
DVSS GND CCR0 TB0
DVCC VCC
69 - P3.6 TB1 CCI1A 69 - P3.6
69 - P3.6 TB1 CCI1B
C
C
R
1
T
B
1
DVSS GND CCR1 TB1
DVCC VCC
68 - P3.7 TB2 CCI2A 68 - P3.7
68 - P3.7 TB2 CCI2B
C
C
R
2
T
B
2
DVSS GND CCR2 TB2
DVCC VCC
Comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
SD16_A
The SD16_A module integrates three (MSP430F471x3), six (MSP430F471x6) or seven (MSP430F471x7)
independent 16-bit sigma-delta A/D converters. Each channel is designed with a fully differential analog input
pair and programmable gain amplifier input stage. In addition to external analog inputs, an internal VCC sense
and temperature sensor are also available.
LCD driver with regulated charge pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump.
Furthermore it is possible to control the level of the LCD voltage and thus contrast in software.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
embedded emulation module (EEM)
All MSP430F471x3, MSP430F471x6, and MSP430F471x7 devices have an EEM that supports real-time
in-system debugging. The implemented L version of the EEM has the following features:
DEight hardware triggers on memory address or data bus
DTwo hardware triggers on write accesses to CPU register
DEight combinational triggers to combine any of the 10 above hardware triggers
DTrigger sequencer
DCPU break reaction on combinational triggers for breakpoints
DState storage to trace internal buses
DClock control on module level
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
22 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog Watchdog timer control WDTCTL 0120h
Flash_A Flash control 4
Flash control 3
Flash control 2
Flash control 1
FCTL4
FCTL3
FCTL2
FCTL1
01BEh
012Ch
012Ah
0128h
Timer_B3 Capture/compare register 2 TBCCR2 0196h
_
Capture/compare register 1 TBCCR1 0194h
Capture/compare register 0 TBCCR0 0192h
Timer_B register TBR 0190h
Capture/compare control 2 TBCCTL2 0186h
Capture/compare control 1 TBCCTL1 0184h
Capture/compare control 0 TBCCTL0 0182h
Timer_B control TBCTL 0180h
Timer_B interrupt vector TBIV 011Eh
Timer_A3 Capture/compare register 2 TACCR2 0176h
_
Capture/compare register 1 TACCR1 0174h
Capture/compare register 0 TACCR0 0172h
Timer_A register TAR 0170h
Capture/compare control 2 TACCTL2 0166h
Capture/compare control 1 TACCTL1 0164h
Capture/compare control 0 TACCTL0 0162h
Timer_A control TACTL 0160h
Timer_A interrupt vector TAIV 012Eh
32-bit Hardware
M
l
i
l
i
MPY32 control 0 MPY32CTL0 015Ch
Multiplier 64-bit result 3 -- most significant word RES3 015Ah
64-bit result 2 RES2 0158h
64-bit result 1 RES1 0156h
64-bit result 0 -- least significant word RES0 0154h
Second 32-bit operand, high word OP2H 0152h
Second 32-bit operand, low word OP2L 0150h
Multiply signed + accumulate/
32-bit operand1, high word
MACS32H 014Eh
Multiply signed + accumulate/
32-bit operand1, low word
MACS32L 014Ch
Multiply + accumulate/
32-bit operand1, high word
MAC32H 014Ah
Multiply + accumulate/
32-bit operand1, low word
MAC32L 0148h
Multiply signed/32-bit operand1, high word MPYS32H 0146h
Multiply signed/32-bit operand1, low word MPYS32L 0144h
Multiply unsigned/32-bit operand1, high word MPY32H 0142h
Multiply unsigned/32-bit operand1, low word MPY32L 0140h
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
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peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
32-bit Hardware Sum extend SUMEXT 013Eh
Multiplier Result high word RESHI 013Ch
Result low word RESLO 013Ah
Second operand OP2 0138h
Multiply signed + accumulate/operand1 MACS 0136h
Multiply + accumulate/operand1 MAC 0134h
Multiply signed/operand1 MPYS 0132h
Multiply unsigned/operand1 MPY 0130h
USCI_B0
(
see also: Peri
p
her-
USCI_B0 I2C own address UCB0I2COA 016Ch
(
s
e
e
a
l
s
o
:
P
e
r
i
p
h
e
r
-
als with Byte Ac-
cess) USCI_B0 I2C slave address UCB0I2CSA 016Eh
USCI_B1
(
see also: Peri
p
her-
USCI_B1 I2C own address UCB1I2COA 017Ch
(
s
e
e
a
l
s
o
:
P
e
r
i
p
h
e
r
-
als with Byte Ac-
cess) USCI_B1 I2C slave address UCB1I2CSA 017Eh
SD16_A
(
l
P
i
h
General Control SD16CTL 0100h
_
(see also: Peripher-
a
l
s
w
i
t
h
B
y
t
e
A
c
-Channel 0 Control SD16CCTL0 0102h
a
l
s
w
i
t
h
B
y
t
e
A
c
-
cess) Channel 1 Control SD16CCTL1 0104h
)
Channel 2 Control SD16CCTL2 0106h
Channel 3 Control SD16CCTL3 0108h
Channel 4 Control SD16CCTL4 010Ah
Channel 5 Control SD16CCTL5 010Ch
Channel 6 Control SD16CCTL6 010Eh
Channel 0 conversion memory SD16MEM0 0110h
Channel 1 conversion memory SD16MEM1 0112h
Channel 2 conversion memory SD16MEM2 0114h
Channel 3 conversion memory SD16MEM3 0116h
Channel 4 conversion memory SD16MEM4 0118h
Channel 5 conversion memory SD16MEM5 011Ah
Channel 6 conversion memory SD16MEM6 011Ch
SD16 Interrupt vector word register SD16IV 01AEh
Port PA Port PA resistor enable PAREN 014h
Port PA selection PASEL 03Eh
Port PA direction PADIR 03Ch
Port PA output PAOUT 03Ah
Port PA input PAIN 038h
Port PB Port PB resistor enable PBREN 016h
Port PB selection PBSEL 00Eh
Port PB direction PBDIR 00Ch
Port PB output PBOUT 00Ah
Port PB input PBIN 008h
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
24 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
DMA DMA module control 0 DMACTL0 0122h
DMA module control 1 DMACTL1 0124h
DMA interrupt vector DMAIV 0126h
DMA Channel 0 DMA channel 0 control DMA0CTL 01D0h
DMA channel 0 source address DMA0SA 01D2h
DMA channel 0 destination address DMA0DA 01D6h
DMA channel 0 transfer size DMA0SZ 01DAh
DMA Channel 1 DMA channel 1 control DMA1CTL 01DCh
DMA channel 1 source address DMA1SA 01DEh
DMA channel 1 destination address DMA1DA 01E2h
DMA channel 1 transfer size DMA1SZ 01E6h
DMA Channel 2 DMA channel 2 control DMA2CTL 01E8h
DMA channel 2 source address DMA2SA 01EAh
DMA channel 2 destination address DMA2DA 01EEh
DMA channel 2 transfer size DMA2SZ 01F2h
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
SD16_A
(see also:
Peripherals with
Word Access)
Channel 0 Input Control
Channel 1 Input Control
Channel 2 Input Control
Channel 3 Input Control
Channel 4 Input Control
Channel 5 Input Control
Channel 6 Input Control
Reserved
Channel 0 preload
Channel 1 preload
Channel 2 preload
Channel 3 preload
Channel 4 preload
Channel 5 preload
Channel 6 preload
Reserved
SD16INCTL0
SD16INCTL1
SD16INCTL2
SD16INCTL3
SD16INCTL4
SD16INCTL5
SD16INCTL6
SD16PRE0
SD16PRE1
SD16PRE2
SD16PRE3
SD16PRE4
SD16PRE5
SD16PRE6
SD16CONF1
0B0h
0B1h
0B2h
0B3h
0B4h
0B5h
0B6h
0B7h
0B8h
0B9h
0BAh
0BBh
0BCh
0BDh
0BEh
0BFh
LCD_A LCD Voltage Control 1
LCD Voltage Control 0
LCD Voltage Port Control 1
LCD Voltage Port Control 0
LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDAVCTL1
LCDAVCTL0
LCDAPCTL1
LCDAPCTL0
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDACTL
0AFh
0AEh
0ADh
0ACh
0A4h
:
0A0h
09Fh
:
091h
090h
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
26 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
USCI_A0 USCI_A0 transmit buffer
USCI_A0 receive buffer
USCI_A0 status
USCI_A0 modulation control
USCI_A0 baud rate control 1
USCI_A0 baud rate control 0
USCI_A0 control 1
USCI_A0 control 0
USCI_A0 IrDA receive control
USCI_A0 IrDA transmit control
USCI_A0 auto baud rate control
UCA0TXBUF
UCA0RXBUF
UCA0STAT
UCA0MCTL
UCA0BR1
UCA0BR0
UCA0CTL1
UCA0CTL0
UCA0IRRCTL
UCA0IRTCTL
UCA0ABCTL
067h
066h
065h
064h
063h
062h
061h
060h
05Fh
05Eh
05Dh
USCI_B0 USCI_B0 transmit buffer
USCI_B0 receive buffer
USCI_B0 status
USCI_B1 I2C interrupt enable
USCI_B0 bit rate control 1
USCI_B0 bit rate control 0
USCI_B0 control 1
USCI_B0 control 0
UCB0TXBUF
UCB0RXBUF
UCB0STAT
UCB0I2CIE
UCB0BR1
UCB0BR0
UCB0CTL1
UCB0CTL0
06Fh
06Eh
06Dh
06Ch
06Bh
06Ah
069h
068h
USCI_A1 USCI_A1 transmit buffer
USCI_A1 receive buffer
USCI_A1 status
USCI_A1 modulation control
USCI_A1 baud rate control 1
USCI_A1 baud rate control 0
USCI_A1 control 1
USCI_A1 control 0
USCI_A1 IrDA receive control
USCI_A1 IrDA transmit control
USCI_A1 auto baud rate control
USCI_A1 interrupt flag
USCI_A1 interrupt enable
UCA1TXBUF
UCA1RXBUF
UCA1STAT
UCA1MCTL
UCA1BR1
UCA1BR0
UCA1CTL1
UCA1CTL0
UCA1IRRCTL
UCA1IRTCTL
UCA1ABCTL
UC1IFG
UC1IE
0D7h
0D6h
0D5h
0D4h
0D3h
0D2h
0D1h
0D0h
0CFh
0CEh
0CDh
007h
006h
USCI_B1 USCI_B1 transmit buffer
USCI_B1 receive buffer
USCI_B1 status
USCI_B1 I2C interrupt enable
USCI_B1 bit rate control 1
USCI_B1 bit rate control 0
USCI_B1 control 1
USCI_B1 control 0
USCI_A1 interrupt flag
USCI_A1 interrupt enable
UCB1TXBUF
UCB1RXBUF
UCB1STAT
UCB1I2CIE
UCB1BR1
UCB1BR0
UCB1CTL1
UCB1CTL0
UC1IFG
UC1IE
0DFh
0DEh
0DDh
0DCh
0DBh
0DAh
0D9h
0D8h
007h
006h
Comparator_A Comparator_A port disable CAPD 05Bh
p
_
Comparator_A control2 CACTL2 05Ah
Comparator_A control1 CACTL1 059h
BrownOUT, SVS SVS control register (Reset by brownout signal) SVSCTL 056h
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
27
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
FLL+ Clock FLL+ Control2 FLL_CTL2 055h
FLL+ Control1 FLL_CTL1 054h
FLL+ Control0 FLL_CTL0 053h
System clock frequency control SCFQCTL 052h
System clock frequency integrator SCFI1 051h
System clock frequency integrator SCFI0 050h
RTC Real Time Clock Year High Byte RTCYEARH 04Fh
(Basic Timer 1) Real Time Clock Year Low Byte RTCYEARL 04Eh
Real Time Clock Month RTCMON 04Dh
Real Time Clock Day of Month RTCDAY 04Ch
Basic Timer1 Counter 2 BTCNT2 047h
Basic Timer1 Counter 1 BTCNT1 046h
Real Time Counter 4
(Real Time Clock Day of Week)
RTCNT4
(RTCDOW)
045h
Real Time Counter 3
(Real Time Clock Hour)
RTCNT3
(RTCHOUR)
044h
Real Time Counter 2
(Real Time Clock Minute)
RTCNT2
(RTCMIN)
043h
Real Time Counter 1
(Real Time Clock Second)
RTCNT1
(RTCSEC)
042h
Real Time Clock Control RTCCTL 041h
Basic Timer1 Control BTCTL 040h
Port P10 Port P10 resistor enable P10REN 017h
Port P10 selection P10SEL 00Fh
Port P10 direction P10DIR 00Dh
Port P10 output P10OUT 00Bh
Port P10 input P10IN 009h
Port P9 Port P9 resistor enable P9REN 016h
Port P9 selection P9SEL 00Eh
Port P9 direction P9DIR 00Ch
Port P9 output P9OUT 00Ah
Port P9 input P9IN 008h
Port P8 Port P8 resistor enable P8REN 015h
Port P8 selection P8SEL 03Fh
Port P8 direction P8DIR 03Dh
Port P8 output P8OUT 03Bh
Port P8 input P8IN 039h
Port P7 Port P7 resistor enable P7REN 014h
Port P7 selection P7SEL 03Eh
Port P7 direction P7DIR 03Ch
Port P7 output P7OUT 03Ah
Port P7 input P7IN 038h
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
28 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P5 Port P5 resistor enable P5REN 012h
Port P5 selection P5SEL 033h
Port P5 direction P5DIR 032h
Port P5 output P5OUT 031h
Port P5 input P5IN 030h
Port P4 Port P4 resistor enable P4REN 011h
Port P4 selection P4SEL 01Fh
Port P4 direction P4DIR 01Eh
Port P4 output P4OUT 01Dh
Port P4 input P4IN 01Ch
Port P3 Port P3 resistor enable P3REN 010h
Port P3 selection P3SEL 01Bh
Port P3 direction P3DIR 01Ah
Port P3 output P3OUT 019h
Port P3 input P3IN 018h
Port P2 Port P2 resistor enable P2REN 02Fh
Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt-edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
Port P1 Port P1 resistor enable P1REN 027h
Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt-edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
Special Functions SFR interrupt flag2 IFG2 003h
p
SFR interrupt flag1 IFG1 002h
SFR interrupt enable2 IE2 001h
SFR interrupt enable1 IE1 000h
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
29
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings (see Note 1)
Voltage applied at VCC to VSS --0.3 V to 4.1 V......................................................
Voltage applied to any pin (see Note 2) --0.3 V to VCC +0.3V.......................................
Diode current at any device terminal . 2mA......................................................
Storage temperature, Tstg: Unprogrammed device (see Note 3) --55C to 150C.......................
Programmed device (see Note 3) --40Cto85C..........................
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage
is applied to the TDI/TCLK pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J--STD--020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
30 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage during program execution,
VCC (AVCC = DVCC = VCC)(seeNote1) 1.8 3.6 V
Supply voltage during program execution, SVS enabled, PORON = 1,
VCC (AVCC = DVCC = VCC) (see Notes 1, 2) 2.0 3.6 V
Supply voltage during program/erase flash memory,
VCC (AVCC = DVCC = VCC)(seeNote1) 2.2 3.6 V
Supply voltage, VSS 0 V
Operating free-air temperature range, TA-- 4 0 85 C
VCC =1.8V,
Duty cycle = 50% 10% dc 4.15 MHz
Processor frequency fS
Y
STEM (Maximum MCLK frequency)
VCC =2.2V,
Duty cycle = 50% 10% dc 7.5 MHz
P
r
o
c
e
s
s
o
r
f
r
e
q
u
e
n
c
y
f
S
Y
S
T
E
M
(
M
a
x
i
m
u
m
M
C
L
K
f
r
e
q
u
e
n
c
y
)
(see Notes 3, 4 and Figure 1) VCC =2.7V,
Duty cycle = 50% 10% dc 12
M
H
z
VCC 3.3 V,
Duty cycle = 50% 10% dc 16
MHz
NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can
be tolerated during power up and operation.
2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage.
POR is going inactive when the supply voltage is raised above minimum supply voltage plus the hysteresis of the SVS circuitry.
3. The MSP430 CPU is clocked directly with MCLK.
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
4. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this data
sheet.
4.15 MHz
12 MHz
16 MHz
1.8 V 2.2 V 2.7 V 3.3 V 3.6 V
Supply Voltage --V
System Frequency --MHz
Supply voltage range,
during flash memory
programming
Supply voltage range,
during program execution
Legend:
7.5 MHz
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.
Figure 1. Operating Area
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
31
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC +DV
CC excluding external current
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
I
Active mode, (see Note 1)
f(MCLK) =f
(SMCLK) =1MHz,
f
3
2
7
6
8
H
z
T
4
0
C
t
o
8
5
C
2.2 V 350 400
A
I(AM)
(
)
(
)
f
(ACLK) = 32768 Hz
XTS = 0, SELM = (0,1)
(Program executes from flash)
TA=--40Cto85C
3V 500 560
A
I
Low-
p
ower mode,
(
LPM0
)
T
4
0
C
t
o
8
5
C
2.2 V 45 70
A
I(LPM0)
L
o
w
p
o
w
e
r
m
o
d
e
,
(
L
P
M
0
)
(see Notes 1, 4) TA=--40Cto85C3V 75 110
A
I
Low-power mode, (LPM2),
f
(
M
C
L
K
)
f
(
S
M
C
L
K
)
0
M
H
z
T
4
0
C
t
o
8
5
C
2.2 V 11 14
A
I(LPM2)
f
(MCLK) =
f
(SMCLK) = 0 MHz,
f(ACLK) = 32768 Hz, SCG0 = 0 (see Notes 2, 4)
TA=--40Cto85C3V 17 22
A
L
o
w
p
o
w
e
r
m
o
d
e
(
L
P
M
3
)
TA=--40C0.7 2.0
Low-power mode, (LPM3)
f
(
M
C
L
K
)
=
f
(
S
M
C
L
K
)
=
0
M
H
z
,
TA=25C
2
2
V
0.8 2.0
A
f
(MCL
K
)=
f
(SMCL
K
)=
0
M
H
z
,
f
(
A
CL
K
)
= 32768 Hz, SCG0 = 1 TA=60C2.2
V
2.0 3.5
A
I
f
(
A
C
L
K
)
3
2
7
6
8
H
z
,
S
C
G
0
1
Basic Timer1 and RTC enabled , ACLK selected
L
C
D
A
e
n
a
b
l
e
d
L
C
D
C
P
E
N
0
:
TA=85C5.0 9.5
I(LPM3) LCD
_
A
enabled, LCDCPEN = 0:
(
s
t
a
t
i
c
m
o
d
e
,
f
L
C
D
=
f
(
A
C
L
K
)
/
3
2
)
TA=--40C1.1 3.0
(
s
t
a
t
i
c
m
o
d
e
,
f
LCD =
f
(
A
CL
K
)
/
3
2
)
(see Notes 2, 3, and 4) TA=25C
3
V
1.2 3.0
A
(
s
e
e
o
t
e
s
,
3
,
a
d
)
TA=60C3
V
2.5 4.0
A
TA=85C6.0 10.0
L
o
w
p
o
w
e
r
m
o
d
e
(
L
P
M
3
)
TA=--40C3.5 5.5
Low-power mode, (LPM3)
f
(
M
C
L
K
)
=
f
(
S
M
C
L
K
)
=
0
M
H
z
,
TA=25C
2
2
V
3.5 5.5
A
f
(MCL
K
)=
f
(SMCL
K
)=
0
M
H
z
,
f
(
A
CL
K
)
= 32768 Hz, SCG0 = 1 TA=60C2.2
V
5.5 7.0
A
I
f
(
A
C
L
K
)
3
2
7
6
8
H
z
,
S
C
G
0
1
Basic Timer1 and RTC enabled , ACLK selected
L
C
D
A
e
n
a
b
l
e
d
L
C
D
C
P
E
N
0
:
TA=85C11.0 17.0
I(LPM3) LCD
_
A
enabled, LCDCPEN = 0:
(
4
-
m
u
x
m
o
d
e
,
f
L
C
D
=
f
(
A
C
L
K
)
/
3
2
)
TA=--40C4.0 6.5
(
4
-
m
u
x
m
o
d
e
,
f
LCD =
f
(
A
CL
K
)
/
3
2
)
(see Notes 2, 3, and 4) TA=25C
3
V
4.0 6.5
A
(
s
e
e
o
t
e
s
,
3
,
a
d
)
TA=60C3
V
6.0 8.0
A
TA=85C13.0 20.0
TA=--40C0.1 1.0
TA=25C
2
2
V
0.2 1.0
A
TA=60C2.2
V
1.0 2.5
A
I
Low-power mode, (LPM4)
f
0
M
H
z
f
0
M
H
z
TA=85C4.5 8.5
I(LPM4)
f
(MCLK) =0MHz,
f
(SMCLK) =0MHz,
f
(
A
C
L
K
)
=
0
H
z
,
S
C
G
0
=
1
(
s
e
e
N
o
t
e
s
2
a
n
d
4
)
TA=--40C0.1 2.0
f
(
A
CL
K
)=
0
H
z
,
S
C
G
0
=
1
(
s
e
e
N
o
t
e
s
2
a
n
d
4
)
TA=25C
3
V
0.2 2.0
A
TA=60C3
V
1.5 3.0
A
TA=85C5.0 9.0
NOTES: 1. Timer_Aisclockedbyf
(DCOCLK) =f
(DCO) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
2. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
3. The LPM3 currents are characterized with a Micro Crystal CC4V--T1A (9 pF) crystal and OSCCAPx = 01h.
4. Current for brownout included.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
32 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
typical characteristics -- active mode supply current (into VCC)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
1.5 2.0 2.5 3.0 3.5 4.0
VCC -- Supply Voltage -- V
Active Mode Current -- mA
Figure 2. Active Mode Current vs VCC,T
A
=25C
fDCO =1MHz
fDCO =8MHz
fDCO =12MHz
fDCO =16MHz
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0.0 4.0 8.0 12.0 16.0
fDCO -- DCO Frequency -- MHz
Active Mode Current -- mA
Figure 3. Active Mode Current vs DCO Frequency
TA=25C
TA=85C
VCC =2.2V
VCC =3V
TA=25C
TA=85C
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
33
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs -- Ports P1 to P5, P7 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
P
i
t
i
i
i
t
t
h
h
l
d
0.45 0.75 VCC
VIT+
Positive-going input threshold
v
o
l
t
a
g
e
2.2 V 1.00 1.65
V
V
I
T
+
vo
l
t
age
3V 1.35 2.25
V
N
t
i
i
i
t
t
h
h
l
d
0.25 0.55 VCC
VIT--
Negative-going input threshold
v
o
l
t
a
g
e
2.2 V 0.55 1.20
V
V
I
T
-- vo
l
t
age
3V 0.75 1.65
V
V
In
p
ut volta
g
eh
y
steresis
(
V
I
T
+
-- 2.2 V 0.2 1.0
V
Vhys
I
n
p
u
t
v
o
l
t
a
g
e
h
y
s
t
e
r
e
s
i
s
(
V
I
T
+
VIT--)3V 0.3 1.0
V
RPull Pullup/pulldown resistor
(not RST/NMI and JTAG pins)
For pullup: VIN =V
SS,
For pulldown: VIN =V
CC 20 35 50 kΩ
CIInput capacitance VIN =V
SS or VCC 5pF
inputs -- Ports P1, P2
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
t(int) External interrupt timing
Port P1, P2: P1.x to P2.x, external
trigger puls width to set interrupt flag
(see Note 1)
2.2 V/3 V 20 ns
NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t(int) is met. It may be set even with trigger signals
shorter than t(int).
leakage current -- Ports P1 to P5, P7 to P10
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Ilkg(Px.x) High-impedance leakage current See Notes 1 and 2 2.2 V/3 V 50 nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
34 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs -- Ports P1 to P5, P7 to P10
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
I(OHmax) = --1.5 mA (see Note 1) 2.2 V VCC--0.25 VCC
V
H
i
g
h
l
e
v
e
l
o
u
t
p
u
t
v
o
l
t
a
g
e
I(OHmax) = --6 mA (see Note 2) 2.2 V VCC-- 0 . 6 VCC
V
VOH High-level output voltage I(OHmax) = --1.5 mA (see Note 1) 3V VCC--0.25 VCC
V
I(OHmax) = --6 mA (see Note 2) 3V VCC-- 0 . 6 VCC
I(OLmax) = 1.5 mA (see Note 1) 2.2 V VSS VSS+0.25
V
L
o
w
l
e
v
e
l
o
u
t
p
u
t
v
o
l
t
a
g
e
I(OLmax) = 6 mA (see Note 2) 2.2 V VSS VSS+0.6
V
VOL Low-level output voltage I(OLmax) = 1.5 mA (see Note 1) 3V VSS VSS+0.25
V
I(OLmax) = 6 mA (see Note 2) 3V VSS VSS+0.6
NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum
voltage drop specified.
2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed 48 mA to hold the maximum
voltage drop specified.
output frequency -- Ports P1 to P5, P7 to P10
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
f
P
o
r
t
o
u
t
p
u
t
f
r
e
q
u
e
n
c
y
(
w
i
t
h
l
o
a
d
)
P1.4/TBCLK/SMCLK,
C
2
0
p
F
R
1
k
Ω
a
g
a
i
n
s
t
V
/
2
2.2 V 10 MHz
f
Px.y Port output
f
requency (with load) CL=20pF,R
L=1kΩagainst
V
CC
/
2
(see Notes 1 and 2) 3V 12 MHz
f
C
l
o
c
k
o
u
t
p
u
t
f
r
e
q
u
e
n
c
y
P1.1/TA0/MCLK, P1.5/TACLK/ACLK,
P
1
4
/
T
B
C
L
K
/
S
M
C
L
K
2.2 V 12 MHz
f
Port_CLK Clock output
f
requency P1.4
/
TBCLK
/
SMCLK,
CL=20pF(seeNote2) 3V 16 MHz
NOTES: 1. Alternatively a resistive divider with 2 times 2 kΩbetween VCC and VSS is used as load. The output is connected to the center tap
of the divider.
2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
35
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- outputs
Figure 4
VOL -- Low-Level Output Voltage -- V
0.0
5.0
10.0
15.0
20.0
25.0
30.0
0.0 0.5 1.0 1.5 2.0 2.5
VCC =2.2V
P1.6
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA=25C
TA=85C
OL
I -- Typical Low-Level Output Current -- m
A
Figure 5
VOL -- Low-Level Output Voltage -- V
0.0
10.0
20.0
30.0
40.0
50.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC =3V
P1.6
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA=25C
TA=85C
OL
I -- Typical Low-Level Output Current -- mA
Figure 6
VOH -- High-Level Output Voltage -- V
--30.0
--25.0
--20.0
--15.0
--10.0
-- 5 . 0
0.0
0.0 0.5 1.0 1.5 2.0 2.5
VCC =2.2V
P1.6
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA=25C
TA=85C
OH
I -- Typical High-Level Output Current -- m
A
Figure 7
VOH -- High-Level Output Voltage -- V
--60.0
--50.0
--40.0
--30.0
--20.0
--10.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC =3V
P1.6
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA=25C
TA=85C
OH
I -- Typical High-Level Output Current -- mA
NOTE: One output loaded at a time.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
36 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VCC(start) (See Figure 8) dVCC/dt 3V/s 0.7 V(B_IT--) V
V(B_IT--) (See Figure 8 through Figure 10) dVCC/dt 3V/s 1.71 V
Vhys(B_IT--) (See Figure 8) dVCC/dt 3V/s 70 130 180 mV
td(BOR) (See Figure 8) 2000 s
t(reset)
Pulse length needed at RST/NMI pin
to accepted reset internally 2.2 V/3 V 2s
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data.
The voltage level V(B_IT--) +V
hys(B_IT--) is 1.8 V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC =V
(B_IT--) +V
hys(B_IT--). The default FLL+
settings must not be changed until VCC VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit.
0
1
td(BOR)
VCC
V(B_IT--)
Vhys(B_IT--)
VCC(start)
Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
37
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- POR/brownout reset (BOR)
VCC(drop)
VCC
3V
tpw
0
0.5
1
1.5
2
0.001 1 1000
Typical Conditions
1ns 1ns
tpw -- Pulse Width -- s
VCC(drop) -- V
tpw -- Pulse Width -- s
VCC =3V
Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
0
0.5
1
1.5
2
VCC(drop)
tpw
tpw -- Pulse Width -- s
VCC(drop) -- V
3V
0.001 1 1000 tftr
tpw -- Pulse Width -- s
tf=tr
Typical Conditions
VCC =3V
Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
38 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
SVS (supply voltage supervisor/monitor) (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
dVCC/dt 30 V/ms (see Figure 11) 5150 s
t(SVSR) dVCC/dt 30 V/ms 2000 s
td(SVSon) SVSon, switch from VLD = 0 to VLD 0, VCC =3V 150 300 s
tsettle VLD 0(seeNote2) 12 s
V(SVSstart) VLD 0, VCC/dt 3 V/s (see Figure 11) 1.55 1.7 V
VLD = 1 70 120 155 mV
Vh
y
s
(
S
V
SIT--
)
VCC/dt 3 V/s (see Figure 11) VLD=2to14 V(SVS_IT--)
0.001
V(SVS_IT--)
0.016
V
h
y
s
(
S
V
S
_
I
T
--
)
VCC/dt 3 V/s (see Figure 11),
External voltage applied on A7 VLD = 15 4.4 10.4 mV
VLD = 1 1.8 1.9 2.05
VLD = 2 1.94 2.1 2.25
VLD = 3 2.05 2.2 2.37
VLD = 4 2.14 2.3 2.48
VLD = 5 2.24 2.4 2.6
VLD = 6 2.33 2.5 2.71
V
/
d
t
3
V
/
s
(
s
e
e
F
i
g
u
r
e
1
1
)
VLD = 7 2.46 2.65 2.86
V
(
S
V
S
I
T
)
VCC
/
dt 3V
/
s (see Figure 11) VLD = 8 2.58 2.8 3
V
V
(SVS_IT--) VLD = 9 2.69 2.9 3.13
V
VLD = 10 2.83 3.05 3.29
VLD = 11 2.94 3.2 3.42
VLD = 12 3.11 3.35 3.61†
VLD = 13 3.24 3.5 3.76†
VLD = 14 3.43 3.7†3.99†
VCC/dt 3 V/s (see Figure 11),
External voltage applied on A7 VLD = 15 1.1 1.2 1.3
ICC(SVS)
(see Note 1) VLD 0, VCC =2.2V/3V 10 15 A
†The recommended operating voltage range is limited to 3.6 V.
NOTES: 1. The current consumption of the SVS module is not included in the ICC current consumption data.
2. tsettle is the settling time that the comparator output needs to have a stable level after VLD is switched VLD 0 to a different VLD
value somewhere between 2 and 15. The overdrive is assumed to be > 50 mV.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
39
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
typical characteristics
VCC(start)
VCC
V(B_IT--)
Brownout
Region
V(SVSstart)
V(SVS_IT--)
Software Sets VLD>0:
SVS is Active
td(SVSR)
undefined
Vhys(SVS_IT--)
0
1
td(BOR)
Brownout
0
1
td(SVSon)
td(BOR)
0
1
Set POR
Brown-
Out
Region
SVS Circuit is Active From VLD > to VCC <V(
B_IT--)
SVSOut
Vhys(B_IT--)
Figure 11. SVS Reset (SVSR) vs Supply Voltage
0
0.5
1
1.5
2
VCC
VCC
1ns 1ns
VCC(min)
tpw
tpw -- Pulse Width -- s
VCC(min)-- V
3V
1 10 1000
tftr
t -- Pulse Width -- s
100
tpw
3V
tf=tr
Rectangular Drop
Triangular Drop
VCC(min)
Figure 12. VCC(min) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
40 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
DCO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(DCOCLK) N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2,
DCOPLUS = 0 VCC =2.2V/3V 1MHz
f
F
N
8
F
N
4
F
N
3
F
N
2
0
D
C
O
P
L
U
S
1
VCC =2.2V 0.3 0.65 1.25
M
H
z
f
(DCO = 2) FN
_
8=FN
_
4=FN
_
3=FN
_
2 = 0, DCOPLUS = 1 VCC =3V 0.3 0.7 1.3 MHz
f
F
N
8
F
N
4
F
N
3
F
N
2
0
D
C
O
P
L
U
S
1
VCC =2.2V 2.5 5.6 10.5
M
H
z
f
(DCO = 27) FN
_
8=FN
_
4=FN
_
3=FN
_
2 = 0, DCOPLUS = 1 VCC =3V 2.7 6.1 11.3 MHz
f
FN
_
8=FN
_
4=FN
_
3=0,FN
_
2 = 1, DCOPLUS = 1 VCC =2.2V 0.7 1.3 2.3
M
H
z
f
(DCO = 2)
F
N
_
8
=
F
N
_
4
=
F
N
_
3
=
0
,
F
N
_
2
=
1
,
D
C
O
P
L
U
S
=
1
VCC =3V 0.8 1.5 2.5 MHz
f
F
N
8
F
N
4
F
N
3
0
F
N
2
1
D
O
P
L
U
S
1
VCC =2.2V 5.7 10.8 18
M
H
z
f
(DCO = 27) FN
_
8=FN
_
4=FN
_
3=0,FN
_
2 = 1, DOPLUS = 1 VCC =3V 6.5 12.1 20 MHz
f
F
N
8
F
N
4
0
F
N
3
1
F
N
2
x
D
C
O
P
L
U
S
1
VCC =2.2V 1.2 2 3
M
H
z
f
(DCO = 2) FN
_
8=FN
_
4=0,FN
_
3=1,FN
_
2 = x, DCOPLUS = 1 VCC =3V 1.3 2.2 3.5 MHz
f
F
N
8
F
N
4
0
F
N
3
1
F
N
2
x
D
C
O
P
L
U
S
1
VCC =2.2V 915.5 25
M
H
z
f
(DCO = 27) FN
_
8=FN
_
4=0,FN
_
3=1,FN
_
2 = x, DCOPLUS = 1 VCC =3V 10.3 17.9 28.5 MHz
f
F
N
8
0
F
N
4
1
F
N
3
F
N
2
x
D
C
O
P
L
U
S
1
VCC =2.2V 1.8 2.8 4.2
M
H
z
f
(DCO = 2) FN
_
8=0,FN
_
4=1,FN
_
3=FN
_
2 = x, DCOPLUS = 1 VCC =3V 2.1 3.4 5.2 MHz
f
F
N
8
0
F
N
4
1
F
N
3
F
N
2
x
D
C
O
P
L
U
S
1
VCC =2.2V 13.5 21.5 33
M
H
z
f
(DCO = 27) FN
_
8=0,FN
_
4=1,FN
_
3=FN
_
2 = x, DCOPLUS = 1 VCC =3V 16 26.6 41 MHz
f
F
N
8
1
F
N
4
F
N
3
F
N
2
x
D
C
O
P
L
U
S
1
VCC =2.2V 2.8 4.2 6.2
M
H
z
f
(DCO = 2) FN
_
8=1,FN
_
4=FN
_
3=FN
_
2 = x, DCOPLUS = 1 VCC =3V 4.2 6.3 9.2 MHz
f
F
N
8
1
F
N
4
F
N
3
F
N
2
x
D
C
O
P
L
U
S
1
VCC =2.2V 21 32 46
M
H
z
f
(DCO = 27) FN
_
8=1,FN
_
4=FN
_
3=FN
_
2 = x, DCOPLUS = 1 VCC =3V 30 46 70 MHz
S
Ste
p
size between ad
j
acent DCO ta
p
s: 1<TAP20 1.06 1.11
Sn
S
t
e
p
s
i
z
e
b
e
t
w
e
e
n
a
d
j
a
c
e
n
t
D
C
O
t
a
p
s
:
Sn=f
DCO(Tap n+1) /f
DCO(Tap n), (see Figure 14 for taps 21 to 27) TAP = 27 1.07 1.17
D
t
Tem
p
erature dri
f
t, N
(
D
C
O
)
= 01Eh, FN
_
8=FN
_
4=FN
_
3=FN
_
2=0 VCC =2.2V –0.2 –0.4 –0.6
%
_
C
D
t
T
e
m
p
e
r
a
t
u
r
e
d
r
i
f
t
,
N
(
D
C
O
)
=
0
1
E
h
,
F
N
_
8
=
F
N
_
4
=
F
N
_
3
=
F
N
_
2
=
0
D = 2, DCOPLUS = 0 VCC =3V –0.2 –0.4 –0.6 %_C
DV
Drift with VCC variation, N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 =
FN_2=0,D=2,DCOPLUS=0 VCC =2.2V/3V 0 5 15 %/V
T
A
-- CVCC -- V
f(DCO)
f(DCO25C)
f(DCO)
f(DCO3V)
1.8 3.02.4 3.6
1.0
20 6040 85
1.0
0-- 2 0-- 4 00
Figure 13. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
41
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12720
1.11
1.17
DCO Tap
Sn- Stepsize Ratio between DCO Taps
Min
Max
1.07
1.06
Figure 14. DCO Tap Step Size
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Legend
Tolerance at Tap 27
Tolerance at Tap 2
DCO Frequency
Adjusted by Bits
29to 2 5in SCFI1 {N (DCO)}
Overlapping DCO Ranges:
uninterrupted frequency range
f(DCO)
Figure 15. Five Overlapping DCO Ranges Controlled by FN_x Bits
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
42 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
crystal oscillator, LFXT1, low-frequency mode (see Note 4)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fLFXT1,LF LFXT1 oscillator crystal
frequency, LF mode XTS = 0 1.8 V to 3.6 V 32768 Hz
O
A
Oscillation allowance
f
or LF
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz,
CL,eff =6pF
500 kΩ
O
A
LF
O
s
c
i
l
l
a
t
i
o
n
a
l
l
o
w
a
n
c
e
f
o
r
L
F
crystals XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz,
CL,eff =12pF
200 kΩ
XTS = 0, XCAPxPF = 0 1pF
C
Integrated effective load
c
a
p
a
c
i
t
a
n
c
e
L
F
m
o
d
e
XTS = 0, XCAPxPF = 1 5.5 pF
CL,eff capacitance, LF mode
(
s
e
e
N
o
t
e
1
)
XTS = 0, XCAPxPF = 2 8.5 pF
(
s
e
e
N
o
t
e
1
)
XTS = 0, XCAPxPF = 3 11 pF
Duty Cycle LF mode XTS = 0, fLFXT1,LF = 32768 Hz
Measured at P1.5/TACLK/ACLK 2.2 V/3 V 30 50 70 %
fFault,LF Oscillator fault frequency,
LF mode (see Note 3) XTS=0(seeNote2) 2.2 V/3 V 10 10,000 Hz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
crystal oscillator, LFXT1, high-frequency mode
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fXT1 XT1 oscillator crystal frequency XTS = 1, Ceramic resonator 1.8 V to 3.6 V 0.45 6MHz
fXT1 XT1 oscillator crystal frequency XTS = 1, Crystal 1.8 V to 3.6 V 1 6 MHz
CL,eff Integrated effective load
capacitance (see Note 1) (see Note 2) 1pF
Duty Cycle Measured at P1.5/TACLK/ACLK 2.2 V/3 V 40 50 60 %
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
43
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
crystal oscillator, XT2 oscillator (see Note 5)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fXT2,0 XT2 oscillator crystal frequency,
mode 0 XT2Sx = 0 1.8 V to 3.6 V 0.4 1MHz
fXT2,1 XT2 oscillator crystal frequency,
mode 1 XT2Sx = 1 1.8 V to 3.6 V 1 4 MHz
X
T
2
i
l
l
t
t
l
f
1.8 V to 3.6 V 210 MHz
f
X
T2
,
2
XT2 oscillator crystal frequency,
m
o
d
e
2
XT2Sx = 2 2.2 V to 3.6 V 212 MHz
f
X
T
2
,
2
mo
d
e
2
X
T
2
S
x
2
3.0 V to 3.6 V 216 MHz
X
T
2
i
l
l
t
l
i
l
l
1.8 V to 3.6 V 0.4 10 MHz
f
X
T2
,
lo
g
ic
XT2 oscillator logic level square
w
a
v
e
i
n
p
u
t
f
r
e
q
u
e
n
c
y
XT2Sx = 3 2.2 V to 3.6 V 0.4 12 MHz
f
X
T
2
,
l
o
g
i
c
wave
i
npu
t
f
requency
X
T
2
S
x
3
3.0 V to 3.6 V 0.4 16 MHz
XT2Sx = 0,
fXT2 =1MHz,C
L,eff =15pF 2700 Ω
OAXT2 Oscillation allowance for HF
crystals (see Figure 16)
XT2Sx = 1
fXT2 =4MHz,C
L,eff =15pF 800 Ω
c
r
y
s
t
a
l
s
(
s
e
e
F
i
g
u
r
e
1
6
)
XT2Sx = 2
fXT2 =16MHz,C
L,eff =15pF 300 Ω
CL,eff Integrated effective load
capacitance (see Note 1) (see Note 2) 1pF
D
u
t
y
c
y
c
l
e
Measured at P1.5/TACLK/ACLK,
fXT2 =10MHz 2.2 V/3 V 40 50 60 %
Duty cycle Measured at P1.5/TACLK/ACLK,
fXT2 =16MHz 2.2 V/3 V 40 50 60 %
fFault,XT2 Oscillator fault frequency
(see Note 4) XT2Sx = 3 (see Notes 3) 2.2 V/3 V 30 300 kHz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the frequency. For a correct
setup the effective load capacitance should always match the specification of the used crystal.
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
3. Measured with logic level input frequency but also applies to operation with crystals.
4. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
5. To improve EMI on the XT2 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
-- Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
44 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- XT2 oscillator
Crystal Frequency -- MHz
10.00
100.00
1000.00
10000.00
100000.00
0.10 1.00 10.00 100.00
Oscillation Allowance -- Ohms
XT2Sx = 0
XT2Sx = 2
XT2Sx = 1
Figure 16. Oscillation Allowance vs Crystal Frequency, CL,eff =15pF,T
A=25C
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
45
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
f=1MHz 6
td
(
LPM3
)
Delay time f=2MHz 2.2 V/3 V 6s
t
d
(
L
P
M
3
)
D
e
l
a
y
t
i
m
e
f=3MHz
2
.
2
V
/
3
V
6
s
LCD_A
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VCC(LCD) Supply voltage range Charge pump enabled
(LCDCPEN = 1, VLCDx > 0000) 2.2 3.6 V
CLCD Capacitor on LCDCAP (see Note 1) Charge pump enabled
(LCDCPEN = 1, VLCDx > 0000) 4.7 F
ICC(LCD) Supply current
VLCD(typ) =3V,LCDCPEN=1,
VLCDx = 1000, all segments on,
fLCD =f
ACLK/32
no LCD connected (see Note 2),
TA=25C
2.2 V 3.8 A
fLCD LCD frequency 1.1 kHz
VLCD LCD voltage VLCDx = 0000 VCC V
VLCD LCD voltage VLCDx = 0001 2.60 V
VLCD LCD voltage VLCDx = 0010 2.66 V
VLCD LCD voltage VLCDx = 0011 2.72 V
VLCD LCD voltage VLCDx = 0100 2.78 V
VLCD LCD voltage VLCDx = 0101 2.84 V
VLCD LCD voltage VLCDx = 0110 2.90 V
VLCD LCD voltage VLCDx = 0111 2.96 V
VLCD LCD voltage VLCDx = 1000 3.02 V
VLCD LCD voltage VLCDx = 1001 3.08 V
VLCD LCD voltage VLCDx = 1010 3.14 V
VLCD LCD voltage VLCDx = 1011 3.20 V
VLCD LCD voltage VLCDx = 1100 3.26 V
VLCD LCD voltage VLCDx = 1101 3.32 V
VLCD LCD voltage VLCDx = 1110 3.38 V
VLCD LCD voltage VLCDx = 1111 3.44 3.60 V
RLCD LCD driver output impedance VLCD = 3 V, LCDCPEN = 1,
VLCDx = 1000, ILOAD = 10 A2.2 V 10 k
NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device.
2. Connecting an actual display will increase the current consumption depending on the size of the LCD.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
46 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
I
C
A
O
N
1
C
A
R
S
E
L
0
C
A
R
E
F
0
2.2 V 25 40
A
I(CC) C
A
ON = 1, C
A
RSEL = 0, C
A
REF = 0 3V 45 60
A
I
C
A
ON = 1, C
A
RSEL = 0, C
A
REF = 1
/
2
/
3, 2.2 V 30 50
A
I(Refladder/RefDiode)
C
A
O
N
=
1
,
C
A
R
S
E
L
=
0
,
C
A
R
E
F
=
1
/
2
/
3
,
No load at P2.6/CA0 and P2.7/CA1 3V 45 80
A
V(Ref025)
Voltage @ 0.25 VCC node
VCC
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at P2.6/CA0 and P2.7/CA1 2.2 V / 3 V 0.23 0.24 0.25
V(Ref050)
Voltage @ 0.5 VCC node
VCC
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at P2.6/CA0 and P2.7/CA1 2.2V / 3 V 0.47 0.48 0.5
V
See Fi
g
ure 17 and PCA0 = 1, CARSEL = 1, CAREF = 3,
N
o
l
o
a
d
a
t
P
2
6
/
C
A
0
a
n
d
P
2
7
/
C
A
1
2.2 V 390 480 540
m
V
V(RefVT)
S
e
e
F
i
g
u
r
e
1
7
a
n
d
Figure 18 No load at P2.6
/
C
A
0 and P2.7
/
C
A
1,
TA=85C3V 400 490 550 m
V
VIC Common-mode input
voltage range CAON = 1 2.2 V / 3 V 0 VCC-- 1 V
Vp-- V SOffset voltage SeeNote2 2.2 V / 3 V -- 3 0 30 mV
Vhys Input hysteresis CAON = 1 2.2 V / 3 V 00.7 1.4 mV
T
A
=25C, 2.2 V 80 165 300
n
s
t
(
S
e
e
N
o
t
e
3
)
T
A
=
2
5
C
,
Overdrive 10 mV, without filter: CAF = 0 3V 70 120 240 ns
t(response LH and HL) (See Note 3) T
A
=25C2.2 V 1.4 1.9 2.8
s
T
A
=
2
5
C
Overdrive 10 mV, with filter: CAF = 1 3V 0.9 1.5 2.2 s
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
3. The response time is measured at P2.6/CA0 with an input voltage step and the Comparator_A already enabled (CAON = 1). If CAON
is set at the same time, a settling time of up to 300 ns is added to the response time.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
47
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
typical characteristics
TA-- Free-Air Temperature -- C
400
450
500
550
600
650
-- 4 5 -- 2 5 -- 5 1 5 3 5 5 5 7 5 9 5
VCC =3V
Figure 17. V
(
Ref
V
T
)
vs Temperature
VREF -- Reference Voltage -- mV
Typical
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
Figure 18. V
(
Ref
V
T
)
vs Temperature
TA-- Free-Air Temperature -- C
400
450
500
550
600
650
-- 4 5 -- 2 5 -- 5 1 5 3 5 5 5 7 5 9 5
VCC =2.2V
Typical
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
VREF -- Reference Voltage -- mV
_
+
CAON
0
1
V+ 0
1
CAF
Low-Pass Filter
2s
To Internal
Modules
Set CAIFG
Flag
CAOUT
V--
VCC
1
0V
0
Figure 19. Block Diagram of Comparator_A Module
Overdrive VCAOUT
t(response)
V+
V--
400 mV
Figure 20. Overdrive Definition
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
48 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer_A
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
f
T
i
m
e
r
A
c
l
o
c
k
f
r
e
q
u
e
n
c
y
Internal: SMCLK, ACLK,
E
x
t
e
r
n
a
l
:
T
A
C
L
K
I
N
C
L
K
2.2 V 10
M
H
z
f
TA Timer
_
A
clock
f
requency E
x
ternal: T
A
CLK, INCLK,
Duty cycle = 50% 10% 3V 16
MHz
tTA,cap Timer_A, capture timing TA0, TA1, TA2 2.2 V/3 V 20 ns
Timer_B
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
f
T
i
m
e
r
B
c
l
o
c
k
f
r
e
q
u
e
n
c
y
Internal: SMCLK, ACLK,
E
x
t
e
r
n
a
l
:
T
B
C
L
K
2.2 V 10
M
H
z
f
TB Timer
_
Bclock
f
requency E
x
ternal: TBCLK,
Duty cycle = 50% 10% 3V 16
MHz
tTB,cap Timer_B, capture timing TB0, TB1, TB2 2.2 V/3 V 20 ns
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
49
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode) -- recommended operating conditions
PARAMETER CONDITIONS MIN MAX UNIT
fUSCI USCI input clock frequency
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% 10%
fSYSTEM MHz
fBITCLK BITCLK clock frequency
(equals baud rate in MBaud) 1MHz
USCI (UART mode)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
t
U
A
RT receive de
g
litch time 2.2 V 50 150 600 ns
t
U
A
R
T
r
e
c
e
i
v
e
d
e
g
l
i
t
c
h
t
i
m
e
(see Note 1) 3V 50 100 600 ns
NOTES: 1. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI master mode) -- recommended operating conditions
PARAMETER CONDITIONS MIN MAX UNIT
fUSCI USCI input clock frequency SMCLK, ACLK
Duty cycle = 50% 10% fSYSTEM MHz
USCI (SPI master mode) (see Note 1, Figure 21, and Figure 22)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
fUSCI USCI input clock frequency SMCLK, ACLK
Duty cycle = 50% 10% fSYSTEM MHz
t
S
O
M
I
i
n
p
u
t
d
a
t
a
s
e
t
u
p
t
i
m
e
2.2 V 110 ns
tSU,MI SOMI input data setup time 3V 75 ns
t
S
O
M
I
i
n
p
u
t
d
a
t
a
h
o
l
d
t
i
m
e
2.2 V 0ns
tHD,MI SOMI input data hold time 3V 0ns
t
S
I
M
O
o
u
t
p
u
t
d
a
t
a
v
a
l
i
d
t
i
m
e
(
N
o
t
e
2
)
UCLK ed
g
etoSIMOvalid, 2.2 V 30 ns
tVALID,MO SIMO output data valid time (Note 2)
U
C
L
K
e
d
g
e
t
o
S
I
M
O
v
a
l
i
d
,
CL=20pF 3V 20 ns
t
S
I
M
O
o
u
t
p
u
t
d
a
t
a
h
o
l
d
t
i
m
e
(
N
o
t
e
3
)
C
2
0
p
F
2.2 V 0ns
tHD,MO SIMO output data hold time (Note 3) CL=20pF 3V 0ns
NOTES: 1. fUCxCLK =1
2tLO∕HI
with tLO∕HI ≥max(tVALID,MO(USCI) +tSU,SI(Slave), tSU,MI(USCI) +tVALID,SO(Slave)).
For the slave’s parameters tSU,SI(Slave) and tVALID,SO(Slave) refer to the SPI parameters of the attached slave.
2. Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 21 and Figure 22.
3. Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the
data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams
in Figure 21 and Figure 22.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
50 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
UCLK
CKPL=0
CKPL=1
SIMO
1/fUCxCLK
tLO/HI tLO/HI
SOMI
tSU,MI
tHD,MI
tVALID,MO
tHD,MO
Figure 21. SPI Master Mode, CKPH = 0
UCLK
CKPL=0
CKPL=1
SIMO
1/fUCxCLK
tLO/HI tLO/HI
SOMI
tSU,MI
tHD,MI
tVALID,MO
tHD,MO
Figure 22. SPI Master Mode, CKPH = 1
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
51
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (SPI slave mode) (see Note 1, Figure 23, and Figure 24)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
tSTE,LEAD STE lead time
STE low to clock 2.2 V/3 V 50 ns
tSTE,LAG STE lag time
Last clock to STE high 2.2 V/3 V 10 ns
tSTE,ACC STE access time
STE low to SOMI data out 2.2 V/3 V 50 ns
tSTE,DIS STE disable time
STE high to SOMI high impedance 2.2 V/3 V 50 ns
t
S
I
M
O
i
n
p
u
t
d
a
t
a
s
e
t
u
p
t
i
m
e
2.2 V 20 ns
tSU,SI SIMO input data setup time 3V 15 ns
t
S
I
M
O
i
n
p
u
t
d
a
t
a
h
o
l
d
t
i
m
e
2.2 V 10 ns
tHD,SI SIMO input data hold time 3V 10 ns
t
S
O
M
I
o
u
t
p
u
t
d
a
t
a
v
a
l
i
d
t
i
m
e
(
N
o
t
e
2
)
UCLK ed
g
etoSOMIvalid, 2.2 V 75 110 ns
tVALID,SO SOMI output data valid time (Note 2)
U
C
L
K
e
d
g
e
t
o
S
O
M
I
v
a
l
i
d
,
CL=20pF 3V 50 75 ns
t
S
O
M
I
o
u
t
p
u
t
d
a
t
a
h
o
l
d
t
i
m
e
(
N
o
t
e
3
)
C
2
0
p
F
2.2 V 0ns
tHD,MO SOMI output data hold time (Note 3) CL=20pF 3V 0ns
NOTES: 1. fUCxCLK =1
2tLO∕HI
with tLO∕HI ≥max(tVALID,MO(Master) +tSU,SI(USCI), tSU,MI(Master) +tVALID,SO(USCI)).
For the master’s parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached master.
2. Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 23 and Figure 24.
3. Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Negative values indicate that the
data on the SOMI output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams
in Figure 23 and Figure 24.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
52 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
STE
UCLK
CKPL=0
CKPL=1
SOMI
tSTE,ACC tSTE,DIS
1/fUCxCLK
tLO/HI tLO/HI
SIMO
tSU,SI
tHD,SI
tVALID,SO
tSTE,LEAD tSTE,LAG
tHD,SO
Figure 23. SPI Slave Mode, CKPH = 0
STE
UCLK
CKPL=0
CKPL=1
tSTE,LEAD tSTE,LAG
tSTE,ACC tSTE,DIS
tLO/HI tLO/HI
tSU,SI
tHD,SI
tVALID,SO
SOMI
SIMO
1/fUCxCLK
tHD,SO
Figure 24. SPI Slave Mode, CKPH = 1
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
53
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (I2C mode) (see Figure 25)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fUSCI USCI input clock frequency
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% 10%
fSYSTEM MHz
fSCL SCL clock frequency 2.2 V/3 V 0400 kHz
t
H
o
l
d
t
i
m
e
(
r
e
p
e
a
t
e
d
)
S
T
A
R
T
fSCL 100kHz (standard mode) 2.2 V/3 V 4.0 s
tHD,STA Hold time (repeated) ST
A
RT fSCL > 100kHz (fast mode) 2.2 V/3 V 0.6 s
t
S
e
t
p
t
i
m
e
f
o
r
a
r
e
p
e
a
t
e
d
S
T
A
R
T
fSCL 100kHz (standard mode) 2.2 V/3 V 4.7 s
tSU,STA Setup time
f
or a repeated ST
A
RT fSCL > 100kHz (fast mode) 2.2 V/3 V 0.6 s
tHD,DAT Data hold time 2.2 V/3 V 0ns
tSU,DAT Data setup time 2.2 V/3 V 250 ns
t
S
e
t
u
p
t
i
m
e
f
o
r
S
T
O
P
fSCL 100kHz (standard mode) 2.2 V/3 V 4.0 s
tSU,STO Setup time
f
or STOP fSCL > 100kHz (fast mode) 2.2 V/3 V 0.6 s
t
Pulse width o
f
s
p
ikes su
p
p
ressed b
y
2.2 V 50 150 600 ns
tSP
P
u
l
s
e
w
i
d
t
h
o
f
s
p
i
k
e
s
s
u
p
p
r
e
s
s
e
d
b
y
input filter 3V 50 100 600 ns
SDA
SCL
1/fSCL
tHD,DAT
tSU,DAT
tHD,STA tSU,STA tHD,STA
tSU,STO
tSP
Figure 25. I2C Mode Timing
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
54 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, power supply and recommended operating conditions
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC Analog supply voltage AVCC =DV
CC
AVSS =DV
SS =0V 2.5 3.6 V
S
D
1
6
L
P
=
0
,
GAIN: 1,2 3V 800 1100
A
n
a
l
o
g
s
p
p
l
c
r
r
e
n
t
1
a
c
t
i
e
S
D
1
6
L
P
=
0
,
fSD16 =1MHz, GAIN: 4,8,16 3V 900 1200
I
S
D
1
6
A
nalog supply current: 1 active
S
D
1
6
A
c
h
a
n
n
e
l
i
n
c
l
u
d
i
n
g
f
S
D
1
6
1
M
H
z
,
SD16OSR = 256 GAIN: 32 3V 1200 1700
A
I
SD16
S
D
1
6
_
A
c
h
a
n
n
e
l
i
n
c
l
u
d
i
n
g
internal reference SD16LP = 1,
f
0
5
M
H
z
GAIN: 1 3V 800 1100
A
f
SD16 =0.5MHz,
SD16OSR = 256 GAIN: 32 3V 900 1200
f
A
nalo
g
f
ront-end in
p
ut clock SD16LP = 0 (low-power mode disabled) 3V 0.03 11.1
M
H
f
SD16
A
n
a
l
o
g
f
r
o
n
t
e
n
d
i
n
p
u
t
c
l
o
c
k
frequency SD16LP = 1 (low-power mode enabled) 3V 0.03 0.5 MHz
SD16_A, input range (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
V
Di
f
f
erential
f
ull scale Bipolar mode, SD16UNI = 0 -- V REF/2GAIN +VREF/2GAIN mV
VID,FSR
D
i
f
f
e
r
e
n
t
i
a
l
f
u
l
l
s
c
a
l
e
input voltage range Unipolar mode, SD16UNI = 1 0+VREF/2GAIN mV
SD16GAINx = 1 500
Differential input SD16GAINx = 2 250
V
D
i
f
f
e
r
e
n
t
i
a
l
i
n
p
u
t
voltage range for
s
p
e
c
i
f
i
e
d
SD16REFON = SD16GAINx = 4 125
m
V
VID speci
f
ied
p
e
r
f
o
r
m
a
n
c
e
S
D
1
6
R
E
F
O
N
1SD16GAINx = 8 62 m
V
p
e
r
f
o
r
m
a
n
c
e
(see Note 2) SD16GAINx = 16 31
(
s
e
e
N
o
t
e
2
)
SD16GAINx = 32 15
Z
Input impedance
(
o
n
e
i
n
p
u
t
p
i
n
t
o
f
1
M
H
z
SD16GAINx = 1 3V 200
k
ZI(one input pin to
AVSS)
f
SD16 =1MHz SD16GAINx = 32 3V 75 k
Z
Differential input
i
m
p
e
d
a
n
c
e
f
1
M
H
z
SD16GAINx = 1 3V 300 400
k
ZID impedance
(IN+ to IN--)
f
SD16 =1MHz SD16GAINx = 32 3V 100 150 k
VIAbsolute input
voltage range AVSS -1V AVCC V
VIC Common-mode
input voltage range AVSS -1V AVCC V
NOTES: 1. All parameters pertain to each SD16_A channel.
2. The full-scale range is defined by VFSR+ =+(V
REF/2)/GAIN and VFSR-- =--(V
REF/2)/GAIN.
If VREF is sourced externally, the analog input range should not exceed 80% of VFSR+ or VFSR--; i.e., VID =0.8V
FSR-- to 0.8 VFSR+.
If VREF is sourced internally, the given VID ranges apply.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
55
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, performance (fSD16 = 1 MHz, SD16OSRx = 256, SD16REFON = 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SD16GAINx = 1,
Signal amplitude VPP = 500 mV 3V 83 85
SD16GAINx = 2,
Signal amplitude VPP = 250 mV 3V 81 84
S
I
N
A
D
Si
g
nal-to-noise + distortion
SD16GAINx = 4,
Signal amplitude VPP = 125 mV fIN =50Hz,
1
0
0
H
z
3V 76 79
d
B
SIN
A
D
S
i
g
n
a
l
t
o
n
o
i
s
e
+
d
i
s
t
o
r
t
i
o
n
ratio SD16GAINx = 8,
Signal amplitude VPP =62mV
100 Hz
(see Note 1) 3V 73 76
dB
SD16GAINx = 16,
Signal amplitude VPP =31mV 3V 69 73
SD16GAINx = 32,
Signal amplitude VPP =15mV 3V 62 69
SD16GAINx = 1 3V 0.97 1.00 1.02
SD16GAINx = 2 3V 1.90 1.96 2.02
G
SD16GAINx = 4 3V 3.76 3.86 3.96
GNominal gain SD16GAINx = 8 3V 7.36 7.62 7.84
SD16GAINx = 16 3V 14.56 15.04 15.52
SD16GAINx = 32 3V 27.20 28.35 29.76
E
O
f
f
s
e
t
e
r
r
o
r
SD16GAINx = 1 3V 0.2
%
F
S
R
EOS O
f
f
set error SD16GAINx = 32 3V 1.5 %FSR
d
E
/
d
T
O
f
f
set error tem
p
erature SD16GAINx = 1 3V 420
p
p
m
dEOS
/
dT
O
f
f
s
e
t
e
r
r
o
r
t
e
m
p
e
r
a
t
u
r
e
coefficient SD16GAINx = 32 3V 20 100
p
p
m
FSR/_C
C
M
R
R
Common-mode re
j
ection
SD16GAINx = 1, Common-mode input signal:
VID = 500 mV, fIN = 50 Hz, 100 Hz 3V 90
d
B
CMRR
C
o
m
m
o
n
m
o
d
e
r
e
j
e
c
t
i
o
n
ratio SD16GAINx = 32, Common-mode input signal:
VID =16mV,f
IN = 50 Hz, 100 Hz 3V 75
dB
AC PSRR AC power supply rejection
ratio SD16GAINx = 1, VCC =3V100 mV, fVCC =50Hz 3V 80 dB
XTCrosstalk SD16GAINx = 1, VID = 500 mV, fIN = 50 Hz, 100 Hz 3V <--100 dB
NOTE 1: The following voltages were applied to the SD16_A inputs:
VIN,A+(t) = 0V + VPP/2 sin(2fIN t)
VIN,A--(t) = 0V -- VPP/2 sin(2fIN t)
resulting in a differential voltage of Vdiff =V
IN,A+(t) -- VIN,A--(t) = VPP sin(2fIN t)
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
56 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
typical characteristics -- SD16_A SINAD performance over OSR
OSR
50.0
55.0
60.0
65.0
70.0
75.0
80.0
85.0
90.0
95.0
100.0
10.00 100.00 1000.00
SINAD -- dB
Figure 26. SINAD performance over OSR, fSD16 = 1 MHz, SD16REFON = 1, SD16GAINx = 1
SD16_A, temperature sensor and built--in VCC sense
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
TCSensor Sensor temperature
coefficient 1.18 1.32 1.46 mV/K
VOffset,sensor Sensor offset voltage --100 100 mV
S
t
t
l
t
Temperature sensor voltage at TA=85C3V 435 475 515
VSensor
Sensor output voltage
(
s
e
e
N
o
t
e
2
)
Temperature sensor voltage at TA=25C3V 355 395 435 mV
V
S
e
n
s
o
r
(
see
N
o
t
e
2
)
Temperature sensor voltage at TA=0C3V 320 360 400
m
V
VCC,Sense VCC divider at input 5 fSD16 = 1 MHz, SD16OSRx = 256, SD16REFON = 1 0.08 1/11 0.1 VCC
RSource,VCC Source resistance of
VCC divider at input 5 20 k
NOTES: 1. The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ =TC
Sensor ( 273 + T [C] ) + VOffset,sensor [mV]
2. Results based on characterization and/or production test, not TCSensor or VOffset,sensor.
Measured with fSD16 = 1 MHz, SD16OSRx = 256, SD16REFON = 1.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
57
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, built-in voltage reference
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VREF Internal reference
voltage SD16REFON = 1, SD16VMIDON = 0 3V 1.14 1.20 1.26 V
IREF Reference supply
current SD16REFON = 1, SD16VMIDON = 0 3V 175 260 A
TC Temperature coefficient SD16REFON = 1, SD16VMIDON = 0 (see Note 1) 3V 18 50 ppm/C
CREF VREF load capacitance SD16REFON = 1, SD16VMIDON = 0 (see Note 2) 100 nF
ILOAD VREF(I) maximum load
current SD16REFON = 1, SD16VMIDON = 0 3V 200 nA
tON Turn-on time SD16REFON = 0-->1, SD16VMIDON = 0,
CREF = 100nF 3V 5ms
DC PSR DC power supply
rejection VREF/VCC
SD16REFON = 1, SD16VMIDON = 0,
VCC = 2.5 V to 3.6 V 100 uV/V
NOTES: 1. Calculated using the box method: (MAX(-40...85C) -- MIN(-40...85C)) / MIN(--40...85C) / (85C--(-40C))
2. There is no capacitance required on VREF
. However, a capacitance of at least 100 nF is recommended to reduce any reference
voltage noise.
SD16_A, reference output buffer
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VREF,BUF Reference buffer output
voltage SD16REFON = 1, SD16VMIDON = 1 3V 1.2 V
IREF,BUF
Reference supply +
reference output buffer
quiescent current
SD16REFON = 1, SD16VMIDON = 1 3V 385 600 A
CREF(O) Required load
capacitance on VREF SD16REFON = 1, SD16VMIDON = 1 470 nF
ILOAD,Max Maximum load current
on VREF SD16REFON = 1, SD16VMIDON = 1 3V 1mA
Maximum voltage
variation vs load current |ILOAD|=0to1mA 3V -- 1 5 +15 mV
tON Turn-on time SD16REFON = 0-->1, SD16VMIDON = 0-->1,
CREF = 470nF 3V 100 s
SD16_A, external reference input
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VREF(I) Input voltage range SD16REFON = 0 3V 1.0 1.25 1.5 V
IREF(I) Input current SD16REFON = 0 3V 50 nA
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
58 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
flash memory
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VCC(PGM/
ERASE) Program and erase supply voltage 2.2 3.6 V
fFTG Flash timing generator frequency 257 476 kHz
IPGM Supply current from VCC during program 2.2 V/3.6 V 3 5 mA
IERASE Supply current from VCC during erase 2.2 V/3.6 V 3 7 mA
tCPT Cumulative program time (see Note 1) 2.2 V/3.6 V 10 ms
tCMErase Cumulative mass erase time 2.2 V/3.6 V 20 ms
Program/Erase endurance 104105cycles
tRetention Data retention duration TJ=25C100 years
tWord Word or byte program time 30 tFTG
tBlock, 0 Block program time for 1st byte or word 25 tFTG
tBlock, 1-63 Block program time for each additional byte or word
s
e
e
N
o
t
e
2
18 tFTG
tBlock, End Block program end-sequence wait time seeNote2 6 tFTG
tMass Erase Mass erase time 10593 tFTG
tSeg Erase Segment erase time 4819 tFTG
fMCLK,MGR MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4.MGR1 = 1) 0 1 MHz
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. These values are hardwired into the Flash Controller’s state machine (tFTG =1/f
FTG).
RAM
PARAMETER TEST CONDITIONS MIN MAX UNIT
V(RAMh) RAM retention supply voltage (see Note 1) CPU halted 1.6 V
NOTE 1: This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
JTAG interface
PARAMETER TEST
CONDITIONS VCC MIN TYP MAX UNIT
f
T
C
K
i
n
p
t
f
r
e
q
e
n
c
S
e
e
N
o
t
e
1
2.2 V 0 5 MHz
f
TCK TCK input
f
requency See Note 1 3V 010 MHz
RInternal Internal pullup resistance on TMS, TCK, TDI/TCLK SeeNote2 2.2 V/ 3 V 25 40 90 k
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG fuse (see Note 1)
PARAMETER TEST
CONDITIONS VCC MIN NOM MAX UNIT
VCC(FB) Supply voltage during fuse-blow condition TA=25C2.5 V
VFB Voltage level on TDI/TCLK for fuse-blow: F versions 6 7 V
IFB Supply current into TDI/TCLK during fuse blow 100 mA
tFB Time to blow fuse 1ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/test and emulation features is possible. The JTAG block is switched
to bypass mode.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
59
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics
Port P1, P1.0 to P1.5, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P1SEL.x
1
0
P1DIR.x
P1IN.x
P1IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P1OUT.x
Interrupt
Edge
Select
Q
EN
Set
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
1
0
DVSS
DVCC
P1REN.x
DVSS
1
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
60 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P1 (P1.0 to P1.5) pin functions
P
I
N
N
A
M
E
(
P
1
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P1.
X
)
X
FUNCTION P1DIR.x P1SEL.x
P1.0/TA0 0P1.0 (I/O) I: 0, O: 1 0
/
Timer_A3.CCI0A 0 1
Timer_A3.TA0 1 1
P1.1/TA0/MCLK 1P1.1 (I/O) I: 0, O: 1 0
/
/
Timer_A3.CCI0B 0 1
MCLK 1 1
P1.2/TA1 2P1.2 (I/O) I: 0, O: 1 0
/
Timer_A3.CCI1A 0 1
Timer_A3.TA1 1 1
P1.3/ 3P1.3 (I/O) I: 0, O: 1 0
/
TBOUTH/SVSOUT Timer_B7.TBOUTH 0 1
SVSOUT 1 1
P1.4/TBCLK/SMCLK 4P1.4 (I/O) I: 0, O: 1 0
/
/
Timer_B7.TBCLK 0 1
SMCLK 1 1
P1.5/TACLK/ACLK 5P1.5 (I/O) I: 0, O: 1 0
/
/
Timer_A3.TACLK 0 1
ACLK 1 1
NOTES: 1. X: Don’t care
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
61
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P1, P1.6 and P1.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P1SEL.x
1
0
P1DIR.x
P1IN.x
P1IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P1OUT.x
Interrupt
Edge
Select
Q
EN
Set
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x
P1.6/UCA1TXD/UCA1SIMO
P1.7/UCA1RXD/UCA1SOMI
1
0
DVSS
DVCC
P1REN.x
1
USCI Direction
Control
DVSS
Port P1 (P1.6 and P1.7) pin functions
P
I
N
N
A
M
E
(
P
1
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P1.
X
)
X
FUNCTION P1DIR.x P1SEL.x
P1.6/ 4P1.6 (I/O) I: 0, O: 1 0
/
UCA1TXD/UCA1SIMO UCA1TXD/UCA1SIMO (see Note 1, 2) X 1
P1.7/ 5P1.7 (I/O) I: 0, O: 1 0
/
UCA1RXD/UCA1SOMI UCA1RXD/UCA1SOMI (see Note 1, 2) X 1
NOTES: 1. X: Don’t care
2. The pin direction is controlled by the USCI module.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
62 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P2, P2.0 to P2.5, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P2SEL.x
1
0
P2DIR.x
P2IN.x
P2IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P2OUT.x
Interrupt
Edge
Select
Q
EN
Set
P2SEL.x
P2IES.x
P2IFG.x
P2IE.x
P2.0/UCB1STE/UCA1CLK
P2.1/UCB1SIMO/UCB1SDA
P2.2/UCB1SOMI/UCB1SCL
P2.3/UCB1CLK/UCA1STE
P2.4/UCA0TXD/UCA0SIMO
P2.5/UCA0RXD/UCA0SOMI
1
0
DVSS
DVCC
P2REN.x
1
USCI Direction
Control
CAPD.x
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
63
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P2 (P2.0 to P2.5) pin functions
P
I
N
N
A
M
E
(
P
2
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P2.
X
)
X
FUNCTION P2DIR.x P2SEL.x CAPD.x
P2.0/ 4P2.0 (I/O) I: 0, O: 1 0 0
/
UCB1STE/UCA1CLK UCB1STE/UCA1CLK (see Note 1, 2, 3) X 1 0
Input buffer disabled (see Note 6) X X 1
P2.1/ 4P2.1 (I/O) I: 0, O: 1 0 0
/
UCB1SIMO/UCB1SDA UCB1SIMO/UCB1SDA (see Note 1, 2, 4) X 1 0
Input buffer disabled (see Note 6) X X 1
P2.2/ 4P2.2 (I/O) I: 0, O: 1 0 0
/
UCB1SOMI/UCB1SCL UCB1SOMI/UCB1SCL (see Note 1, 2, 4) X 1 0
Input buffer disabled (see Note 6) X X 1
P2.3/ 4P2.3 (I/O) I: 0, O: 1 0 0
/
UCB1CLK/UCA1STE UCB1CLK/UCA1STE (see Note 1, 2, 5) X 1 0
Input buffer disabled (see Note 6) X X 1
P2.4/ 4P2.4 (I/O) I: 0, O: 1 0 0
/
UCA0TXD/UCA0SIMO UCA0TXD/UCA0SIMO (see Note 1, 2) X 1 0
Input buffer disabled (see Note 6) X X 1
P2.5/ 5P2.5 (I/O) I: 0, O: 1 0 0
/
UCA0RXD/UCA0SOMI UCA0RXD/UCA0SOMI (see Note 1, 2) X 1 0
Input buffer disabled (see Note 6) X X 1
NOTES: 1. X: Don’t care
2. The pin direction is controlled by the USCI module.
3. UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output USCI_B1 will be
forced to 3-wire SPI mode even if 4-wire SPI mode is selected.
4. In case the I2C functionality is selected the output drives only the logical 0 to VSS level.
5. UCB1CLK function takes precedence over UCA1STE function. If the pin is required as UCB1CLK input or output USCI_A1 will be
forced to 3-wire SPI mode even if 4-wire SPI mode is selected.
6. Setting the CAPD.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying
analog signals.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
64 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P2, P2.6 and P2.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P2SEL.x
1
0
P2DIR.x
P2IN.x
P2IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P2OUT.x
Interrupt
Edge
Select
Q
EN
Set
P2SEL.x
P2IES.x
P2IFG.x
P2IE.x
P2.6/CA0
P2.7/CA1
1
0
DVSS
DVCC
P2REN.x
CAPD.x
Pad Logic
From Comparator_A
To Comparator_A
1
(internal signal)
Port P2 (P2.6 and P2.7) pin functions
P
I
N
N
A
M
E
(
P
2
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P2.
X
)
X
FUNCTION P2DIR.x P2SEL.x CAPD.x
P2.6/CA0 6P2.6 (I/O) I: 0, O: 1 0 0
/
N/A 0 1 0
DVSS 1 1 0
CA0(seeNote3) X X 1
P2.7/CA1 7P2.7 (I/O) I: 0, O: 1 0 0
/
N/A 0 1 0
DVSS 1 1 0
CA1(seeNote3) X X 1
NOTES: 1. X: Don’t care
2. N/A: Not available or not applicable.
3. Setting the CAPD.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying
analog signals.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
65
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P3, P3.0 to P3.3, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P3SEL.x
1
0
P3DIR.x
P3IN.x
D
EN
Module X IN
1
0
Module X OUT
P3OUT.x
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
1
0
DVSS
DVCC
P3REN.x
Pad Logic
1
USCI Direction
Control
DVSS
Port P3 (P3.0 to P3.3) pin functions
P
I
N
N
A
M
E
(
P
3
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P3.
X
)
X
FUNCTION P3DIR.x P3SEL.x
P3.0/ 0P3.0 (I/O) I: 0, O: 1 0
/
UCA0CLK/UCB0STE UCA0CLK/UCB0STE (see Notes 1, 2, 3) X 1
P3.1/
U
C
B
0
S
I
M
O
/
1P3.1 (I/O) I: 0, O: 1 0
U
C
B0
S
IM
O
/
UCB0SDA UCB0SIMO/UCB0SDA (see Notes 1, 2, 4) X 1
P3.2/
U
C
B
0
S
O
M
I
/
2P3.2 (I/O) I: 0, O: 1 0
U
C
B0
S
O
MI
/
UCB0SCL UCB0SOMI/UCB0SCL (see Notes 1, 2, 4) X 1
P3.3/ 3P3.3 (I/O) I: 0, O: 1 0
/
UCB0CLK/UCA0STE UCB0CLK/UCA0STE (see Notes 1, 2, 5) X 1
NOTES: 1. X: Don’t care
2. The pin direction is controlled by the USCI module.
3. UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output USCI_B0 will be
forced to 3-wire SPI mode even if 4-wire SPI mode is selected.
4. In case the I2C functionality is selected the output drives only the logical 0 to VSS level.
5. UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output USCI_A0 will be
forced to 3-wire SPI mode even if 4-wire SPI mode is selected.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
66 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P3, P3.4, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P3SEL.4
1
0
P3DIR.4
P3IN.4
D
EN
Module X IN
1
0
Module X OUT
P3OUT.4
P3.4/TA2/S39
1
0
DVSS
DVCC
P3REN.4
Pad Logic
LCDS36
Segment S39
1
Port P3 (P3.4) pin functions
P
I
N
N
A
M
E
(
P
3
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P3.
X
)
X
FUNCTION P3DIR.x P3SEL.x LCDS36
P3.4/TA2/S39 4P3.4 (I/O) I: 0, O: 1 0 0
/
/
Timer_A3.CCI2A 010
Timer_A3.TA2 110
S39 X X 1
NOTES: 1. X: Don’t care
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
67
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P3, P3.5 to P3.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P3SEL.x
1
0
P3DIR.x
P3IN.x
D
EN
Module X IN
1
0
Module X OUT
P3OUT.x
P3.5/TB0/S38
P3.6/TB1/S37
P3.7/TB2/S36
1
0
DVSS
DVCC
P3REN.x
1
P1DIR.3
P1SEL.3
P1.3/TBOUTH/SVSOUT
Timer_B Output Tristate Logic
Pad Logic
LCDS36
Segment Sz
Port P3 (P3.5 to P3.7) pin functions
P
I
N
N
A
M
E
(
P
3
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P3.
X
)
X
FUNCTION P3DIR.x P3SEL.x LCDS36
P3.5/TB0/S38 5P3.5 (I/O) I: 0, O: 1 0 0
/
/
Timer_B3.CCI0A and Timer_B3.CCI0B 0 1 0
Timer_B3.TB0 (see Note 2) 1 1 0
S38 X X 1
P3.6/TB1/S37 6P3.6 (I/O) I: 0, O: 1 0 0
/
/
Timer_B3.CCI1A and Timer_B3.CCI1B 0 1 0
Timer_B3.TB1 (see Note 2) 1 1 0
S37 X X 1
P3.7/TB2/S36 7P3.7 (I/O) I: 0, O: 1 0 0
/
/
Timer_B3.CCI2A and Timer_B3.CCI2B 0 1 0
Timer_B3.TB3 (see Note 2) 1 1 0
S36 X X 1
NOTES: 1. X: Don’t care
2. Setting TBOUTH causes all Timer_B outputs to be set to high impedance.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
68 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P4, P4.0 and P4.1, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P4SEL.x
1
0
P4DIR.x
P4IN.x
D
EN
Module X IN
1
0
Module X OUT
P4OUT.x
P4.0/CAOUT/S35
P4.1/DMAE0/S34
1
0
DVSS
DVCC
P4REN.x
1
Pad Logic
LCDS32
Segment Sz
Port P4 (P4.0 and P4.1) pin functions
P
I
N
N
A
M
E
(
P
4
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P4.
X
)
X
FUNCTION P4DIR.x P4SEL.x LCDS32
P4.0/CAOUT/S35 0P4.0 (I/O) I: 0, O: 1 0 0
/
/
N/A 0 1 0
CAOUT 110
S35 X X 1
P4.1/DMAE0/S34 1P4.1 (I/O) I: 0, O: 1 0 0
/
/
DMAE0 010
DVSS 110
S34 X X 1
NOTES: 1. X: Don’t care
2. N/A: Not available or not applicable.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
69
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P4, P4.2 to P4.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P4SEL.x
1
0
P4DIR.x
P4IN.x
D
EN
Module X IN
1
0
Module X OUT
P4OUT.x
P4.2/S33
P4.3/S32
P4.4/S31
P4.5/S30
P4.6/S29
P4.7/S28
1
0
DVSS
DVCC
P4REN.x
Pad Logic
LCDS...
Segment Sz
1
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
70 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P4 (P4.2 and P4.3) pin functions
P
I
N
N
A
M
E
(
P
4
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P4.
X
)
X
FUNCTION P4DIR.x P4SEL.x LCDS32
P4.2/S33 2P4.2 (I/O) I: 0, O: 1 0 0
/
N/A 0 1 0
DVSS 1 1 0
S33 X X 1
P4.3/S32 3P4.3 (I/O) I: 0, O: 1 0 0
/
N/A 0 1 0
DVSS 1 1 0
S32 X X 1
NOTES: 1. X: Don’t care
2. N/A: Not available or not applicable.
Port P4 (P4.4 to P4.7) pin functions
P
I
N
N
A
M
E
(
P
4
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P4.
X
)
X
FUNCTION P4DIR.x P4SEL.x LCDS28
P4.4/S31 4P4.4 (I/O) I: 0, O: 1 0 0
/
N/A 0 1 0
DVSS 1 1 0
S31 X X 1
P4.5/S30 5P4.5 (I/O) I: 0, O: 1 0 0
/
N/A 0 1 0
DVSS 1 1 0
S30 X X 1
P4.6/S29 5P4.6 (I/O) I: 0, O: 1 0 0
/
N/A 0 1 0
DVSS 1 1 0
S29 X X 1
P4.7/S28 5P4.7 (I/O) I: 0, O: 1 0 0
/
N/A 0 1 0
DVSS 1 1 0
S28 X X 1
NOTES: 1. X: Don’t care
2. N/A: Not available or not applicable.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
71
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P5, P5.0, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P5SEL.0
1
0
P5DIR.0
P5IN.0
1
0
DVSS
P5OUT.0
P5.0/SVSIN
1
0
DVSS
DVCC
P5REN.0
Pad Logic
To SVS
1
SVSCTL.VLDx=15
Port P5 (P5.0) pin functions
P
I
N
N
A
M
E
(
P
5
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P5.
X
)
X
FUNCTION P5DIR.x P5SEL.x
P5.0/SVSIN 0P5.0 (I/O) (see Note 1) I: 0, O: 1 0
/
SVSIN (see Notes 1 and 3) X 1
NOTES: 1. X: Don’t care
2. N/A: Not available or not applicable.
3. Setting the P5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. To enable the SVSIN function the SVS input also needs to be selected in the SVS module by setting the
VLDx bits to 15.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
72 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P5, P5.1 to P5.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P5SEL.x
1
0
P5DIR.x
P5IN.x
1
0
DVSS
P5OUT.x
P5.1/COM0
P5.2/COM1
P5.3/COM2
P5.4/COM3
P5.5/R03
P5.6/LCDREF/R13
P5.7/R23
1
0
DVSS
DVCC
P5REN.x
Pad Logic
LCD Signal
1
Port P5 (P5.1 to P5.7) pin functions
P
I
N
N
A
M
E
(
P
5
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P5.
X
)
X
FUNCTION P5DIR.x P5SEL.x
P5.1/COM0 2P5.2 (I/O) I: 0, O: 1 0
/
COM0 (see Note 2) X 1
P5.2/COM1 2P5.2 (I/O) I: 0, O: 1 0
/
COM1 (see Note 2) X 1
P5.3/COM2 3P5.3 (I/O) I: 0, O: 1 0
/
COM2 (see Note 2) X 1
P5.4/COM3 4P5.4 (I/O) I: 0, O: 1 0
/
COM3 (see Note 2) X 1
P5.5/R03 5P5.5 (I/O) I: 0, O: 1 0
/
R03(seeNote2) X 1
P5.6/LCDREF/R13 6P5.6 (I/O) I: 0, O: 1 0
/
/
R13 or LCDREF (see Notes 2 and 3) X 1
P5.7/R23 7P5.7 (I/O) I: 0, O: 1 0
/
R23(seeNote2) X 1
NOTES: 1. X: Don’t care
2. Setting the P5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
3. External reference for the LCD_A charge pump is applied when VLCDREFx = 01. Otherwise R13 is selected.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
73
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P7 to port P10, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
PySEL.x
1
0
PyDIR.x
PyIN.x
D
EN
Module X IN
1
0
Module X OUT
PyOUT.x
Py.x/Sz
1
0
DVSS
DVCC
PyREN.x
Pad Logic
LCDS...
Segment Sz
1
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
74 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P7 (P7.0 to P7.3) pin functions
P
I
N
N
A
M
E
(
P
7
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P7.
X
)
X
FUNCTION P7DIR.x P7SEL.x LCDS24
P7.0/S27 0P7.0 (I/O) I: 0, O: 1 0 0
/
N/A 0 1 0
DVSS 1 1 0
S27 X X 1
P7.1/S26 1P7.1 (I/O) I: 0, O: 1 0 0
/
N/A 0 1 0
DVSS 1 1 0
S26 X X 1
P7.2/S25 2P7.2 (I/O) I: 0, O: 1 0 0
/
N/A 0 1 0
DVSS 1 1 0
S25 X X 1
P7.3/S24 3P7.3 (I/O) I: 0, O: 1 0 0
/
N/A 0 1 0
DVSS 1 1 0
S24 X X 1
NOTES: 1. X: Don’t care
2. N/A: Not available or not applicable.
Port P7 (P7.4 to P7.7) pin functions
P
I
N
N
A
M
E
(
P
7
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P7.
X
)
X
FUNCTION P7DIR.x P7SEL.x LCDS20
P7.4/S23 4P7.4 (I/O) I: 0, O: 1 0 0
/
N/A 0 1 0
DVSS 1 1 0
S23 X X 1
P7.5/S22 5P7.5 (I/O) I: 0, O: 1 0 0
/
N/A 0 1 0
DVSS 1 1 0
S22 X X 1
P7.6/S21 6P7.6 (I/O) I: 0, O: 1 0 0
/
N/A 0 1 0
DVSS 1 1 0
S21 X X 1
P7.7/S20 7P7.7 (I/O) I: 0, O: 1 0 0
/
N/A 0 1 0
DVSS 1 1 0
S20 X X 1
NOTES: 1. X: Don’t care
2. N/A: Not available or not applicable.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
75
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P8 (P8.0 to P8.3) pin functions
P
I
N
N
A
M
E
(
P
8
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P8.
X
)
X
FUNCTION P8DIR.x P8SEL.x LCDS16
P8.0/S19 0P8.0 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S19 X X 1
P8.1/S18 1P8.0 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S18 X X 1
P8.2/S17 2P8.2 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S17 X X 1
P8.3/S16 3P8.3 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S16 X X 1
NOTES: 1. X: Don’t care
2. N/A: Not available or not applicable.
Port P8 (P8.4 to P8.7) pin functions
P
I
N
N
A
M
E
(
P
8
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P8.
X
)
X
FUNCTION P8DIR.x P8SEL.x LCDS12
P8.4/S15 4P8.4 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S15 X X 1
P8.5/S14 5P8.5 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S14 X X 1
P8.6/S13 6P8.6 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S13 X X 1
P8.7/S12 7P8.7 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S12 X X 1
NOTES: 1. X: Don’t care
2. N/A: Not available or not applicable.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
76 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P9 (P9.0 to P9.3) pin functions
P
I
N
N
A
M
E
(
P
9
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P9.
X
)
X
FUNCTION P9DIR.x P9SEL.x LCDS8
P9.0/S11 0P9.0 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S11 X X 1
P9.1/S10 1P9.1 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S10 X X 1
P9.2/S9 2P9.2 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S9 X X 1
P9.3/S8 3P9.3 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S8 X X 1
NOTES: 1. X: Don’t care
2. N/A: Not available or not applicable.
Port P9 (P9.4 to P9.7) pin functions
P
I
N
N
A
M
E
(
P
9
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P9.
X
)
X
FUNCTION P9DIR.x P9SEL.x LCDS4
P9.4/S7 4P9.4 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S7 X X 1
P9.5/S6 5P9.5 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S6 X X 1
P9.6/S5 6P9.6 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S5 X X 1
P9.7/S4 7P9.7 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S4 X X 1
NOTES: 1. X: Don’t care
2. N/A: Not available or not applicable.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
77
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Port P10 (P10.0 to P10.3) pin functions
P
I
N
N
A
M
E
(
P
1
0
X
)
X
F
U
N
C
T
I
O
N
CONTROL BITS / SIGNALS
PIN N
A
ME (P10.
X
)
X
FUNCTION P10DIR.x P10SEL.x LCDS0
P10.0/S3 0P10.0 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S3 X X 1
P10.1/S2 1P10.1 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S2 X X 1
P10.2/S1 2P10.2 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S1 X X 1
P10.3/S0 3P10.3 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S0 X X 1
NOTES: 1. X: Don’t care
2. N/A: Not available or not applicable.
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
78 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
JTAG pins (TMS, TCK, TDI/TCLK, TDO/TDI), input/output with Schmitt trigger or output
TDI
TDO
TMS
TDI/TCLK
TDO/TDI
Controlled
by JTAG
TCK
TMS
TCK
DVCC
Controlled by JTAG
Test
JTAG
and
Emulation
Module
DVCC
DVCC
Burn and Test
Fuse
RST/NMI
G
D
S
U
G
D
S
U
TCK
Tau ~ 50 ns
Brownout
Controlled by JTAG
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
79
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current (I(TF)) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 27). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition). The JTAG pins are terminated internally and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
I(TF)
ITDI/TCLK
Figure 27. Fuse Check Mode Current MSP430F471x3/6/7
MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
80 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Data Sheet Revision History
LITERATURE
NUMBER SUMMARY
SLAS626 Product Preview release
SLAS626A Production Data release
SLAS626B Added MSP430F471x3, MSP430F47126, and MSP430F47127 devices
SLAS626C Corrected pin numbers in BSL function table (page 16)
Changed limits on td(SVSon) parameter (page 38)
NOTE: Page and figure numbers refer to the respective document revision and may differ in other revisions.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Mar-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430F47126IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47126IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47127IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47127IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47163IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47163IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47166IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47166IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47167IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47167IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47173IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47173IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47176IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47176IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47177IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47177IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47183IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com 1-Mar-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430F47183IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47186IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47186IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47187IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47187IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47193IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47193IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47196IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47196IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47197IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F47197IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Mar-2011
Addendum-Page 3
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
MSP430F47163IPZR LQFP PZ 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2
MSP430F47173IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2
MSP430F47183IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2
MSP430F47193IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430F47163IPZR LQFP PZ 100 1000 367.0 367.0 45.0
MSP430F47173IPZR LQFP PZ 100 1000 367.0 367.0 45.0
MSP430F47183IPZR LQFP PZ 100 1000 367.0 367.0 45.0
MSP430F47193IPZR LQFP PZ 100 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK
4040149/B 11/96
50
26 0,13 NOM
Gage Plane
0,25
0,45
0,75
0,05 MIN
0,27
51
25
75
1
12,00 TYP
0,17
76
100
SQ
SQ
15,80
16,20
13,80
1,35
1,45
1,60 MAX
14,20
0°–7°
Seating Plane
0,08
0,50 M
0,08
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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