Features
•Read Access Time – 200 ns
•Automatic Page Write Operation
– Internal Address and Data Latches for 256 Bytes
– Internal Control Timer
•Fast Write Cycle Time
– Page Write Cycle Time – 10 ms Maximum
– 1 to 256 Byte Page Write Operation
•Low Power Dissipation
– 50 mA Active Current
•Hardware and Software Data Protection
•DATA Polling for End of Write Detection
•High Reliability CMOS Technology
– Endurance: 10,000 Cycles
– Data Retention: 10 Years
•Single 5V ± 10% Supply
•CMOS and TTL Compatible Inputs and Outputs
•JEDEC Approved Byte-Wide Pinout
1. Description
The AT28C040 is a high-performance electrically erasable and programmable read-
only memory (EEPROM). Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 200 ns with power dissipation of just 440 mW.
The AT28C040 is accessed like a static RAM for the read or write cycle without the
need for external components. The device contains a 256-byte page register to allow
writing of up to 256 bytes simultaneously. During a write cycle, the address and 1 to
256 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by Data Polling of I/O7. Once the end of a write cycle has been detected, a
new access for a read or write can begin.
Atmel's AT28C040 has additional features to ensure high quality and manufacturabil-
ity. The device utilizes internal error correction for extended endurance and improved
data retention characteristics. An optional software data protection mechanism is
available to guard against inadvertent writes. The device also includes an extra 256
bytes of EEPROM for device identification or tracking.
4-Megabit
(512K x 8)
Paged Parallel
EEPROMs
AT28C040
0542F–PEEPR–2/09
2
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AT28C040
2. Pin Configurations
2.1 44-lead LCC – Top View
Pin Name Function
A0 - A18 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
A12
A7
A6
A5
NC
NC
NC
A4
A3
A2
A1
A13
A8
A9
A11
NC
NC
NC
NC
OE
A10
CE
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
A0
I/O0
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
A15
A16
A18
NC
NC
NC
VCC
WE
NC
A17
A14
2.2 32-lead Flatpack – Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
3
0542F–PEEPR–2/09
AT28C040
3. Block Diagram
4. Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
4
0542F–PEEPR–2/09
AT28C040
5. Device Operation
5.1 Read
The AT28C040 is accessed like a static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their systems.
5.2 Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write
cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Once a byte write has been started, it will automati-
cally time itself to completion. Once a programming operation has been initiated and for the
duration of tWC, a read operation will effectively be a polling operation.
5.3 Page Write
The page write operation of the AT28C040 allows 1 to 256 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; the first byte written can then be followed by 1 to 255 additional
bytes. Each successive byte must be written within 150 μs (tBLC) of the previous byte. If the tBLC
limit is exceeded, the AT28C040 will cease accepting data and commence the internal program-
ming operation. All bytes during a page write operation must reside on the same page as
defined by the state of the A8 - A18 inputs. For each WE high to low transition during the page
write operation, A8 - A18 must be the same.
The A0 to A7 inputs specify which bytes within the page are to be written. The bytes may be
loaded in any order and may be altered within the same load period. Only bytes which are spec-
ified for writing will be written; unnecessary cycling of other bytes within the page does not occur.
5.4 Data Polling
The AT28C040 features Data Polling to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will result in the complement of the written
data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all
outputs, and the next write cycle may begin. Data Polling may begin at anytime during the write
cycle.
5.5 Toggle Bit
In addition to Data Polling, the AT28C040 provides another method for determining the end of a
write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-
gling and valid data will be read. Reading the toggle bit may begin at any time during the write
cycle.
5.6 Data Protection
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel® has incorporated both hardware and software features that will protect the
memory against inadvertent writes.
5
0542F–PEEPR–2/09
AT28C040
5.6.1 Hardware Protection
Hardware features protect against inadvertent writes to the AT28C040 in the following ways:
(a) VCC sense – if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on
delay – once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before
allowing a write: (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write
cycles; (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate
a write cycle.
5.6.2 Software Data Protection
A software controlled data protection feature has been implemented on the AT28C040. When
enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP
feature may be enabled or disabled by the user; the AT28C040 is shipped from Atmel with SDP
disabled.
SDP is enabled when the host system issues a series of three write commands; three specific
bytes of data are written to three specific addresses (refer to Software Data Protection Algo-
rithm). After writing the 3-byte command sequence and after tWC, the entire AT28C040 will be
protected against inadvertent write operations. It should be noted that once protected, the host
can still perform a byte or page write to the AT28C040. To do so, the same 3-byte command
sequence used to enable SDP must precede the data to be written.
Once set, SDP will remain active unless the disable command sequence is issued. Power transi-
tions do not disable SDP, and SDP will protect the AT28C040 during power-up and power-down
conditions. All command sequences must conform to the page write timing specifications. The
data in the enable and disable command sequences is not written to the device, and the
memory addresses used in the sequence may be written with data in either a byte or page write
operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will
start the internal write timers. No data will be written to the device; however, for the duration of
tWC, read operations will effectively be polling operations.
5.7 Device Identification
An extra 256 bytes of EEPROM memory are available to the user for device identification. By
raising A9 to 12V ± 0.5V and using address locations 7FF80H to 7FFFFH, the bytes may be writ-
ten to or read from in the same manner as the regular memory array.
5.8 Optional Chip Erase Mode
The entire device can be erased using a 6-byte software erase code. Please see Software Chip
Erase application note for details.
6
0542F–PEEPR–2/09
AT28C040
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
6. DC and AC Operating Range
AT28C040-20 Operation
Read Program
Operating Temperature (Case) Industrial -40°C - 85°C -40°C - 85°C
Extended -55°C - 125°C -40°C - 85°C
VCC Power Supply 5V ± 10% 5V ± 10%
7. Operating Modes
Mode CE OE WE I/O
Read VIL VIL VIH DOUT
Write(2) VIL VIH VIL DIN
Write Inhibit X X VIH
Write Inhibit X VIL X
Output Disable X VIH X High Z
8. DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC + 1V 10 µA
ILO Output Leakage Current VI/O = 0V to VCC 10 µA
ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 50 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 2.1 mA 0.45 V
VOH1 Output High Voltage IOH = -400 µA 2.4 V
VOH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V
7
0542F–PEEPR–2/09
AT28C040
10. AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE May be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
11. Input Test Waveforms and Measurement Level
tR, tF < 5 ns
12. Output Test Load
Note: 1. This parameter is characterized and is not 100% tested.
9. AC Read Characteristics
Symbol Parameter
AT28C040-20
UnitsMin Max
tACC Address to Output Delay 200 ns
tCE(1) CE to Output Delay 200 ns
tOE(2) OE to Output Delay 0 55 ns
tDF(3)(4) CE or OE to Output Float 0 55 ns
tOH Output Hold from OE, CE or Address, whichever occurred first 0 ns
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol Typ Max Units Conditions
CIN 410pFV
IN = 0V
COUT 812pFV
OUT = 0V
8
0542F–PEEPR–2/09
AT28C040
15. AC Write Waveforms
15.1 WE Controlled
15.2 CE Controlled
14. AC Write Characteristics
Symbol Parameter Min Max Units
tAS, tOES Address, OE Set-up Time 0 ns
tAH Address Hold Time 50 ns
tCS Chip Select Set-up Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Width (WE or CE)100ns
tDS Data Set-up Time 50 ns
tDH, tOEH Data, OE Hold Time 0 ns
9
0542F–PEEPR–2/09
AT28C040
17. Page Mode Write Waveforms(1)(2)
Notes: 1. A8 through A18 must specify the page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
16. Page Mode Characteristics
Symbol Parameter Min Max Units
tWC Write Cycle Time 10 ms
tAS Address Set-up Time 0 ns
tAH Address Hold Time 50 ns
tDS Data Set-up Time 50 ns
tDH Data Hold Time 0 ns
tWP Write Pulse Width 100 ns
tBLC Byte Load Cycle Time 150 μs
tWPH Write Pulse Width High 50 ns
10
0542F–PEEPR–2/09
AT28C040
18. Software Data
Protection Enable Algorithm(1)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Write Protect state will be activated at end of write
even if no other data is loaded.
3. Write Protect state will be deactivated at end of write
period even if no other data is loaded.
4. 1 to 256 bytes of data are loaded.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS
(4)
LOAD LAST BYTE
TO
LAST ADDRESS ENTER DATA
PROTECT STATE
WRITES ENABLED
(2)
19. Software Data
Protection Disable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 20
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS
(4)
LOAD LAST BYTE
TO
LAST ADDRESS
LOAD DATA 55
TO
ADDRESS 2AAA
EXIT DATA
PROTECT STATE
(3)
20. Software Protected Program Cycle Waveform(1)(2)(3)
Notes: 1. A0 - A14 must conform to the addressing sequence for the first 3 bytes as shown above.
2. After the command sequence has been issued and a page write operation follows, the page address inputs (A8 - A18) must
be the same for each high to low transition of WE (or CE).
3. OE must be high only when WE and CE are both low.
11
0542F–PEEPR–2/09
AT28C040
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
22. Data Polling Waveforms
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
24. Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
21. Data Polling Characteristics(1)
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay(2) ns
tWR Write Recovery Time 0 ns
23. Toggle Bit Characteristics(1)
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay(2) ns
tOEHP OE High Pulse 150 ns
tWR Write Recovery Time 0 ns
12
0542F–PEEPR–2/09
AT28C040
25. Ordering Information
Note: 1. SL703 requires testing to Mil-883 standards; SL703 is marked on the package.
25.1 Standard Packaging
tACC
(ns)
ICC (mA)
Ordering Code Package Operation RangeActive
200
50 AT28C040-20FI 32F Industrial
(-40° to 85°C)
AT28C040-20LI 44L
50 AT28C040-20FI SL703 32F Extended
(See DC and AC Operating Range Table)
AT28C040-20LI SL703 44L
Package Type
32F 32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack)
44L 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)
Options
Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
13
0542F–PEEPR–2/09
AT28C040
26. Packaging Information
26.1 32F – Flatpack
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
32F, 32-lead, Non-windowed, Ceramic Bottom-brazed
Flat Package (FlatPack) B
32F
10/21/03
Dimensions in Millimeters and (Inches).
Controlling dimension: Inches.
JEDEC Outline MO-115 AA
PIN #1 ID 9.40(0.370)
6.86(0.270)
0.51(0.020)
0.38(0.015)
1.27(0.050) BSC
1.14(0.045) MAX
3.05(0.120)
2.49(0.098)
1.14(0.045)
0.66(0.026)
1.83(0.072)
0.76(0.030)
10.36(0.408)
9.02(0.355)
0.18(0.007)
0.10(0.004)
12.40(0.488)
11.99(0.472)
21.08(0.830)
20.60(0.811)
14
0542F–PEEPR–2/09
AT28C040
26.2 44L – LCC
16.81(0.662)
16.26(0.640)
16.81(0.662)
16.26(0.640)
2.74(0.108)
2.16(0.085)
2.03(0.080)
1.40(0.055)
INDEX CORNER
0.635(0.025)
0.381(0.015) X 45˚
0.305(0.012)
0.178(0.007)RADIUS
0.737(0.029)
0.533(0.021)
1.02(0.040) X 45˚
PIN 1
1.40(0.055)
1.14(0.045)
2.41(0.095)
1.91(0.075)
2.16(0.085)
1.65(0.065)
12.70(0.500) BSC
1.27(0.050) TYP
12.70(0.500) BSC
Dimensions in Millimeters and (Inches)
Controlling dimension: Inches
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
44L, 44-pad (0.600" Wide), Non-windowed, Ceramic Lid, Leadless
Chip Carrier (LCC) A
44L
04/11/01
MIL-STD-1835 C-5
0542F–PEEPR–2/09
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