March 1999 Application Note 42043 ML4803 240W Off-Line Power Supply with PFC INTRODUCTION Included in this Application Note are a reference schematic, ML4803 design equations, the circuit layout, and parts list. The reference schematic demonstrates how the ML4803 can meet the requirements of a PFC corrected power supply for desktop computer applications. The design features include a low-cost single sided PCB with 240W of output power, a form factor compatible with desk top computer requirements, and line frequency harmonic content compliant with IEC1000-3-2. Electrical Specifications THEORY OF OPERATION PFC CONTROL CIRCUIT DESIGN The ML4803 Power Factor Control section uses an input current wave-shaping technique that senses the boost inductor current. It compares the inductor current downslope during the off-time of the main power switch with a ramp programmed by the PFC output voltage variation. When the two signals intersect the off-time is terminated and the on-time is initiated for the remainder of the cycle. Any line or load transients to the PFC will cause the output to either surge or dip below its regulated value. This will either increase or decrease the programmed ramp dv/dt, increasing or decreasing the offtime of the main power switch and compensating for load demand. Unity power factor is maintained because the sensed inductor current ramp is proportional to the input voltage. Internal Voltage Ramp Line voltage Line harmonic content Switching frequency POUT Regulation Ripple Efficiency @ 115VAC, 240W 85 to 265VAC IEC1000-3-2 67kHz 240W 0.1% 30mVRMS 85% The internal ramp current source is programmed by way of the VEAO signal voltage (see Figure 1). This current source is used to develop the internal ramp by charging the internal 30pF capacitor. Steady-state operation ensures that the VEAO signal is 5V. The frequency of the internal ramp is set to 67kHz. One-Pin Error Amp The ML4803 utilizes a one-pin voltage error amplifier in the PFC section (VEAO). The error amplifier is in reality a 35A current sink, which forces 35A through the output programming resistor. The nominal voltage of the VEAO signal is 5V and its range is from 4V to 6V. The boost 50 FF @ -55C TYP @ -55C 40 IRAMP (A) TYP @ ROOM TEMP TYP @ 155C 30 SS @ 155C 20 10 0 0 1 2 3 4 5 6 7 VEAO (V) Figure 1. Internal Ramp Current vs. VEAO REV. 1.0 10/25/2000 Application Note 75 PFC CONTROL CIRCUIT DESIGN (Continued) output voltage would be 400V for a 11.3M resistor to the boost output voltage and 5V steady-state at the VEAO pin. R12 + R13 = VBOOST - VEAO = IPGM (1) 400V - 5V = 113 . M 35A The IPGM variation over temperature and process is 4%. Adding an additional 2% variation in the programming resistor results in a total variation of approximately 6% in the PFC output voltage. This assumes a temperature coefficient of less than 200ppm for the programming resistance. This results in a spread of 377V to 426V in the PFC output voltage, requiring a PFC output capacitor rated at 450V. Voltage Loop Compensation The voltage loop bandwidth must be set to less than 120Hz to limit line current harmonic distortion. A typical crossover frequency is 30Hz. Equation 2 assumes that the pole capacitor (C15) in the compensation network dominates the error amp gain at the unity gain frequency. Equation 3 places a pole at the crossover frequency providing 45 of phase margin. Equation 4 places a zero a decade prior to the pole providing the necessary phase boost. Figure 3 displays a simplified schematic of the voltage control loop. Bode plots illustrating the overall gain and phase are shown in Figures 4 and 5. C15 = PIN b g RP x VBOOST x VEAO x C OUT x 2f 2 = (2) VOUT = 400V RP VC1 VEAO 4 RCOMP GATE OUTPUT + COMP C1 30pF CCOMP 35A - 5V R1 CZERO 3 ISENSE -4 VI SENSE Figure 2. ML4803 PFC Control 60 VO 40 20 VEAO IOUT 220F VEAO + RLOAD 667 330k 15nF ML4803 IVEAO 35A GAIN (dB) 11.3M ML4803 Power Stage Overall Gain Compensation Network Gain 0 -20 - 0.15F POWER STAGE -40 COMPENSATION -60 0.1 1 10 100 1000 FREQUENCY (Hz) Figure 3. Voltage Control Loop 2 Figure 4. Voltage Loop Gain REV. 1.0 10/25/2000 Application Note 75 PFC CONTROL CIRCUIT DESIGN 300 W a 113 . M x 400V x 0.5V x 220F x 2 x 30Hz R25 = f 2 (Continued) 16nF 1 = 2f x C15 (3) IPK = 1 = 330k 2 x 30Hz x 16nF POUT x 2 = VAC x (5) 240 x 2 = 5.3A 85V x 0.75 1 C8 = = f 2 x x R25 10 (4) 1 = 0.16F 2 x 3Hz x 330k D= VOUT - VIN = VOUT (6) 400 - 85 x 2 = 0.7 400 PFC Start-Up and Soft Start During steady state operation VEAO draws 35A. At startup the internal current mirror, which sinks this current, is defeated until VCC reaches 12V. This forces the PFC error voltage (VEAO) to 12V at the time that the IC is enabled (see Figure 6). With leading edge modulation, 6V or more of VEAO signal forces zero duty in the PFC output. When designing the external compensation components and the VCC supply circuits VEAO must not be prevented from reaching 6V prior to VCC reaching 12V in the turn-on sequence. This will guarantee the PFC stage will enter soft start at turn-on. Once VCC reaches 12V the VEAO current sink is enabled. The VEAO compensation components are then discharged by way of the 35A current sink until the steady-state operating point is reached. L= VRMS x 2 x D = 0.2IPK x f (7) 85V x 2 x 0.7 = 1134H 0.2 x 5.3A x 70kHz PFC Output Capacitor The dominant consideration in selecting the output capacitor is providing sufficient holdup time at the output to sustain output regulation in the event the AC line drops out for one cycle. The voltage to which the boost cap is allowed to drop is limited by the maximum PWM duty cycle and the main transformer turns ratio (see Transformer section, following). 2POUT x t HOLDUP = C1 = 2 V1 - V22 PFC POWER STAGE DESIGN PFC Inductor The boost inductor value should ensure that the ripple current is limited to roughly 20% of the peak input current 0 at low line voltage. This provides for continuous conduction throughout much of the line cycle with sufficient ramp slope to trip the overcurrent comparator at the trailing edge of the "ON" pulse. Power Stage Overall Gain Compensation Network Gain (8) 2 x 240W x 15ms 0.9 = 190F (380V )2 - (320V )2 VCC 50 PHASE () 0 VEAO 0 100 VOUT 0 150 VBOOST 200 0.1 1 10 100 FREQUENCY (Hz) Figure 5. Voltage Loop Phase REV. 1.0 10/25/2000 1000 0 200ms/Div. Figure 6. PFC Soft Start 3 Application Note 75 PFC POWER STAGE DESIGN (Continued) harmonic distortion in the input AC current, it should kept to a minimum by this low-pass network. In Discontinous Conduction Mode (DCM) the input current wave shaping technique used by the ML4803 can cause the input current to run away, forcing the PFC output to increase until the VCCOVP point is reached. In order for the PWM technique to work properly under DCM, the programmed ramp must meet the boost inductor current down slope at zero amps. Assuming the programmed ramp is zero under light load, the off time will be terminated once the inductor current reaches zero. Subsequently, the PFC gate drive would be initiated eliminating any necessary deadtime needed for the DCM mode. The problem is resolved by adding an offset voltage to the current sense signal, which forces the duty cycle to zero at light loads. The offset prevents the PFC from operating in the Discontinous Conduction Mode (DCM) and forces pulse skipping from Continuous Conduction Mode (CCM) to no duty, avoiding the DCM problem altogether. External filtering of the current sense signal helps to smooth out the signal, expanding the operating range somewhat into the DCM range. This should be done carefully as the filtering reduces the bandwidth of the signal feeding the pulse-by-pulse current limit information. Figure 7 displays the circuit used to provide offset to the ISENSE pin under light load conditions. It adds a negative offset to the ISENSE pin that is inversely proportional to the PFC pulse width, preventing excessive input current under light load conditions. Components C23 and CR16 offset the PFC gate drive by -15V, while the subsequent lowpass network averages the offset square wave. The net effect is a negative voltage summed with the input current sense that increases as the PFC pulse width decreases. Figure 8 illustrates how ILIMIT vs. duty cycle varies with the PFC gate drive offset signal. The 120Hz component of the PFC gate drive is attenuated by more than -50dB at the ISENSE pin. Because this 120Hz component added to the ISENSE input will increase the To select the PFC RSENSE value, use a peak current that is 120% of that found in Equation 5. R3 = PFC and PWM Gate Drive The peak current rating of the PFC and PWM gate drive outputs is 1A. A 36 gate drive resistor is used to drive two MOSFETs in parallel and limit the gate drive peak current to less than 1A. The charge required to elevate the gate of the IRF840 to 15V is taken from the manufacturer's data sheet in order to estimate the gate drive turn-on time. Estimating the current as a constant allows the approximate time to be derived from Equation 10. Given the switching frequency, the average gate current drawn from VCC can be calculated from Equation 11. Since a typical carbon film resistor is only capable of a peak power of 4 times its average, rated power, a 1/4W resistor is limited to 1W peak. With a peak current of 0.416A in a 36 resistor, the peak power is 6.23W, well in excess of the 1W limitation. For this reason carbon composition resistors are typically used for gate drive applications. t QGATE QGATE = = VCC IPK RGATE R4 1k R28 20k PFC GATE CR16 1N4148 C22 1F R19 10k C5 8.2nF R3 .015 3W (10) 60nC 60nC = = 144ns 15V 0.416A 36 ILIMIT (A) R29 20k (9) 1V = 0.15 12 . x 5.3A ISENSE C23 0.01F VLIMIT = 120% x IPK 6.8 0 6.6 -0.05 6.4 -0.10 6.2 -0.15 6.0 -0.20 VOFFSET ILIMIT ILIMITMOD 5.8 VCC RTN 5.6 0 20 40 60 80 OFFSET (V) PFC Current Sense Resistor -0.25 -0.30 100 DUTY CYCLE (%) Figure 7. ISENSE Offset Circuit 4 Figure 8. ISENSE and VOFFSET Over Duty Cycle REV. 1.0 10/25/2000 Application Note 75 PFC POWER STAGE DESIGN (Continued) ICCDRIVE = QGATE x fS = (11) 60nC x 70kHz = 4.2mA The high-side gate drive transformer magnetizing current can be estimated from Equation 12. VCC = = 8 x fS x LMAG IAVG (12) 15V = 60mA 8 x 70kHz x 450H The total ICC due to gate drive can now be estimated from the sum of all of the above. PWM POWER STAGE DESIGN Output Filter VOUT + VD = VBOOST x N (13) 12V + 0.5V = 0.376 400V x 0.083 L OUT bV = OUT g a f= + VD x 1- D IOUT x 20% x fS (14) (17) N= VOUT + VD = VHU x D MAX x k (18) N= 12V + 05 .V = 0087 . 320V x 05 . x 09 . The primary magnetizing inductance of the main transformer is selected so that the magnetizing current is roughly equal to the reflected output inductor ripple current. The output capacitor ripple current can be estimated from Equation 15, while the RMS output voltage ripple is calculated from Equation 16. 2 IPP = 12 a20A x 0.2f (15) 2 = 115 . A RMS VOUTRMS = ICAPRMS x ESR = (16) 115 . A RMS x 0.03 = 35mVRMS Transformer The transformer turns-ratio is set by the holdup voltage available at the boost output in the case of a missing cycle in the AC line. With a 50% maximum duty cycle, a REV. 1.0 10/25/2000 VOUT x D = IPP x N x fS (19) 400V x 0.376 = 6.5mH (20A x 0.2) x 0.083 x 70kHz Current Sense Resistor The peak current seen at the primary is the sum of the reflected load current and the primary magnetizing current. The trip level for the PWM current limit is 1.65V. The kMAG term in Equation 20 accounts for the magnetizing current in the primary and the ripple current in the secondary. The 1.1 factor sets the current limit at 110% of rated full load. VILIMIT = IOUT x kMAG x 110%xN (20) 165 . V = 0.75 20A x 12 . x 11 . x 0.083 20 x 0.2 x 70kHZ 12 N SEC NPRI RSENSE = a12V + 0.5Vf x a1- 0.376f = 28H ICAPRMS = N= LPRI = The output inductor value is selected so that the PWM converter can transition into the CCM at roughly 10% of full load and provide sufficient ramp slope for peak current mode operation. With a turns ratio of 0.083 (see Equation 17) and an input voltage of 400V, the steady state duty cycle can be calculated from Equation 13. Given the steady state duty cycle the output filter inductance can be calculated from Equation 14. D= holdup voltage of 320V (Equation 8), and a transformer coupling coefficient of 0.9, the transformer turns ratio required is 0.087. The actual transformer used in this example has a turns ratio of 0.083. VCCOVP and VCC Full-load to no-load transients at low input voltages can cause excessive overshoot in the PFC output voltage. The VCCOVP is designed to limit the PFC output voltage under a large transient at load off. However, when generating VCC via a winding off the main PWM transformer, the winding will not generate sufficient voltage to trip the VCCOVP during a load off transient. This is due to the fact that the PWM duty approaches zero under the load off transient, thus removing the drive necessary to raise the VCC rail high enough to trip the VCCOVP. By generating the VCC from the boost choke, as shown on the reference schematic, this problem can be eliminated. In the design example VCC is generated from a winding of the PFC choke. The turns ratio of the auxiliary winding vs. the primary winding is 102:4. VCC should be set as high as possible while guaranteeing the VCCOVP does not trip under normal steady state operating conditions. The output 5 Application Note 75 PWM POWER STAGE DESIGN (Continued) voltage will range from 377V to 426V, as discussed in the "one-pin error amp" section. Given this variation, the minimum VCCOVP trip level must be guaranteed to occur at a voltage greater than 426V while the maximum OVP trip level must be less than the output capacitor's rated voltage (450V). The spread on the VCCOVP is 0.5V for a maximum of 16.5V and a minimum of 15.5V. Given the specified PFC choke winding turns ratio, one can calculate the required additional series drop required to limit the minimum OVP trip level to greater than 426V. This additional drop can be achieved by selecting an appropriate value for resistor R31. The maximum VCCOVP trip level can then be checked. N2 = NAUX 4 = = 0.039 NPRI 102 (21) VSERIES = (VOUTMIN x N2 x k ) - VCCOVPMIN = (22) (426V x 0.039 x 0.95) - 155 . V = 0.283V VOUTMAX = VCCOVPMAX + VSERIES N2 x k = (23) 16.5V + 0.283V = 450V 0.039 x 0.95 In general, the VCCOVP trip level should not interfere with the normal steady-state operation of the PFC, and at the same time should be guaranteed to trip at a level below the maximum rating of the 450V output capacitor. Figure 9. Input AC Current @ 85 V AC. 50W, 100W, 200W, 300W Input Power. 2 A/div. 6 The maximum voltage at VCC is limited internally by a low current (<10mA) zener clamp ranging from 16.7V to 18.3V. This will limit the VCC voltage applied to the IC during conditions where VCC is applied through the high impedance start up resistors R26 and R27. During normal operation, when the VCC voltage is supplied by way of the boost choke bootstrap winding, VCC will be limited by the VCCOVP protection circuitry (<16.5V). In the case where VCC is supplied by a low impedance source other than a bootstrap winding, the zener minimum voltage (16.7V) must not be exceeded. RESULTS AND CONCLUSIONS Table 1 displays the IEC input current harmonic content requirements. A summary of the power supply performance is shown in Table 2. Figures 9 through 14 display input current under various operating conditions, load transients, and turn-on overshoot. This design shows that the ML4803 provides an effective, inexpensive solution for a power factor corrected 240W switching power supply. Higher power levels can be achieved with proper buffering of the gate drive outputs and detailed attention paid to printed circuit board (PCB) layout. The design has also shown that proper layout can be achieved with a single-sided PCB layout. Applications include desktop PCs, servers, monitors, and distributed power systems. Figure 10. Input AC Current @ 115 V AC. 50W, 100W, 200W, 300W Input Power. 1 A/div. REV. 1.0 10/25/2000 Application Note 75 Figure 11. Input AC Current @ 230 V AC. 50W, 100W, 200W, 300W Input Power. 0.5 A/div. Figure 12. Input AC Current @ 265 V AC. 50W, 100W, 200W, 300W Input Power. 0.5 A/div. Figure 13. Boost Output Voltage Turn-On Overshoot @ 115 V AC Full Load and No Load 230 V AC Full Load and No Load Figure 14. Boost Output Voltage Load Transient Responce Top Trace: Load Current Step No Load to 15A Bottom Traces: Boost Output Voltage Transient Responce @ 85 V AC, 115 V AC, and 265 V AC Input Voltage REV. 1.0 10/25/2000 7 Application Note 75 HARMONIC ORDER MAXIMUM PERMISSABLE harmonic current per Watt INPUT POWER n mA/W 50 100 200 300 W 3 3.4 170 340 680 1020 mA 5 1.9 95 190 380 570 mA 7 1 50 100 200 300 mA 9 0.5 25 50 100 150 mA 11 0.35 17.5 35 70 105 mA 13<= n => 39 odd harmonics only 3.85/n 192.5/n 385/n 770/n 1155/n mA Table 1 . IEC 1000-3-2 Input Current Harmonic Distortion Limits HARMONIC DISTORTION SUMMARY PF FREQUENCY (Hz) LINE (V) POWER (W) THD (%) 3RD 5 TH (mA) (mA) 7 TH (mA) 9 TH (mA) 11TH (mA) L OUT (A) VOUT (V) EFFICIENCY (%) 0.997 60 85 50.04 5 27 8.6 1.8 2.2 3.3 2.64 12.112 64 0.986 60 120 52.9 13.3 56 19.1 6 3 2.5 2.85 12.112 65 0.966 60 230 47.9 18.8 40.7 11.8 4.3 1.35 3 2.89 12.112 73 0.936 60 265 49.86 22 41.4 10.9 3.2 1.4 2 2.89 12.112 70 0.996 60 120 0.973 60 230 105 7.2 56 19 11.9 5.3 2.1 6.56 12.116 76 101.4 18.8 81 12.9 15.3 1.2 7.8 6.56 12.116 78 0.959 60 265 101 22.9 85.8 9.4 8.2 4.2 2.6 6.56 12.118 79 0.978 60 230 202 17.2 148 36 7.4 4.5 6.27 13.64 12.122 82 0.970 60 265 199.5 20.2 149 18 13.5 13.5 3.8 13.64 12.122 83 0.983 60 230 293 15.5 182 59 25 13.6 3.5 19.81 12.125 82 0.975 60 265 290 18.8 200 46 9 6.9 8.03 19.81 12.125 83 Table 2. ML4803 Performance Summary 8 REV. 1.0 10/25/2000 Application Note 75 LINE F1 5A 250V J1-1 R24 470k 0.5W C19 4.7nF 250VAC L2 TH1 1000H 102T 10 5A C4 0.47F 250VAC CR1 8A, 600V BR1 600V 4A 36 Q2 NEUTRAL J1-2 Q5 R1 R2 L3 C20 4.7nF 250VAC C1 220F 450V 36 R22 10k C16 0.01F CR5 16V 0.5W R3 0.15 3W Q4 CR18 51V R8 36 CR7 CR3 R30 200 T2 3 10 4 C9 1F C22 1F 2 R4 1k 3 CR12 4 R25 390k 7.0V C8 0.15F ML4803 PFC GND ISENSE VEAO PWM VCC ILIMIT VDC 8 CR10 C6 1F C28 1F 12VRET J2-2 4T C21 1F CR15 R6 1.2k 5 6 R11 150 5 R32 100 CR11 CR9 R21 10k U3 1 R37 330 C17 0.1F 2 4 R10 0.75 3W C14 4.7F R9 1.5k Q3 R5 36 C10 2.2nF R14 150 2W C26 0.01F 500V 7 C5 0.01F C15 0.015F C2 2200F L2 R31 5.1 R28 20k 1 C3 1F CR8 R29 20k R19 10k J2-1 CR2 30A, 60V L1 25H C11 1000F R12 5.62M 12V CR2 30A 60V R26 20k 3W CR16 IN4148 C25 0.01F 500V R36 220 T1 R27 20k 3W R7 10 C23 0.01F C18 4.7nF R23 10k 2N3906 C29 0.01F C7 0.1F R13 5.62M Q1 R38 22 1 R15 9.09k C13 1nF R17 3.3k CR4 C27 0.01F R20 510 3 1 U2 2 C12 0.1F R18 1k R16 2.37k Figure 15. Application Schematic REV. 1.0 10/25/2000 9 Application Note 75 Figure 16. Top Silkscreen 10 REV. 1.0 10/25/2000 Application Note 75 Figure 17. Bottom Plane REV. 1.0 10/25/2000 11 Application Note 75 PARTS LIST QUANTITY DESIGNATOR 12 DESCRIPTION MANUFACTURER Mouser 30BJ250-36 Huntington Electric ALSR3F-0.15 Digi Key ALSR3F-0.15-ND Mouser 29SJ250-100 Mouser 30BJ250-10 Mouser 29SJ250-1.2k Mouser 29SJ250-1.5k Huntington Electric ALSR3F-0.75 Digi Key ALSR3F-0.75-ND Mouser 29SJ250-150 Dale CMF-55-5.62M Digi Key 150W-2-ND Mouser 29MF250-9.09k Mouser 29MF250-2.37k Mouser 29SJ250-3.3k Mouser 29SJ250-1k Mouser 29SJ250-200 Mouser 29SJ250-510 Mouser 29SJ250-10k Mouser 29SJ250-470k Mouser 29SJ250-390k Digi Key P20kW-3BK-ND Mouser 30BJ250-20k Mouser 30BJ250-5.1 Digi Key 220W-1-ND Mouser 29SJ250-330 Mouser 30BJ250-22 Panasonic ECO-S2WB221CA Digi Key P10163-ND Panasonic ECA-1CFQ222 Digi Key P5681-ND Panasonic ECU-S1H105MEB Digi Key P4968-ND Panasonic ECQ-E2A474MW Digi Key P4607-ND Panasonic ECU-S1H104MEB Digi Key P4924-ND Panasonic ECU-S1H154KBB Digi Key P4957-ND Panasonic ECU-S1H222KBB Digi Key P4900-ND Panasonic ECA-1EM102 Digi Key P5156-ND Panasonic ECU-S1H102KBB Digi Key P4898-ND Panasonic ECS-F1EE475K Digi Key P2047-ND Panasonic ECU-S1H153KBB Digi Key P4952-ND 4 1 R1, R2, R5, R8 R3 36 1/4W 5% Carbon Comp. resistor 0.15 3W 1% Wirewound resistor 1 2 1 1 1 R32 R7 R6 R9 R10 100 1/4W 5% Carbon Film 10 1/4W 5% Carbon Comp resistor 1.2k 1/4W 5% Carbon Film resistor 1.5k 1/4W 5% Carbon Film resistor 0.75 3W 1% Wirewound resistor 1 2 1 2 1 1 2 1 1 4 1 1 2 2 1 1 1 1 1 R11 R12, R13 R14 R15 R16 R17 R18,R4 R30 R20 R19, R21, R22, R23 R24 R25 R26, R27 R28, R29 R31 R36 R37 R38 C1 1 C2 150 1/4W 5% Carbon Film resistor 5.62M 1/4W 1% Metal Film resistor 150 2W 5% Metal Oxide Film resistor 9.09k 1/4W 1% Metal Film resistor 2.37k 1/4W 1% Metal Film resistor 3.3k 1/4W 5% Carbon Film resistor 1k 1/4W 5% Carbon Film resistor 200 1/4W 5% Carbon Film resistor 510 1/4W 5% Carbon Film resistor 10k 1/4W 5% Carbon Film resistor 470k 1/2W 5% Carbon Film resistor 390k 1/4W 5% Carbon Film resistor 20k 3W 5% Metal Oxide Film resistor 20k 1/4W 5% Carbon Film resistor 5.1 1/4W 5% Carbon Film resistor 220 1W 5% Metal Oxide Film resistor 330 1/4W 5% Carbon Film resistor 22 1/4W 5% Carbon Film resistor 220F 450V 25mm x 50mm TSHB Series capacitor 2200F 16V 12.5mm x 30mm capacitor 5 1F 50V 20% Z5U capacitor 1 C3, C6, C9, C21, C22 C4 3 C7, C12, C17 0.1F 50V 20% Z5U capacitor 1 C8 0.15F 100V 10% X7R capacitor 1 C10 2.2nF 100V 10% X7R capacitor 1 C11 1000F 25V 20% capacitor 1 C13 1nF 100V 10% X7R capacitor 1 C14 4.7F 25V 10% capacitor 1 C15 15nF 100V 10% X7R capacitor 0.47F 250V capacitor PART NUMBER REV. 1.0 10/25/2000 Application Note 75 PARTS LIST (Continued) QUANTITY DESIGNATOR DESCRIPTION MANUFACTURER PART NUMBER Panasonic Digi Key Panasonic Digi Key Panasonic Digi Key Panasonic Digi Key Panasonic Digi Key Panasonic Digi Key Panasonic Digi Key Liteon Int'l Rect. Microsemi Int'l Rect. Int'l Rect. Liteon Microsemi Liteon ECK-D2H103KB5 P4198A-ND ECU-S1H472KBB P4902-ND ECQ-U2A472MV P4625-ND ECK-D2H103KB5 P4198A-ND ECK-F1E103ZV P4300A-ND ECJ-3YF1E105Z PCC1903CT-ND ECU-S1H103MEB P4963-ND 2N3906 IRF840 RS405L HFA08TB60 30CPQ060 MUR160 1N5246BMSCT-ND 1N5818 Liteon Microsemi Micro Linear Nat. Semi. Motorola Premier Mag. Premier Mag. Panasonic Digi Key XFMRS, Inc. P0584 Littlefuse Digi Key Littlefuse Keystone Digi Key RDI Mouser Molex Digi Key Molex Digi Key Molex Digi Key AAVID Digi Key 1N4148DITR P6KE51CAMSCT ML4803CP-1 LM431A MOC8112 TSD-1273 TSD-1274 EXC-ELSA38 P98188K-ND XF4317-00 Pulse Series 216 F920-ND 111501 KC006L-ND KC006L-ND NC6-02 506-NC6-P107-02 26-60-4030 WM4621-ND 09-50-3031 WM2101-ND 08-50-0106 WM2300-ND 530102B00150 HS152-ND 1 C16 0.01F 500V 10% Y5P capacitor 1 C18 4.7nF 100V 10% X7R capacitor 2 C19, C20 4.7nF 250V capacitor 2 C25, C26 0.01F 500V Ceramic disk capacitor 1 C27 0.01F 25V Ceramic Disk capacitor 1 C28 1F 50V Y5V 20% 1206 capacitor 3 C5, C23, C29 0.01F 50V 20% Z5U capacitor 1 4 1 1 1 2 2 4 PNP transistor 500V MOSFET 600V 4A Diode bridge 8A 600V HEXFRED diode TO247 30 Amp 60 Volt Schottky diode 1A 600V diode 16V 0.5W Zener diode 1A 30V Schottky Diode 3 1 1 1 1 1 1 1 Q1 Q2, Q3, Q4, Q5 BR1 CR1 CR2 CR3, CR4 CR5, CR9 CR7, CR10, CR11, CR12 CR8, CR15, CR16 CR18 U1 U2 U3 L1 L2 L3 1 1 1 T1 T2 F1 2 1 Ref. F1 TH1 67kHz 12V Transformer Gate Drive Transformer 5A 250VAC 5 x 20mm Fast Blow Fuse 5 x 20mm Fuse Clips 10 5A RMS Thermistor 1 J2 20A 2-pin Connector 1 J1 3-pin 0.156 Header 1 J1 3-pin 0.156 Connector 2 Ref. J1 Terminal for 0.156 Housing 4 Ref. CR1, CR2, Q2, Q5 Heatsinks REV. 1.0 10/25/2000 150mA 75V Diode 51V Bidirectional Transorb PFC/PWM Combo IC Three-Terminal Zener Regulator IC Opto-isolator IC Output Choke inductor Boost Choke inductor Ferrite bead 13 Application Note 75 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 14 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. (c) 2000 Fairchild Semiconductor Corporation REV. 1.0 10/25/2000