ML4803CS-1 - Fairchild Semiconductor

March 1999

Application Note 42043

ML4803 240W Off-Line Po wer Suppl y with PFC

INTRODUCTION

Included in this Application Note are a reference

schematic, ML4803 design equations, the circuit layout,

and parts list. The reference schematic demonstrates how

the ML4803 can meet the requirements of a PFC

corrected power supply for desktop computer

applications. The design features include a low-cost single

sided PCB with 240W of output power, a form factor

compatible with desk top computer requirements, and

line frequency harmonic content compliant with

IEC1000-3-2.

THEORY OF OPERA TION

The ML4803 Power Factor Control section uses an input

current wave-shaping technique that senses the boost

inductor current. It compares the inductor current

downslope during the off-time of the main power switch

with a ramp programmed by the PFC output voltage

variation. When the two signals intersect the off-time is

terminated and the on-time is initiated for the remainder

of the cycle. Any line or load transients to the PFC will

cause the output to either surge or dip below its regulated

value. This will either increase or decrease the

programmed ramp dv/dt, increasing or decreasing the off-

time of the main power switch and compensating for load

demand. Unity power factor is maintained because the

sensed inductor current ramp is proportional to the input

voltage.

Electrical Specifications

Line voltage 85 to 265VAC

Line harmonic content IEC1000-3-2

Switching frequency 67kHz

POUT 240W

Regulation ±0.1%

Ripple 30mVRMS

Efficiency @ 115VAC, 240W 85%

PFC CONTROL CIRCUIT DESIGN

Internal V oltage Ramp

The internal ramp current source is programmed by way of

the VEAO signal voltage (see Figure 1). This current source

is used to develop the internal ramp by charging the

internal 30pF capacitor. Steady-state operation ensures

that the VEAO signal is 5V. The frequency of the internal

ramp is set to 67kHz.

One-Pin Error Amp

The ML4803 utilizes a one-pin voltage error amplifier in

the PFC section (VEAO). The error amplifier is in reality a

35µA current sink, which forces 35µA through the output

programming resistor. The nominal voltage of the VEAO

signal is 5V and its range is from 4V to 6V. The boost

Figure 1. Internal Ramp Current vs. VEAO

IRAMP (µA)

VEAO (V)

02 7

13 64

FF @ –55ºC

TYP @ –55ºC

TYP @ 155ºC

SS @ 155ºC

TYP @ ROOM TEMP

REV. 1.0 10/25/2000

Application Note 75

2REV. 1.0 10/25/2000

output voltage would be 400V for a 11.3MΩ resistor to

the boost output voltage and 5V steady-state at the VEAO

pin.

RR VV

BOOST EAO

PGM

12 13+= =

–(1)

400 5

35 113

–.

µ=Ω

The IPGM variation over temperature and process is 4%.

Adding an additional 2% variation in the programming

resistor results in a total variation of approximately 6% in

the PFC output voltage. This assumes a temperature

coefficient of less than 200ppm for the programming

resistance. This results in a spread of 377V to 426V in the

PFC output voltage, requiring a PFC output capacitor

rated at 450V.

V oltage Loop Compensation

The voltage loop bandwidth must be set to less than

120Hz to limit line current harmonic distortion. A typical

crossover frequency is 30Hz. Equation 2 assumes that the

pole capacitor (C15) in the compensation network

dominates the error amp gain at the unity gain frequency.

Equation 3 places a pole at the crossover frequency

providing 45º of phase margin. Equation 4 places a zero a

decade prior to the pole providing the necessary phase

boost. Figure 3 displays a simplified schematic of the

voltage control loop.

Bode plots illustrating the overall gain and phase are

shown in Figures 4 and 5.

RV V C f

P BOOST EAO OUT

15 22

=××××

∆

bg (2)

Figure 4. Voltage Loop Gain

–20

–40

–60

GAIN (dB)

FREQUENCY (Hz)

0.1 10 1000

1 100

Power Stage

Overall Gain

Compensation

Network Gain

Figure 3. Voltage Control Loop

ML4803

IVEAO

35µA

IOUT

220µF

RLOAD

667Ω330kΩ

11.3MΩ

0.15µF

15nF

POWER

STAGE COMPENSATION

VEAO

∆VEAO +

–

CZERO

ISENSE

VC1

VI SENSE

GATE

OUTPUT

RCOMP

VOUT = 400V

VEAO

35µA R1

–

COMP

–4

CCOMP

30pF

PFC CONTROL CIRCUIT DESIGN (Continued)

Figure 2. ML4803 PFC Control

Application Note 75

REV. 1.0 10/25/2000 3

Figure 5. Voltage Loop Phase Figure 6. PFC Soft Start

300

113 400 0 5 220 2 30 16

MVVF Hz

..Ω× × × µ × × ≅

RfC

25 1

215

×=

(3)

230 16 330

××=

Hz nF kΩ

CfR

210 25

=×× =

(4)

2 3 330 016

×× =µ

Hz k F

Ω.

PFC Start-Up and Soft Start

During steady state operation VEAO draws 35µA. At start-

up the internal current mirror, which sinks this current, is

defeated until VCC reaches 12V. This forces the PFC error

voltage (VEAO) to 12V at the time that the IC is enabled

(see Figure 6). With leading edge modulation, 6V or more

of VEAO signal forces zero duty in the PFC output. When

designing the external compensation components and the

VCC supply circuits VEAO must not be prevented from

reaching 6V prior to VCC reaching 12V in the turn-on

sequence. This will guarantee the PFC stage will enter soft

start at turn-on. Once VCC reaches 12V the VEAO current

sink is enabled. The VEAO compensation components are

then discharged by way of the 35µA current sink until the

steady-state operating point is reached.

PFC POWER STAGE DESIGN

PFC Inductor

The boost inductor value should ensure that the ripple

current is limited to roughly 20% of the peak input current

PFC CONTROL CIRCUIT DESIGN (Continued)

100

150

200

PHASE (º)

FREQUENCY (Hz)

0.1 1 10 1000100

Power Stage

Overall Gain

Compensation

Network Gain

200ms/Div.

VBOOST

VOUT

VEAO

VCC

at low line voltage. This provides for continuous

conduction throughout much of the line cycle with

sufficient ramp slope to trip the overcurrent comparator at

the trailing edge of the “ON” pulse.

PK OUT

=×

×=

(5)

240 2

85 0 75 53

×=

DVV

OUT IN

OUT

–(6)

400 85 2

400 07

–.

×=

LVD

RMS

=××

×=

02. (7)

85 2 0 7

02 53 70 1134

AkHz H

××

×× =µ

PFC Output Capacitor

The dominant consideration in selecting the output

capacitor is providing sufficient holdup time at the output

to sustain output regulation in the event the AC line drops

out for one cycle. The voltage to which the boost cap is

allowed to drop is limited by the maximum PWM duty

cycle and the main transformer turns ratio (see

Transformer section, following).

OUT HOLDUP

–(8)

2 240 15

380 320 190

××

=µ

Wms

VV F

()–()

Application Note 75

4REV. 1.0 10/25/2000

Figure 8. ISENSE and VOFFSET Over Duty CycleFigure 7. ISENSE Offset Circuit

PFC Current Sense Resistor

In Discontinous Conduction Mode (DCM) the input

current wave shaping technique used by the ML4803 can

cause the input current to run away, forcing the PFC

output to increase until the VCCOVP point is reached. In

order for the PWM technique to work properly under

DCM, the programmed ramp must meet the boost

inductor current down slope at zero amps. Assuming the

programmed ramp is zero under light load, the off time

will be terminated once the inductor current reaches zero.

Subsequently, the PFC gate drive would be initiated

eliminating any necessary deadtime needed for the DCM

mode. The problem is resolved by adding an offset voltage

to the current sense signal, which forces the duty cycle to

zero at light loads. The offset prevents the PFC from

operating in the Discontinous Conduction Mode (DCM)

and forces pulse skipping from Continuous Conduction

Mode (CCM) to no duty, avoiding the DCM problem

altogether. External filtering of the current sense signal

helps to smooth out the signal, expanding the operating

range somewhat into the DCM range. This should be done

carefully as the filtering reduces the bandwidth of the

signal feeding the pulse-by-pulse current limit

information.

Figure 7 displays the circuit used to provide offset to the

ISENSE pin under light load conditions. It adds a negative

offset to the ISENSE pin that is inversely proportional to the

PFC pulse width, preventing excessive input current under

light load conditions. Components C23 and CR16 offset

the PFC gate drive by –15V, while the subsequent low-

pass network averages the offset square wave. The net

effect is a negative voltage summed with the input

current sense that increases as the PFC pulse width

decreases. Figure 8 illustrates how ILIMIT vs. duty cycle

varies with the PFC gate drive offset signal. The 120Hz

component of the PFC gate drive is attenuated by more

than –50dB at the ISENSE pin. Because this 120Hz

component added to the ISENSE input will increase the

harmonic distortion in the input AC current, it should kept

to a minimum by this low-pass network.

To select the PFC RSENSE value, use a peak current that is

120% of that found in Equation 5.

R3 V

LIMIT

=×=

120% (9)

12 5 3 015

A.. .

×=Ω

PFC and PWM Gate Drive

The peak current rating of the PFC and PWM gate drive

outputs is 1A. A 36Ω gate drive resistor is used to drive

two MOSFETs in parallel and limit the gate drive peak

current to less than 1A. The charge required to elevate the

gate of the IRF840 to 15V is taken from the

manufacturer’s data sheet in order to estimate the gate

drive turn-on time. Estimating the current as a constant

allows the approximate time to be derived from Equation

10. Given the switching frequency, the average gate

current drawn from VCC can be calculated from Equation

11. Since a typical carbon film resistor is only capable of

a peak power of 4 times its average, rated power, a ¼W

resistor is limited to 1W peak. With a peak current of

0.416A in a 36Ω resistor, the peak power is 6.23W, well

in excess of the 1W limitation. For this reason carbon

composition resistors are typically used for gate drive

applications.

GATE

≈== (10)

0 416 144

Ans

Ω

PFC POWER STAGE DESIGN (Continued)

R29

20kΩ

C23

0.01µF

8.2nF

PFC GATE

VCC RTN

ISENSE

C22

1µF

R28

20kΩ

R19

10kΩ

1kΩ

.015Ω

CR16

1N4148

6.8

6.6

6.4

6.2

6.0

5.8

5.6

ILIMIT (A)

DUTY CYCLE (%)

0 40 60 100

8020

–0.05

–0.10

–0.15

–0.20

–0.25

–0.30

OFFSET (V)

VOFFSET

ILIMIT

ILIMITMOD

Application Note 75

REV. 1.0 10/25/2000 5

IQf

CC GATE S

DRIVE =×= (11)

60 70 4 2nC kHz mA×=.

The high-side gate drive transformer magnetizing current

can be estimated from Equation 12.

AVG CC

SMAG

×× =

8(12)

8 70 450 60

kHz H mA

××µ

The total ICC due to gate drive can now be estimated from

the sum of all of the above.

PWM POWER STAGE DESIGN

Output Filter

The output inductor value is selected so that the PWM

converter can transition into the CCM at roughly 10% of

full load and provide sufficient ramp slope for peak

current mode operation. With a turns ratio of 0.083 (see

Equation 17) and an input voltage of 400V, the steady

state duty cycle can be calculated from Equation 13.

Given the steady state duty cycle the output filter

inductance can be calculated from Equation 14.

DVV

OUT D

BOOST

=+×=(13)

12 0 5

400 0 083 0 376

×=

LVV D

OUT OUT D

OUT S

=+×

××=

20%

–(14)

12 0 5 1 0 376

20 0 2 70 28

kHZ H

+×

×× =µ

.–.

afaf

The output capacitor ripple current can be estimated from

Equation 15, while the RMS output voltage ripple is

calculated from Equation 16.

CAP PP

RMS ==

12 (15)

20 0 2

12 115

AARMS

×=

VIESR

OUT CAP

RMS RMS

=×= (16)

115 0 03 35..AmV

RMS RMS

×=Ω

Transformer

The transformer turns-ratio is set by the holdup voltage

available at the boost output in the case of a missing

cycle in the AC line. With a 50% maximum duty cycle, a

holdup voltage of 320V (Equation 8), and a transformer

coupling coefficient of 0.9, the transformer turns ratio

required is 0.087. The actual transformer used in this

example has a turns ratio of 0.083.

SEC

PRI

=(17)

NVV

VD k

OUT D

HU MAX

××

=(18)

NVV

××=

12 05

320 0 5 09 0087

.. .

The primary magnetizing inductance of the main

transformer is selected so that the magnetizing current is

roughly equal to the reflected output inductor ripple

current.

LVD

INf

PRI OUT

PP S

=×

×× =(19)

400 0 376

20 0 2 0 083 70 65

AkHz

×× × =

(.). .

Current Sense Resistor

The peak current seen at the primary is the sum of the

reflected load current and the primary magnetizing

current. The trip level for the PWM current limit is 1.65V.

The kMAG term in Equation 20 accounts for the

magnetizing current in the primary and the ripple current

in the secondary. The 1.1 factor sets the current limit at

110% of rated full load.

RVI

Ik xN

SENSE LIMIT

OUT MAG

=×× =

110% (20)

165

20 12 11 0 083 075

... .

A××× =Ω

CCOVP and VCC

Full-load to no-load transients at low input voltages can

cause excessive overshoot in the PFC output voltage. The

VCCOVP is designed to limit the PFC output voltage under

a large transient at load off. However, when generating

VCC via a winding off the main PWM transformer, the

winding will not generate sufficient voltage to trip the

VCCOVP during a load off transient. This is due to the fact

that the PWM duty approaches zero under the load off

transient, thus removing the drive necessary to raise the

VCC rail high enough to trip the VCCOVP. By generating

the VCC from the boost choke, as shown on the reference

schematic, this problem can be eliminated.

In the design example VCC is generated from a winding of

the PFC choke. The turns ratio of the auxiliary winding vs.

the primary winding is 102:4. VCC should be set as high as

possible while guaranteeing the VCCOVP does not trip

under normal steady state operating conditions. The output

PFC POWER STAGE DESIGN (Continued)

Application Note 75

6REV. 1.0 10/25/2000

Figure 9. Input AC Current @ 85 V AC.

50W, 100W, 200W, 300W Input P ower.

2 A/div.

Figure 10. Input AC Current @ 115 V AC.

50W, 100W, 200W , 300W Input P ow er .

1 A/div.

voltage will range from 377V to 426V, as discussed in the

"one-pin error amp" section. Given this variation, the

minimum VCCOVP trip level must be guaranteed to occur

at a voltage greater than 426V while the maximum OVP

trip level must be less than the output capacitor’s rated

voltage (450V). The spread on the VCCOVP is ±0.5V for a

maximum of 16.5V and a minimum of 15.5V. Given the

specified PFC choke winding turns ratio, one can

calculate the required additional series drop required to

limit the minimum OVP trip level to greater than 426V.

This additional drop can be achieved by selecting an

appropriate value for resistor R31. The maximum VCCOVP

trip level can then be checked.

AUX

PRI

102 0039===.(21)

VV NkV

SERIES OUTMIN CCOVPMIN

=×× =()–2 (22)

(..)–..426 0 039 0 95 155 0 283VVV×× =

VVV

OUTMAX

CCOVP SERIES

MAX

×=

2(23)

16 5 0 283

0 039 0 95 450

In general, the VCCOVP trip level should not interfere

with the normal steady-state operation of the PFC, and at

the same time should be guaranteed to trip at a level

below the maximum rating of the 450V output capacitor.

PWM POWER STAGE DESIGN (Continued)

The maximum voltage at VCC is limited internally by a

low current (<10mA) zener clamp ranging from 16.7V to

18.3V. This will limit the VCC voltage applied to the IC

during conditions where VCC is applied through the high

impedance start up resistors R26 and R27. During normal

operation, when the VCC voltage is supplied by way of the

boost choke bootstrap winding, VCC will be limited by the

VCCOVP protection circuitry (<16.5V). In the case where

VCC is supplied by a low impedance source other than a

bootstrap winding, the zener minimum voltage (16.7V)

must not be exceeded.

RESUL TS AND CONCLUSIONS

Table 1 displays the IEC input current harmonic content

requirements. A summary of the power supply

performance is shown in Table 2. Figures 9 through 14

display input current under various operating conditions,

load transients, and turn-on overshoot.

This design shows that the ML4803 provides an effective,

inexpensive solution for a power factor corrected 240W

switching power supply. Higher power levels can be

achieved with proper buffering of the gate drive outputs

and detailed attention paid to printed circuit board (PCB)

layout. The design has also shown that proper layout can

be achieved with a single-sided PCB layout. Applications

include desktop PCs, servers, monitors, and distributed

power systems.

Application Note 75

REV. 1.0 10/25/2000 7

Figure 11. Input AC Current @ 230 V AC.

50W , 100W, 200W, 300W Input P ow er .

0.5 A/div.

Figure 12. Input AC Current @ 265 V AC.

50W, 100W, 200W, 300W Input P ower.

0.5 A/div.

Figure 13. Boost Output Voltage Turn-On Overshoot @

115 V AC Full Load and No Load

230 V AC Full Load and No Load

Figure 14. Boost Output Voltage Load Tr ansient Responce

Top Trace: Load Current Step No Load to 15A

Bottom Traces: Boost Output V oltage T r ansient Responce

@ 85 V AC, 115 V AC, and 265 V AC Input Voltage

Application Note 75

8REV. 1.0 10/25/2000

HARMONIC DISTORTION SUMMARY

PF FREQUENCY LINE POWER THD 3RD 5TH 7TH 9TH 11TH LOUT VOUT EFFICIENCY

(Hz) (V) (W) (%) (mA) (mA) (mA) (mA) (mA) (A) (V) (%)

0.997 60 85 50.04 5 27 8.6 1.8 2.2 3.3 2.64 12.112 64

0.986 60 120 52.9 13.3 56 19.1 6 3 2.5 2.85 12.112 65

0.966 60 230 47.9 18.8 40.7 11.8 4.3 1.35 3 2.89 12.112 73

0.936 60 265 49.86 22 41.4 10.9 3.2 1.4 2 2.89 12.112 70

0.996 60 120 105 7.2 56 19 11.9 5.3 2.1 6.56 12.116 76

0.973 60 230 101.4 18.8 81 12.9 15.3 1.2 7.8 6.56 12.116 78

0.959 60 265 101 22.9 85.8 9.4 8.2 4.2 2.6 6.56 12.118 79

0.978 60 230 202 17.2 148 36 7.4 4.5 6.27 13.64 12.122 82

0.970 60 265 199.5 20.2 149 18 13.5 13.5 3.8 13.64 12.122 83

0.983 60 230 293 15.5 182 59 25 13.6 3.5 19.81 12.125 82

0.975 60 265 290 18.8 200 46 9 6.9 8.03 19.81 12.125 83

Table 2. ML4803 Performance Summary

HARMONIC ORDER MAXIMUM PERMISSABLE INPUT POWER

harmonic current per W att

n mA/W 50 100 200 300 W

3 3.4 170 340 680 1020 mA

5 1.9 95 190 380 570 mA

7 1 50 100 200 300 mA

9 0.5 25 50 100 150 mA

11 0.35 17.5 35 70 105 mA

13<= n => 39 3.85/n 192.5/n 385/n 770/n 1155/n mA

odd harmonics only

Table 1 . IEC 1000-3-2

Input Current Harmonic Distortion Limits

Application Note 75

REV. 1.0 10/25/2000 9

Figure 15. Application Schematic

BR1

600V

LINE

NEUTRAL

F1 5A 250V

J1-1

J1-2

C19

4.7nF

250VAC

C20

4.7nF

250VAC

R24

470kΩ

0.5W

TH1

10Ω

R3 0.15Ω 3W

2N3906

1000µH

102T

36Ω

CR1 8A, 600V

CR7

CR3

CR18 51V

C26

0.01µF

500V

C18 4.7nF

CR2

30A, 60V

R36 220Ω

L1 25µH

C29 0.01µF

CR2

30A

60V C2

2200µF

1µF

220µF

450V

36Ω

CR5

16V

0.5W

R22

10kΩ

R8 36Ω

R23

10kΩ

R38 22Ω

R30 200Ω

0.1µF

R27

20kΩ

R26

20kΩ

R10

0.75Ω

C23

0.01µF

CR4

CR11

CR10

CR12

CR9

R5 36Ω

R11 150Ω

R4 1kΩ

ML4803

C15

0.015µF C6

1µF

0.01µF

C28

1µF

C10

2.2nF

R17 3.3kΩ

R6 1.2kΩ

C12 0.1µF

C25

0.01µF

500V

12V

J2-1

12VRET

J2-2

R18 1kΩ

CR8

CR15

R32 100Ω

C27

0.01µF

R15

9.09kΩ

7.0V R21

10kΩ

C14

4.7µF

C17

0.1µF

R16

2.37kΩ

R13

5.62MΩR7

10Ω

CR16

IN4148

R12

5.62MΩ

0.47µF

250VAC

R14

150Ω

R37

330Ω

1.5kΩ

C13 1nF

R31

5.1Ω

C11

1000µF

C21

1µF

C22

1µF

R29 20kΩ

R28

20kΩ

R19

10kΩ

PFC

GND

ISENSE

VEAO

PWM

VCC

ILIMIT

VDC

R20

510Ω

R25

390kΩ

0.15µF

C16

0.01µF

Application Note 75

10 REV. 1.0 10/25/2000

Figure 16. Top Silkscreen

Application Note 75

REV. 1.0 10/25/2000 11

Figure 17. Bottom Plane

Application Note 75

12 REV. 1.0 10/25/2000

PARTS LIST

QUANTITY DESIGNA T OR DESCRIPTION MANUFACTURER PART NUMBER

4 R1, R2, R5, R8 36Ω ¼W 5% Carbon Comp. resistor Mouser 30BJ250-36

1 R3 0.15Ω 3W 1% Wirewound resistor Huntington Electric ALSR3F-0.15

Digi Key ALSR3F-0.15-ND

1 R32 100Ω ¼W 5% Carbon Film Mouser 29SJ250-100

2R7 10Ω ¼W 5% Carbon Comp resistor Mouser 30BJ250-10

1 R6 1.2kΩ ¼W 5% Carbon Film resistor Mouser 29SJ250-1.2k

1 R9 1.5kΩ ¼W 5% Carbon Film resistor Mouser 29SJ250-1.5k

1 R10 0.75Ω 3W 1% Wirewound resistor Huntington Electric ALSR3F-0.75

Digi Key ALSR3F-0.75-ND

1 R11 150Ω ¼W 5% Carbon Film resistor Mouser 29SJ250-150

2 R12, R13 5.62MΩ ¼W 1% Metal Film resistor Dale CMF-55-5.62MΩ

1 R14 150Ω 2W 5% Metal Oxide Film resistor Digi Key 150W-2-ND

2 R15 9.09kΩ ¼W 1% Metal Film resistor Mouser 29MF250-9.09k

1 R16 2.37kΩ ¼W 1% Metal Film resistor Mouser 29MF250-2.37k

1 R17 3.3kΩ ¼W 5% Carbon Film resistor Mouser 29SJ250-3.3k

2 R18,R4 1kΩ ¼W 5% Carbon Film resistor Mouser 29SJ250-1k

1 R30 200Ω ¼W 5% Carbon Film resistor Mouser 29SJ250-200

1 R20 510Ω ¼W 5% Carbon Film resistor Mouser 29SJ250-510

4 R19, R21, R22, R23 10kΩ ¼W 5% Carbon Film resistor Mouser 29SJ250-10k

1 R24 470kΩ ½W 5% Carbon Film resistor Mouser 29SJ250-470k

1 R25 390kΩ ¼W 5% Carbon Film resistor Mouser 29SJ250-390k

2 R26, R27 20kΩ 3W 5% Metal Oxide Film resistor Digi Key P20kW-3BK-ND

2 R28, R29 20kΩ ¼W 5% Carbon Film resistor Mouser 30BJ250-20k

1 R31 5.1Ω ¼W 5% Carbon Film resistor Mouser 30BJ250-5.1

1 R36 220Ω 1W 5% Metal Oxide Film resistor Digi Key 220W-1-ND

1 R37 330Ω ¼W 5% Carbon Film resistor Mouser 29SJ250-330

1 R38 22Ω ¼W 5% Carbon Film resistor Mouser 30BJ250-22

1 C1 220µF 450V 25mm x 50mm TSHB Series Panasonic ECO-S2WB221CA

capacitor Digi Key P10163-ND

1 C2 2200µF 16V 12.5mm x 30mm capacitor Panasonic ECA-1CFQ222

Digi Key P5681-ND

5 C3, C6, C9, 1µF 50V 20% Z5U capacitor Panasonic ECU-S1H105MEB

C21, C22 Digi Key P4968-ND

1 C4 0.47µF 250V capacitor Panasonic ECQ-E2A474MW

Digi Key P4607-ND

3 C7, C12, C17 0.1µF 50V 20% Z5U capacitor Panasonic ECU-S1H104MEB

Digi Key P4924-ND

1 C8 0.15µF 100V 10% X7R capacitor Panasonic ECU-S1H154KBB

Digi Key P4957-ND

1 C10 2.2nF 100V 10% X7R capacitor Panasonic ECU-S1H222KBB

Digi Key P4900-ND

1 C11 1000µF 25V 20% capacitor Panasonic ECA-1EM102

Digi Key P5156-ND

1 C13 1nF 100V 10% X7R capacitor Panasonic ECU-S1H102KBB

Digi Key P4898-ND

1 C14 4.7µF 25V 10% capacitor Panasonic ECS-F1EE475K

Digi Key P2047-ND

1 C15 15nF 100V 10% X7R capacitor Panasonic ECU-S1H153KBB

Digi Key P4952-ND

Application Note 75

REV. 1.0 10/25/2000 13

PARTS LIST (Continued)

QUANTITY DESIGNA TOR DESCRIPTION MANUFACTURER PART NUMBER

1 C16 0.01µF 500V 10% Y5P capacitor Panasonic ECK-D2H103KB5

Digi Key P4198A-ND

1 C18 4.7nF 100V 10% X7R capacitor Panasonic ECU-S1H472KBB

Digi Key P4902-ND

2 C19, C20 4.7nF 250V capacitor Panasonic ECQ-U2A472MV

Digi Key P4625-ND

2 C25, C26 0.01µF 500V Ceramic disk capacitor Panasonic ECK-D2H103KB5

Digi Key P4198A-ND

1 C27 0.01µF 25V Ceramic Disk capacitor Panasonic ECK-F1E103ZV

Digi Key P4300A-ND

1 C28 1µF 50V Y5V 20% 1206 capacitor Panasonic ECJ-3YF1E105Z

Digi Key PCC1903CT-ND

3 C5, C23, C29 0.01µF 50V 20% Z5U capacitor Panasonic ECU-S1H103MEB

Digi Key P4963-ND

1 Q1 PNP transistor Liteon 2N3906

4 Q2, Q3, Q4, Q5 500V MOSFET Int’l Rect. IRF840

1 BR1 600V 4A Diode bridge Microsemi RS405L

1 CR1 8A 600V HEXFRED diode Int’l Rect. HFA08TB60

1 CR2 TO247 30 Amp 60 Volt Schottky diode Int’l Rect. 30CPQ060

2 CR3, CR4 1A 600V diode Liteon MUR160

2 CR5, CR9 16V 0.5W Zener diode Microsemi 1N5246BMSCT-ND

4 CR7, CR10, CR11, 1A 30V Schottky Diode Liteon 1N5818

CR12

3 CR8, CR15, CR16 150mA 75V Diode Liteon 1N4148DITR

1 CR18 51V Bidirectional Transorb Microsemi P6KE51CAMSCT

1 U1 PFC/PWM Combo IC Micro Linear ML4803CP-1

1 U2 Three-Terminal Zener Regulator IC Nat. Semi. LM431A

1 U3 Opto-isolator IC Motorola MOC8112

1 L1 Output Choke inductor Premier Mag. TSD-1273

1 L2 Boost Choke inductor Premier Mag. TSD-1274

1 L3 Ferrite bead Panasonic EXC-ELSA38

Digi Key P98188K-ND

1 T1 67kHz 12V Transformer XFMRS, Inc. XF4317-00

1 T2 Gate Drive Transformer P0584 Pulse

1 F1 5A 250VAC 5 x 20mm Littlefuse Series 216

Fast Blow Fuse Digi Key F920-ND

2 Ref. F1 5 x 20mm Fuse Clips Littlefuse 111501

1 TH1 10Ω 5A RMS Thermistor Keystone KC006L-ND

Digi Key KC006L-ND

1 J2 20A 2-pin Connector RDI NC6-02

Mouser 506-NC6-P107-02

1 J1 3-pin 0.156 Header Molex 26-60-4030

Digi Key WM4621-ND

1 J1 3-pin 0.156 Connector Molex 09-50-3031

Digi Key WM2101-ND

2 Ref. J1 Terminal for 0.156 Housing Molex 08-50-0106

Digi Key WM2300-ND

4 Ref. CR1, CR2, Heatsinks AAVID 530102B00150

Q2, Q5 Digi Key HS152-ND

Application Note 75

14 REV. 1.0 10/25/2000

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES

OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR

CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, and (c) whose failure to

perform when properly used in accordance with

instructions for use provided in the labeling, can be

reasonably expected to result in a significant injur y of the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be

reasonably e xpected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO

ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME

ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.