CA91C142X-33CE - Integrated Device Technology

Tundra Semiconductor Corporation

Universe II™

VME-to-PCI Bus Bridge Manual

User Manual

Document Number: 80A3010_MA001_03

Document Status: Final

Release Date: November 2002

This document discuss es the features, capabilities, and

configuration requirements of the Universe II. It is intended for

hardware and software engineers who are designing system

interconnect applications with the Univers e II.

Title P age - 80A 3010 _MA001_0 3

Trademarks

TUNDRA is a r egist er ed trademark of Tundra Se mico nductor Corpo rati on ( Canada, U.S., and U.K.). TUNDRA,

the Tundra logo, Universe II, and Silicon Behind the Network, are trademarks of Tundra Semiconductor

Corpor atio n. All other regis tered and unregi stere d marks (incl uding tr ademarks , servi ce mark s and logos ) are the

property of their respective owners. The absence of a mark identifier is not a representation that a particular

product name is not a mark.

Published in Canada

This document contains information which is proprietary to Tundra and may be used for non-commercial

purposes within your organization in support of Tundra products. No other use or transmission of all or any part

of this document is permitted without written permission from Tundra, and must include all copyright and other

proprietary notices. Use or transmission of all or any part of this document in violation of any applicable

Canadian or other legislation is hereby expressly prohibited.

User o btains no r ights in the i nformat ion or in any pr oduc t, proc ess, techn ology or trade mark which it inclu des or

describes, and is expressly prohibited from modifying the information or creating derivative works without the

express written consent of Tundra.

Disclaimer

Tundra as sum e s no respo nsi bility fo r t he accura cy or complet eness of the i nformation pres ent ed wh ich is s ubj ect

to change without notice. In no event will Tundra be liable for any direct, indirect, special, incidental or

conse quenti al da mages , incl uding l ost p rofit s, los t busine ss or lost d ata, r esult ing f rom t he use of or reli ance upo n

the information, whether or not Tundra has been advised of the possibility of such damages.

Mention of non-Tundra products or services is for information purposes only and constitutes neither an

endorsement nor a recommendation.

Universe II VME-to-PCI Bus Bridge Manual 3

80A3010_MA001_03

Corporate Profile

Tundra Semiconductor Corporation

Tundra Semiconductor Corporation (TSE:TUN) designs, develops, and markets

advanced System Interconnect for use by the world’s leading Internet and

communications infrastructure vendors. Tundra chips provide the latest interface

and throughput features to help these vendors design and deliver more powerful

equipment in shorter timeframes. Tundra pr oducts are essential to a range of

applications, including telecommunications, data communications, wireless

communications, industrial automation, and ruggedized systems. Tundra

headquarters are located in Kanata, Ontario, Canada, and sales offices are based in

Mountain View, California and Maidenhead, U.K. Tundra sells its products

worldwide through a network of direct sale s personnel, independent distributors,

and manufactur ers’ representatives. More information is available online at

www.tundra.com.

Greater Demand, Greater Opportunity

The increasingly complex require ments pl aced on the Inte rn et, intran ets and

extranets have created an insatiable demand for highe r speed and greate r capacity in

communications networks. The evolution of co nverging c omm unications networks

requires higher levels of security and increasingly sophisticated network

intelligence. These network demands, and the user expectations that drive them,

have create d a global need for we ll-managed and ever-increasing bandwidth.

Tundra helps meet those demands by creating underlying technology that enables

the acceler ated flow of voice, data, and video information over communications

networks. Tundra products can be found in a broad range of applications, including

telecommunications, data communications, wire less communications, industrial

automation, and avionics. Communications infrastructure vendors rely on Tundra

for off-the-shelf, standards-based, easy-to-deploy and highly scalable System

Interconnect products.

Universe II VME-to-PCI B us Bridge Man ual

480A3010_MA001_03

Tundra System Interconnect

Tundra is System Inter conne ct. Tundra uses the term Syste m Int erconnect to refer to

the technology used to connect all the components and sub-systems in almost any

embedded system. This concept applies to the interfacing of f unctional elements

(CPU, memory, I/ O complexes, etc.) withi n a single-board s ystem, and t he

interfacing of multiple boards in a larger syste m.

System Interc onnect is a vital enabling technology for the networked world. The

convergence of voice, video, and data traffic, the ne ed for more secure

communications, and the exploding dem and for high-speed network access are

putting communications infrastructure vendors under inte nse pressure to provide

faster, well-managed bandwidth that also integrates smoothly with existing

technology. T u ndra System Interconnect helps the se vendors address their customer

needs. It e na bles them to build standa rd s-based n etwork equipment that can sc ale t o

multi-gigahertz speeds and also integrate with existing infrastructure.

Partnerships

Fundamental to the success of Tundra is its partnerships with leading

manufacturers, including Motorola, Compaq and Texas Instruments. As a result of

these alliances, Tundra devices grea tly influence the design of customers’

architectur e s. Custo mers a re cha nging the ir designs to incorporate Tundra products.

This highlights the commitment Tundra holds to be a significant pa rt of its

customers’ success.

The Tundra design philosophy is one in which a number of strategic customers are

invited to participate in the definition, design, test, and early silicon supply phases

of product development. Close working relationships with customers and clear

product roadmaps ensure that Tundra can anticipate and meet the future directions

and needs of communications systems designers and manufacturers.

Tundra Customers

Tundra semiconductor products are used by the world's leading communications

infrastruc ture vendors, including Cisco, Motorola, Ericsson, Nortel, Lucent, IB M,

Xerox, Hewlet t-Packard, 3Com, Nokia , Siemens, Alca tel, Matsushita, OKI , Fujitsu,

Samsung, and LGS.

Tundra Customer Support

Tundra is respec ted throughout the industry for its outstanding commitment to

customer support. Tundra ensures that its customers can take im mediate advantage

of the company's products through its Applications Engineering Group, unmatched

Design Support Tools (DST), and full doc u mentation. Customer support also

includes Web-base d and telephone access to in-house technic al resources.

Tundra System Interconnect … Silicon Behind the Network ™

Universe II VME-to-PCI Bus Bridge Manual 5

80A3010_MA001_03

Contact Information

Tundra is dedic ated to providing its customers with superior technical

documentation and support. The following types of support are available:

Webpages

Product information www.tundra.com /Universe II describes

Universe II’s features, benefits, typical

applications, and block diagram. This webpage

also provides links to other product-related

information located on the Tundra website.

Design Support Tools (DST) www.tundra.com /dst contains an extensive

collection of technical documents that explain

Universe II’s features and how to implement

them. Some of the DST resources include the

device manual, m anual addenda, applica tion

notes, design notes, and device errata.

Once you register for access to the Design

Support Tools webpage you can opt to r eceive

email notificat ion when a re source is added or

changed.

FAQ database www.tundra.com /faq is a support da tabase that

contains answers to common technical questions

fielded by our knowledgeable Tec hnical

Support team.

Sales support www.tundra.com /sales contains information

that will help you locate a Tundra sales

representative nearest you.

Universe II VME-to-PCI B us Bridge Man ual

680A3010_MA001_03

Technical support Use support@tundra.com to send technical

questions and feedback to our Technical Support

team. Please include Universe II in the subject

header of your me ssage.

Document feedback Use docfeedback@tundra.com to provide

feedback on the Universe II VME-to-PCI Bus

Bridge Manual.

Document ordering Use docs@tundra.com to order printed copies of

Tundra product manuals (Final status only).

Please include Universe II in the subject header

of your message.

Mail

Tundra headquarters Tundra Se miconductor Corporation

603 March Road

Kanata, ON

K2K 2M5

Universe II VME-to-PCI Bus Bridge Manual 7
80A3010_MA001_03
Contents
 Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.1 Universe II Features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.2 Universe II Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.3 Universe II Typical Applications  . . . . . . . . . . . . . . . . . . . . . . . . . 29
2 Main Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.1 VMEbus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2 PCI Bus Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3 Interrupter and Interrupt Handler  . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.4 DMA Controller  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
 VMEbus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2 VMEbus Requester  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35
2.1 Internal Arbitration for VMEbus Requests . . . . . . . . . . . . . . . . . . 35
2.2 Request Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  37
2.3 VMEbus Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  37
3 Universe II as VMEbus Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.1 Addressing Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2 Data Transfer Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3 Cycle Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  42

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4 Universe II as VMEbus Slave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1 Coupled Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2 Posted Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3 Prefetched Block Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.4 VMEbus Lock Commands (ADOH Cycles) . . . . . . . . . . . . . . . . . 49
4.5 VMEbus Read-Modify-Write Cycles (RMW Cycles). . . . . . . . . . 50
4.6 Register Accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.7 Location Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.8 Generating PCI Configuration Cycles . . . . . . . . . . . . . . . . . . . . . . 52
5 VMEbus Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.1 First Slot Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.2 VMEbus Register Access at Power-up . . . . . . . . . . . . . . . . . . . . . 55
6 Automatic Slot Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.1 Auto Slot ID: VME64 Specified . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.2 Auto-ID: A Proprietary Tundra Method  . . . . . . . . . . . . . . . . . . . . 57
6.3 System Controller Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.4 IACK Daisy-Chain Driver Module . . . . . . . . . . . . . . . . . . . . . . . . 59
6.5 VMEbus Time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.6 BI-Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
 PCI Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2 PCI Cycles  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.1 32-Bit Versus 64-Bit PCI  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.2 PCI Bus Request and Parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3 Address Phase  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.4 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.5 Termination Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.6 Parity Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3 Universe II as PCI Master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.1 Command Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.2 PCI Burst Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.3 Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.4 Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Contents
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4 Universe II as PCI Target. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.1 Command Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.2 Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3 Coupled Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.4 Posted Writes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.5 Special Cycle Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.6 Using the VOWN bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.7 Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
 Slave Image Programming. . . . . . . . . . . . . . . . . . . . . . . . . .83
2 VME Slave Image Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.1 VMEbus Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.2 PCI Bus Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.3 Control Fields  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3 PCI Bus Target Images  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.1 PCI Bus Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.2 VMEbus Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.3 Control Fields  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4 Special PCI Target Image  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
 Registers Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
2 Register Access from the PCI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.1 PCI Configuration Access  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  94
2.2 Memory or I/O Access  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2.3 Locking the Register Block from the PCI bus. . . . . . . . . . . . . . . . 96
3 Register Access from the VMEbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.1 VMEbus Register Access Image (VRAI) . . . . . . . . . . . . . . . . . . . 9 7
3.2 CR/CSR Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.3 RMW and ADOH Register Access Cycles . . . . . . . . . . . . . . . . . .  99
4 Mailbox Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5 Semaphores  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Contents
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 DMA Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
2 DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
2.1 Source and Destination Addresses. . . . . . . . . . . . . . . . . . . . . . . . 104
2.2 Non-incrementing DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2.3 Transfer Size  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
2.4 Transfer Data Width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
2.5 DMA Command Packet Pointer  . . . . . . . . . . . . . . . . . . . . . . . . . 109
2.6 DMA Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3 Direct Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4 Linked-list Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.1 Linked-list Updating  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5 FIFO Operation and Bus Ownership  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.1 PCI-to-VMEbus Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.2 VMEbus-to-PCI Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6 DMA Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7 DMA Channel Interactions with Other Channels. . . . . . . . . . . . . . . . . . . 125
8 DMA Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
8.1 DMA Software Response to Error. . . . . . . . . . . . . . . . . . . . . . . . 126
8.2 DMA Hardware Response to Error . . . . . . . . . . . . . . . . . . . . . . . 127
8.3 Resuming DMA Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
 Interrupt Generation and Handling  . . . . . . . . . . . . . . . . . 129
2 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
2.1 PCI Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
2.2 VMEbus Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
3 Interrupt Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
3.1 PCI Interrupt Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
3.2 VMEbus Interrupt Handling  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
3.3 Internal Interrupt Handling  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
3.4 VME64 Auto-ID  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

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 Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
2 Errors on Coupled Cycles  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
3 Errors on Decoupled Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
3.1 Posted Writes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
3.2 Prefetched Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
3.3 DMA Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
3.4 Parity Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
 Resets, Clocks and Power-up Options. . . . . . . . . . . . . . .153
2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
2.1 Universe II Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
2.2 Reset Implementation Cautions. . . . . . . . . . . . . . . . . . . . . . . . . . 158
3 Power-Up Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
3.1 Power-up Option Descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . 161
3.2 Power-up Option Implementation. . . . . . . . . . . . . . . . . . . . . . . . 164
3.3 Hardware Initialization (Normal Operating Mode). . . . . . . . . . . 165
4 Test Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
4.1 Auxiliary Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
4.2 JTAG support  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
5 Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Signals and Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
2 VMEbus Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
3 PCI Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
4 Pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
4.1 Pin List for 313-pin Plastic BGA Package (PBGA) . . . . . . . . . . 178
4.2 361 DBGA Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .185
1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
1.1 Non-PCI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
1.2 PCI Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
3 Power Dissipation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
4 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Contents
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12 80A3010_MA001_03
12. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
12.2 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
A.  Packaging Information  . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
A.1 313 Pin PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
A.2 361 Pin DBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
B.  Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
B.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
B.2 PCI Slave Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
B.2.1 Coupled Cycles  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
B.2.2 Decoupled Cycles  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
B.3 VME Slave Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
B.3.1 Coupled Cycles  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
B.3.2 Decoupled Cycles  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
B.4 DMA Channel and Relative FIFO Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . 389
B.4.1 VMEbus Ownership Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
B.4.2 VME Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
B.4.3 PCI Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
B.5 Universe II Specific Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
B.5.1 Overview of the U2SPEC Register . . . . . . . . . . . . . . . . . . . . . . . 392
B.5.2 Adjustable VME Timing Parameters. . . . . . . . . . . . . . . . . . . . . . 393
B.6 Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
C.  Reliability Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
C.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
C.2 Physical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
C.3 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
C.4 Universe II Ambient Operating Calculations . . . . . . . . . . . . . . . . . . . . . . 399
C.5 Thermal vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
D.  Endian Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
D.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
D.2 Little-endian Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

Contents
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E.  Typical Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
E.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
E.2 VME Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
E.2.1 Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
E.2.2 Direction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
E.2.3 Power-up Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
E.3 PCI Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
E.3.1 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
E.3.2 Local Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
E.4 Manufacturing Test Pins  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
E.5 Decoupling VDD and VSS on the Universe II  . . . . . . . . . . . . . . . . . . . . 415
F.  Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417
F.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

Contents

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Universe II VME-to-PCI Bus Bridge Manual 13
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List of Figures
Figure 1: Universe II Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 2: Universe II In Single Board Computer Application . . . . . . . . . . . . . . . . . 30
Figure 3: Universe II Data Flow Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 4: VMEbus Slave Channel Dataflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 5: Timing for Auto-ID Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 6: PCI Bus Target Channel Dataflow  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  74
Figure 7: Address Translation Mechanism for VMEbus to PCI Bus Transfers . . . . 86
Figure 8: Address Translation Mechanism for PCI Bus to VMEbus Transfers . . . . 89
Figure 9: Memory Mapping in the Special PCI Target Image . . . . . . . . . . . . . . . . . 92
Figure 10: Universe II Control and Status Register Space . . . . . . . . . . . . . . . . . . . . . 94
Figure 11: PCI Bus Access to UCSR as Memory or I/O Space . . . . . . . . . . . . . . . . . 95
Figure 12: UCSR Access from the VMEbus Register Access Image. . . . . . . . . . . . . 98
Figure 13: UCSR Access in VMEbus CR/CSR Space . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 14: Direct Mode DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 15: Command Packet Structure and Linked List Operation . . . . . . . . . . . . . 116
Figure 16: DMA Linked List Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 17: Universe Interrupt Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 18: STATUS/ID Provided by Universe II . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 19: Sources of Internal Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 20: Reset Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 21: Resistor-Capacitor Circuit Ensuring Power-Up Reset Duration . . . . . . . 159
Figure 22: Power-up Options Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 23: UCSR Access Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 24: 313 PBGA - Bottom View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Figure 25: 313 PBGA - Top and Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Figure 26: 361 DBGA - Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

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Figure 27: 361 DBGA - Top View  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Figure 28: 361 DBGA - Bottom View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Figure 29: Coupled Read Cycle - Universe II as VME Master. . . . . . . . . . . . . . . . . 378
Figure 30: Several Coupled Read Cycles - Universe II as VME Master. . . . . . . . . . 378
Figure 31: Coupled Write Cycle - Universe II as VME Master  . . . . . . . . . . . . . . . . 379
Figure 32: Several Non-Block Decoupled Writes - Universe II as VME Master . . . 381
Figure 33: BLT Decoupled Write - Universe II as VME Master  . . . . . . . . . . . . . . . 381
Figure 34: Coupled Read Cycle - Universe II as VME Slave . . . . . . . . . . . . . . . . . . 383
Figure 35: Coupled Write Cycle - Universe II as VME Slave 
(bus parked at Universe II) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Figure 36: Non-Block Decoupled Write Cycle - Universe II as VME Slave . . . . . . 385
Figure 3 7 : BLT Decoupled Write Cycle - Univ erse II as VME Sl ave . . . . .  . . . . . . 385
Figure 38: MBLT Decoupled Write Cycle - Universe II as VME Slave. . . . . . . . . . 386
Figure 39: BLT Pre-fetched Read Cycle - Universe II as VME Slave . . . . . . . . . . . 388
Figure 40: PCI Read Transactions During DMA Operation . . . . . . . . . . . . . . . . . . . 391
Figure 41: Multiple PCI Read Transactions During DMA Operation. . . . . . . . . . . . 392
Figure 4 2: Universe II C onnections  to the VMEbu s Through TTL  Buffers . . . . . . . 407
Figure 4 3: Universe II C onnections  to the VMEbu s Through TTL  Buffers . . . . . . . 408
Figure 44: Power-up Configuration Using Passive Pull-ups . . . . . . . . . . . . . . . . . . . 411
Figure 45: Power-up Configuration Using Active Circuitry . . . . . . . . . . . . . . . . . . . 412
Figure 46: Analog Isolation Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Figure 47: Noise Filter Scheme   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

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List of Tables
Table 1:  VMEbus Address Modifier Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 2:  PCI Address Line Asserted as a Function of VA[15:11]. . . . . . . . . . . . . . 53
Table 3:  Command Type Encoding for Transfer Type  . . . . . . . . . . . . . . . . . . . . . . 66
Table 4:  Register Fields for the Special Cycle Generator . . . . . . . . . . . . . . . . . . . . 78
Table 5:  VMEbus Fields for VMEbus Slave Image. . . . . . . . . . . . . . . . . . . . . . . . .  84
Table 6:  PCI Bus Fields for VMEbus Slave Image . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 7:  Control Fields for VMEbus Slave Image. . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 8:  PCI Bus Fields for the PCI Bus Target Image . . . . . . . . . . . . . . . . . . . . . . 87
Table 9:  VMEbus Fields for the PCI Bus Target Image  . . . . . . . . . . . . . . . . . . . . . 88
Table 10:  Control Fields for PCI Bus Target Image  . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 11:  PCI Bus Fields for the Special PCI Target Image . . . . . . . . . . . . . . . . . . . 90
Table 12:  VMEbus Fields for the Special PCI Bus Target Image . . . . . . . . . . . . . . . 91
Table 13:  Control Fields for the Special PCI Bus Target Image . . . . . . . . . . . . . . . . 91
Table 14:  Programming the VMEbus Register Access Image. . . . . . . . . . . . . . . . . .  97
Table 15:  VON Settings for Non-Inc Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 16:  DMA Interrupt Sources and Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . 125
Ta ble 17:  Source,  Enabli n g, Mapping , and Sta tus of  PCI Interrupt Output. . . .  . . . 13 2
Ta ble 18:   Source, Enabling, Mapping, and Status of VM Ebus Inter rupt Out puts. . 134
Table 19:  Internal Interrupt Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 20:  Hardware Reset Mechanisms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 21:  Software Reset Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 22:  Functions Affected by Reset Initiators. . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 23:  Power-Up Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 24:  VRAI Base Address Power-up Options. . . . . . . . . . . . . . . . . . . . . . . . . . 162
Ta ble 25:  Manufactu ring Pin Requiremen ts for Normal Opera ting M ode . . . . . . . 165
Table 26:  Test Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

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Table 27:  VMEbus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 28:  PCI Bus Signals  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 29:  Pin List for 361 Pin DBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 29:  DBGA Pin List (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 29:  DBGA Pin List (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 29:  DBGA Pin List (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 30:  Ground, Power and N/C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 31:  Non-PCI Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 32:  AC/DC PCI Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 33:  Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 34:  Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 35:  Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 36:  Universe II Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 37:  PCI Configuration Space ID Register (PCI_ID). . . . . . . . . . . . . . . . . . . . 202
Table 38:  PCI Configuration Space Control and Status Register (PCI_CSR) . . . . . 203
Table 39:  PCI Configuration Class Register (PCI_CLASS)  . . . . . . . . . . . . . . . . . . 207
Ta ble 40:  PCI Co nfiguration Mi scella neous 0 Re gister (PCI_MISC0) . . . . . . . . . . 208
Table 41:  PCI Configuration Base Address Register (PCI_BS0). . . . . . . . . . . . . . . 209
Table 42:  PCI Configuration Base Address 1 Register (PCI_BS1) . . . . . . . . . . . . . 210
Ta ble 43:  PCI Co nfiguration Mi scella neous 1 Re gister (PCI_MISC1) . . . . . . . . . . 212
Table 44:  PCI Target Image 0 Control (LSI0_CTL)  . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 45:  PCI Target Image 0 Base Address Register (LSI0_BS). . . . . . . . . . . . . . 215
Table 46:  PCI Target Image 0 Bound Address Register (LSI0_BD) . . . . . . . . . . . . 216
Table 47:  PCI Target Image 0 Translation Offset (LSI0_TO) . . . . . . . . . . . . . . . . . 217
Table 48:  PCI Target Image 1 Control (LSI1_CTL)  . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 49:  PCI Target Image 1 Base Address Register (LSI1_BS). . . . . . . . . . . . . . 220
Table 50:  PCI Target Image 1 Bound Address Register (LSI1_BD) . . . . . . . . . . . . 221
Table 51:  PCI Target Image 1 Translation Offset (LSI1_TO) . . . . . . . . . . . . . . . . . 222
Table 52:  PCI Target Image 2 Control (LSI2_CTL)  . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 53:  PCI Target Image 2 Base Address Register (LSI2_BS). . . . . . . . . . . . . . 225
Table 54:  PCI Target Image 2 Bound Address Register (LSI2_BD) . . . . . . . . . . . . 226
Table 55:  PCI Target Image 2 Translation Offset (LSI2_TO) . . . . . . . . . . . . . . . . . 227
Table 56:  PCI Target Image 3 Control (LSI3_CTL)  . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 57:  PCI Target Image 3 Base Address Register (LSI3_BS). . . . . . . . . . . . . . 230
Table 58:  PCI Target Image 3 Bound Address Register (LSI3_BD) . . . . . . . . . . . . 231

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Table 59:  PCI Target Image 3 Translation Offset (LSI3_TO). . . . . . . . . . . . . . . . . 232
Table 60:  Special Cycle Control Register (SCYC_CTL). . . . . . . . . . . . . . . . . . . . . 233
Table 61:  Special Cycle PCI Bus Address Register (SCYC_ADDR) . . . . . . . . . . . 234
Table 62:  Special Cycle Swap/Compare Enable Register (SCYC_EN) . . . . . . . . . 235
Table 63:  Special Cycle Compare Data Register (SCYC_CMP). . . . . . . . . . . . . . . 236
Table 64:  Special Cycle Swap Data Register (SCYC_SWP). . . . . . . . . . . . . . . . . . 237
Table 65:  PCI Miscellaneous Register (LMISC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 66:  Special PCI Target Image (SLSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 67:  PCI Command Error Log Register (L_CMDERR) . . . . . . . . . . . . . . . . . 241
Table 68:  PCI Address Error Log (LAERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 69:  PCI Target Image 4 Control Register (LSI4_CTL) . . . . . . . . . . . . . . . . . 243
Table 70:  PCI Target Image 4 Base Address Register (LSI4_BS)  . . . . . . . . . . . . . 245
Table 71:  PCI Target Image 4 Bound Address Register (LSI4_BD). . . . . . . . . . . . 246
Table 72:  PCI Target Image 4 Translation Offset (LSI4_TO). . . . . . . . . . . . . . . . . 247
Table 73:  PCI Target Image 5 Control Register (LSI5_CTL) . . . . . . . . . . . . . . . . . 248
Table 74:  PCI Target Image 5 Base Address Register (LSI5_BS)  . . . . . . . . . . . . . 250
Table 75:  PCI Target Image 5 Bound Address Register (LSI5_BD). . . . . . . . . . . . 251
Table 76:  PCI Target Image 5 Translation Offset (LSI5_TO). . . . . . . . . . . . . . . . . 252
Table 77:  PCI Target Image 6 Control Register (LSI6_CTL) . . . . . . . . . . . . . . . . . 253
Table 78:  PCI Target Image 6 Base Address Register (LSI6_BS)  . . . . . . . . . . . . . 255
Table 79:  PCI Target Image 6 Bound Address Register (LSI6_BD). . . . . . . . . . . . 256
Table 80:  PCI Target Image 6 Translation Offset (LSI6_TO). . . . . . . . . . . . . . . . . 257
Table 81:  PCI Target Image 7 Control Register (LSI7_CTL) . . . . . . . . . . . . . . . . . 258
Table 82:  PCI Target Image 7 Base Address Register (LSI7_BS)  . . . . . . . . . . . . . 260
Table 83:  PCI Target Image 7 Bound Address Register (LSI7_BD). . . . . . . . . . . . 261
Table 84:  PCI Target Image 7 Translation Offset (LSI7_TO). . . . . . . . . . . . . . . . . 262
Table 85:  DMA Transfer Control Register (DCTL)  . . . . . . . . . . . . . . . . . . . . . . . . 263
Table 86:  DMA Transfer Byte Count Register (DTBC) . . . . . . . . . . . . . . . . . . . . . 265
Table 87:  DMA PCI Bus Address Register (DLA) . . . . . . . . . . . . . . . . . . . . . . . . . 266
Table 88:  DMA VMEbus Address Register (DVA)  . . . . . . . . . . . . . . . . . . . . . . . . 267
Table 89:  DMA Command Packet Pointer (DCPP). . . . . . . . . . . . . . . . . . . . . . . . . 268
Table 90:  DMA General Control/Status Register (DGCS) . . . . . . . . . . . . . . . . . . . 269
Table 91:  DMA Linked List Update Enable Register (D_LLUE). . . . . . . . . . . . . . 273
Table 92:  PCI Interrupt Enable Register (LINT_EN) . . . . . . . . . . . . . . . . . . . . . . . 274
Table 93:  PCI Interrupt Status Register (LINT_STAT). . . . . . . . . . . . . . . . . . . . . . 277

List of Tables
Universe II VME-to-PCI B us Bridge Man ual
18 80A3010_MA001_03
Table 94:  PCI Interrupt Map 0 Register (LINT_MAP0) . . . . . . . . . . . . . . . . . . . . . 280
Table 95:  PCI Interrupt Map 1 Register (LINT_MAP1) . . . . . . . . . . . . . . . . . . . . . 281
Table 96:  VMEbus Interrupt Enable Register (VINT_EN) . . . . . . . . . . . . . . . . . . . 282
Table 97:  VMEbus Interrupt Status Register (VINT_STAT). . . . . . . . . . . . . . . . . . 285
Table 98:  VME Interrupt Map 0 Register (VINT_MAP0). . . . . . . . . . . . . . . . . . . . 287
Table 99:  VME Interrupt Map 1 Register (VINT_MAP1). . . . . . . . . . . . . . . . . . . . 288
Table 100: Interrupt STATUS/ID Out Register (STATID) . . . . . . . . . . . . . . . . . . . . 289
Table 101: VIRQ1 STATUS/ID Register (V1_STATID) . . . . . . . . . . . . . . . . . . . . . 290
Table 102: VIRQ2 STATUS/ID Register (V2_STATID) . . . . . . . . . . . . . . . . . . . . . 291
Table 103: VIRQ3 STATUS/ID Register (V3_STATID) . . . . . . . . . . . . . . . . . . . . . 292
Table 104: VIRQ4 STATUS/ID Register (V4_STATID) . . . . . . . . . . . . . . . . . . . . . 293
Table 105: VIRQ5 STATUS/ID Register (V5_STATID) . . . . . . . . . . . . . . . . . . . . . 294
Table 106: VIRQ6 STATUS/ID Register (V6_STATID) . . . . . . . . . . . . . . . . . . . . . 295
Table 107: VIRQ7 STATUS/ID Register (V7_STATID) . . . . . . . . . . . . . . . . . . . . . 296
Table 108: PCI Interrupt Map 2 Register (LINT_MAP2) . . . . . . . . . . . . . . . . . . . . . 297
Table 109: VME Interrupt Map 2 Register (VINT_MAP2). . . . . . . . . . . . . . . . . . . . 298
Table 110: Mailbox 0 Register (MBOX0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Table 111: Mailbox 1 Register (MBOX1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Table 112: Mailbox 2 Register (MBOX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Table 113: Mailbox 3 Register (MBOX3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Table 114: Semaphore 0 Register (SEMA0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 115: Semaphore 1 Register (SEMA1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 116: Master Control Register (MAST_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Table 117: Miscellaneous Control Register (MISC_CTL). . . . . . . . . . . . . . . . . . . . . 308
Table 118: Miscellaneous Status Register (MISC_STAT). . . . . . . . . . . . . . . . . . . . . 311
Table 119: User AM Codes Register (USER_AM) . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Table 120: Universe II Specific Register (U2SPEC) . . . . . . . . . . . . . . . . . . . . . . . . . 314
Table 121: VMEbus Slave Image 0 Control (VSI0_CTL). . . . . . . . . . . . . . . . . . . . . 316
Ta ble 122: VMEbus Slav e Image  0 Base Address Registe r (VSI0 _BS) . . . . . . . . . . 318
Ta ble 123: VMEbus Slav e Image 0 Bound Address Register (VSI0_BD)  . . . . . . . . 319
Table 124: VMEbus Slave Image 0 Translation Offset (VSI0_TO)  . . . . . . . . . . . . . 320
Table 125: VMEbus Slave Image 1 Control (VSI1_CTL). . . . . . . . . . . . . . . . . . . . . 321
Ta ble 126: VMEbus Slav e Image  1 Base Address Registe r (VSI1 _BS) . . . . . . . . . . 323
Ta ble 127: VMEbus Slav e Image 1 Bound Address Register (VSI1_BD)  . . . . . . . . 324
Table 128: VMEbus Slave Image 1 Translation Offset (VSI1_TO)  . . . . . . . . . . . . . 325

List of Tables
Universe II VME-to-PCI Bus Bridge Manual 19
80A3010_MA001_03
Table 129: VMEbus Slave Image 2 Control (VSI2_CTL). . . . . . . . . . . . . . . . . . . . . 326
Table 130: VMEbus Slave Image 2 Base Address Register (VSI2_BS) . . . . . . . . . . 328
Ta ble 131: VMEbus Slave Image 2 Bound Address Register (VSI2_BD) . . . . .  . . . 329
Table 132: VMEbus Slave Image 2 Translation Offset (VSI2_TO) . . . . . . . . . . . . . 330
Table 133: VMEbus Slave Image 3 Control (VSI3_CTL). . . . . . . . . . . . . . . . . . . . . 331
Table 134: VMEbus Slave Image 3 Base Address Register (VSI3_BS) . . . . . . . . . . 333
Ta ble 135: VMEbus Slave Image 3 Bound Address Register (VSI3_BD) . . . . .  . . . 334
Table 136: VMEbus Slave Image 3 Translation Offset (VSI3_TO) . . . . . . . . . . . . . 335
Table 137: Location Monitor Control Register (LM_CTL). . . . . . . . . . . . . . . . . . . . 336
Table 138: Location Monitor Base Address Register (LM_BS) . . . . . . . . . . . . . . . . 338
Table 139: VMEbus Regist er Access Image Control Reg ister (V RAI_CTL). . . . . . 339
Table 140: V MEbus  R egister Access Image Base Address Register (VRA I_BS) . . 340
Table 141: Power-up Option behavior of the VAS field in VRAI_CTL. . . . . . . . . . 340
Table 142: VMEbus CSR Control Register (VCSR_CTL) . . . . . . . . . . . . . . . . . . . . 341
Table 143: VMEbus CSR Translation Offset (VCSR_TO). . . . . . . . . . . . . . . . . . . . 342
Table 144: VMEbus AM Code Error Log (V_AMERR). . . . . . . . . . . . . . . . . . . . . . 343
Table 145: VMEbus Address Error Log (VAERR). . . . . . . . . . . . . . . . . . . . . . . . . . 344
Table 146: VMEbus Slave Image 4 Control (VSI4_CTL). . . . . . . . . . . . . . . . . . . . . 345
Table 147: VMEbus Slave Image 4 Base Address Register (VSI4_BS) . . . . . . . . . . 347
Ta ble 148: VMEbus Slave Image 4 Bound Address Register (VSI4_BD) . . . . .  . . . 348
Table 149: VMEbus Slave Image 4 Translation Offset (VSI4_TO) . . . . . . . . . . . . . 349
Table 150: VMEbus Slave Image 5 Control (VSI5_CTL). . . . . . . . . . . . . . . . . . . . . 350
Table 151: VMEbus Slave Image 5 Base Address Register (VSI5_BS) . . . . . . . . . . 352
Ta ble 152: VMEbus Slave Image 5 Bound Address Register (VSI5_BD) . . . . .  . . . 353
Table 153: VMEbus Slave Image 5 Translation Offset (VSI5_TO) . . . . . . . . . . . . . 354
Table 154: VMEbus Slave Image 6 Control (VSI6_CTL). . . . . . . . . . . . . . . . . . . . . 355
Table 155: VMEbus Slave Image 6 Base Address Register (VSI6_BS) . . . . . . . . . . 357
Ta ble 156: VMEbus Slave Image 6 Bound Address Register (VSI6_BD) . . . . .  . . . 358
Table 157: VMEbus Slave Image 6 Translation Offset (VSI6_TO) . . . . . . . . . . . . . 359
Table 158: VMEbus Slave Image 7 Control (VSI7_CTL). . . . . . . . . . . . . . . . . . . . . 360
Table 159: VMEbus Slave Image 7 Base Address Register (VSI7_BS) . . . . . . . . . . 362
Ta ble 160: VMEbus Slave Image 7 Bound Address Register (VSI7_BD) . . . . .  . . . 363
Table 161: VMEbus Slave Image 7 Translation Offset (VSI7_TO) . . . . . . . . . . . . . 364
Table 162: VMEbus CSR Bit Clear Register (VCSR_CLR). . . . . . . . . . . . . . . . . . . 365
Table 163: VMEbus CSR Bit Set Register (VCSR_SET) . . . . . . . . . . . . . . . . . . . . . 366

List of Tables

Universe II VME-to-PCI B us Bridge Man ual

20 80A3010_MA001_03

Table 164: VMEbus CSR Base Address Register (VCSR_BS) . . . . . . . . . . . . . . . . . 367

Table 165: PCI Slave Channel Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

Table 166: VME Slave Channel Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

Table 167: DMA Channel Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

Table 168: Ambient to Junction Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . . . . 399

Table 169: Maximum Universe II Junction Temperature. . . . . . . . . . . . . . . . . . . . . . 400

Table 170: Mapping of 32-bit Little-Endian PCI Bus to 32-bit VMEbus . . . . . . . . . 402

Table 171: Mapping of 32-bit Little-Endian PCI Bus to 64-bit VMEbus . . . . . . . . . 403

Table 172: VMEbus Signal Drive Strength Requirements . . . . . . . . . . . . . . . . . . . . 409

Table 173: VMEbus Transceiver Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

Table 174: Reset Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413

Table 175: Standard Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

Universe II VME-to-PCI Bus Bridge Manual 21

80A3010_MA001_03

About this Document

This chapter discusses general document information about the xx Manual. The

following topic s are described:

•“Revision History” on page 21

•“Document Conventions” on page 22

•“Related Documents” on page 25

Revision History

80A91142_MA001_03, Final Manual, November 2002

This is the final version of the Universe II VME-to-PCI Bus Bridge Manual. This

document information applies to both the Universe IIB and the U niverse IID

devices. The Universe IID is re comme nded for all new designs. For more

information a bout the two devices, refer to the UniverseIID and the UniverseIIB

Differences Summary on the Tundra website at www.tundr a.com.

The following chapter was updated for the release of this m anual:

•“Reliability Prediction” on page 397

Universe II VME-to-PCI B us Bridge Man ual

22 80A3010_MA001_03

80A91142_MA001_02, Final Manual, October 2002

This is the final version of the Universe II VME-to-PCI Bus Bridge Manual. This

document information applies to both the Universe IIB and the U niverse IID

devices. The Universe IID is re comme nded for all new designs. For more

information a bout the two devices, refer to the UniverseIID and the UniverseIIB

Differences Summary on the Tundra website at www.tundr a.com.

There was an er ratum found in the 361 DBGA package drawing. The following

section of the document has been updated:

•“361 Pin DBGA Package” on page 372

80A91142_MA001_01, Final Manual, June 2002

This is the final version of the Universe II VME-to-PCI Bus Bridge Manual. This

document information applies to both the Universe IIB and the U niverse IID

devices. The Universe IID is re comme nded for all new designs. For more

information a bout the two devices, refer to the Universe IID and the Universe IIB

Differences Summary on the Tundra website at www.tundr a.com.

Document Conventions

This section explains the document conventions used in this manual.

Signal Notation

Signals are either active high or active low. Active low signa ls are defined as tr ue

(asserted) when they are at a logic low. Similarly, ac tiv e h igh sign als are defined as

true at a logic high. Signals are considered asserted when active and negated when

inactive, irrespective of voltage levels. For volta ge levels, the use of 0 indicates a

low voltage while a 1 indicates a high voltage.

For voltage levels, the use of 0 indicates a low voltage while a 1 indicates a high

voltag e. For vol ta ge level s, the use of 0 i ndicat es a low voltage while a 1 indica te s a

high voltage.

Each si gnal that assu mes a logi c low state when asserted is foll o wed by an

underscore sign, “_”. For example, SIGNAL_ is asser ted low to indicate an active

low signal. Signals that are not followed by an underscore are asserted when they

assume the logic high state. For example, SIGNAL is asserted high to indicate an

active high signal.

The asterisk sign “*” is used in this manual to show that a signal is asserte d low and

that i s used on the on the VMEbus backplane. For e xample, SIGNAL* is asse rted to

low to indicate an active low signal on the VMEbus backplane.

Universe II VME-to-PCI Bus Bridge Manual 23

80A3010_MA001_03

Bit Ordering Notation

This document adopts the convention that the m ost significant bit is always the

largest number (also referred to as Little-Endian bit ordering). For example, the PCI

address/da ta bus c onsis ts of AD[ 31:0], where AD[ 31] is the mos t s ignif ica nt b it and

AD[0] is the least-signific ant bit of the field.

Object Size Notation

The following object size conventions are used:

•A byte is an 8-bit object.

•A word is a 16-bit (2 byte) object.

•A doubleword is a 32-bit (4 byte) objec t.

•A quadword is a 64- bit (8 byte) object.

•A Kword is 1024 16- bit words.

Numeric Notation

The following numeric conventions are used:

• Hexadecimal numbers are de noted by the prefix 0x. For e xam ple, 0x04.

• Binary numbers are denoted by the suffix b. For example, 10b.

Typographic Notation

The following typographic conventions are used in this manual:

•Italic type is used for the following purposes:

— Book titles: For example, PCI Loc al Bus Specification.

— Important term s: For example, when a device is granted access to the PC I

bus it is called the bus master.

— Undefined value s: For example, the device supports four channels

depending on the setting of the PCI_Dx regis ter.

•Courier type is used to represent a file name or text that appears on a

computer di splay. For example, “run load.exe by typing it at a command

prompt.”

Universe II VME-to-PCI B us Bridge Man ual

24 80A3010_MA001_03

Symbol s Used

The following symbols are used in this manual.

Document S tatus I nformati on

Tundra technical doc umentation is classified as either Advance, Pre liminary, or

Final:

• Advance: The Advance manual contains information that is subject to c h ange

and exists until prototypes are available. This type of manual can be

downloaded from our website at www.tundra.com.

• Preliminary : The Preliminary manual contains infor mation about a product that

is near produc tion-ready, and is revised as required. The Preliminary manual

exists until the product is released to production. This type of manual can be

downloaded from our website at www.tundra.com.

• Final: The Fina l manual contains information about a final, customer-ready

product. This type of manual can be downloaded from our website. It can also

be ordered in print format by calling 613-592-0714 or 1-800-267-7231 (please

ask for customer service), or by email at docs@tundra.com.

Tip

This symbol indica te s a ba sic de sign c oncept or infor mation co nside red

helpful.

This symbol indicates important configuration information or

suggestions.

This symbol indicates proce dures or opera ting leve ls tha t may resul t in

misuse or damage to the device.

Universe II VME-to-PCI Bus Bridge Manual 25

80A3010_MA001_03

Related Documents

The following doc uments are useful f or refer ence purpos es when using this manual.

PC I Local Bus Specifica t ion

(Revision 2.2) This specification def ines the PCI hardware

environment including the protocol, elec trical,

mechanical and conf iguration specif ication for

the PCI local bus components and expansion

boards. Fo r more information, see

www.pcisig.com.

VME64 Specification This specification defines the VME64 hardware

environment including the protocol, elec trical,

mechanical, and configura tion specification.

For more information, se e www.vita.com

Universe II VME-to-PCI B us Bridge Man ual

26 80A3010_MA001_03

Universe II VME-to-PCI Bus Bridge Manual 27

80A3010_MA001_03

1. Functional Overview

This chapter outl ine s the funct iona lity of the Unive rse II . This c ha pter discusse s the

following topic s:

•“V MEbus Interface” on page 32

•“PCI Bu s Interface” on p age 33

•“Interrupter and Interrupt Handler” on page 33

•“DMA C ontroller” on page 34

1.1 Overview

The Tundra Universe II is the industry's leading high performance PCI-to-VMEbus

interconnec t. Universe II is fully compliant with the VME64 bus standard, and

tail ored for th e next-ge neration of advance d PCI processo rs and peri pherals. Wi th a

zero-wait state implementation, multi-beat transactions, and support for

bus-parking, Universe II provides high performance on the PCI bus.

The Universe II eases development of multi-master, multi-processor architec tures

on VMEbus and PCI bus systems. The device is ide ally suited for CPU boards

functioni ng as both master and slave in the VMEbus system, and that requi re access

to PCI systems. Br idging is accomplished through a decoupled architecture with

independent FIFOs for inbound, outbou nd, and DMA traffic . W ith this archit ecture,

throughput is maximized without sacrificing bandwidth on either bus.

With the Universe II, you know that as your system becomes more complex, you

have proven sil icon that conti nues to provide everyt hing you need in a PCI-to-VME

bridge.

1. Functional Overview

Universe II VME-to-PCI B us Bridge Man ual

28 80A3010_MA001_03

Figure 1: Universe II Block Diagram

1.1.1 Unive rse II Fea t ures

The U n iverse II has t he following features:

• Industry-proven, high performance 64-bit VMEbus interconnect

• Fully compliant, 32-bit or 64-bit, 33 MHz PCI bus inte rconnect

• Integral FIFOs for write posting to maximize ba ndwidth utilization

• Programmable DMA controlle r with Linked-List mode (Scatter/Gather)

support

• Flexible interrupt logic

• Sustained transf er rates up to 60-70 Mbytes/s

• Extensive suite of VMEbus address and data transfer modes

• Automatic initialization for slave-only applica tions

PCI Interface

VMEbus Interface

32-bit Address / 64-bit Data

33 MHz PCI Bus

IEEE1149.1

Boundary

Scan

JTAG

VMEbus Slave Channel

Posted Writes, Prefetched Reads,

Coupled Reads

DMA Channel

Bidirectional FIFO,

Direct/Linked List Mode

Configuration Registers,

Mailbox Registers, Semaphores

Interrupt Channel

Interrupt Handler,

Interrupter

PCI Target Channel

Posted Writes, Coupled Read

8091862_BK001_03

32-bit Address / 64-bit Data

VMEbus

Arbiter

Fixed priority,

Round robin,

Single level modes

Location

Monitor

Four location

montiors

to support VMEbus

broadcast capability

1. Functional Overview

Universe II VME-to-PCI Bus Bridge Manual 29

80A3010_MA001_03

• Flexible register set, programmable from both the PCI bus and VMEbus ports

• Full VMEbus system controller

• Support for RMWs, ADOH, PCI LOCK_ cycles, and semaphores

• Commercial, industrial, and extended temperature variants

• IEEE 1149.1 JTAG

• Available packaging:

— 25mm x 25mm, 361-contac t dimpled ceramic BGA (DBGA)

— 35mm x 35mm, 313-contact plastic BGA (PBGA) package

1.1.2 Universe II Benefits

The Universe II offers the following benefits to designers:

• Conserves board space with

25mm x 25mm, 361-contac t dimpled ceramic BGA (DBGA) and

• Industry proven device

• Reliable custom er support with experience in hundreds of customer designs

1.1.3 Unive rse II Typical App licati on s

The Universe II is targeted at today’s technology demands, such as the following:

• Single-board computers

• Telecommunications equipment

• Test equipment

• Command and control systems

• Factory automation equipment

• Medical equipment

• Military

• Aerospace

1.1.3.1 Typical Application Example: Single Board Computers

The Universe II is widely used on VME-based Single Board Computers (SBC ) that

employ PCI as their local bus and VME as the backplane bus, as shown in the

accompanying diagram. These SBC cards suppor t a variety of applications

including telecom, datacom, medical, industrial, and m ilitary equipment.

The Universe II high performance architecture seamlessly bridges the PCI and

VME busses, and is the VME industry's standard for single board com puter

interconnect device.

1. Functional Overview

Universe II VME-to-PCI B us Bridge Man ual

30 80A3010_MA001_03

Figure 2: Universe II In Single Board Computer Application

Memory

Universe II

PMC

Connection

I/O

Controller

PCI Bus

32-bit / 64-bit Data

33 MHz

VMEbus

64-bit Data

Processor Bus Processor-

to-PCI Bridge

Processor

8091142_TA001_01

1. Functional Overview

Universe II VME-to-PCI Bus Bridge Manual 31

80A3010_MA001_03

1.2 Main Inte rfac es

The Universe II has two main interface s: the PCI Bus Interf ace and the VMEbus

Interface . Each of the inter faces, VMEbus and PCI bus, there are three functionally

distinct modules: maste r m odule, slave module, and interrupt module. These

modules are conne cted to the different functional channels operating in the

Universe II. The device had the following channels:

• VMEbus Slave Channel

• PCI Bus Target Channe l

• DMA Channel

• Interrupt Channel

• Register Channe l

Figure 3 shows the Universe II in terms of the different modules and channels.

Figure 3: Universe II Data Flow Diagram

PCI

Slave

PCI

Interrupts

DMA Channel

PCI

Master

VME

Master

VME

Interrupts

VME

Slave

VMEbus Slave Channel

VMEb

PCI

Interrupt Channel

PCI Bus Slave Channel

PCI Bus

Interface VMEbus

Interface

DMA bidirectional FIFO

prefetch read FIFO

coupled read

posted writes FIFO

coupled read logic

posted writes FIFO

Interrupter

Interrupt Handler

Mailbox Registers

Semaphores

8091142_BK001_01

1. Functional Overview

Universe II VME-to-PCI B us Bridge Man ual

32 80A3010_MA001_03

1.2.1 VMEbus Interface

The VME Interface is a VME64 Specification complian t interface.

1.2.1.1 Universe II as VMEbus Slave

The Universe II VMEbus Slave Channel accepts all of the addressing and data

transfer mode s documented in the VME64 Specification - except A64 and those

intended to a ugme nt 3U applications. Incoming write transactions from the

VMEbus can be trea ted as either coupled or posted, depending upon the

programming of the VMEbus slave imag e (see “VME Slave Image Programming”

on page 84). With posted write transactions, data is written to a Posted Write

Receive FIFO (RXFIFO), and the VMEbus master receives data a cknowledgment

from th e Universe II . W rite da ta is tr ansferred t o the PCI r esource from the RXFIFO

without the involvement of the initiating VMEbus master (se e “Posted Writes” on

page 45 for a full e xpla nation of thi s opera tion ). With a coup led cycle , the VMEbus

maste r only recei ves data acknowledgment when the trans action is co mplete on t he

PCI bus. This means that the VMEbus is una vaila ble to other masters while the P CI

bus transaction is executed.

Read transactions m ay be either prefetched or coupled. A prefetched read is

initiated when a VMEbus master requests a block read transaction (BLT or MBLT)

and th is mode i s enabled. When th e Universe II r eceives th e b lock re ad request, it

begins to fill its Read Data FIFO (RDFIF O) using burst transactions from the PCI

resource. The initiating VMEbus master then acquires its block read data from the

RDFIFO instead of dir ectly from the PCI resources.

1.2.1.2 Universe II as VMEbus Master

The Universe II becomes VMEbus master when the VMEbus Master Interface is

internally requested by the PCI Bus Target Channel, the DMA Channel, or the

Interrupt Channel. The Interrupt C hannel always has priority over the other two

channels. Several mechanisms are available to configure the relative priority that the

PCI Bus Target Channel and DMA Channel have over ownership of the VMEbus

Master Interface.

The Universe II’ s VMEbus Master Interface generates all of the addressing and data

transfer mode s documented in the VME64 Specification - except A64 and those

intended to a u gment 3U applications. The Universe II is also compatible with all

VMEbus modules conform ing to pre-VME64 specifications.

As VMEbus slave, the Universe II does not assert RETRY* as a

termination of the transaction.

1. Functional Overview

Universe II VME-to-PCI Bus Bridge Manual 33

80A3010_MA001_03

As VMEbus master, the Universe II supports Read-Modify-Write (R MW), and

Address-Only-with-Handshake (ADOH) but does not accept RETRY* as a

termination from the VMEbus slave. The ADOH cycle is used to implement the

VMEbus Lock command allowing a PCI master to lock VMEbus resource s.

1.2.2 PCI Bus Interface

The PCI In terface is a PCI 2.1 Specification compliant interface

1.2.2.1 Universe II as PCI Target

Read transactions from the PCI bus are always processed as coupled transactions.

Write transactions can be either couple d or posted, depending upon the setting of

the PCI bus t arget i mage (s ee “PCI Bus Target Images” on page 87) . With a posted

write transaction, write data is written to a Posted Write Transm it FIFO (TXFIFO)

and the PCI bus master receives data acknowledgment from the Universe II with

zero wait-states. Meanwhile, the Universe II obtains the VMEbus and writes the

data to the VMEbus resource independent of the initiating PCI master (see “Posted

Writes” on page 76 for a full description of this operation).

The Univers e II has a Special Cycle Ge ne rator that ena bles PCI maste rs to perform

RMW and ADOH cycles. The Special Cycle Ge nerator must be used in

combination with a VMEbus ownership function to guarantee PCI masters

exclusive access to VMEbus resources over several VMEbus transaction s (see

“Specia l Cycle Generator ” on page 78 and “Using the VOWN bit” on page 81 fo r a

full description of this functionality).

1.2.2.2 Universe II as PCI Master

The Universe II become s PCI master when the PCI Master I n terface i s internally

requested by the VMEbus Slave Channel or the DMA Channel. There are

mechanisms provided which allow the user to configure the relative priority of the

VMEbus Slave Channel and the DMA Channel.

1.2.3 Interrup te r and Interrupt Handl er

The Universe II has both interrupt generation and interrupt handling capability.

1.2.3.1 Interrupter

The Universe II Interrupt Channel provides a flexible sche me to map interrupts to

the PCI bus or VMEbus I nterface. Interrupts are generated from hardware or

software sources (see “Interrupt Generation” on page 131 and “Interrupt Handl ing ”

on page 136 for a full description of hardware and softwa re sources). Interr upt

sources can be m apped to any of the PCI bus or VM Ebus interrupt output pins.

Interrupt sources mapped to VMEbus interrupts are generated on the VMEbus

interrupt output pins VIRQ_ [7:1]. Whe n a software and hardware source are

assigned to the same VIRQ_ pin, the software source always has higher prior ity.

1. Functional Overview

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Interrupt sources mapped to PCI bus interrupts are generated on one of the INT_

[7:0] pi ns. To be fully P CI compliant, all interr upt sources m ust be routed to a single

INT_ pin.

For VMEbus interrupt outputs, the Universe II interrupter supplies an 8-bit

STATUS/ID to a VMEbus interrupt handler during the IACK cycle. The interr upter

also genera tes an internal interrupt in this situation if the SW_IACK bit, in the PCI

Interr upt Status (LINT _ STAT) registe r, is set to 1 (see “VMEbus Interrupt

Generation” on page 133).

Interrupts mapped to PCI bus outputs are serviced by the PC I interrupt controller.

The CPU determines which interrupt sources are active by rea ding an interrupt

status register in the Universe II. The source negates its interrupt when it has been

serviced by th e CPU ( see “PCI Interrupt Gene ration” on page 131).

1.2.3.2 VMEbus Interrupt Handling

A VMEbus interrupt triggers the Universe II to generate a norm al VMEbus IACK

cycle and generate the specified interrupt output. When the IACK cycle is complete,

the Universe I I releases the VMEbus and the interrupt vector is read by the PCI

resource servicing the interrupt output. Software interrupts are ROAK, while

hardware, and internal interrupts ar e RO RA.

1.2.4 DMA Controlle r

The Universe II has an internal DMA controller for high performance data transfer

between the PCI and VMEbus. DMA operation s between t he source a nd destinat ion

bus are decoupled through the use of a single bidirectional FIFO (DMAFIFO).

Parameter s for the DMA transfer are software configurable in the Universe II

registers (see “DMA Controller” on page 103).

The principal mechanism for DMA transfers i s the same for operation s in either

direction (PCI-to-VMEbus, or VMEbus-to-PCI), only the relative identity of the

source and destination bus changes. In a DMA transfer, the Universe II gains

control of the source bus and reads data into its DMAFIFO. Following specific rule s

of DMAFIFO op eration (see “FIFO Operation and Bu s Ownership” on pa ge 121), it

then acquires the destination bus and writes data from its DMAFIFO.

The DMA controller can be programmed to perform multiple blocks of transfers

using linked-list mode. The DMA works through the transfers in the linked-list

following pointers at the end of each linked-list entry. Linked -list operation is

initia ted through a pointer in a n intern al Universe II register, but the l inked-list itself

resides in PC I bus memory.

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2. VMEbus Interface

This c hapter e xplains the operati on of the VM Ebus Inte r face.Thi s cha pter d isc usses

the following topics:

•“VMEbus Requester” on page 35

•“Universe II as VMEbus Master” on page 39

•“Universe II as VMEbus Slave” on page 43

•“VMEbus Configuration” on page 54

•“Automatic Slot Identification” on page 56

•“System Clock Driver” on page 59

2.1 Overview

The VMEbus Interface inco rporates all o peration s associ at ed with th e VMEbus.

This includes master and slave functions, VM Ebus configuration and system

controller functions.

2.2 VMEbus Re quester

There are different channels in the Universe II which require the use of the

VMEbus. They are referred to as VMEbus requesters and are de scribed in the

following sections.

2.2.1 Internal Arbitration for VMEbus Requests

Different internal channels within the Universe II require use of the VM Ebus: the

Interrupt C hannel, the PCI Target Channel, and the DMA Channel. These three

channels do not directly request the VM Ebus, instead they compete internally for

ownership of the VMEbus Master Interface.

2. VMEbus Interface
Universe II VME-to-PCI B us Bridge Man ual
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2.2.1.1 Interrupt Channel
The Interrupt Channel (refer to Figure 3 on page 31) always has the highes t prior ity 
for a ccess to t he VMEbus Mas ter Interface. The D MA  and PCI Ta rget Ch annel 
requests are handled in a fair manne r. The channel awarded VMEbus mastership 
maintains owner ship of the VMEbus until it is has completed the  transaction. The 
definition of a complete transaction for each channel is in “VMEbus Releas e” on 
page 37. 
The Interrup t Channel  requests the VMEbu s master when i t detects  an enabled 
VMEbus interrupt line asserted and must run an interrupt acknowledge cycle to 
acquire the STATUS/ID.
2.2.1.2 PCI Target Channel
The PCI Target Channel  requ es ts t he VMEbus Master Interface to ser vice the 
following conditions:
• TXFIFO contains a complete transaction
• a coupled cycle request.
2.2.1.3 DMA Channel
The DMA Channel requests the VMEbus Master Interfa ce in the following 
instances:
• the DMAFIFO has 64 bytes available (if it is reading from the VMEbus) or 64 
bytes in its FIFO (if it is writing to the VMEbus), or
• the DMA block is complete (see  “DMA Controller ” on page 103).
In the case of the DMA Channel, the user can optionally use the DMA Channel 
VMEbus-off-timer to further qualify requests from this channel. The 
VMEbus-off-timer controls how long the DMA remains off the VMEbus before 
making another request (see “PCI-to-VMEbus Transfe rs” on page 121).
The Universe II provides a software mechanism for VMEbus acquisition through 
the VMEbus ownership bit (VOWN in the MAST_CTL register, Table 116). When 
the VMEbus ownership bit is set, the Universe II acquires the VMEbus and sets an 
acknowledgment bit (VOWN_AC K in the MAST_CTL register, Table 116) and 
optionally generates an interrupt to the PCI bus (see “VME Lock 
Cycles—Exclusive Ac cess to VMEbus Resources” on page 80). Th e Univers e II 
maintains VMEbus ownership until the ownership bit is cleared. During the 
VMEbus tenure initiated by setting the ownership bit, only the PCI Target Channel 
and Interrupt Channel can access the  VMEbus Master Interface.

2. VMEbus Interface

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2.2.2 Request Modes

The Universe II has configurable request modes of operation, as described in the

following sections.

2.2.2.1 Request Levels

The Universe II is softwa re configurable to request on any one of the four VMEbus

request leve ls: BR3*, BR2*, BR1*, and BR0*. The default setting is for leve l 3

VMEbus request. The request level is a global programming option set through the

VM E bus Release Mode (VRL) field in the Master Cont rol (MAST_CTL) register

(Table 116). The progra mmed request leve l is used by the VMEbus Master Interf ace

regardless of the channel (Interrupt Channe l, DMA Channel, or PCI Target

Cha n nel) currently accessi n g the V MEbus Master Interface.

2.2.2.2 Fair and Demand Modes

The Universe II requeste r may be programmed for either Fair or Demand mode. The

request mode is a global programming option set through the VMEbus Request

Mode (VRM) bits in the MAS T_CTL r egister (Table 116).

In Fair mode, the Universe II does not re quest the VMEbus until the re are no other

VMEbus requests pe nding at its progr am med level. This mode ensures that every

requester on an equal level has ac cess to the bus.

In the default setting of Demand mode, the requester asserts its bus request

regardless of the state of the BRn* line. By re questing the bus freque ntly, requesters

far do wn the daisy cha in may be prevent ed from ever obta ining bus owner ship. This

is referred to as starving those requesters. Note that in order to achieve f airness, all

bus requesters in a VMEbus system must be set to fair m ode.

2.2.3 VMEbus Release

The Universe II VMEbus requester can be configured as either R WD (release when

done) or ROR (release on request) using the VREL bit in the MAST_CTL register

(Table 116). The d efault setting is fo r RWD. RO R means the U niverse II relea ses

BBSY* only if a bus request is pending from another VMEbus master and once the

channel that is the current owner of the VM Ebus Master Interface is done.

Ownership of the bus can be assumed by another channel without re -arbitration on

the bus if there are no pending requests on any level on the VMEbus. When set for

RWD, th e VMEbus Master Interface releases BB SY * when the channel accessing

the VMEbus Master Interface is done (see below). Note that the MYBBSY status

bit in the MISC_STAT register (Table 118) is 0 when th e Universe II ass ert s

BBSY*.

2. VMEbus Interface
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In RWD m ode, the V MEbus is released when the c hannel (fo r example, the  DMA 
Channel) is done , even if another c hannel has a request pe nding (for example, the 
PCI Target Channel). A re-arbitra tion of the VMEbus is re quired for any pending 
channel requests. Each channel has a set of rules that determ ine when it is ‘done’  
with its VMEbus transaction.
2.2.3.1 Transaction Complete
The interrupt is c omplete when a single interrupt acknowledge cycle is complete.
The PCI Target Channel is complete  under the following conditions:
• when the TXFIFO is empty, the TXFE bit is clear (the TXFE bit is set by the 
Universe II in the MISC_STAT register,  Table 118),
• when the maximum number of bytes per PCI Target Channel tenure has been 
reached (as programmed with the PWON field in the M AST_CTL register, 
Table 116)1,
• after each posted write, if the PWON is equal to 0b1111, as programmed in the 
MAST_CTL register, Table 116
• when the coupled cycle is complete and the Coupled Window Timer has 
expired,
• if the Coupled Request Timer (page 75) expires before a coupled cycle is 
retrie d by  a P CI  ma st er, or
• when VMEbus ownership is acquired with the VOWN bit in the MAST_CTL 
register a nd then the VOWN bit is cleared (in other words, if the VMEbus is 
acquired thr ough the use of the VOWN bit, the Universe II does not release 
BBSY* until the VOWN bit is cleared—see “V ME Lo ck Cyc le s—Exclusive 
Access to VMEbus Resour ces” on page 80).
The DMA Channel is complete under the following conditions:
• DMAFIFO full during VMEbus to PCI bus transfers,
• DMAFIFO empty during PCI bus to VMEbus transfers,
• if an error is encountered during the DMA oper ation,
• the DMA VMEbus Tenure Byte Counter has expired, or
• DMA block is complete.
Refer to “FIFO Operation and B us Ownership” on page 121 and “DMA  Error 
Handling” on page 126 for m ore information.
1. This setting is overridden if the VOWN mechanism is used.

2. VMEbus Interface

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Universe II ownership of the VMEbus is not a ffected by the assertion of BCLR*

because it does not monitor BCLR*.

2.3 Universe II as VM Ebus Master

The Universe II becomes VMEbus master under the following circumstances:

1. PCI master acces ses a Uni verse II PCI target image (leading to V MEbus

access) or the DMA C hannel initiates a transaction,

2. Eithe r the Universe II P CI Target Channel or the DMA Channel wins acc ess to

the VMEbus Master Interface through inte rnal arbitration

3. Universe II Master Interface requests and obtains ownership of the VMEbus

The Universe II also becomes VMEbus master if the VMEbus ownership bit is set

(see “VME Lock Cycles—Exclusive Ac cess to VMEbus Resources” on page 80)

and in its role in VMEbus interrupt handling (see “VMEbus Interrupt Handling” on

page 136).

The followin g sections de scribe the func tion of t he Universe II as a VMEbus master

in terms of the different phases of a VMEbus transaction: addressing, data transfer,

cycle termination, and bus release.

2.3 .1 Add ressin g C apabilities

Depending upon the programming of the PCI target image (see “PCI Bus Target

Images” on page 87), the Universe II generates A16, A24, A32, and CR/CSR

address phases on the VMEbus. The address mode and type

(super visor/non-privi leged an d progra m/data) are also progr ammed thr ough the PCI

target image. Address pipelining is provided, except during MB LT cycles. The

VMEbus Specification does not permit pipelining during MBLT cycles.

The addr ess and Addres s Modifier (AM) c odes that are genera ted by the Universe II

are functions of the PCI address and PCI target image programming (see “PCI Bus

Targe t Images” on page 87) or through DMA programming. Table 1 shows the AM

codes used for the VMEbus.

Table 1: VMEbus Address Modifier Codes

Add res s M odi fier Address Bi ts Description

0x3F 24 A24 supervi sory block t ran sf er (BLT)

0x3E 24 A24 supervi sory prog ra m ac ces s

0x3D 24 A24 su per vi so ry data acce ss

2. VMEbus Interface

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0x3C 24 A24 super vi sory 64-bit bl ock tr ans fe r (MBLT)

0x3B 24 A24 non-privil eged block transfer (BLT)

0x3A 24 A24 non-privil eged progr am access

0x39 24 A24 non-privil eged data ac cess

0x38 24 A24 non-privi leged 64-bi t block t ra nsf er (M BLT)

0x37 40 A40BLT [MD32]

0x35 40 A40 lock command (LCK)

0x34 40 A40 access

0x32 24 A24 l ock comm and

0x2F 24 CR/CSR

0x2D 16 A16 su per visory access

0x2C 16 A16 lock com m and

0x29 16 A16 non-privi leged acc ess

0x21 32 or 40 2eVME for 3U bus modules (address size in XAM code)

0x20 32 or 40 2eVME for 6U bus modules (address size in XAM code)

0x10 - 0x1F Un defi ned Use r -def ined

0xF 32 A32 supervi sory block t ran sf er (BLT)

0xE 32 A32 superviso ry program ac cess

0xD 32 A32 supervi sory data access

0xC 32 A32 supervisory 64-b it block transfe r (MBLT)

0xB 32 A32 non-p rivi leged block tr ans fe r (B LT)

0xA 32 A32 non-p rivi l ege d pr ogram acc ess

0x9 32 A32 non-privil eged data ac cess

0x8 32 A32 non-privi leged 64-bi t block t ra nsf er (M BLT)

0x5 32 A32 l ock comm and

0x4 64 A64 l ock comm and

Table 1: VMEbus Address Modifier Codes

Add res s M odi fier Address Bi ts Description

2. VMEbus Interface

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The Universe II generates Address-Only-with-Ha ndshake (ADOH) cycles in

support of lock commands for A16, A24, and A32 space s. ADOH cycles can only

be generated through the Special Cycle Generator (see “Special Cy cle G enerator”

on page 78).

There are two Use r Defined AM codes that can be programmed through the

USER_AM register (Table 119). The USER_AM register can only be use d to

generate and a ccept AM codes 0x10 through 0x1F. The default USER_AM code is

0x10. These AM codes ar e designated as USERAM codes in the VMEbus

Specification. After power-up, the two values in the USER_AM r egister default to

the same VME64 Us er-def ined AM code.

2.3.2 Data Transfer Capab i lities

PCI and VMEbus protocols have different data transfer capabilities. The maximum

data width f or a VMEbus dat a transf e r is pro grammed wi th the VMEbus Maximum

Datawidth (VDW) field in the PCI Target Image control (see Table 44 on page 213).

Fo r example, co nsider a 32-bit PCI transac tion accessing a PCI target image with

VDW set to 16 bits. A data beat with all byte lanes enabled will be broken into two

16-bit cycles on the VMEbus. If the PCI target image is also programmed with

block transfers enabled, the 32-bit PCI data beat will result in a D16 block transfer

on the VMEbus. Write data is unpacked to the VMEbus and r ead data is packed to

the PCI bus data width.

If the data width of the PCI data beat is the same as the maximum data width of the

PCI target image, then the Universe II maps the data beat to an equivalent VMEbus

cycle. For example, consid er a 32 -b it PCI transacti on acc essing a PCI target image

with VDW set to 32 bits. A data beat with all byte lanes enabled is tra nslated to a

single 32-bit cycle on the VMEbus.

0x3 64 A64 bl ock tran sfer ( BLT)

0x1 64 A64 si ngle trans fe r acc ess

0x0 64 A64 64-bit block transfer (MBLT)

If USER_AM code is used with the VMEbus Slave Interface, the cycles

must use 32-bit addressing, and only single cycle accesses are used.

BLTs and MBLTs with USER_AM codes will le ad to unpredictable

behavior.

Table 1: VMEbus Address Modifier Codes

Add res s M odi fier Address Bi ts Description

2. VMEbus Interface

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As the general rule, if the PCI bus data width is less than the VMEbus data width

then there i s no packing or unp acking between the two buse s. The only exception t o

this is during 32-bit PCI multi-data beat transactions to a PCI target image

programmed with maximum VMEbus data width of 64 bits. In this case,

packing/unpacking occurs to make maximum use of the full bandwidth on both

buses.

Only aligned VMEbus transactions are generated, so if the requested PCI data beat

has unaligned, or non-, byte enables, the n it is broken int o multiple aligned VMEbus

transactions no wider than the programmed VMEbus data width. For example,

consider a three-byte PCI data beat (on a 32-bit PCI bus) accessing a PCI target

image with VDW set to 16 bits. The three-byte PCI data beat is broken into three

aligned VMEbus cycles: thr ee si ngle-by te cyc le (th e orderi ng of t he cycles depends

on the arrangement of the b yte enab les in the PCI data beat). If in the above example

the PCI target image has a VDW set to 8-bit, then the three- byte PCI data beat is

broken into three single-byte VMEbus cycles.

BLT/MBLT cycles are initiated on the VMEbus if the PCI target image has been

programmed with this capacity (see “PCI Bus Target Im ages” on page 87 ). The

length of the BLT/M BLT transactions on the VMEbus is determined by the

initia ting PCI transactio n. For exampl e, a single data bea t PCI transaction queu ed in

the TXFIFO results in a single data be at block transfer on the VMEbus. With the

PWON field, the use r can specify a transf er byte count that is queued from the

TXFIFO before the VMEbus Master Interface relinquishes the VMEbus. The

PWON field specifies the minimum tenure of the Universe II on the VMEbus.

However, tenure is extended if the VOWN bit in the MAST_CTL registe r is set (se e

“Using the VOWN bit” on page 81).

During DMA operations, the Universe II a ttempts block tra nsfers to the maximum

length permitted by the VMEbus specification (256 bytes for BLT, 2 Kbytes for

MBLT) and is limited by the VON counter (see “DMA VMEbus Ownership” on

page 110).

The Univer se II pr ovid es i ndivis ible tra nsa ctions with the VMEbus lock commands

and the VMEbus ownership bit (see “VME Lock Cycles—Exclusive Access to

VMEbus Resources” on page 80).

2.3.3 Cycle Terminatio ns

The Universe II accepts BERR* or DTACK * as cycle term inations from th e

VMEbus slave. It does not suppor t RETRY*. The assertion of BERR* indic ates that

some type of system error occurred and the transaction did not c omplete properly.

The assertion of BERR* during an IACK also causes the er ror to be logged.

2. VMEbus Interface
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A VMEbus BERR* received by the Universe II during a coupled transaction is 
communicated to the PCI  master as a Target-A bort. No information is logged if the 
Universe II receives BERR* in a coupled transaction. If an error occurs during a 
posted write to the VMEbus or during an IACK cycle, the Universe II uses the 
V_AMERR register (Table 144) to log the AM code of the transaction (AMERR 
[5:0]), and the state of the IACK* signal (IACK  bit, to indicate whether the error 
occurred during an IACK cycle). The current transaction in the FIFO is purged. The 
V_AMERR register also  records  if multipl e er rors have  occurr ed (with t he M_ERR 
bit), although the actual number of errors is not given. The error log is qualified by 
the value of t he V_STAT bit. The address of the error ed transa ction is latched in the 
V_AERR register (Table 144). Wh en  the Uni verse II receives  a VMEb us error 
during a posted write, it generates an interrupt on the VM Ebus and/or PCI bus 
depending  upon whet her the VER R and LER R interrup ts are  enabled ( see “Interrupt 
Handling” on page 136, Table 95 and Table 96). 
DTACK* signals the successful completion of the transaction. 
2.4 Univers e II as VMEbus Slave
This section describes the VMEbus Sla ve Channel and other aspects of the 
Univ erse II as V MEbu s slave. 
The Universe II becomes VMEbus slave when one of its eight programmed slave 
images or register images are accessed by a VMEbus master. Depending upon the 
programming of th e sl ave image, different poss ible  tr ansactio n type s can res ult ( see 
“VME Slave Image Programming” on page 84).
For reads, the transaction can be coupled or prefetched. Write transactions can be 
coupled or posted. The type of read or write transaction allowed by the slave image 
depends on the programming of that particular VMEbus slave image (se e Figure 4 
below and “VME Slave Image Programming” on page 84). To ensure sequential 
consistency, prefetched reads, coupled reads, and coupled write operations are only 
process ed once all previousl y posted write operat ions have completed (the  RXFIFO 
is empty).
The Universe II cannot refle ct a cycl e on the VMEbus and access itself .

2. VMEbus Interface

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Figure 4: VMEbus Slave Channel Dataflow

Incoming cycle s from the VMEbus can have data widths of 8-bit , 16-bit, 32-bit , and

64-bit. Although the PCI bus supports only two port sizes (32-bit and 64-bit), the

byte lanes on the PCI bus can be individua lly enabled, which a llows each type of

VMEbus transaction to be directly mapped to the PCI data bus.

2.4.1 Coupled Transfers

A coupled transfer means that no FIFO is involved in the transaction a nd

handshakes are relayed directly through the Universe II. Coupled mode is the

default setting for the VMEbus slave im ages.

A coupled cycle with multiple data beats (such as block transfers) on the VMEbus

side is alwa ys mapped to single data bea t transactions on the PCI bus, where each

data beat on t he VMEbus is mappe d to a single data beat transa ction on the PCI bus

regardless of data beat size. No packing or unpacking is performed. The only

exception to this is when a D64 VMEbus transa ction is mapped to D32 on the PCI

bus. The data width of the PCI bus depends on the programming of the VMEbus

slave image (32-bit or 64-bit, see “VM E Slave Image Programming” on page 84).

The Universe II ena bles the appropria te byte lanes on the PCI bus as requir ed by the

VMEbus trans action. For example , a VMEbus slave im age programmed to gene rate

32-bit transactions on the PCI bus is accessed by a VMEbus D08 BLT read

transaction (prefetching is not enabled in this slave image). The transaction is

mapped to single data beat 32-bit transfers on the PCI bus with only one byte lane

enabl ed.

In order for a VMEbus s lave im age to re spond t o an i ncoming c ycle , the

PCI Master Interf ace must be enabled (b it BM in t h e PCI_CSR regi ster,

Table 38). If data is queued in the VMEbus Slave Channel FIFO and the

PCI BM bit is cleared, the FIFO empties but no additional transfers are

received.

Coupled transfers only proceed once all posted write entries in the

RXFIFO have completed (see “Posted Writes”).

RDFIFO

RXFIFO

PCI BUS

MASTER

INTERFACE

VMEbus

SLAVE

INTERFACE

PREFETCHED READ DATA

COUPLED READ DATA

COUPLED WRITE DATA

POSTED WRITE DATA

2. VMEbus Interface

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Target-Retry from a PCI target is not communicate d to the VMEbu s master. PCI

transactions terminated with Target-Abort or Master-Abort are terminated on the

VMEbus with BERR*. The Universe II sets the R_ TA or R_MA bits in the

PCI_CSR register (Table 38) when it receives a Target-Abort or Master-Abort.

2.4.2 Poste d Writes

A posted write involves the VMEbus master writing data into the Universe II’s

RX FIFO, instead of directly to t h e PCI address. Write trans actions from the

VMEbus are processed as posted if the PWEN bit is set in the VMEbus slave image

control register (see “VME Slave Image Program ming” on page 84). If the bit is

cleared (de fault setting) the transaction bypasses the FIFO and is perf ormed as a

coupled transfer. Incoming posted writes from the VMEbus are queued in the

64-entry dee p RXF IFO . Each entry in the RXFIFO can conta in 32 address bits, or

64 data bits. Ea ch incoming VMEbus address phase, whether it is 16-bit, 24-bit, or

32-bit , const itutes a si ngle entry in the RXFIFO and is followed by subsequent da ta

entries. The address entry contains the translated PCI address space and command

information mapping relevant to the particular VMEbus sla ve image that has been

acces sed (see “VM E Slave Image Programm i ng” on page 8 4). For this reason, any

reprogramming of VM Ebus slave image attributes are only reflected in RXF IFO

entries queued after the reprogram ming. Transactions queued before the

re-programming are deliv ered to th e PCI bus with the VMEb us slav e image

attributes that were in use befor e the reprogramming.

2.4.2.1 FIFO Entries

Incoming non-block write transactions from the VMEbus require two e ntries in the

RXFIFO: one address entry (with accompanying command information) and one

data entry. The size of the data entry cor responds to the data width of the VM Ebus

transfer. Block transfers require at least two entries: one entry for address and

command information, and one or more data entries. The VM Ebus Slave Channel

packs data received during block transfers to the full 64-bit width of the RXFIFO .

For example, a ten data phase D16 BLT transfer (20 bytes in total) does not require

ten data e ntries in the RXFIFO. Instea d, eight of t he ten da ta phases (16 bits per data

phase for a total of 128 bits) are packed int o two 64-bit data entries in the RXFIFO.

The final two data phases ( 32 bits combined) are queued in the next RXFIFO entry.

When the address entry is added to the three data entries, this VMEbus block write

has been store d in a total of five RX FIFO entries.

The RXFIFO is th e same structure as the RDFIFO. The d ifferent names

are used for the FIFO’ s two roles. In each FIFO, only one role, either the

RXFIFO or the RDFIFO, can used at one time.

2. VMEbus Interface

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Unlike the PCI Ta rget Ch anne l (see “U niverse II as PCI Target”), the VMEbu s

Slave Channel doe s not retry the VMEbus if the RXF IFO does not have enough

space to hold an incoming VMEbus write transaction. Instead, the DTACK*

response from the VMEbus Slave Inter face is delayed unt il space becom es availa ble

in the RXFIFO. Since single transfers require two entries in the RXFIFO, two

entries must be av ailable before the VMEbus Slave Interface asserts D TACK* .

Similarly, the VMEbus Slave Channel requires two available RXFIFO entries

before it can acknowle dge the fir st data phase of a BLT or MBLT transfe r (one entry

for the addr ess phase and one for the first data phase). If the RXFIFO has no

available space for subsequent data phases in the block transfer, then the VMEbus

Slave Interface de la ys assertion of DTACK* until a singl e entry is available for the

next data phase in the block transfer.

The PCI Master Interface uses transactions queued in the RXFIFO to genera te

transactions on the PCI bus. No address phase deletion is performed, so the length

of a transaction on the PCI bus corresponds to the length of the queued VMEbus

transaction. Non-block transfers are generated on the P CI bus as single data beat

transact ions. Blo ck transfers are generated as one or more burst transacti ons, where

the length of the burst transa ction is program med by the (PABS field in the

MAST_CTL register, Table 116).

The Universe II always packs or unpacks data from the VMEbus transaction to the

PCI bus data width programmed into the VMEbus slave image (with all PCI bus

byte lanes enabled). The data width for a VMEbus transaction to the PCI bus is

programmed in the LD64EN bit in the VMEbus Slave Im age Control register (see

Table 121). The LD64EN bit enables 64-bit PCI bus transactions For example,

consider a VMEbus slave image programmed for posted writes and a D32 PCI bus

that is acce ssed with a VMEbus D16 block write transaction. VMEbus D16 write

transa ctions are mapped to D32 write transa ctions on the PCI bus with all byt e lanes

enabled. (However , a sing le D16 transactio n from the VMEbus is mappe d to the PCI

bus as D32 with only two byte lanes ena bled).

During block tr ansf e rs, the Uni verse II pa cks da ta to the full negotiated width of the

PCI bus. This may imply that for block transfers that begin or end on addresses not

aligned to the PCI bus width different byte lanes may be enabled during each data

beat.

2. VMEbus Interface

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2.4.2.2 Errors

If an error occurs during a poste d write to the PCI bus, the Universe II uses the

L_CMDERR registe r (Table 67) t o log the command informati on for the tr ansaction

(CMDERR [3:0]). The L_CMDERR reg ister als o reco rd s if mult iple errors have

occurred (with the M_ERR bit) although the actual number of errors is not given.

The error log is qualified with the L_STAT bit. The address of the errored

transaction is latched in the LAERR register (Table 68). An interrupt is generated

on the VMEbus and/or PCI bus depending upon whether the VERR and LERR

int er ru pts are enabl ed (see “Error Handli ng” on page 147 and “Interrupt Generati on

and Handling” on page 129).

2.4.3 Prefetched Block Reads

Prefetching of read data occurs for VMEbus block transfers (BLT, MBLT) in those

slave images that have the Prefetch Enable (PREN) bit s et (see “VME Slave Image

Programming” on page 84 ). In the VMEbus Slave Channel, prefetching is not

supporte d for

non- BLT/MBLT transfers.

W ithout pr efetching, blo ck read transactio ns from a VMEbus master are handled by

the VMEbus Slave Channel as c oupled reads. This means that each dat a phase of the

block transfer is translated to a single data beat transaction on the PCI bus. In

additi on, only the amount of data re quested during the rele vant data phas e is fetched

from the PCI bus. Fo r example, a D16 bloc k read transa ction with 32 dat a phases on

the VMEbus maps to 32 PCI bus tra nsactions, where each PCI bus transaction has

only two byte lanes enabled.

The VMEbus lies idle during the arbitra tion time required for each PCI

bus transaction, resulting in a performance degradation.

2. VMEbus Interface

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With prefet ch ing enabled, t he VMEbus Slave Channel uses a 64-entry deep

RDFIFO to provide r ead data to the VMEbus with minim um latency. The RDFIFO

is 64-bit, with additional bits for control inform ation. If a VMEbus slave im age is

programmed for prefetching (see “VM E Slave Image Programming” on page 84),

then a block read access to th at image causes the VME bus Slave Channel to

generate aligned burst read tra nsactions on the PCI bus (the size of the burst read

transactions is determined by the setting of the aligned burst size, PAB S in the

MAST_CTL register). These PCI burst read tra nsaction are queued in the RDFIFO

and the data is then delivered to the VM Ebus. The first data phase provided to the

VMEbus master is essentially a coupled read, but subsequent data phases in the

VMEbus block read ar e delivered from the R D FIFO and are decouple d (see

“Prefetched Reads” on page 150 for the impact on bus error handling).

2.4.3.1 FIFO Entries

When there is a trans act ions from the Univers e PCI Sl ave to the Univers e VME

Master, the da ta width of the transaction on the PCI bus (32-bit or 64-bit) depends

on the setting of the LD64EN bit in the VM Ebus Slave Image Control register (see

Table 121) and the capabilities of the accessed PCI target.

Internal ly, the prefet ched read data i s packed to 64- bit, regar dless of the widt h of the

PCI bus or the data width of the original VMEbus block read (no address

information is stored with the data ). Once one entry is queue d in the RDFIFO, the

VMEbus Slave Inter face delivers the data to the VMEbus, unpacking the data as

necessary to fit with the data width of the original VMEbus block r ead (D16, or

D32).

The VMEbus Slave Inte rface continuously delivers data from the RDFIFO to the

VMEbus master performing the block read transaction. B ec ause PCI bus data

transfer rates exceed those of the VMEbus, it is unlikely that the RDFIFO will be

unable to deliver data to the VMEbus master. For this reason, block read

performance on the VMEbus is simila r to tha t obser ved wit h block wr ites. However ,

if the RDFIFO be unabl e to de liver data to the VMEbus m aster ( which can happen i f

there is considerable traffic on the PCI bus or the PCI bus target has a slow

response) the V MEbus Slave Interface delays DTACK* assertion until an entry is

queued and is available for the VMEbus block re ad.

The RXFIFO is th e same structure as the RDFIFO. The d ifferent names

are used for the FIFO’ s two roles. In each FIFO, only one role, either the

RXFIFO or the RDFIFO, can used at one time.

2. VMEbus Interface

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On the PCI bus, prefetching continues as long as there is room for another

transa ction in the RDFIFO and the initiating VMEbus blo ck read is stil l active . The

space required in the RDFIFO for another PCI burst read transaction is determined

by the setting of the PCI aligned burst size (PABS in the MAST_CTL register,

Table 116). If PABS is set for 32 bytes, there must be four entries available in the

RDFIFO; for aligned burst size set to 64 bytes, eight entries m ust be available, for

aligned burst size set to 128 bytes, t here must be 16 e ntr ies avail abl e. When the re is

insufficient room in the RDF IFO to hold another PCI burst read, the read

transactions on the PCI bus are terminated and only resume if room becomes

available for another aligned burst and the original VMEbus block read is still

active. When the VMEbus block transfer terminates, any rem aining data in the

RD FIFO is removed .

Reading on the PCI bus does not cross a 2048-byte boundary. The PCI Master

Interface releases FRAME_ and the VMEbus Slave Channel relinquishes internal

ownership of the PCI Maste r Inter face when it reach es thi s boundary. The VMEbus

Slave Chan nel re-requests i nternal o wnership of the PCI Maste r Interfa ce as soon as

possible, in order to continue reading from the external PC I target.

Regardless of the read request, the data w idth of prefetching on the PCI side is full

width with all byte l anes enable d. If LD64EN is set in t he VMEbus Slave image , the

Universe II requests D64 on the PCI bus by asserting REQ64_ during the address

phase. If the PCI target does not respond with ACK64_, subsequent data beats are

D32.

2.4.3.2 Errors

If an erro r occurs on the PCI bus, the Univers e II does not trans l ate the error

condition into a BERR* on the VMEbus; the Universe II does not dire ctly map the

error. By doing nothing, the Universe II forces the external VMEbus error tim er to

expire.

2.4.4 VMEbus Lock Commands (ADOH Cycles)

The Universe II supports VMEbus lock commands as desc ribed in the VM E64

Specification. Under the specification, ADOH cycles are used to exe cute the lock

command (with a special AM code, see Table 1 on page 39). The purpose of the

Lock command is to lock the resources on a card so a master on the card cannot

modify the re source. Any r esource locked on the VM Ebus cannot be accessed by

any other resource during the bus te nure of the VMEbus master.

The PABS setting determines how much da ta must be available in the

RDFIFO before the VMEbus Slave Channel continues reading.

2. VMEbus Interface

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When the Uni verse II receives a VMEbus lo ck command, it as serts LO CK_ t o th e

addressed resource on the PCI bus. The PCI Master Interface processes this as a

32-bit read transfer with all byte lanes enabled (no data). All subsequent slave

VMEbus transactions are coupled while the Universe II owns PCI LOCK_. The

Universe II holds the PCI bus lock until the VMEbus lock command is terminated

(by negating BBSY*).

The Universe II accepts ADOH cycles in any of the slave images when the

Universe II PC I Master Interface is enabled (BM bit in PCI_CSR registe r) and the

images are programmed to map tra nsactions into PCI Memory Space.

2.4.4.1 Errors

If an error occurs on the PCI bus, a bus error will occur on the VMEbus because

they are coupled. In the event a bus error occurs on the VMEbus once a LOCK_ has

been e stablished, the VMEbus mas ter whic h locked t he VMEbus must t erminat e the

LOCK_ by negating BBSY*.

2.4.4.2 DMA Access

Once an external VM Ebus masters locks the PCI b u s, th e Universe II DMA do es

not perform transfers on the PCI bus until the bus is unlocked.

2.4.5 VMEbus Read-Modify-Write Cycles (RMW Cycles)

A re ad -modify-write (RMW) cycle allows a VMEbus master to read from a

VMEbus sl ave and then write to the same re source without reli nquishi ng bus tenure

between the two operations. Each of the Universe II slave images can be

programmed to m ap RMW transactions to PCI locked transactions. If the LLRMW

enable bit is set in the selected VMEbus slave image control register (Table 121 on

page 316), then every non- block slave read is mapped t o a coupled PCI locked read.

LOCK_ is held on the PCI bus until AS* is negated on the VMEbus. Every

non-block slave read is assumed to be a RMW since there is no possible indication

from the VMEbus master that the single cycle read is just a read or the beginning of

a RMW.

The VM E bus Slav e Channel has dedicated acce s s to the PC I Master

In te rface du ri ng the locked t ransac tio n.

LOCK_ is negated on the PCI bus when AS* is ne gated on t he VMEbus.

LOCK_ is not negated when AS* is negated if LOCK_ was asserted by

an ADOH/lock command.

RMW cycles are not suppor ted with unaligned or D24 cycles.

2. VMEbus Interface

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If the LLRMW enable bit is not set and the Universe II receives a VMEbus RMW

cycle, the read and write por tio ns of the cycle are treat ed as independent

transactions on the PCI bus (a read followed by a write). The write can be coupled

or decoupled de pending on the state of the PWEN bit in the accessed slave image.

When an external VMEbus Master begins a RMW cycle, at some point a read cycle

appears on the PCI bus. During the time between when the read cycle occurs on the

PCI bus and w hen th e as sociated w ri te cycle occurs on the PCI bus, no DM A

transfers o ccu rs on t h e PCI bu s .

2.4.6 Registe r Acces ses

See “Registers” on page 191 for a full description of r egister mapping and register

access.

2.4.7 Location Monitors

Universe II has four location monitors to support a VMEbus broadca st capability.

The location monitors’ image is a 4-Kbyte image in A16, A24 or A32 space on the

VMEbus. If en abled, an acce s s to a locatio n monitor cau ses the PCI Mas ter

Interface to generate an inter ru p t.

The Location Monitor Control Registe r (LM_CTL, Table 137) controls the

Universe II’s location m onitoring. The EN field of the LM_CTL regis ter enables the

capability. The PGM[1:0] field sets the Program/Data AM code. The SUPER[1:0]

field of the LM_CTL register sets the Supervisor/User AM code to which the

Universe II responds. The VAS[3:0] fie ld of the LM_CTL register specifies the

address spac e that is monitored. The BS[31:12] field of the location monitor Base

Address Registe r (LM_BS, Table 138) specifies the low est address in the 4 Kbyte

range that is decode d a s a loc a tion monitor access. While the Unive r se I I is has f our

location monitors, they all share the same LM_CTL and LM_BS registers.

When an access to a location monitor is detected, an interrupt is generated on the

PCI bus. VMEbus address bi ts [4:3] de termine whic h Location Monitor is used, and

hence which of four PCI interrupts to generate (see “Location Monitors” on

page 144).

The location moni tor s do not st ore wr ite dat a. Read data from the location m onitor s

is undefined. Location monitors do not support BLT or MBLT transfers.

There can be an adve rse performance impact for r eads that a re process ed

through a RMW -ca pable slave image This can be increased if LOCK_ is

currently owned by another PCI master.

In address space s A24 and A16, the respective upper address bits are

ignored.

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Each Universe II on the VMEbus must be programmed to monitor the same 4

Kbytes of addresses on the VMEbus. If the Universe II accesses its own (enabled)

location monitor, the same Universe II generates DTACK* on the VMEbus and

terminates its own cycle. This re moves the necessity of the system integrator

ensuring that there is another card enabled to generate DTACK*. The generation of

DTACK* happens after the Universe II ha s decoded and responded to the cycle. If

the location monitor is accessed by a different master, the Universe II does not

respond with DTACK*.

2.4.8 Generating P CI Confi gu ration Cycle s

PCI Configuration cycles can be genera ted by accessing a VMEbus slave image

whose Local Address Space field (LAS) is set for Configuration Space.

Both Type 0 and Type 1 cycles are genera ted and handled through the same

mechanism. Once a VMEbus cycle is received and mapped to a configuration cycle,

the Universe II compares bits [ 23:16] of the incom ing address with the value stored

in the MAST_CTL Register’s Bus Number field (BUS_NO[7:0] in Table 116). If

the bits are th e same as t he BUS_NO field, then a TYPE 0 access is generated. If

they are not the same, a Type 1 configuration access is generated. The PC I

bus-gene rated addres s then becomes an un signed additi on of the inc oming VMEbus

address an d th e VMEbus s la ve image translation offset.

2.4.8.1 Generating Configuration Type 0 Cycles

The Universe II asse r ts one of AD[31:11 ] on the PCI bus to sel ect a device during a

configuration Type 0 access. To perform a configuration Type 0 cycle on the PCI

bus, the following steps must be completed:

1. Program the LAS field of VSIx_CTL for Configur ation Space

2. Program the VSI x_BS, VSIx_BD registers to some suitable value

3. Program the VSI x_TO register to 0

4. Program the BUS _NO field of the MAST_CTL register to some value

Perfo rm a VMEbus acces s where:

• VA[7:2] identifies the PCI Register Number and will be mapped directly to

AD[7:2]

• VA[10:8] identifies the PCI Function Numbe r and will be mapped directly to

AD[10:8]

ADOH, BLT a nd MB LT cycles must not be attempted when the LAS

field of an image is progr am med for PCI Configuration S pace.

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• VA[15:11] sele cts the device on the PCI bus and will be mapped to AD[ 31:12]

according to Table 2

• VA[23:16] matches the BUS_NO in MAST_CTL register

• Other address bits are not important—they are not ma pped to the PCI bus

Table 2: PCI Address Line Asserted as a Function of VA[15:11]

VA[15:11]a

a. The other values of VA[15:11] are not defined and must

not be used.

PCI Address Line

Assertedb

00000 11

00001 12

00010 13

00011 14

00100 15

00101 16

00110 17

00111 18

01000 19

01001 20

01010 21

01011 22

01100 23

01101 24

01110 25

01111 26

10000 27

10001 28

10010 29

10011 30

10100 31

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2.4.8.2 Generating Configuration Type 1 Cycles

The following steps are used to generate a configura tion Type 1 cycle on the

VMEbus:

1. Program LAS field of VSIx_CTL to Configuration Space

2. Program the VSI x_BS, VSIx_BD registers to some suitable value

3. Program the VSI x_TO register to 0

4. Program the BUS _NO field of the MAST_CTL register to some value

Perfo rm a VMEbus acces s where:

• VMEbus Address[7:2] ide ntifies the PCI Register Number,

• VMEbus Address[10:8] ide ntifies the PCI F unction Number,

• VMEbus Address[15:11] identifies the PCI Device Number,

• VMEbus Address[23:16] does not match the BUS_NO in MAST_CTL register,

and

• VMEbus Address[31:24] are mapped directly through to the PCI bus.

2.5 VMEbus Conf iguration

The Uni verse II provides t he f ollowing func tions t o assis t in t he init ial configur ation

of the VMEbus system:

•First Slot Detector

• Register Access at Power-up

• Auto Slot ID (two methods)

b. Only one of AD[ 31 :11] is asser t ed; th e ot her addr ess

lines in AD[3 1: 11] are neg at ed.

ADOH, BLT and MBLT cycles must not be attempted when the LAS of

an image is progra mmed to PCI Configuration space.

PCI Configuration cycles can only be genera ted when the VAS field in

the appropriate VS Ix_CTRL register is programmed for either A32,

USER1, or USER2.

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2.5.1 First Slot Detector

As specified by the VME64 Specification the First Slot Detector module on the

Universe II sam ples BG3IN* immediately after reset to determine whether the

Universe II’s host board resides in slot 1. The VME64 Specification requires that

BG[3:0]* lines be driven high after reset. This means that if a card is pre ceded by

another card in the VMEbus system, it always sample BG3IN* high after reset.

BG3IN* can only be sampled low after reset by the first card in the system — there

is no preceding card to drive BG3IN* high. If BG3IN* is sampled at logic low

immediately af ter reset (due to the Universe II’s internal pull-down), then the

Universe II’s host board is in slot 1 and the Universe II becomes SYSCON:

otherwise, the SYSCON module is disabled.

The Universe II monitors IAC K*, instead of IACKIN*, when it is conf igured as

SYSCON. This permits it to operate as SYSCON in a VMEbus chassis slot other

than slot 1, pr ovided the re a re only empty s lots to its l eft. The slot with SYSCON i n

it becomes a virtual slot 1.

2.5.2 VMEbus Register Acce ss at Power-up

The Universe II prov ides a VMEbus slave image that allows access to all Univer se

II registe rs. The base address for the slave image is programm ed through the

VRAI_BS register ( Table 139). At power-up, the Universe II can program the

VRAI_BS and VRAI_CTL (Table 139) registers with inform ation specifying the

Universe II Control /Status (UCSR) register slave i mage (see “Power-Up Options ”

on page 160).

This mechanism may be overridden by software through clearing or

setting the SYSCON bit in the MISC_CTL register (Table 117).

Regi ster access at power-up is used in systems wh ere the Universe II’s

card has no CPU, or where register acces s for that card needs to be

independent of the local CPU.

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2.6 Automatic Slot Identification

The Universe II supports two types of Auto-ID functionality. One type uses the

Auto Slot ID te chnique as described in the VME64 Specification. The other type

uses a proprietary method developed by DY4 Systems and implemented in the

Tundra SCV64 and the Universe II. Neither system identifies geographical

addressing, only the relative position amongst the boards present in the system , for

example, fourth board versus fourth slot.

Auto-ID prevents the need for jumpers to uniquely identify cards in a system. This

feat ur e ca n ben efits des igners for the fol lowing reasons:

• increase the speed of system level repairs in th e fi eld

• reduce the possibility of incorr ect configurations

• reduce the number of unique spare cards that must be stocked

2.6.1 Auto Slot ID: VME 64 Specified

The VME64 auto ID cycle, as described i n the VME64 Specification, requires at

power-up that the Auto ID slave takes the following actions:

• generat e IRQ2*

• negate SYSFAIL*

When the Auto ID slave responds to the Monarch’s IACK cycle, the following

actions are taken:

1. ena ble accesses to its CR/CSR space

2. provide a Status/ID to the Monarc h indicating the inter rupt is an Auto-ID

request

3. asser t DTACK*

4. re le ase IRQ 2*

The Universe II par tici p ates in t he VME64 auto ID cycle i n either an automatic or

semi-automat ic mode. I n its ful ly autom atic mode, it hold s SYSFAIL* as serted until

SYSRST* is negated. When SYSRST* is negated, the Universe II asser ts IRQ2*

and releases SYSFAIL*. In its semi-automatic mode, the Universe II still holds

SYSFAIL* asserted until SYSRST* is negated. However, when SYSRST* is

negated , the local CPU performs diagnostics and local logic sets the AUTOID bit in

the MISC_CTL registe r (Table 117). This asserts IR Q2* and releases SYSFAIL*.

Both the VME64 Auto Slot ID and the DY4 method of automatic slot

identificat ion are activa ted through a power-up opti on. Refer “Power-Up

Options” on page 160 for m o re information .

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After SYSFAIL* is released and the Universe II det ects a le vel 2 IACK cycle, it

responds with the STATUS/ID stored in its STATID register. The default value is

0xFE.

The Universe II can be programmed so that it does not release S YSFAI L* until the

SYSFAIL bit in the VC SR_CLR register (Table 162) is clea red by local logic

(SYSFAIL* is assert ed if t he SYSFAIL bit in the VC SR_SET regis ter, Table 162, is

set at power- up). Since the sys tem Monarch does not servic e the Auto-I D slave unti l

after SYSFAIL* is negated, not c learing the SYSFAIL bit a llows the Auto-ID

process to be delayed until the CPU completes local diagnostics. Once loca l

diagnostics are complete, the CP U clears the SYSFAIL bit and the A uto-ID cycle

proceeds.

The Monarch c an perfor m CR/CSR r eads and writ es at A[ 23:19] = 0x00 in C R/CSR

space and re-locate the Uni verse II’s CR/CSR b ase address.

2.6.1.1 Universe II and the Auto-ID Monarch

At power -up an Auto-ID Monarch waits to run a IACK cycle until aft er SYSFAIL*

goes high. After the IACK cycle is performed and it has received a Status/ID

indicating an Auto-ID request, the monarch software does the following:

1. masks IRQ2* (so tha t it will not ser vic e other interrupters at that inte rrupt level

until current Auto-ID cycle is completed)

2. performs an access at 0x00 in CR/CSR space to get info rmation abo ut Auto-ID

slave

3. moves the CR/CSR base address to a new location

4. unmasks IRQ2* (to allow it to service the next Auto-ID slave)

The Universe II supports monarch activity through its ca pability to be a level 2

interrupt handler. All other activity must be handled through softwa re residing on

the board.

2.6.2 Auto-ID : A Prop rietary Tundr a Method

The Universe II uses a proprietary Auto-ID scheme when enabled through a

power-up option (see “Auto-ID” on page 162). The Tundra proprietary Auto-ID

function identifies the relative position of each board in the system, without using

jumpers or on-boa rd informat ion. The ID number generate d by Auto-ID can then be

used to determ ine the board’s base address.

After any system reset (assertion of SYSRST*), the Auto-ID logic responds to the

first le vel one IACK cycle on the VMEbus.

2. VMEbus Interface

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After t he level o ne IACK* s igna l has be en asse rte d (ei the r throu gh IRQ1* or with a

synthes ized versio n), the Univer se II in s lot 1 counts fiv e clocks f rom the start of the

cycle and then asserts IACKOUT* to t he se cond boa rd in the syste m (see Figure 5).

All other boards continue counting until they receive IACKIN*, then count four

more clocks and assert I ACKOUT* to the next board. Finall y, the last board asserts

IACKOUT* and the bus pauses until the data transfer time-out circuit ends the bus

cycle by asse rting BERR*.

Figure 5: Timing for Auto-ID Cycle

Because all boards are four clocks wide, the value in the clock counter is divided by

four to identify the slot in which the board is installed; any remainder is discarded.

Note that since the start of the IAC K cycle is not synchroniz ed to SYSCLK, a one

count variation from the theoretical value of the board can occu r. However, in a ll

cases the ID value of a board is greater than that of a board in a lower slot number.

The result is placed in the DY4AUTOID [7:0] field and the DY4DO NE bit is set

(both are loc ated in the MISC_STAT register, Table 118).

2.6.3 System Contro ller F unctions

When located in S lot 1 of the VMEbus system (see “First Slot Detector” on

page 55), the Universe I I assumes th e role o f SYSCON and sets the SYSCON stat us

bit in the MISC_CTL register (Table 117). In accordance with the VME64

Specification, as SYSCON the Universe II provides the following functions:

• a system clock driver

• an arbitra tion module

• an IACK Daisy Chain Driver (DCD)

• a bus timer

SYSCLK

AS*

DS0✴

IACK✴

IACKOUT✴

(CARD 1)

IACKOUT✴

(CARD 2)

IACKOUT✴

(CARD 3)

D COUNTER

VALUE

CBA

00123456789101112131415

ID = 5

ID = 9

ID = 13

2. VMEbus Interface

Universe II VME-to-PCI Bus Bridge Manual 59

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2.6.3.1 System Clock Driver

The Universe II provides a 16 MHz SYSCLK signal derived from CLK64 when

configured a s SYSCON.

2.6.3.2 VMEbus Arbiter

When the Universe II is SYSCON, the Arbitra tion Module is enabled. The

Arbitration Module supports the following arbitration modes:

• Fixed Priority Arbitra tion Mode (PRI)

• Round Robin Arbitra tion Mode (RRS) (default se tting)

These modes are selected with the VARB bit in th e MISC_CTL register

(Table 117).

2.6.3.3 Fixed Priority Arbitration Mode (PRI)

In this mode, the order of priority is VRBR_[3], VRBR_[2], VRBR_[1], and

VRBR_[0] as de fined by t he VME64 Specification. The Arbitrati on Module issues a

Bus Grant (VBGO [3:0] _) to the highest requesting level.

If a Bus Request of higher priority than the current bus owne r is asserted, the

Arbitra tion Module asse rts VBCLR_ until the owne r relea ses the bus (VRBBSY_ is

negated).

2.6.3 .4 Round Robin Arbitration Mode (RRS)

This mode arbitrates all levels in a round robin mode, by scanning f rom levels 3 to

0. Only one grant is issued per level and one owner is never forced from the bus in

favor of another requester (VBCLR_ is ne ver asserted).

Since onl y one grant i s issue d pe r lev el o n each rou nd robin c ycl e, sever al s cans are

required to service a queue of requests at one level.

2.6.3.5 VMEbus Arbiter Time-out

The Universe II’s VMEbus arbiter can be programmed to time-out if the requester

does not assert BBSY* wit hin a specified per iod. This allows BGOUT to be negated

so that the a rbiter can continue with other requesters. The timer is programmed

using the VAR BTO field in the MI SC_CTL register (Table 117), and can be set to

16 µs, 256 µs, or disabled. The default setting for the timer is 16 µs. The arbitration

time-out timer has a granularity of 8 µs; setting the timer for 16 µs means the timer

can timeout in as little as 8 µs.

2.6.4 IACK Daisy-Chain Driver Module

The IACK Daisy-Chain Driver module is enabled when the Universe II becomes

system controller. This m odule guarantees that IA CKIN* stays high for at least 30

ns as specified in rule 40 of the VME64 spe cification.

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2.6.5 VMEbus Time-out

A programmable bus timer allows users to select a VMEbus time-out period. The

time-out period is programmed through the VBTO field in the MISC_CTL register

(Table 117) and can be set to 16µs, 32µs, 64µs, 128 µs, 256 µs, 512 µs, 1024 µs, or

disabled. The default setting for the timer is 64 µs. The VMEbus Timer module

asserts VXBERR_ if a VM Ebus transaction tim es out (indicated by one of the

VMEbus data strobe s remaining asserted beyond the time-out per iod).

2.6.6 BI-Mode

BI-Mode® (Bus Isolation Mode) is a mechanism for logically isolating the

Universe II from the VMEbus. This mechanism is useful for the following

purposes:

• Implementing hot-standby systems

A system may have two identically configured boards, one in BI-Mode. If the

board that is not in BI-Mode fails, it can be put in BI-M ode while the spare

board is rem oved from BI-Mode.

• System diagnostics for routine maintenance

• Fault isolation in the event of a card fa ilure

The faulty board can be isolated

While in BI-Mode, the Universe II data channels cannot be used to communicate

between VMEbus and PCI (Universe II mailboxes do provide a means of

communication) . The only tra ff ic permitted is t o Universe II register s either through

config u ration cycles, the PCI regi ster image, the VMEbus r eg ister image, or

CR/CSR space. No IACK cycles are generated or responded to. No DMA activity

occurs. Any access to other PCI imag es result in a Target-Ret ry. Access to o ther

VMEbus images are ignored.

Entering BI -Mode has the following effects:

• The VMEbus Master In terface becomes inact ive

PCI Targe t Channel coupled accesses are re tried. The PCI Target Channel

Posted Write s FIFO continues to accept transactions but eventually fills and no

further posted writes are accepted. The DMA FIFO event ually empties or fills

and no further DMA activity takes place on the PCI bus. The Universe II

VMEbus Master does not service interrupts while in BI-Mode.

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• The Universe II does not respond as a VMEbus slave

Except for accesses to the r egister i mage and CR/CSR im age.

• The Universe II does not respond to any interrupt it had outstanding.

All VMEbus outputs from the Universe II are tri-stated, so that the Universe II

are not driving any VMEbus signals. The only exception to this is the IACK

and BG daisy chains which must remain in operation as before.

There are four ways t o cause the U niverse II to en t er BI-Mo de. The Unive rs e II is

put into BI -M ode for the following reasons:

• if the BI-Mode power-up option is selected (See “Power-Up Options” on

page 160 and Table 23 on page 160)

• when SYSRST* or RST_ is asserted any time af ter the Universe II has been

powered-up in BI-Mode

• when VRIRQ_ [1] is asserted, provided that the ENGBI bit in the MISC_CTL

reg ister (Table 117 on page 308) has been set

• when the BI bit in the MISC_C TL register is set

Either of the following actions remove the Universe II fr om BI-Mode:

• Power-up the Universe II with the BI-Mode option off (see “ BI-Mode” on

page 163), or

• clear the BI bit in the MISC_CTL register.

This is effective only if the source of the B I-Mode is no longer active. If

VRIRQ_ [1] is still being asserte d while the ENGBI bit in the MISC_CTL

does not work.

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3. PCI Interface

Peripher al Component Int erconnect (PCI) i s a bus pr otocol t hat defines how devices

communicat e on a peripheral bus an d with a host processor. If a devi ce is referred to

as PCI compliant it must be compliant with the PC I Local Bus Specification

(Revision 2.1). The Universe II PCI bus supports frequencies up to 33 MHz, and

32-bit or 64-bit transfe rs.

This c hapter des cribes the Un iverse II ’s PCI Interface. This chapter d iscuss es the

following topic s:

•“PCI Cycles” on page 64

•“Universe II as PCI Maste r” on page 68

•“Universe II as PCI Target” on page 72

3.1 Overview

The Universe II PCI Bus Interface is a direct ly connected to the P CI bus. For

information concerning the different types of PCI accesses available, see “PCI Bus

Target Images” on page 87.

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3.2 PCI C ycles

The PCI Bus Interface of the Universe II op erates as a PCI com pliant po rt with a

64-bit multiplexed address/data bus. The Universe II PCI Bus Interface is

configured as little-endian using address invariant translation when m apping

between the VMEbus and the PCI bus. Address invariant translation preserves the

byte ordering of a data structure in a little-e ndian memory map and a big-endia n

memory map (see “Endian Mapping” on page 401 and the PCI 2.1 Specification).

Universe II PCI cycles are synchronous, meaning that bus and control input signals

are externa lly synchronized to the PCI clock (CLK). PCI cycles a re divided into

four phases:

5. Request

6. Address phase

7. Data transfer

8. Cycle terminat ion

3.2.1 32-Bit Versus 64-Bit PCI

The Universe II is configured with a 32-bit or 64-bit PCI data bus at power-up ( see

“PCI Bus Width” on page 164).

Each of the Unive rse II’s VMEbus slave images can be programmed so that

VMEbus transactions are mapped to a 64-bit data bus on the PCI Interface through

the LD64EN bit, in the DMA Tr ansfer Control (DCTL) register (see Table 85 on

page 263). If the VMEbus slave image is programmed with a 64-bit PCI bus data

width and Univer se II is powered-up in a 64-bit PCI environment, the Universe II

asserts REQ64_ during the address pha se of the PCI transaction.

If the VMEbus slav e images are not progra mmed fo r a 64-bit wide PCI data bus,

then the Universe operates transparently in a 32-bit PCI environment.

The Universe II has all the PCI signals described in the PC I 2.1

Specification) with the exception of SBO_ and SDONE (since the

Universe II does not provide cache support).

REQ64_ is asserte d if LD64EN is set in a 64-bit PCI system

independent of whe ther the Universe II has a full 64-bit transf er. This

can result in a performance degradation because of the extr a clocks

required to a ssert REQ64_ and to sample ACK64_. Also, there can be

some performance de gradation when accessing 32-bit targets with

LD64EN set. Do not set this bit unless there ar e 64-bit targets in the

slave image window.

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Independent of the setting of the LD64EN bit, the Universe I I never attempts a

64-bit cycle on the PCI bus if it is powered-up as a 32-bit de vice.

3.2.2 PCI Bus Request an d P arki ng

The Universe II supports bus parking. If the Universe II re quires the PCI bus it

asserts REQ_ only if its GNT_ is not curre ntly asserted. When the PCI Master

Module is rea dy to begin a transaction and its GNT_ is asserted, the transfer begins

immediately. This eliminates a possible one clock cycle delay before beginning a

transaction on the PCI bus which would exist if the Universe II did not implement

bus parking.

Refer to the PCI 2.1 Specification for mor e i n formation

3.2.3 Addres s Phase

PCI transactions are initiated by asserting FRAME_ and driving a ddress and

command information onto the bus. In the VMEbus Slave Channel, the Universe II

calculates the address for the PCI transaction by a dding a translation offset to the

VMEbus address (see “Universe II as VMEbus Slave” on page 43).

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The command signals (on the C/BE_ lines) contain information about M emory

space, c ycle type and whet her the tr ansaction i s re ad or writ e. Table 3 shows the P CI

command type encoding implemented with the Universe II.

Memory Read Multip le and Memory Rea d Line tr a nsact ions a re ali ased to Memory

Read transactions w hen the U niverse II is accessed as a PCI target with t hese

commands. Likewise , Memory W rite and I nvalidate is a liased to Memory Write . As

a PCI maste r, the Universe II can genera te Memory Read Multiple but not Memory

Read L ine.

Table 3: Command Type Encoding for Transfer Type

C/BE_ [3:0] for

PCI, C/BE_ [7:4 ]

for

non-multiplexed Co mma nd Type Univers e II Capability

0000 Interr upt Ackn owled ge N/A

0001 Special Cycle N/A

0010 I/O Read Target/Ma st er

0011 I/O Wri te Target /Ma st er

0100 Reserved N/A

0101 Reserved N/A

0110 Memory Read Target/Master

0111 M emor y Wri t e Targe t/Master

1000 Reserved N/A

1001 Reserved N/A

1010 Configuration Read Target/Master

1011 Configuration Write Target/Master

1100 Memory Read Multip le (See Te xt )

1101 Dual Address Cycle N/A

1110 Memory Re ad Line (See Text)

1111 Memory Write an d In vali dat e (See Text)

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PCI targets must assert DEVSEL_ if they have decoded the ac cess. During a

Configuration cycle, the target is selected by its particular ID Select (IDS EL). If a

target does not respond with DEVSEL_ within six clocks, a Master-Abort is

generated. The role of config uration cycles i s de scr ibe d i n t he PCI 2.1 Specifi cation.

3.2.4 Data Transfer

Acknowledgment of a data phase occurs on the first rising c lock edge after both

IRDY_ a nd TRDY_ are asserted by the master a nd ta rget , respect ively. REQ64_ c an

be driven during the address phase to indicate that the master wishes to initia te a

64-bit transaction. The PCI target asserts ACK64_ if it is able to respond to the

64-bit transaction.

Wait cycles are introd uced by either th e master or the target by deassertin g IRDY_

or TRDY_. For write c ycles, data is valid on the first rising e dge after IRDY_ is

asserted. Data is acknowledged by the target on the first rising edge with TRDY_

asserted. For read cycles, data is transferred and acknowledge d on first rising edge

with both IRDY_ and TRDY_ asserted.

A singl e d ata tran sfer cycle is repeated ev ery tim e IRDY_ and TRDY_ are both

asserted. The transaction only e nters the termination phase when FRAME_ is

deasserted (m aster-initiated termination) or if STOP _ is asserted (target-initiated).

When both FRAME_ and IRDY_ are deasserted (final data phase is complete), the

bus is define d as idle.

3.2.5 Termination Phase

The PCI Bus Interface permits the following types of PCI ter minations:

1. Master-Abort: the PC I bus master negates FRAME_ when no target responds

(DEV SEL_ not asserted) after six clock cycles.

2. Tar ge t-Disc onnect : a ter minati on is reque sted by the tar g et (S T OP_ is asse rte d)

because it is unable to respond within the latency re quirements of the PCI

specification or it requires a new address phase.

• Target-Disconnect with data: means that the transaction is terminated after

data is transferred. The Universe II deasserts REQ_ for at least two clock

cycles if it re ceives S TOP_ from the PCI targe t.

• Target-Disconnect without data: means that the transaction is terminated

before data is transfe rred. The Universe II deasserts REQ_ for at leas t two

clock cycles if it rece ives STOP_ fr om the P CI t arget.

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3. Target-Retry: termination is requested (STOP_ is asserted) by the target

because it c annot currently process the transaction. Retry means that the

transaction is terminated after the address phase without any data transfer.

4. Target-Abort: is a modified version of target-disconnect where the target

requests a te rmination (asser ts STOP_) of a transaction which it will never be

able to respond to, or during which a fatal error occurred. Although there may

be a fatal error for the initiating application, the transaction completes

gracefully, ensuring normal PCI ope ration for other PCI resources.

3.2.6 Parity Checking

The Universe II both monitors and ge nerates parity informa tion using the PAR

signal. The Universe II monitors PAR when it accepts data as a master during a read

or a target during a write . The Universe II drive s PAR when it provides data as a

target during a read or a master during a write. The Universe II also drives PAR

during the address phase of a transaction when it is a master and monitors PAR

during an addre ss phase when it is the PCI target. In both address and data phases,

the PAR signal provides even parity fo r C/BE_[3:0] and AD[31:0] . The Universe II

continues with a transaction independe nt of any parity error reported during the

transaction.

The Universe II can also be programmed to report address parity errors. It doe s this

by asser ting t he SERR_ signal a nd se tti ng a status bit in its regi sters. No inte r rupt is

generated, and regardless of whether a ssertion of SERR_ is enabled, the Universe II

does not respond to the errored access.

Universe II reports parity errors during all transactions with the PERR_ signal. The

Universe II drives PERR_ high within two clocks of receiving a pa rity error on

incoming data, a nd holds PERR_ for at least one clock for each errore d data phase.

3.3 Univers e II as PCI Master

The Universe II requests PCI bus mastership through its PCI Master Interface. The

PCI Master Interface is available to either the VMEbus Slave Channel (access from

a remote VMEbus maste r) or the DMA Channel.

The VMEbus Slave Channel makes an internal request for the PCI Master Interface

when the following conditions are met:

• RXFIFO contains a complet e transaction,

When the Universe II is powe red-up in a 64-bit PCI environment, it

uses PAR64 in the same way as PAR , except for AD[63:32] and

C/BE[7:4].

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• sufficient data exists in the RXFIFO to generate a transa ction of le ngth defined

by the programmable aligned burst size (PABS)

• there is a couple d cycle request

The DMA Channel makes an internal request for the PCI Master Interface when the

following conditions are met:

• the DMAFIFO has room for 128 bytes to be read from PCI

• the DMAFIFO has queued 128 bytes to be written to PCI

• the DMA block is completely queued during a write to the PCI bus

Arbitration between the two channels for the PCI Master Interfac e follows a round

robin protocol. Each channel is given access to the PCI bus for a single transaction.

Once that tra nsaction completes, owner ship of the PCI Master Interface is granted

to the other channel if it requir es the bus. The VMEbus Slave Channel and the DMA

Channel each ha ve a set of rules that determine when the transaction is complete

and the channe ls no longer need the PCI Master Interface. The VMEbus Slave

Channel is done under the following conditions:

• an entire transaction (no greater in le ngth than the programmed aligned burst

size) is emp t ied from the RX FIFO

• the coupled cycle is c omplete

The DMA Channel is finish ed with the PCI Master Interface when the follow i ng

conditions are met:

• the boundary programmed into the PCI aligne d burst size is em ptied from the

DMAFIFO during writes to the PCI bus

• the boundary programmed into the PCI aligned burst size is queued to the

DMAFIFO during rea ds from the PCI bus

Access from the VMEbus can be either c oupled or dec ouple d. For a f ull des cript ion

of the oper at ion of the se data paths, se e “Universe II as VMEbus S lave” on pa ge 43.

3.3.1 Com mand Types

The PCI Master Interface can generate the following command types:

• I/O Read

• I/O Write

• Memory Read

• Memory Read Multiple

• Memory Write

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• Configuration Read (Type 0 and 1)

• Configuration Write (Type 0 and 1)

The type of cyc le the Universe II generates on the PCI bus depe nds on which

VMEbus slave image is accessed and how it is programmed. For example, one slave

image might be programmed as an I/O space, another as Memory space and another

for Configur ation space (see “VME Slave Image Pr ogr amming” on page 84). When

generating a memory transaction, the addressing is either 32-bit or 64-bit aligned,

depending upon the PCI target. When generating an I/O transaction, the addressing

is 32-bit aligned and all inc oming transactions are coupled.

3.3.2 PCI Burst Transfers

The Universe II generates aligned burst transfers of some maximum alignment,

according to the programmed PCI aligned bur st size (PABS field in the

MAST_CTL register, Table 1 16) . The PCI aligned burst siz e can be progr ammed at

32, 64 or 128 bytes. B urst transfers do not cross the programmed boundaries. For

example, when program med for 32-byte boundaries, a new burst begins at

XXXX_XX20, XXXX_XX40, etc. If necessary, a new burst begins at an address

with the programmed alignment. T o o ptimize PCI bus usage, the Universe II always

attempts to transfer data in aligned bursts at the full width of the PCI bus.

The Universe II can perform a 64-bit data transfer over the AD [63:0] lines, if

operated in a 64-bit PCI environment or against a 64-bit capable target or master.

The LD64EN bit m u st be set if the access is being made through a VMEbus slave

image; the LD64EN bit m ust be set if the access is being perform ed with the DMA.

The Universe II generates burst cycles on the PCI bus if it is performing the

following tasks:

• when the RXFIFO is emptying, the TXFE bit in the MISC_STAT register is

clear

• filling the RDFIFO receives a block read request from a VMEbus master to an

appropriate ly programmed VMEbus slave image

• performing DMA transfers

All other accesses are treated as single data beat transactions on the PCI bus.

During PCI burst transactions, the U niverse II dynamically enables byte lanes on

the PCI bus by changing the BE_ signals during each data phase.

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3.3.3 Termination

The Universe II performs a Master-Abort if the target does not respond within six

clock cycle s. Coupled PCI transactions terminated with Target-Abort or

Master-Abort ar e t erminated on the VM Ebus wit h BERR*. T he R_TA or R_MA

bits in the PCI_C S regist er (Table 38) are set when the Univ erse II receives a

Target-Abort or generates a Ma ster-A bort independent of whether the transaction

was coupled, dec oupled, prefetched, or initiated by the DMA.

If the Univer se II receives a retry from the PCI target, then it relinquishes the PCI

bus and re-requests within three PCI clock cycles. No other transactions are

processed by the PCI Master Interface until the retry condition is cleared. The

Universe II can be programmed to perform a maximum number of retries using the

MAXRTRY field in the MAST_CTL register (Table 116). When this number of

retries ha s been reached, the Universe II responds in the same way as it does to a

Target-Abort on the PCI bus. The Universe II can issue a B ERR * signal on the

VMEbus. All VMEbus slave coupled tr ansactions and decoupled transactions

encounte r a dela yed DTACK once the FIFO fills unti l t he conditi on clea rs eit her due

to success or a retry time-out.

If the error occurs during a poste d write to the PCI bus (se e also “Error Handling”

on page 147), the Universe II uses the L_CMDERR register (Table 67) to log the

command information for the transaction (CMDER R [3:0]) and the address of the

errored transaction is latched in the LAERR register (Table 68). The L_CMDERR

number of errors is not given. The error log is qualified with the L_STAT bit. The

rest of the transaction is purged from the RXFIFO if some portion of the write

encounters a n error. An interrupt is generated on the VMEbus and/or PCI bus

depending upon whet her the VER R and LER R interrup ts are enabled ( see “Interrupt

Generation and Handling” on page 129).

If an erro r occurs on the PCI bus, the Univers e II does not trans l ate the error

condition into a BERR* on the VMEbus; the Universe II does not dire ctly map the

error. By ta king no action, the Universe I I forc es the e xternal VMEbu s error timer to

expire.

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3.3.4 Parity

The Universe II monitors PAR w h en it accepts d ata as a mas ter during a read and

drives PA R when it provides data as a master during a write . The Universe II also

drives PA R during the address phase of a transaction when it is a master. In both

address and da ta phases, the PAR signal pr ovides even parity for C/BE_[3:0] and

AD[31:0].

The PERESP bit in the PCI_CS register (Table 38) determines whether or not the

Universe II responds to parity errors as P CI master. Data parity errors are re ported

through the assertion of PERR_ if the PER ESP bit is set. Regardless of the setting

of these two bits, the D_PE (Detected Parity Error) bit in the PCI_CS r egister is set

if the Universe II encounters a parity error as a master. The DP_D (Data Parity

Detected) bit in the same register is only set if pa rity checking is ena bled through

the PERESP bit and th e Universe II de tect s a parity e rro r whil e it is P CI master (i. e.

it asserts PERR_ during a read transac tion or receives PERR_ dur ing a write).

No interrupts are generated by the Universe II in response to parity errors r eported

during a transaction. Parity errors are reported by the Universe II through assertion

of PERR_ and by setting the appropriate bits in the PCI_CS register. If PERR_ is

asserted to the Universe II while it is PCI master , the only action it ta kes is to set the

DP_D. The Universe II continues with a transaction independent of any parity

errors reported during the transaction.

As a master, the Universe II does not monitor SERR_. It is expected t h at a central

resource on the PCI bus monitors SERR_ and take appropriate action.

3.4 Universe II as PCI Target

The Universe II becomes PCI bus target when one of its nine programmed PCI

target images, or one of its registers, is accessed by a PCI bus master. The

Universe II c anno t acces s its own imag es or reg ister s and master th e PCI bus. Refer

to “Registers” on page 191 for more i nformation o n registe r accesses .

When one of its PC I target images is accessed, the Universe II responds with

DEVSEL_ within two cloc ks of FRAME_. This makes the Universe II a medium

speed device, as reflected by the DEV SEL field in th e PCI_C S register).

3.4.1 Command Types

As PCI target, the Universe II responds to the following command types:

• I/O Read

When the Universe II is powered -up in a 64-bit PCI environment , it uses

PAR 64 in the same way as PAR , except for AD[63:32] and C/BE[7:4].

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• I/O Write

• Memory Read

• Memory Write

• Configuration Read ( Type 0)

• Configuration Write (Type 0)

• Memory Read Multiple (aliased to Memory Read)

• Memory Line Read (aliased to Memory Read)

• Memory Write and Invalidate (aliased to Memory Write)

Type 0 Configuration accesses can only be made to the Universe II’s PCI

configuration registers. The PCI target images do not accept Type 0 accesses.

Address parity errors are reported if both PERESP and SERR_EN are set in the

PCI_CS register (Table 38). Address parit y errors a re reported by th e Universe II by

asserting the SERR_ signal and setting the S_SERR (Signalled SERR_) bit in the

PCI_CS regis ter. Assertion of SERR_ can be disabled by c learing the SERR_EN bit

in the PCI_CS register. No interrupt is generated, and regardless of whether

assertion of SERR_ is enabled or not, the Universe II does not respond to the access

with DEVSEL_. Typically, the master of the transaction times out with a

Master-Abort.

If the Universe II is accessed with REQ64_ in Memory space as a 64-bit targ et, then

it responds with ACK64_ if it is powered up as a 64-bit device.

3.4.2 Data Transfer

Read transaction s are alwa ys coupled, as oppose d to VMEbus slave reads which can

be pre-fet ched ( see “Unive rse II as VMEbus Slave” on page 43). W rite transactions

can be coupled or posted (see Figure 6 and “PCI Bus Ta rget Images” on page 87).

To ensure sequential consistency, coupled operations (reads or writes) are only

process ed onc e al l pr eviously posted wr ite oper ations have completed (t he TXF IFO

is empty).

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Figure 6: PCI Bus Target Cha nnel Dataflow

The PCI bus and the VM Ebus can have different data width capabilities. The

maximum VMEbus data width is programmed into the PCI targe t image through the

VDW bit in the PCI Target I mage C ontrol register (Table 44 on page 213). For

example, consider a 32-bit PCI transaction accessing a PCI target image with VDW

set to 16 bits. A data beat with all byte lanes enabled will be broken into two 16-bit

cycles on the VM Ebus. If the PCI target image is also programm ed with block

transfers enabled, the 32-bit P CI data beat will re sult in a D16 block transfer on the

VMEbus. Write data is unpa cked to the VMEbus and r e ad dat a is packe d to t he PCI

bus data width.

If the data width of the PCI data beat is the same as the maximum data width of the

PCI target image, then the Universe II maps the data beat to an equivalent VMEbus

cycle. For example, consid er a 32 -b it PCI transacti on acc essing a PCI target image

with VDW set to 32 bits. A data beat with all byte lanes enabled is tra nslated to a

single 32-bit cycle on the VMEbus.

If the PCI bus data width is less than the VMEbus da ta width then there is no

packing or unpacking between the two buses. The only exception to this is during

32-bit PCI mu lti-dat a beat transacti ons to a P CI target imag e programmed with

maximum VMEbus data width of 64 bits. In this case, packing/unp acking occu rs to

make maximum use of the full bandwidth on both buse s.

Only aligned VMEbus transactions are generated, so if the requested PCI data beat

has unaligned or non-contiguous byte enables, then it is broken into multiple

aligned VMEbus transactions no wider than the programmed VMEbus data width.

For example, consider a three-byte PC I data beat (on a 32-bit PC I bus) accessing a

PCI target image with VDW set to 16-bit. The three-byte PCI data beat will be

broken into three aligned VMEbus cycles: three single-byte cycle s. If in the above

example the PCI target image ha s a VDW set to 8-bit, then the three-byte PCI data

beat will be broken into three single-byte VMEbus cycles.

TXFIFO

PCI BUS

SLAVE

INTERFACE

VMEbus

MASTER

INTERFACE

COUPLED WRITE DATA

POSTED WRITE DATA

COUPLED READ DATA

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3.4.3 Coupled Transfers

The PCI Target Channel supports coupled transfers. A coupled tra nsfer through the

PCI Target Chan nel is a tr ansfer between PCI and VME where the Universe II

maintains ownership of the VMEbus from the beginning to the end of the transfer

on the PCI bus, and where the termination of the cycle on the VMEbus is relayed

directly to the PCI master in the normal manner (Target-Abort or Target

Completion), rather than through err or-logging and interrupts.

By default, all PCI target image s are set for coupled transfers. Coupled transfers

typically cause the Universe I I to go through thr ee phases: the Coupled

Data-Transfer Phase, and the n the Coupled Wait Phase. When an external PCI

Master attem pts a data transfer through a slave image programmed for c oupled

cycles, and the Universe II currently owns the VM Ebus, the PCI Target Channel

moves directly to the Coupled Data-Transf er Phase

3.4.3.1 Coupled Data-Transfer Phase

At the beginning of the Coupled Data-Transf er Phase, the Universe II latches the

PCI command, byte enable, a ddress and (in the case of a write) data. Regardless of

the state of FRAME_, the Universe II retries1 the master, and then per forms the

transact ion on the VMEbus. The Universe II continue s to signa l Tar ge t-Retr y to the

external PCI master until the transfer completes on the VMEbus.

If the tra nsfer completes normally on the VMEbus then, in the case of a read, the

data is transm itted to the PCI bus m aster. If a data phase of a coupled transfe r

requires packing or unpacking on the VM Ebus, acknowledgment of the transfer is

not given to the PCI bus master until all data has been packed or unpacked on the

VMEbus. Successful termination is signalled on the PCI bus—the data beat is

acknowledged with a Target-Disconne ct, forcing all multi-beat transfers into single

beat. At this point, the Universe II ente rs the Coupled Wait Phase.

If a bus error is signalled on the VM Ebus or an error occurs during packing or

unpacking, the n the transaction is terminated on the PCI bus with Target-Abort.

For more informa tion refer to “Data Transfe r” on page 73.

1. PCI latency requirements (as described in revision 2.1 of the PCI Specif icat ion) re qu i r e t h at on ly 16 clock

cycles can elapse between the first and second data beat of a transaction. Since the Universe II cannot guarantee

that data acknowledgment will be received from the VMEbus in time to meet these PCI latency requirements,

the Universe II performs a target-disconnect after the first data beat of every coupled write transaction.

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3.4.3.2 Coupled Wait Phase

The Coupled Wait Phase is entered after the successful completion of a Coupled

Data-Transfer phase. The Coupled Wait P h ase allows cons ecutive coupled

transact ions to oc c ur without releasing the VMEbu s. If a new c ouple d tra nsact ion i s

attempt ed while the Univ erse II is in the C oupled Wait Phase, the Universe II moves

directly to the Coupled Data-Transfer Phase.

The Coupled Window T imer deter mines t he maximum duratio n of the Coupled Wait

Phase. When the Universe II enters the C oupled Wait Phase, the C oupled Window

Timer starts. The pe riod of this timer is specified in PCI clocks and is

programmable thr ough the CWT field of the LMISC register (Table 65). If this f ield

is programmed to 0000, the Universe II does an early r elease of BBSY* during the

coupled transfer on the VMEbus and will not enter the Coupled Wait Phase. In this

case, VMEbus ownership is relinquished immedia tely by the PCI Target Channel

after eac h coupled cycle.

Once the tim er associated w ith t he Coupl ed Wai t P hase expi res, the Universe II

releases the VMEbus if release m ode is set for RWD, or the release mode is set for

ROR and there is a pending (external) request on the VMEbus.

3.4.4 Poste d Writes

Posted writes are enabled for a PCI t arget image by setting the PWEN bit in th e

control register of th e PCI ta rget im age (see “PCI Bus Target Images” on page 87)

to 1 and setting the LAS bit to 0. W r ite transa ctions a re relaye d from the PCI bus to

the VMEbus through a 64-entry deep TXFIFO. The TXFIFO allows e ach entry to

contain 32 address bits (with extra bits provided for command information), or to a

full 64-bit width. For each posted write transaction received from the PCI bus, the

PCI Target Interface queues an address entry in the FIFO. This entry contains the

transla ted a ddre ss sp ace a nd mapped VM Ebus a tt ri butes information re levant to the

particular PCI target image that has been accessed (see “PCI Bus Target Images” on

page 87). For this reason, any reprogramming of PCI bus target image attributes

will only be reflected in TXFIFO entries queued after the reprogramming.

Transactions queued before the re-programming are delivered to the VMEbus with

the PCI bus target image attributes that were in use before the reprogramming.

Care must be taken before reprogramming tar get images. To ensure the

FIFO is empty there are the following possible options:

• Perform a coupled read. The coupled re ad does not

complete until a ll posted-write data has been queued

• Read the MISC_STAT register until the TXFE bit

has a value of 0

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3.4.4.1 FIFO Entries

Once the address phase is queued in one TXFIFO entry, the PCI Target Inte rface

may pack the subsequent data beats to a full 64-bit width before queuing the data

into new entries in t he TXFI FO.

For 32-bit PCI transfers in the Universe II, the TXFIFO accepts a single burst of one

address phase and 59 data phases when it is empty. For 64-bit PCI, the TXFIFO

accepts a single burst of one address phase and 31 data phases when it is em pty. To

improve PCI bus utilization, the TXF IFO does not accept a new address phase if it

does not have room for a burst of one address pha se and 128 bytes of data. If the

TXFIFO does not have e nough space for an aligne d burst, then the posted write

transaction is terminated with a Target-Retry immediately after the address phase.

When an external P CI Master posts w rites to the PCI Target Channel of the

Universe II, the Universe II issues a disconnect if the addr ess crosses a 256-byte

boundary.

Before a transaction ca n be delivered to the VMEbus from the TXF IFO, the PCI

Targe t Channel must obt ain ownershi p of the VMEbus Mast er Interface. Owne rship

of the VMEbus Master Interface is grante d to the different channels on a round

robin basis (see “VMEbus Release” on page 37 ). Once the PCI Target Channel

obtains the VM Ebus through the VMEbus Master Interface, the manner in which

the TXFIFO entries are delivered depends on the programming of the VMEbus

attributes in the PCI target image (see “PCI Bus Target Images” on page 87). For

example, if the VMEbus data width is programmed to 16-bit, and block tran sfers are

disabled, the n each data entry in the TXFIF O corresponds to four transactions on

the VMEbus.

If block transfers are enabled in the PCI targe t image, th en each t ransaction queu ed

in the TXFIFO, inde pendent of its length, is delivered to the VMEbus as a block

transfer. This means that if a single data beat transactio n is queued in the TXF IFO, it

appears on the VMEbus as a single data phase block transfer.

Any PCI master attempting coupled transa ctions is retried while the TXFIFO

contains data. If posted writes are continually written to the PCI Target Channel by

another master, and the FIFO does not empty, coupled transactions requested by the

first PCI master in the PCI Target Channel does not proc eed and are continually

retried. This presents a potential starvation scenario.

This functionality is intended to support earlier ve rsions of PCI-to-PCI

bridges.

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3.4.5 Spec ial Cycle Gen erator

The Special Cycle G enerator in the PCI Ta rget Ch annel of the U niverse II can be

used in conjunction with one of the PCI Target Images to generate

Read-Modify-Write (RMW) and Address Only With Handshake (ADOH) cycles.

The address pr ogrammed into the SCYC_ADDR register (Table 61), in the address

space speci fied by th e LAS fie ld of the S CYC_CTL re gist er ( Memory or I/O), mus t

appear on the PCI bus during the addr ess phase of a transf er for the Special Cycle

Generator to perform its function. Whe never this address on the PCI bus (bits

[31:2]) is used to m atches the a ddress in the SCYC_ADDR registe r, the Universe II

does not respond with ACK64_ (since the Special Cycle Generator only processes

up to 32-bit cycles).

The cycle tha t is produced on the VMEbus use s attributes programm ed into the

Image Control R egister of the image that contains the address programmed in the

SCYC_ADDR register.

The Special Cyc le Generator is configured through the register fields shown in

Table 4.

The following se ctions describe the specific pro perti es for eac h of the tra nsfer types:

RMW and ADOH.

Table 4: Register Fields for the Special Cycle Generator

Field Register Bits Description

32-b it add res s ADDR in Tabl e 61 Speci f ies PC I bus targ et image add re ss

PCI Address

Space LAS in Table 60 Specifie s whether the ad dress specified in the A DDR

field lies in PCI memory or I/O space

Special cyc le SCYC[1:0] in Table 60 Disabled, RMW or ADOH

32-b it ena bl e EN [31: 0] in Table 62 A bit ma sk t o sel ect the bits to be mo dified in the

VMEb us r ead data durin g a R M W cy cl e

32-b it compare CM P [ 31:0] in Table 63 Data which is compared to the VM Ebus read da ta

during a RMW cycle

32-bit swap SWP [31:0] in Table 64 Data which is swapped with the VMEbus read data

and w ritte n to the origi nal addre ss

during a RMW cycle

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3.4.5.1 Read-Modify-Write

When the SCY C field is set to RMW, any PCI bus read access to t h e specified PC I

bus address (SCYC_ADDR register) results in a RM W cycle on the VMEbus

(provided the constraints listed below are satisfied). RMW cycles on the VMEbus

consis t of a si ngle rea d f ollowed by a single wr ite operation. The data from the r ead

portion of the RMW on the VM Ebus is returned as the read data on the PCI bus.

RMW cycles make use of three 32-bit registers (see Table 4). The bit enable f iel d is

a bit mask which lets the user specif y w hich bits in the read data are compared and

modified in the R MW cycle. This bit enable setting is completely independent of

the RMW cycle data width, which is determined by the data width of the initiating

PCI transaction. During a RMW, the VMEbus read data is bitwise compared with

the SCYC_CMP and SCYC_EN regis ters. The valid compared and enabl ed bits a re

then swapped using the SCYC_SWP register.

Each enabled bit that compares equal is swapped with the corresponding bit in the

32-bit swap field. A false comparison results in the original bit being writte n back.

Once the RMW cycle completes, the VMEbus read data is returned to the waiting

PCI b u s mas ter and the PCI cycle termin at es.

RMW Constraints

Certain restrictions apply to the use of R MW cycles. If a write transaction is

initia ted to the VMEbus address when the spe cial cyc le field ( SCYC in Table 60) is

set for RMW, then a standard write occurs with the attributes programmed in the

PCI target image (in other words, the special c ycle generator is not used). The

Universe II performs no packing and unpac king of data on the VMEbus during a

RMW operation. The following constraints must also be met.

1. The Special Cycle Generator only generates a RMW if it is accessed with an

8-bit, aligned 16-bit, or aligned 32-bit read cycle.

2. The S pecial Cycle Generator only ge nerate s a R MW if t he siz e of the re que st i s

less than or equal to the programmed VMEbus Maximum Data width.

3. The destination VMEbus address space must be one of A16, A24 or A32.

In the event that the Special Cycle Generator is accessed with a read cycle that does

not meet the RMW criteria, the Universe II ge nerates a Target-Abort. The

Universe II must be correctly programmed and a ccessed with correct byte-lane

information.

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3.4.5.2 VME Lock Cycles—Exclusive Access to VMEbus Resources

The VME Lo ck cycle is us ed, in combinatio n with the VOWN bit in the

MAST_CTL register Table 116 on page 305), to lock resources on the VMEbus.

The VME Lock cycle can be used by the Universe II to inform the resource that a

locked cycle is intended. The VOWN bit in the MAS T_CTL register can be set to

ensure that wh en the Univer se II acquires the VMEbus, it is the only ma ster given

access to the bus (until the VOWN bit is cleared). It may also be necessary for the

PCI master to have locked the Universe II using the PCI LOCK_ signal.

When the SCYC field is set to VME Lock, any write access to the specified

VMEbus address will result in a VME Lock cycle on the VMEbus. A VME Lock

cycle is coupled: the cycle does not complete on the PCI bus until it completes on

the VMEbu s. Reads to t he specifi ed address tran slate to V MEbus reads in the

standard fa shion. The data during writes is ignored. The AM code gene rated on the

VMEbus is determined by the P CI tar get image definit ion for the spe cified VMEbus

address (see Table 9 on page 88).

However, after the VME Lock cycle is complete, there is no guarantee that the

Universe II remains VMEbus master unless it has set the VOWN bit. If the

Universe II loses VMEbus ownership, the VMEbus resouce d oes not remain locked.

The following procedure is require d to lock the VMEbus through an ADOH cycle:

1. If there is more than one master on the PCI bus, it may be necessary to use PCI

LOCK_ to ensure tha t the PCI master driving the ADOH cycle has sole PCI

access to the Universe II registers and the VMEbus

2. program the V O WN bit in the MAST_CTL register to a value of 1 (see “Using

the VOWN bit”)

3. wait until the VOWN_ACK bit in the MAST_CTL register is a value of 1

4. generate an AD OH cycle with the Special Cycle Generator

5. perform transactions to be locked on the VMEbus

6. release the VM Ebus by programming the VOWN bit in the MAST_CTL

regist er t o a value of 0

7. wait until the VOWN_ACK bit in the MAST_CTL register is a value of 0

In the event that BERR* is asserted on the VMEbus once the Universe II has locked

and owns t he VMEbus, it is th e responsibilit y of the user to rel ease ownership of the

VMEbus by programming the VOWN bit in the MAST_CTL register to a value of

The followi ng restri ctions app ly to the u se of VME Lock cycl es:

• All byte lane inf o rmation is ignored for VME Lock cycles

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• The Universe II generates a VME Lock cycle on the VMEbus if the PCI Target

Image, which includes the special cycle, has posted writes disabled

• The Universe II Specia l Cycle Generator doe s not gene rate VME Lock c ycles if

the address space is not one of A16, A24 or A32 — it produces regular cycles

instead

3.4.6 Using the VOWN bit

The Universe II provides a VMEbus ownership bit (VOWN bit in the MAST_CTL

regist er, Table 116 ) t o ensure t hat the Universe II has access to the locked VMEbu s

resource for an indeterminate period. The Universe II can be programmed to assert

an interrupt on the PCI bus when it acquires the VMEbus and the VOWN bit is set (

VOWN enable bit in the LINT_EN register, Table 92). While the VMEbus is held

using the VOWN bit, the Universe II sets the VOWN_ACK bit in the MAST_CTL

interrupt. The VMEbus Master Interface m aintains bus tenure while the ownership

bit is set, and only releases the VMEbus when the ownership bit is cleared.

3.4.6.1 Reasons for Using the VOWN Bit

If the VMEbus Maste r Interface is progr ammed for RWD (VREL bit in

MAST_CTL regi ster), it may re lease the VMEbus when the PCI Target Channel has

completed a transaction. If exclusive access to the VMEbus resource is required for

multiple transactions, then the VMEbus ownership bit holds the bus until the

exclusive access is no longer r equired.

Altern atively, if the VMEbu s Master Interface is pr ogrammed for ROR, th e

VMEbus ownership bit ensures VMEbus tenure even if other VMEbus requesters

require the VMEbus.

3.4.7 Terminations

The Universe II performs the following terminations as PCI target:

1. Target-Disconnect

• when registers are accessed with FRAME_ asserted (no bursts allowed to

registers)

• after the first data beat of a coupled cyc le with FRAME_ asserted

• after the first data phase of a PCI Memory command (with FRAME_

asserted) if AD[1:0] is not equal to 00 (refer to Revision 2.1 of the PCI

Specification)

A Target-Disconnect with data only occurs if FRAME_ is asserted.

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2. Target-Retry

• for 64-bit PCI, when a new poste d write is att empted and the TXFIFO does

not have room for a burst of one address phase and sixteen 64-bit data

phases,

• when a coupled transaction is attempted and the Universe II does not own

the VMEbus

• when a coupled transaction is attempted while the TXFIFO has entries to

process

• Register Cha n nel is locked by the VME Slave Chan nel if a register access

(including a RMW access) is in progress or the re gisters have been locked

by an ADOH access. If the registers are locked by the VME Slave Channel,

reg ist er acc esses by external PCI m as ters a re retried

3. Target-Abort

• when the Universe II re ceives BERR* on the VMEbus during a coupled

cycle (BERR* translated as Tar get- Abor t on the PCI side and the S_TA bit

is set in the PCI_CS register, Table 38)

Whether to ter minate a transaction or for retry purposes, the Universe II keeps

STOP _ asserted until FRAME_ is deasserted, independent of the logic levels of

IRDY_ and TRDY_. If STOP_ is asserted whil e TRDY_ is deasse rted, it means that

the Universe I I does not transfer any more data to the master.

3.4.7.1 Error During Posted Write

If an error occurs during a poste d write to the VMEbus, the Universe II uses the

V_AMERR register (Table 144) to log the A M c ode of the transaction (AMER R

[5:0]), and the state of the IACK* signal (IACK bit, to indicate whether the error

occurred duri ng an IACK cycle). The FIFO entrie s for the cy cle are purged. The

V_AMERR register also records whether multiple erro rs have occurred (with the

M_ERR bit) although the number is not given. The error log is qualif ied with the

V_STAT bit (logs are valid if the V_STAT bit is set). The ad dress of the errored

transact ion is l atched i n the VAERR registe r (Table 12.2.108). When the Universe I I

receives a VM Ebus error during a posted write, it generates an interrupt on the

VMEbus and/or PCI bus depending upon whether the VERR and VERR interrupts

are en abled (see “I nterrupt Generation and Handling” on page 129).

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4. Slave Image Programming

This chapter describes the Slave Image Programming functionality of the

Universe II. This chapter discusse s the following topics:

•“VME S lave Image Programming” on page 84

•“PCI Bu s Target Images” on page 87

•“Special PCI Target Image” on page 90

4.1 Overview

The PowerSpan recognizes two types of a ccesses on its bus interfaces: accesses

desti ned for the oth er bus, and accesse s decoded f or its own registe r spa ce. Address

decoding for the PowerSpan’s register space is desc ribed in “Registers” on

page 191. This section describes the slave images used to map transactions between

the PCI bus and VMEbus.

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4.2 VME Slave Im age Programming

The Universe II accepts accesses from th e VMEbus with in speci fic programmed

slave images. Each VMEbus slave image opens a window to the resources of the

PCI bus and, through its specific attributes, allows the user to control the type of

access to those resources. The tables below describe programming for the VMEbus

slave images by dividing them into VMEbus, PCI bus and Control fields.

Table 5: VMEbus Fields for VMEbus Slave Image

Field Register Bits Description

Base BS[31:12] or B S[3 1:16] in

VSIx_BS Multiples of 4 or 64 Kbytes (base to bound:

maximum of 4 GByte s)

Bound BD[31:12] or BD[31:16] in

VSIx_BD

Address space VAS in VSI x_CTL A16, A24, A32, U ser 1, User 2

Mod e SUPER in VSIx_C TL Super vi so r an d/ or no n- pr ivileged

Type PGM in VSIx_ CTL Prog ra m an d/or dat a

Table 6: PCI Bus Fields for VMEbus Slave Image

Field Register Bi ts Description

Translatio n offset TO[31:12] or TO[31:1 6] in

VSIx_TO Offsets VMEbus sla ve ad dr ess to a

selecte d PCI addr ess

Address space LAS in VSIx_CTL Memory, I/O, Confi gur at io n

RMW LLRMW in VSIx_CTL RMW enable bit

Table 7: Control Fields for VMEbus Slave Image

Field Register Bi ts Description

Image enable EN in VSIx_CTL Enable bit

Post ed wr ite PWEN in VSIx_ C TL Poste d writ e enable bit

Prefetched read PREN in VSIx _CTL Prefetched read ena ble bi t

Enable PC I D64 LD 64 E N in VSIx_CTL Ena bl es 64-bit PCI bu s tran sactions

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The Bus Maste r Enabl e (BM) bit of the PCI_CS regist er m ust be set in order for the

image to accept poste d writes from an external VMEbus master. If this bit is cleared

while there is data in the VMEbus Slave Posted Write FIFO, the data is written to

the PCI bus but no further data is acc epted into this FIFO until the bit is set.

4.2.1 VME bus Fields

Decoding for VMEbus accesses is based on the address, and address modifiers

produced by the VMEbus master . B efore re sponding to an externa l VMEbus master ,

the addr ess must l ie in the window define d by the ba se and boun d addresses, and the

Address Modifie r must match one of those specified by the address space, mode,

and type fields.

The Universe II’s eight VMEbus slave images (images 0 to 7) are bounded by A32

space. The first and fourth of these images (VMEbus slave image 0 and 4) have a

4-Kbyte resolution while VMEbus slave images 1 to 3 and 5 to 7 have 64-Kbyte

resolution (maximum image size of 4 Gbytes) .

4.2.2 PCI Bus Fields

The PCI bus fields specify how the VMEbus tra nsaction is mapped to the

appropriate PC I bus transaction. T he translation offset field allows the user to

translate the VMEbus address to a different address on the PCI bus. The translation

of VMEbus transacti ons beyo nd 4 Gbytes results in wrap-around to the low portion

of the address range.

Tundra recommends that the a ttributes in a slav e image not be changed

while data is enqueue d in the Posted Writes FIFO. To ensure data is

queued from the FIFO, check the RX FE status bit in the MIS C_STAT

regi ster (Tab le 118) or perfor m a read f ro m t h at imag e. If the

programming for an im age is changed after the transaction is queued in

the FIFO, the transaction’s a ttributes are not c hanged. Only subsequent

transactions are affected by the change in attributes.

The address spac e o f a VMEbus sla ve imag e must no t overlap with the

address space for the Universe II’s control and status registers.

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The LAS field controls generation of the PCI transaction command. The LLRMW

bit allows indivisible mapping of incoming VMEbus RMW cycles to the PCI bus

via t he PCI LOCK _ mech anism (see “ VMEbus Read -Modi fy-Wri te Cycles (RMW

Cycles)” on page 50). When the LLRMW bit is set, single cycle reads are always be

mapped to single data beat locked PCI transactions. Setting this bit has no effect on

non-block writes: they can be coupled or decoupled.

Figure 7: Address Translation Mechanism for VMEbus to PCI Bus

Transfers

4.2.3 Contro l Fiel ds

The control fi elds enab le a VME bus sl ave image (usin g the EN bit), as w el l as

specify how re ads and writes are processed. At power-up, all images are disable d

and are configured for coupled reads and writes.

If the PREN bit is set, the Universe II prefetches for incoming VMEbus block read

cycles. It is the user's responsibility to ensure that prefetched reads are not

destructive and that the entire image contains prefetchab le res o urces.

If the PWEN bit is set, incoming write data from the VMEbus is loaded into the

RX FIFO (see “Posted Writes” on page 45). Note that posted write transac tions can

only be mapped to M em ory space on the PCI bus. Setting the LAS bit in the PCI

fields to I /O or Configuration Space will force all incom ing cycles to be couple d

independent of this bit.

Only accesses to PC I M emo ry Space are decoupled, accesses to I/O or

Configuration Space are always coupled.

Prefetching is only possible in PCI Memory Space.

Offset [31..12] PCI [31..12] PCI [11..0]

VME [31..12] VME [11..0]

A32 Image

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If the LD64EN bit is set, the Universe II generates 64-bit transactions on the PCI

bus by asserting R EQ64_. The REQ64_ line is asserted during the address phase in

a 64-bit PCI system, and is the means of determining whether the PCI target is a

64-bit port. If the target asserts ACK64_ with DEVSEL_, then the Universe II uses

the 64-bit data bus. If the target does not assert ACK64_ with DEVSEL_, then the

Universe II us es a 32- bit da ta b us. Howe ver, note t hat use of REQ64 _ re quir es e xtra

clocks internally. If no 64-bit targets are expected on the PCI bus then performance

can be improved by disabling LD64EN on the VMEbus slave images.

4.3 PCI Bu s Target Images

The Universe II ac cep ts accesses from the PCI bus with program med PCI target

images. Each im age opens a window t o the res ources of the VMEbus and allows the

user to control the type of access to those resources. The Table 8, Table 9 and

Table 10 de scribe programming for the eight standard PCI bus target images

(numbered 0 to 7) by dividing them into VMEbus, PCI bus and C o ntrol fields. One

special PCI target image is described in “Special PCI Target Image” on page 90.

Universe II only performs 64-bit PCI transactions if the power-up

option LCLS IZE bit, in the MISC_STAT register, is set to 1 (see

Table 118 on page 311). If the Universe II is set fo r a 32-bit PCI

transaction (LCLSIZE bit set to 0) it does not perform 64-bit PCI

transactions.

Table 8: PCI Bus Fields for the PCI Bus Target Image

Field Register Bi ts Description

Base BS[3 1: 12] or BS[3 1:16] in

LSIx_BS Multiples of 4 or 64 Kbytes (base to bound:

maximum of 4 G Bytes)

Bound BD[31:12] or BD[31:16] in

LSIx_BD

Address space LAS in LSIx_CTL Memory or I/O

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4.3.1 PCI Bus Fields

All decoding for VMEbus accesses are base d on the address and command

information produced by a PCI bus ma ster. The PCI Target Interface claims a cycle

if there is an address match and if the command matches certain cr iteria.

All of the Universe II’s eight PC I target images are A32-capable only. The first and

fifth of them (PCI tar get images 0 and 4) have a 4 Kbyte resolution while PCI tar get

images 1 to 3 and 5 to 7 have 64 Kbyte resolution. Typically, image 0 or image 4

would be used for an A16 image since they have the finest granularity.

Table 9: VMEbu s Fields for the PCI Bus Target Image

Field Register Bi ts Description

Translatio n offset TO[31:12] or TO[31:1 6] in

LSIx_TO Translates address supplied by PCI master

to a specified VMEbus address

Maximum data widt h VDW in LSIx_CTL 8, 16, 32, or 64 bits

Address space VAS in LSI x_CTL A16, A24 , A32, CR/ C SR, U ser1, User 2

Mode SUPER in LSIx_CTL Supervisor or non-privileged

Type PG M in LSIx_C TL Progr am or data

Cycl e VCT in LS Ix_C TL single or bl ock

Table 10: Control Fields for PCI Bus Target Image

Field Register Bi ts Description

Image enable EN in LSIx_CTL Enable bit

Post ed wr ite PWEN in LS Ix _CTL enable bit

T undra rec ommends that the attributes in a targ et image not be changed

while data is enqueued in the Posted Writes FIFO . To ensure data is

queued from the FIFO, check the TXFE status bit in the MISC_STAT

programming for an image is changed after the transaction is queued in

the FIFO, the transaction’s attributes are not changed. Only subsequent

transactions are affected b y the chan ge in attribute s .

The address space of a VMEbus slave image must not overlap with the

address space for the Universe II’s registers.

4. Slave Image Programming

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4.3.2 VME bus Fields

The VMEbus fields m ap PCI transactions to a VMEbus transaction, causing the

Universe II to generate the approp riate VMEbus address, AM code, and cycle type.

Some invalid combinations exist within the PCI target image definition fields. For

example, A16 and C R/CSR spaces do not support block transfers, and A16 space

does not support 64-bit transa ctions. Note that the Universe II does not attempt to

detect or prevent these invalid programmed combinations, and that use of these

combinations may cause illegal ac tivity on the VMEbus.

The 21-bit tr anslation offset allows the user to tran slate the PCI address to a

different address on the VMEbus. Figure 8 illustrates the translation process.

Figure 8: Address Translation Mechanism for PCI Bus to VMEbus Transfers

Translations beyond the 4 Gbyte lim it will wrap around to the low address range.

The Universe II provides support f or user defined AM codes. The USER_AM

USER_AM register can only be used to generate a nd accept AM codes 0x10

through 0x1F. These AM codes are designated as USERAM codes in the VMEbus

specifica tion. If the user selects one of these two, then the corresponding AM code

from the globa l register is genera ted on the VMEbus. This approach results in

standard single cycle transfers to A32 VMEbus address space independent of other

settings in the VMEbus fields.

The VCT bits in the LSIx_CTL registers determine whether or not the VMEbus

Master Inter face will generate B LT transfers. The VC T bit will only be used if the

VAS fiel d is progr ammed fo r A24 or A32 spac e and the VDW bits a r e progra mmed

for 8, 16, or 32 bits. If VAS bits of the control register a re programmed to A24 or

A32 and the VDW bits are programmed for 64-bit, the Universe II may perform

MBLT transfers independent of the state of the VCT bit.

Offset [31..12] PCI [31..12] PCI [11..0]

VME [31..12] VME [11..0]

A32 Image

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4.3.2.1 Transfers

Transfers appea r on the VMEbus as 16-bit transfers when the PowerSpan is

programmed in the following manner:

•PWEN= 1

• VDW=16-bit, 32-bit or 64-bit

•VCT= 0

Externa l PCI master be gins a bur st 32- bit write with A2=0 and B E_=001 1, fo llowed

by a transfe r with BE_=1100.

These criteri a optimize performance of 32-bit PCI systems which regular ly perform

16-bit transfers. A series of 16- bit transfers is a lso performed if 64-bit posted write

is receive d with BE_=11000011.

4.3.3 Contro l Fiel ds

The control fi elds enab le a PCI target ima g e (the EN b it), as wel l as speci fy how

writes are processed. If the PWEN bit is set, then the Universe II performs posted

writes when that particular PCI target image is accessed. Posted write transactions

are only decoded within PCI Memory space. Acc esses from I/O spaces results in

coupled cycle s independent of the se tting of the PWEN bit.

4.4 Special PC I Targe t Image

The Universe II provides a special PCI target ima ge located in Memory or I/O

space. Its ba se address is aligned to 64-Mbyte boundaries and its size is fixed a t

64 Mbytes (decoded using PCI address lines [31:26]). The Special PC I Target

Image is divided into four 16Mbyte regions numbered 0 to 3 (see Figure 9 on

page 92). These sep arate regions are se lected with PCI address bits AD [25:24]. For

example, i f AD[25:24] = 01, then re gion 1 is decoded. Within ea ch region, t he upper

64Kbytes map to VMEbus A16 space, while the remai ning portion of the 16 Mbytes

maps to VMEbus A24 space. Note that no offsets are provided, so address

information f rom the PCI transaction is mapped directly to the VMEbus.

The general a ttr ibutes of e ach regi on are pr ogr ammed accordi ng to the ta bles be low.

Table 11: PCI Bus Fields for the Special PCI Target Image

Field Register Bits Description

Base BS[5:0] in Table 6 6 64 Mbyte alig ned base ad dr ess for the

image

Address spac e LAS in Table 66 Places image in Memory or I/O

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The special PCI target ima ge provides access to a ll of A16 and most of A24 space

(all e xcept the uppe r 64 Kbytes) . By using t he special P CI ta rget image for A16 and

A24 transactions, it is possible to free the eight standar d PC I target imag es (see

“PCI Bus Target Images” on page 87), which are typically progra mmed to access

A32 space.

Address space redundancy is provided in A16 space. The VMEbus specification

requires only two A16 spaces, while the special PCI target image allows for four

A16 address spac es.

Table 12: VMEbus Fields for the Special PCI Bus Target Image

Field Register Bits Description

Max imum data w id th VDW in Tabl e 66 Separ at el y set s each region for 16 or 32

bits

Mod e SUPER in Ta bl e 66 Separat ely set s each region as sup erv isor

or non-privileged

Type PGM in Table 66 Separately sets each region as program or

data

Table 13: Control Fields for the Special PCI Bus Target Image

Field Register B its Description

Image enable EN in Tab le 66 Ena ble bi t for the image

Post ed wr ite PWEN in Table 66 Ena bl e bi t for posted writes fo r the image

4. Slave Image Programming

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Figure 9: Memory Mapping in the Special PCI Target Image

A16

A24

16 Mbyte

64 Kbytes

BASE+400 0000

BASE+3FF 0000

BASE+300 0000

BASE+2FF 0000

BASE+200 0000

BASE+1FF 0000

BASE+100 0000

BASE+0FF 0000

BASE+000 0000

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5. Registers Overview

The Universe II C ontrol and Status R egisters (UCSR) occupy 4 Kbytes of internal

memory. This chapter discusses the following topics:

•“Regis ter Ac ces s from the PCI Bus” o n page 94

•“Register Access from the VMEbus” on page 97

•“Mailbox Registers” on page 101

•“Semaphores” on page 102

5.1 Overview

The Universe II C ontrol and Status R egisters (UCSR) occupy 4 Kbytes of internal

memory. This 4 Kbytes is logically divided into the following three groups (see

Figure 10):

• PCI Configuration Space (PCICS)

• Universe II Device Specific Registers ( UDSR)

• VMEbus Control and Status Registers (VCSR)

The access mecha nisms for the UCSR are different depending upon whether the

PCI bus and VMEbus is discussed in the following sections.

The Universe II r egisters are little-endian.

5. Registers Overview

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Figure 10: Universe II Control and Status Register Space

5.2 Register Access from the PCI Bus

There are d iffere nt mecha nisms t o access the UCSR space from the PCI bus:

Configuration space, PCI Memory or I/O sp ace (Table 41).

5.2.1 P CI Confi guration Access

When the UCSR space is accessed as Configurat ion space, it means that the access

is externally decoded and the Universe II is notified through IDSEL (much like a

standard chip select signal). Since the regis ter location is e ncoded by a 6-bit register

number (a value used to index a 32-bit area of Configuration space), only the lower

256 bytes of the UCSR can be accessed as Configuration space (this corre sponds to

the PCICS in the UCSR space, see Figure 11 on page 95). Only the PCI

configuration registers are accessible through PCI Configuration cycles.

PCI CONFIGURATION

SPACE

(PCICS)

UNIVERSE DEVICE

SPECIFIC REGISTERS

(UDSR) 4 Kbytes

UCSR Spac

VMEbus Configuration

and Status Registers

(VCSR)

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Figure 11: PCI Bus Access to UCSR as Memory or I/O Space

5.2.2 Memory or I /O Access

Two 4-Kbyte r anges of addresses in PCI Memory space a nd/or PCI I/O space c an be

dedicated to the Universe II registers. There is one 4-Kbyte range in PCI Memory

space and one 4-Kbyte range in PCI I/O spa ce .

The Universe II has the following two programmable register s: PCI_BS0 register

(Table 41 on page 209) and PCI_BS1 register (Table 42 on page 210). These

Universe II’s registers. The PCI_BSx registers c an be programmed through PCI

Configur ation spa ce or thr ough a VMEbus a ccess, to m ake the Univ erse I I re gist ers

available anywhere in the 32-bit M emory spac e an d in I/O space (as offsets of the

BS[31:12] field in PCIBSx).

PCI CONFIGURATION

SPACE

(PCICS)

UNIVERSE DEVICE

SPECIFIC REGISTERS

(UDSR) All 4 Kbytes

Accessible as

Memory or I/O

Space

4 Gbytes

of Memory

or I/O Spac

PCI_BS

ccessible

hrough PCI

onfiguration

ycle

VMEbus Configuration

and Status Registers

(VCSR)

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The SPACE bit of the PCI_BSx registers spe cifies whether the address lies in

Memory space or I/O space. The SPACE bit of these two registers are read-only.

There is a powe r-up option that determines the value of the SPACE bit of the

PCI_BSx register s. At power-up the SPACE bit of the PCI_BS1 register is the

negation of the SPACE bit of the PCI_BS0 register.

• When the VA[1] pin is samp led low at power-up, the PCI_BS0 register’s

SPACE bit is set to 1, which signifies I/O space, and the PCI_BS1 register’s

SPACE bit is set to 0, which signifies Memory space.

• When VA[1] is sampled high at power-up, the PCI_B S0 register’s SPAC E

5.2.2.1 Conditions of Target-Retry

Attempts to access UCSR s pace fro m the PCI bus can be retried b y the Universe II

under the following conditions:

• While UCSR s pace is bei ng accessed by a VMEbus master, PCI mast ers are

retried.

• If a VMEbus mas t er is performing a RMW access to the UCSRs t h en PCI

attempts to access t he USCR space results in a Ta rget-Retry until AS * is

negated.

• If the Universe II registers are a ccessed through an ADOH cycle from the

VMEbus, any PCI attem pt to access the UCSRs is retr ied until BBSY* is

negated.

5.2.3 Locking the Reg iste r Block from the PCI bus

The Universe II re gisters can be lo cked by a PCI master by using a PCI locked

transaction. When an external PCI master locks the register block of the Universe II,

an access to the register block from the VMEbus does not terminate with the

assertion of DTACK* until the register block is unlocked. Hence a prolonged lock

of the register block by a PCI resource may cause the VMEbus to timeout with a

BERR*.

Universe II registers are not prefetchable and do not accept burst

writes.

5. Registers Overview
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5.3 Register Access from the VMEbus
There are two mechanisms  to access the UCSR sp ace from the VMEbus. One 
method uses a VMEbus Register Access Image (VRAI) which can put the UCSR in 
an A16, A24 or A32 addre ss space. The VRAI approach is useful in systems not 
implementing  CR/CSR space as  defined in the  VME64 Specification . The ot her way 
to access the UCSR is as CR/CSR space, where each s lot  i n the VMEbus sy s tem is 
assigned 512 Kbytes of CR/CSR space. 
5.3.1 VMEbus  Register Access Image (VRAI )
The VMEbus register access image is defined by Table 14.
The VMEbus Register Ac cess Image occupies 4 Kbyte s in A16, A24 or A32 space 
(depending upon the programming of the address space described in Table 14, and 
Figure 1 2). All regi sters are acc essed as addre ss off sets fro m the VRAI base address 
programmed in the  VRAI_BS register (Table 140). The image can be enable d or 
disabled using the EN bit in the VRAI_CTL registe r (Table 139).
Note that the VRAI  base address can be conf igured as a power-up option (see 
“Resets, Clocks and Power-up Options” on page 153).
Table 14: Programming the VMEbus Register Access Image
Field Register Bits  Description
Address space VAS in Table 139 One of A16 , A24, A3 2
Base ad dre ss BS[31 :12]  in Ta bl e 140 Lowest  add res s i n the 4Kbyte slave 
image
Slave image 
enable EN  i n Table 1 39 enables VMEbus register access image
Mod e SUP ER  in Ta ble 139 Super visor  and /o r Non- Pr ivi leged
Type PGM in Table 1 39 Program  and/or Data

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Figure 12: UCSR Access from the VMEbus Register Access Image

5.3.2 CR/CSR Accesses

The VME64 Specification assigns a total of 16 Mbytes of CR/CSR space for the

VMEbus syst em. The C R/CSR im age is ena ble d wit h the EN bit in the VCSR_CTL

of 32 slots. The first 512 Kbyte block is reserved for use by the Auto-ID

mechanism. The UCSR space occupies the upper 4 Kbytes of the 512 Kbytes

available for its slot posi tion (see Figure 13). The base address of the CR/CSR space

allocated to the Universe II’s slot is programmed in the VCSR_BS register

(Table 164).

PCI CONFIGURATION

SPACE

(PCICS)

VMEbus Configuration

and Status Registers

(VCSR)

UNIVERSE DEVICE

SPECIFIC REGISTERS

(UDSR)

4 Kbytes

of UCSR

Total Memory

in A16, A24 or A32

Address Space

VRAI_BS

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For CSRs not supported in the Univer se II and for CR accesses, the LAS field in the

VCSR_CTL register specifies the PCI bus command that is generated when the

cycle is mapped to the PCI bus. There is also a translation offset added to the 24-bit

VMEbus address to produce a 32-bit PCI bus address (programmed in the

VCSR_TO registe r, Table 143).

5.3.3 RMW and ADOH Register Acce ss Cycl es

The Universe II supports RMW and ADOH accesses to its registers.

A re ad -modify-write (RMW) cycle allows a VMEbus master to read from a

VMEbus slave and the n write to the sam e r esource without relinquishing VMEbus

tenure betwe en the two operations. The Universe II accepts RMW cycles to any of

its reg ist ers. Thi s prevents an external PCI Mas ter from accessing th e registers of

the Universe I I until VMEbus AS* is asserted. This is useful if a single RMW

access to the ADOH is required.

If a sequence of accesses to the Universe registers must be performed without

intervening PC I access to UCSR is require d, then the VMEbus master should lock

the Universe I I through the use of ADOH. This prevents a n external PCI Master

from accessing the registers of the Universe II until VMEbus BBSY* is negated. It

also prevents other VMEbus masters from accessing the Universe II regis t ers.

The regis t ers in the UCSR space are located as addres s offsets from

V CSR_B S. These offsets are differen t from those u sed in the V RAI

mechanisms, where the first regi ster in the UCS R h as address offset of

zero (see Table 36 in Appendix A). When accessing the UC SR in

CR/CSR space, the first r egister has an address offset of 508 Kbytes

(512 Kbytes minus 4 Kbytes). A simple approach for determining the

Kbytes (0x7F000) to the address offsets given in Table 36.

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Figure 13: UCSR Access in VMEbus CR/CSR Space

PCI CONFIGURATION

SPACE

(PCICS)

UNIVERSE DEVICE

SPECIFIC REGISTERS

(UDSR) 4 Kbytes

of UCSR

Mapped

PCI

512 Kbytes

of VMEbus

CR/CSR Space

(Portion of 16 Mbyte

Total for Entire

VMEbus System)

VCSR_BS

VMEbus Configuration

and Status Registers

(VCSR)

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5.4 Mailbox Registers

The Universe II has four 32-bit ma ilbox registers which provide an additional

communication path between the VMEbus and the PCI bus (see Table 110 to

Table 1 13). The mailboxes supp ort read and wri te accesses from either bus, and may

be enabled to generate interrupts on either bus when they are written to. The

mailboxes are a ccessible from the same address spaces and in the same manner as

the other Universe II registers, as desc ribed above.

Mailbox registers are useful for the communication of concise command, status,

and parameter data. The specific uses of mailboxes depend on the application. For

example, they ca n be used when a master on one bus needs to pass information (a

message) on the other bus, without knowi ng where the inf ormation should be st ored

in the other bus’s address space. Or they can be used to store the address of a longer

message written by the processor on one bus to the address space on the other bus,

through the Universe II. They can al so be used to ini tiate la r ger tra nsfers thr ough the

FIFO , i n a user-defined manner.

Often users will enable and map mailbox interrupts, so that when the processor

writes to a mailbox from one bus, the Unive rse II will interrupt the opposite bus.

The interrupt service routine on the opposite bus would then cause a read from this

same mailbox.

Reading a mailbox cannot automatically trigger an interrupt. However, a similar

effect can be achieved by r eading the mailbox and then triggering an interrupt

through hardwar e or software. Or one may use a “polling” approach, where one

designates a bit in a mailbox register to indicate whether one has read from the

mailbox.

For details on how the mailbox inte rrupts are enabled and mapped, see “Interrupt

Generation and Handling” on page 129 and “Mailbox R egister Access Interrupts”

on page 144.

Applications will sometimes designate two mailboxes on one inter face as being

read/write from the PCI bus, and read-only from the VMEbus, and the two other

mailboxes as r ead/write from the VMEbus and read-only from the PCI bus. This

eliminates the need to implement locking. The Universe II provides semaphores

which can be also be used to synchronize acc ess to the mailboxes. Sem aphores are

described in the next section.

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5.5 Semaphores

The Universe II has two general-purpose sem aphore registers each containing four

semaphores. The r egisters are SEMA0 (Table 114) and SEMA1 (Table 115). To

gain o wnership of a semaphore, a process writ es a logic 1 to th e semaphore bi t and a

unique pattern to t he associ ated tag f ield. If a subsequent read of th e tag f ield retur ns

the same pattern, the process can consider itself the owner of the semaphore. A

process writes a value of 0 to the se ma phore to release it.

When a semaphore bit is a value of 1, the assoc iated tag field cannot be updated.

Only when a semaphore is a value of 0 can the associated tag fie l d be updated.

These semaphore s shares resources in the system. While the Universe I I provides

the semaphores, it is up to the user to determine access to which part of the system

will be controlled by semaphores, and to design the system to enforc e these rules.

An example of a use of the semaphore involves gating access to the Special Cycle

Generator (“Special Cycle G enerator” on page 78). It may be necessary to ensure

that while one process uses the Special Cycle Generator on an addre ss, no other

process accesses thi s address. Before performing a Special Cycle, a process would

be required to obtain the semaphore. This process would hold the semaphore until

the Special Cyc le completes. A separate process that intends to modify the same

address would need to obtain the se ma phore before proceeding (it need not verify

the state of the SCYC[1:0] bit). This mechanism requires that processes know

which addresses might be accessed through the Special Cycle Generator.

Each of the four semaphores in a semaphore regi ster are intended to be

acces s ed with 8-bit tran sfers

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6. DMA Controller

Direct memory ac cess (DMA) allows a transaction to occur between two devices

without involving the host proce ssor (for example, a read transaction between a

peripheral device and host processor memory). Because less time is required to

complete t ransactions, applicat ions that co ntain one or m ore DMA channels s upport

faster rea d and write transfers than applications that support only host-assisted

transactions.

This chapter discusses the following topics:

•“DMA Registe rs” on page 104

•“Direct Mode Operation” on page 112

•“Linked-list Mode” on page 115

•“FIFO Operation and Bus Owne rship” on page 121

•“DMA Interrupts” on page 125

•“DMA Channel Interactions with Othe r Channels” on page 125

•“DMA Error Handling” on page 126

6.1 Overview

The Universe II has a DMA controller for high performance data transfer between

the PCI bus and VMEbus. It is op era ted thr ough a ser ie s of r egiste r s that cont rol the

source and destin ation fo r the data, length of the transfer and the tr ansfer protoc ol to

be used.

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There are two m odes of operation for the DMA: Direct Mode, a nd Linked List

Mode. In direct mode, the DMA registers are programmed directly by the external

PCI master. In linked list mode, the registers are loaded from PCI memory by the

Universe II, and the transfer described by these registers is executed. A block of

DMA registers sto red in PC I memory is cal led a com mand packet. A co mmand

packet can be linked to another command packet, so that when the DMA has

completed the ope rati ons described by one command packet, it automatic ally moves

on to the next comm and packed in the linked-list of command packets.

6.2 DMA Regi sters

The DMA register s resi de i n a re gist er block starting at offset 0x200. The y describe

the following information for a single DMA transfer:

• wh ere to transfer da ta from

• wh ere to tran s fer d ata to

• how much data to transfer

• the transfer attributes to use on the PCI bus and VMEbus.

A final register contains status and control information for the transfe r. While the

DMA is active, the registers are locked against any changes so that any writes to the

registers will have no impact.

In direct- mode operation, these registers are programmed directly. In linked-list

operation, they are repeatedly loade d by the Universe II from command pac k ets

residing in PCI memory until the end of the linked-list is reached (see “Linked-list

Mode” on page 115).

6.2.1 Source and Destina tio n Add resses

The sourc e and destinati on addresses for the DMA reside in two r egister s: the DMA

PCI bus Address (DLA) register (see Table 87), and the DM A VMEbus Address

(DVA) register (see Table 88). The determination of which is the source address,

and whi ch is the destinatio n is made by the L2V bi t in the DCTL regi ster (Table 85).

When set, the DMA transfers data from the PCI to the VMEbus. The DLA becomes

the PCI source register and DVA becomes the VMEbus destination register. When

cleared, the DM A transfers data from the VM Ebus to PCI bus and DLA becomes

the PCI destination register ; DVA becomes the VMEbus source register.

The PCI address ma y be programmed to any byte address in PCI Memory space. It

cannot transfer to or from PCI I/O or Configuration spaces.

6. DMA Controller

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The VMEbus address ca n also be programmed to any byte address, and can acce ss

any VMEbus address space from A16 to A32 in supervisory or non-privileged

space, and data or program space. The set ting of address space, A16, A24 or A32, is

programmed in the VAS field of the DCTL re gister (Table 85). The sub-spaces ar e

programmed in the PGM and SU PER fields of the same register.

In direct mode the user must re prog ram the source and destin ati on address registers

(DMA, DLA) b efore each transfer. These registers are not u pdated i n di rect mod e.

In linked-list m ode, these registers are updated by the DMA when the DMA is

stopped, ha lted, or at the completion of processing a command packet. I f read

during DMA activity, the y return the number of bytes remaining to transf er on the

PCI side. All of the DMA registers are locke d against any change s by the user while

the DMA is active .

When stopped due to an error situation, the DLA and DVA registers must not be

used, but the DTB C is valid (see “DM A Error Handling” on page 126 for details).

At the end of a successful linked-list transfer, the DVA and DLA registers point to

the next addre ss at the end of the transfer block, and the DTB C r egister is 0.

6.2.2 Non-incrementing D MA Mo de

The VMEbus Non-Incrementing Mode (Non-Inc Mode) enable s the DMA

Controlle r to pe rfor m tr ansfer s to or f rom a f ixed VMEbus address. Thi s means that

the sp ecified VMEbus addre ss is not i ncremented during DMA reads or write s. This

applies to both Direct and Linked List modes of DMA operation. For mor e

information on these two types of DMA operation, refer to “Direct Mode

Operati on” on page 112 and “Linked-list Mode ” on page 115.

Unlike increm enting DMA operation, in Non-Inc Mode the DMA Controller can

only pe rform 8-,16- or 32-bit s ingle cycle transfers on the VMEbus. This m eans tha t

BLT and MBLT transfers cannot be performed when operating in Non-Inc Mode.

6.2.2.1 Using Non-Inc Mode

The VMEbus Non-Inc Mode is enabled by writing a 1 to the NO_VINC bit of the

DCTL register (see Table 90 on page 269).

Although the PCI and VMEbus addresses may be programmed to any

byte aligned address, they must be 8-byte a ligned to each other (the low

three bits of e ach must be identical). If not program med with aligned

source and destination addresses and an attempt to start the DMA is

made, the DMA does not start. It sets the protocol error bit (P_ERR) in

the DCSR register (Table 90), and if enabled to, generates an interrupt.

Linked-list operations cea se.

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In orde r to set -up and ini tiate DMA operation, the same steps which are described i n

the DMA Controller Section in the Universe II User Manual must be followed for

Non-Inc Mode.

The steps in setting-up and initiating DMA operation are as f ollows:

4. Program the tenure and interrupt requirements in the DGCS register (offset

0x220).

5. Program the source and destination addresses in the DLA and DVA registers.

6. Set the GO bit in the DGCS register.

6.2.2.2 Issues with Non-Inc Mode

The VMEbus Address

In Non-Inc Mode, the D VA register (offset 0x210) does not necessarily contain the

fixed VMEbus addres s. This register must not be read during a DMA Non-Inc Mode

transfer. Once a DMA transfe r has been stopped — by setting the STOP bit of the

DGCS regist er — the Non-Inc Mode t ransfer c annot be restarte d by simply writing a

1 to the GO bit of t he DGCS regist er. The DVA registe r must be r eprogrammed with

the required address before setting the DGCS GO bit.

The VON Counter

When the VON counter in the DG CS register reaches its programmed limit, the

VMEbus Master Inte rface of the Universe II stops transferring data until the VOFF

timer expires. If the device is operating in Non-Inc Mode, the VON counter has

different limits than those indicated in the DMA C ontroller section.

The different settings are detailed in Table 15.

Table 15: VON Settings for Non-Inc Mode

VON VMEbus Aligned DMA Transfer Co unt

001 128 bytes

010 256 bytes

011 512 bytes

100 1024 bytes

101 2048 bytes

110 4096 bytes

111 8192 bytes

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P_ERR Flag Behavior

When the GO bit is set in Non- I nc Mode, the P_ERR fl ag of the DGCS register is 1

when the following conditions are true:

• VCT bit of the DCTL register has a value of 1

• VDW field of the DCTL register ha s a value of 01 and bit 0 of the DVA registe r

is a value of 0

• VDW field of the DCTL register has a value of 10 and bits 1 and 0 of the DVA

• VDW field of the DCTL register has a value of 11.

Single Cycle Transfers

The Universe II and PowerSpan perform 8-,16- or 32-bit single cycle transfers on

the VMEbus. BLT and MBLT transfers cannot be performed when operating in

Non-Inc Mode.

6.2.2.3 Non-Inc Mode Performance

The transfer perfor mance of DMA in Non-Inc Mode has been simulated at 14 MB/s

for 32-bit writes and at 8 MB/s for 32-bit reads. This perfor mance was determined

using ideal slave responses; lower performa nce can be expected in a ctual systems.

6.2.3 Transfer Size

The DMA can be programmed through the DMA Transfer Byte Count register

(DTBC register in Table 86) to transfer any number of bytes from 1 byte to 16

MBytes. There are no alignment requirements to the source or destination

addresses. If the width of the da ta turnovers ( 8- through 64-bit on VMEbus and 32-

or 64-bit on PCI) do not align to the length of the transfer or the source/de stination

addresses, the DMA inserts transfe rs of smaller width on the appropriate bus. For

example, if a 15-byte transfer is programmed to start at address 0x1000 on the

VMEbus, and the width is set for D32, the DMA will perfor m three D32 transfers,

followed by a D08 transfer. The Universe II does not generate unaligned transfers.

On a 32-bit PCI bus, i f the star t address was 0x2000, the DMA would generate three

data beats with all byte lanes enabled, and a fourth with three byte lanes enabled.

The DTBC register is not updated while the DMA is active ( DMA is indic ated as

active by the AC T bit in the DGCS register). At the end of a transfer it contains 0.

However, if stoppe d by the user (t hrough the STOP bit in the DGCS register) or the

DMA encounters an e rror, the DTBC register contains the number of bytes

remaining to transfer on the source side. See “DMA Error Handling” on page 126.

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Starting the DMA while DTBC is 0 results in one of two situations. If the CHAIN

bit in the DGCS register (Table 90) is not set, the DMA does not start; it performs

no action. If the CHAIN bit is set, then the DMA loads the DMA registers with the

contents of the command packet pointed to by the DC PP register (Table 89), and

starts the transfers described by that packet. Note that the DCPP[31:5] field of the

DCPP register implies that the command pac kets be 32-byte aligne d (bits 4:0 of this

6.2.4 Transfer Data Width

The VMEbus and PCI bus data widths are determined by three fields in the DC TL

for the maximum allowable width that the destination devic e is capable of

accepting.

On the VMEbus, the DMA supports the following da ta widths:

• D08(EO)

•D8BLT

•D16

• D16BLT

•D32

•D64

• D32BLT

• D64BLT (MBLT)

The width of the transfer is set with the VDW field in the DCTL register. The VCT

bit determine s whether or not the Unive rse II VMEbus Master will generate BLT

transfers. The value of this bit only has meaning if the address space is A24 or A32

and the data width is not 64 bits. If the data width is 64 bits the Universe II m ay

perform MBLT transfers independent of the sta te of the VCT bit.

The Universe II can perform data transfers smaller than that programmed in the

VDW field in order to bring itself into alignment with the programmed width. For

example if the width is set for D32 and the starting VMEbus address is 0x101, the

DMA performs a D08 cycle. Only once it has achieved the a lignment set in the

VDW field does it start D32 transfers. At the end of the transfer, the DMA also

performs more low-width transfers if the last address is not aligne d to VDW.

Similarly, if the VCT bit is set to enable bloc k transfers, the DMA can perform

non-block transfers to bring itself into alignment.

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On the PCI bus, the DMA provides the option of performing 32- or 64-bit PCI

transactions through the LD64EN bit in the DCTL register (Table 85). If the

Universe II has powered-up on a 32-bit bus ( see “Power -Up Options” on page 160),

this bit has have no effect. If powered-up on a 64-bit bus, this bit can provide some

performance improvements whe n accessing 32-bit t argets on that bus. Following the

PCI 2.1 Specification, before a 64-bit PCI initiator starts a 64-bit transaction, it

engages in a pr otocol with the intended targe t to determine if it is 64-bit capable.

This protocol typically consumes one c lock period. To save bandwidth, the

LD64EN bit can be cleared to bypass this protocol when it is known that the target

is only 32-bit capable.

6.2.5 DMA Command Packet Pointer

The DMA Command Packet P ointer (DCPP in Table 89) points to a 32-byte aligned

address loca tion i n P CI Memory s pace that c ontains the next com mand packet to be

loaded once the transfer currently programmed into the DMA registers has be en

successfully comple ted. Wh en it has been completed (or the DT BC register i s 0

when the GO bit is set) the DMA reads the 32-byte command pack et from PCI

memory and execute s the transfer it describes.

6.2.6 DMA Control and Status

The DMA General Control/Status Register (DGCS in Table 90) conta ins a number

of fields that control initiation and operation of the DMA as well as actions to be

taken on completion.

6.2.6.1 DMA Initiation

Once all the pa rameters associate d with the transfer have been programmed

(source/d est ination addresses, transf e r len gth and da ta widt hs, a nd i f desi red, l inke d

lists enabled), the DMA transfer is started by setting the GO bit in the DGCS

it latches the values programm ed into the DCTL, DTBC, DLA, and DVA registers

and init iate s the tr ansfer pr ogrammed into tho se re gist ers. If DTBC=0, it checks the

CHAIN bi t in th e DGCS register and if that bit is cleared it assume s th e trans fer to

have complete d and stops . Otherwise, if the CHAIN bit is set, it loads int o the DMA

registers the command packet pointed to by the DCPP register and initiates the

transfer describe there.

If the GO bit is set, but the Unive rse II has not been enabled as a PCI master with

the BM (bus master enable) bit in the PCI_CSR register, or if the DVA and DLA

contents are not 64-bit aligne d to each other, the transfer does not start, a protocol

error is indicated by the P_ERR bit in the DGCS register and, if enabled, an

interrupt is generated.

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If the DMA has been terminated (stopped, ha lted, or error), all DMA registers

contain value s indicating where the DMA terminated. Once all st atus bits have been

cleared, the DM A may be resta rted from where it lef t off by sim ply setting the GO

bit. The GO bit only has an effect if all status bits have been clea red. These bits

include STOP, HALT, DONE, LERR, VERR, and P_ERR and are located in the

DGCS register (Table 90 on page 269). These bits are all cleared by writing 1 to

them, either before or while setting the GO bit.

The GO bit always returns a 0 when read independent of the DMA’s current state.

Clearing the bit has no impact at any tim e. The ACT bit in the DGCS register

indicate s whether the DMA is currently a ctive. It is set b y the DMA once the GO bit

is set, and cleare d when the DMA is idle. Generally, when the ACT bit is cleared,

one of the other status bits in the DG CS register is set ( DONE, STOP, HALT,

LERR, VERR, or P_ERR), indicating why the DMA is no longer active.

6.2.6.2 DMA VMEbu s Ownership

Two fields in the DGCS register determine how the DMA share s the VMEbus with

the other two potential maste rs in the Universe II (PCI Targ et Channel, and Interrupt

Channel), and with other VMEbus masters on the bus. These fields are: VON and

VOFF.

VON

VON affects how much data the DMA transfe rs before giving the opportunity to

another master (ei ther the Unive rse II or a n exter nal master) to assume ownershi p of

the bus. The VON counter is used to te mporarily stop the DMA from transferring

data once a programmed number of bytes have been transferred (256 bytes, 512

bytes, 1K, 2K, 4K, 8K, or 16K) . When performing MBLT transfers on the VMEbus,

the DMA stops performing transf ers within 2048 bytes after the programmed VON

limit has been reache d. When not performing MBLT transfers, the DMA will stop

performing tr ansfers within 256 bytes once the progr ammed limit has been reached.

When programmed for Re lease-When-Done opera tion, the Universe II perform s an

early release of BBSY* when the VON counter reaches its prog rammed limit. VON

may be disabled by setting the field to zero. When the VON bit is set to 0, the DMA

continues transferring data as long as it is able.

There are othe r conditions unde r which the DMA may relinquish bus ownership.

See“F IFO Operation and Bus Ownership” on page 121 for details on the VMEbus

request and release conditions for the DMA.

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VOFF

VOFF affects how long the DMA waits before re-requesting the bus af ter the VON

limit has been r eached. By setting VOFF to 0, the DMA immedi ately r e-requests the

bus once the VON boundary has been reached. Since the DM A operates in a

round-robin fashion with the PCI Target Channel, and in a priority fashion with the

Interrupt C hannel, if either of these channels require ownership of the V MEbus,

they receive it at this time.

VOFF is only invoked when VMEbus tenure is relinquis hed due to encounter ing the

VON boundary. When the VMEbus i s released due to other conditions (for example,

the DMAFIFO has become full while reading from the VMEbus), it will be

re-requested as soon as that condition is cleared. The VOFF timer can be

programmed to variou s time inter vals from 0µs to 1024µs. See “FIFO Operation and

Bus Ownership” on page 121 for details on the VMEbus request and release

conditions for the DMA.

See “DMA Channel Interact ions with Other Channels” on page 125 for information

on other mechanisms which can delay the DMA Channel from acquiring the

VMEbus or the PCI bus.

6.2.6.3 DMA Completion and Termination

Normally, the DMA c ontinues processing its transfers and comm and packets until

either it complete s all reque sts, or it e ncounters a n error. There ar e also two m ethods

for the user to interrupt this process and cause the DMA to terminate prematurely:

STOP and HALT. STOP causes the DMA to terminate immediately, while HALT

causes the DMA to t ermin at e when it has comple te d processing the current

command packet in a linked list.

STOP

When the STOP_REQ bit in the DGCS register is set, it tells the DMA to cease its

operat ions on the sour ce bus immediat el y. Remaining data in the FIFO continues to

be written to the destination bus until the FIFO is empty. Once the F IFO is empty,

the STOP bit in the same register is set and, if enabled, an interrupt generated. The

DMA registers contain the values that the DMA stopped at: the DTBC register

contains the number of bytes remaining in the transfer, the source and destination

address registers contain the ne xt address to be read/written, the DCPP register

contains the next command packe t in the linked- list, a nd the DCTL register c ontains

the transfer attributes.

If read tr a nsact ions ar e o ccurri ng on t he VMEbus, th en s ett ing a st op r equest can be

af fected by the VOFF ti mer . If the ST OP_REQ bit is set while the DMA is lying idle

waiting for VOFF to expire before re-starting reads, then the request remains

pending until the VOFF timer has expir ed and the bus has been granted.

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HALT

HALT provides a mechanism to interrupt the DM A at command packet boundaries

during a linked-list mode transfer. In contrast, a STOP requests the DMA to be

interru pted immediat el y, wh i le halt ta ke s effect only when the current command

packet is complete . A halt is request ed of the DMA by sett ing the HALT_REQ bit in

the DGCS register. This causes the DM A to complete the transf ers defined by the

current contents of the DMA registers and, if the CHAIN bit is set, load in the next

command packet. The DMA then t erminates, the H ALT bit in th e D GCS register is

set, and, if enabled, an interrupt generated.

After a stop or hal t, the DMA can be restarted fr om the point it left of f by setting the

GO bit; but before it can be re-started, the STOP and HALT bits must be cleared.

Regardless of how the DMA stops—whether normal, bus error or user

interrupted—t he DMA indica tes in the DGC S register why it stopped. The STOP

and HALT bits are set in response to a stop or halt request. The DONE bit gets set

when the DMA has succe s sfully complet ed the DMA transfer, including all entri es

in the lin ked-lis t (if operati n g in that mode). There are also three bits that are set in

response to error conditions: LERR in the case of Target-Abort encountered on the

PCI bus; VERR in the case of a bus error encounte red on the VMEbus; and P_ERR

in the case that the DMA has not been properly progra mmed (the DMA was started

with the BM bit in the PCI_CSR registe r not enabled, or the DLA and DVA registers

were not 64-bit aligned, (see “Source and De stination Addresses” on page 104).

Before the DMA can be restarted, ea ch of these status bits must be cleared.

When the DMA terminates, an interrupt may be generated to VMEbus or PCI bus.

The user has control over which DMA termination conditions cause the interrupt

through the INT_STOP, INT_HALT, INT_DONE, INT_LERR, INT_VERR, and

INT_P_ERR bits in the DGCS register.

6.3 Dir ect Mode Oper atio n

When operated in direct mode, the Univer se II DMA is set through manual register

programming. Once the transfer described by the DVA, DLA, DTB C and DCTL

registers has been completed, the DMA sits idle a waiting the next manual

programming of the registers.

Figure 14 desc ribes the steps involved in operating the D MA in direct mode.

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Figure 14: Direct Mode DMA transfers

Step 1: Program DGCS

with tenure and interrupt

requirements

Step 2: Program

source/destination

addresses, & transfer

size/attributes

Step 4: Set GO bit

Step 5: Await termination

of DMA

Normal

Termination?

transfers

required?

Yes

Handle erro

Yes

Done

Step 3: Ensure status bits are clear

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In Step 1, the DGC S register is set up

— The CHAIN bit is cleared, VON and VOFF are programmed with the

appropriate values for controlling DMA VMEbus tenure, and the interrupt

bits (INT_STOP, INT_HALT, INT_DONE, INT_LERR, INT_VERR, and

INT_P_ERR) are progra mmed to enable generation of interrupts based on

DMA termination events. DMA interrupt enable bits in the LINT_EN or

VINT_EN bits should also be enabled as necessary (see “PCI Interrupt

Generation” on pa ge 131 and “VMEbus Interr upt Generatio n” on page 133

for details on generating interrupts).

In Step 2, the a ctual transfer is programmed into the DMA

— source and destination start addresses into the DLA and DVA registers,

transfer count into the DTBC register, and transfer width, direction and

VMEbus address space into the DCTL registe r. These should be

rep rogrammed aft er eac h transfer.

In Step 3, ensure that if any status bits (DONE, STOP, HALT, LER R, VERR, or

P_ERR) remain set from a previou s transfer they are cleared.

— P_ERR must not be updated at the same time as Step 4, otherwise the

P_ERR that may be generate d by setting GO may be missed (se e Step 4).

These bits can be cleared as p art of Step 1 .

In Step 4, with the transfer programmed, the GO bit in DGCS must be se t.

— If the DMA has been improperly progr ammed, either beca use the BM bit in

the PCI_CSR has no t been set t o enable P CI b us mas t ership, or the source

and destination start addresses are not aligned, then P_ERR will be

asserted. Othe rwise, the ACT bit will be set, and the DMA will then start

transferring data, sharing ownership of the VMEbus with the PC I Target

and Interrupt channels and the PCI bus with the VMEbus Slave Channel.

In Step 5, the DMA waits for termination of the DMA transfers.

— The DMA continues with the transfers until it:

– completes all trans fers

– is terminated early with the STOP_REQ bit

– encounters an error on the PCI bus or VMEbus

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Each of these conditions cause the ACT bit to clear, a nd a corresponding status bit

to be set in the DGCS register. If enabled in Step 1, an interrupt is generated. Once

the software has set the GO bit, the software can monitor for DMA completion by

either waiting for generation of an interrupt, or by polling the status bits. It is

recommended tha t a background timer also be initiate d to time-out the tr ansfer. This

ensures the DMA has not been hung up by a busy VMEbus, or other such system

issues.

If an early termination is desired (pe rhaps because a higher pr iority operation is

required) the STOP_REQ bit in the DGCS register can be set. This stops all DMA

operat ions on the source bus immedia tely, and set the ST OP bit in the same registe r

when the last piece of queued data in the DM A FIFO has been written to the

destination bus. Attempting to terminate the transfer with the HA LT_REQ bit has

no effect in direct mode operation since this bit only requests the DMA to stop

between command packets in linked-list mode operation.

When the softwar e has detected completion, it must verify the status bits in the

DGCS regist er to se e the reason for completion. If one of t he error bits have been set

it pr oceeds into an er ror ha ndling routin e (see “ DMA Error Handling” on page 126).

If the STOP bit was set, the software must take whateve r actions were programmed

when it set the STOP_REQ bit. For example, if it was stopped for a higher priority

transfer, it might record the DLA, DVA and DTBC re gisters, and then re program

them with the higher priority transfer. When that has completed it can restore the

DVA, DLA and DTBC registers to complete the remaining transfers.

If the DONE bit was set, it indicates that the DMA completed its reque sted transfer

successfully, and i f mo re trans fers are required, the software can pr oceed to Step 2

to start a new transfer.

6.4 Linked-list Mode

Unlike direct m ode, in which the DMA performs a single block of data at a time,

linked-list mode allows the DMA to transfer a series of non-contiguous blocks of

data without software intervention. Each entry in the linked- list is described by a

command packet which parallels the DMA register layout. The data structure for

each command packet is the same (see Figure 15 below), and contains all the

necessary information to program the DM A address and control registers. It could

be describe d in software as a record of eight 32-bit data elements. Four of the

elements repre sent the four core registers r equired to de fine a DMA transfer: DCTL,

DTBC, DVA, and DLA. A fifth element represents the DCPP register which points

to the next c ommand packet in the list. The least two signif icant bits of the DCPP

element (the PROCESSED and NULL bits) provide sta tus and control information

for linked list processing.

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The PROCESSED bit indicates whether a command packet has been processed or

not. When the DMA processes t he command packet and has successfull y complete d

all transf ers desc ribed by this packet, it sets the PROCESSED bit to 1 before reading

in the next c ommand packet in the list. The PROCESSED bit must be initially set

for 0. This bit, when set to 1, indic ates that this comm and packet has be en disposed

of by the DMA and its memory can be de-allocated or reused for another transfe r

description.

Figure 15: Command Packet Structure and Linked List Operation

Linked-List Start

Address in

Command Packet

Pointer Register

First Command Packet

in Linked-List

egister information

opied to DMA Control

nd Address Registers

DCPP points

to next command

packet

in Linked-List Second Command Packet

in Linked-List

Last Command Packet

in Linked-List

DCTL Register

DTBC Register

DLA Register

reserved

DVA Register

reserved

DCPP Register

reserved

rPN

DCTL Register

DTBC Register

DLA Register

reserved

DVA Register

reserved

DCPP Register

reserved

rPN

DCTL Register

DTBC Register

DLA Register

reserved

DVA Register

reserved

DCPP Register

reserved

rPN

r = reserved

P = processed bit

(after command packet is p

the bit is set to 1)

N = null bit

N = 1 for last command packet

N = 0 for another command pa

cke

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The NULL bit indicates the termination of the entire linked list. If the NULL bit is

set to 0, the DMA proc esses the next command packet pointed to by the command

packet pointer. If the NULL bit is set to 1 then the address in the command packet

pointer is considered invalid and the DMA stops at the completion of the transfer

described by the current command packet.

Figure 16 outlines the steps in programming the DMA for linked-list operation.

Figure 16: DMA Linked List Operation

In Step 1, the DGC S register is set up

— The CHAIN bit is set, VON and VOFF are programmed with the

appropriate values for controlling DMA VMEbus tenure, and the interrupt

bits (INT_STOP, INT_HALT, INT_DONE, INT_LERR, INT_VERR, and

INT_P_ERR) are progra mmed to enable generation of interrupts based on

DMA termination events. DMA interrupt enable bits in the LINT_EN or

VINT_EN bits should also be enabled as necessary (“PCI Interrupt

Generation” on page 131 and “VMEbus Interrupt Genera tion” on

page 133).

Step 1: Program DGCS

with tenure and interrupt

requirements

Step 4 : Set GO bit

Step 5 : Await termination

of DMA

Normal

Termination?

Yes

Step 2 : Set up linked-list

in PCI memory space

Step 3 : Clear DTBC

Done

handle erro

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In Step 2, the linked-list structure is programmed with the required transfers.

— The actual str ucture may be set up at any time with command packet

pointers pre-programmed and then only the remaining DMA transfer

elements need be programmed later. One common way is to set up the

command packets as a circular queue: ea ch packet points to the next in the

list, and the last points to the first. This allows continuous programming of

the packets without having to set-up or tear down packets later.

Once the struc ture for the linked-list is established, the individual packets are

programmed with the appropriate source and destination addresses, transfer sizes

and attributes.

In Step 3, Clear the DTBC register and program the DCPP register to point to the

first command packet in the list.

In Step 4, to start the linked-list transfer, set the GO bit in the DGCS register.

— The DMA first p erforms th e transfers defined by the current c ontents of the

DCTL, DTBC, DVA and DLA registe rs. Once that is compl ete it the n starts

the transfers defined by the linked-list pointed to in the DCPP register.

In Step 5, await and deal with termination of the DMA.

— Once the D MA ch annel is enabled, it pr o cesses the first command p acket

as specified by the D CPP register. The DMA transfer regi sters are

programmed by information in the command packe ts and the DMA

transfer st eps along each c ommand packet i n sequence (see Figure 15). The

DMA terminate when one of the following conditions are met:

– proc esses a command packet with the NULL bit set indicating the last

packet of the list

– is stopped with the STOP_REQ bit in the DGCS register

– is halted with the HALT_REQ bit in the DGCS register

– encounters an error on either the PCI bus or VMEbus

When using the DMA to perform linked-list transfers, it is important to

ensure that t he DTBC re gister co ntains a value of ze ro befor e set ting t he

GO bit of the DGCS register. Otherwise, the DMA cannot read the first

command packet but instead performs a dir ect mode transfer based on

the contents of the DCTL, DTBC, DLA, DVA and DGCS r egiste rs. After

this direct mode transfer is completed, the PROC ESSED bit of the first

command packet is programmed with a value of 1 even though the

packet was not actually pr ocessed. The DMA continues as expected with

the next command packet.

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Each of these conditions cause the ACT bit to clear, a nd a corresponding status bit

to be set in the DGCS register. If enabled in step 1, an interrupt is generated. Once

the software has set the GO bit, the software can monitor for DMA completion by

either waiting for generation of an interrupt, by polling the status bits in the DGCS

recommended tha t a background timer also be initiate d to time-out the tr ansfer. This

ensures that the DMA has not been hung up by a busy VMEbus, or other such

system issues.

Linked-list mode can be halted by setting the HALT_REQ bit in the DGCS register

(Table 90). When the HALT_REQ bit is set, t he DMA termina tes when all tran sfers

defined by the c urrent command pa cket is complete. It then loads the next command

packet into its registers. The HALT bit in the DGCS register is asserted, and the

ACT bit in the DGCS register is cleared. The PROCESSED bit in the linked-list is

set t o 1 approximately 1 µs after the HALT bit is s et: the refor e afte r a DMA halt the

user should wait at least 1 µs before checking the status of the PROCESSED bit.

The DMA can be restar ted by clearing the HALT status bit and setting the GO bit

during the same register write. If the DMA is restarted, the ACT bit is set by the

Universe II and execution continues as if no HALT had occurred: i.e., the

Universe II processes the current command packet ( see Figure 15 above).

In contrast to a halt, the DMA can also be immediate ly terminated through the

ST OP_REQ bit. This st ops al l DMA operation s on the source bus immediately, and

set the ST OP bit in the same registe r when the last piece of queued data in the DMA

FIFO has been written to the destination bus.

Once stopped, the DVA, DLA and DTBC registers contain values indicating the

next addresse s to read/write and the number of bytes rem aining in the transfer.

Clearing the STOP bi t and setting the GO bit causes the DMA to start -up again from

where it left off, inc luding continuing with subsequent command packets in the list.

If the DMA is being stopped to insert a high priority DMA transfer, the remaining

porti on of the DMA transf er can be stor ed as a ne w command packet inse r ted at t he

top of the linked list. A ne w co mmand packet with the attr ibute s o f t he high pr io ri ty

transfer is then placed before that one in the list. Now the linked list is set up with

the high priority packet first, followed be the remainder of the interrupted packet,

followed in turn by the rest of the linked list. Finally, the DTBC register is cleared

and the DCPP program med with a pointer to the top of the list where the high

priority command packet has been placed. When the GO bit is set (after clearing the

ST OP status bit in the DGCS regist er), the DMA performs the tran sfer s in the or der

set in the linked list. For more details on updating the linked list see “Linke d-list

Updating” on page 120.

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DMA transfers continue until the DM A encounters a comm and packet with the

NULL bit s et to 1, indicating t hat the la st pac ke t has been reached. At th is point, the

DMA stops, the DONE bit is set, and the ACT flag is c leared. As it completes the

transfers indicated by each command packet, the DMA sets the PROCESSED bit in

that command packet before reading in the next command packet and processing its

contents.

6.4.1 Linked- lis t Upd ati ng

The Universe II provides a mechanism which enables the linked-list to be updated

with additional linked list e ntries without ha lting or stopping the DM A. This takes

place through the use of a semaphore in the devic e: the UPDATE bit in the D_LLUE

command p acket into the DMA registers while th e command p acket (outside t he

Universe II) is being updated. This semaphore does not prevent e xternal masters

from updating the DMA registers.

Adding to a linked list begins by writing a 1 to the UPDATE bit. The DMA checks

this bit be fore proceeding to the nex t command packet. If the UPDATE bit is 0, then

the DMA locks the UPDATE bit against wr ites and proceeds to the next command

packet. I f the UPDATE bit is 1, then the DMA waits until the bit is cleared before

proceeding to the next command packet. Setting the UPDATE bit is a means of

stalling the DMA at command packet boundaries while local logic updates the

linked-list.

In order to e nsure that the DMA is not currently reading a command packet during

updates, t he update l ogic must write a 1 to the UPDATE bit an d read a value back. If

a 0 is read ba ck from the UPDATE bit, then the DM A is currently reading a

command packet and has locked the UPDATE bit against w ri tes. If a 1 is read back

from the UPDATE bit, then the DMA is idle or processing a tra n saction and

command packets ca n be updated. If the DMA attem pts to proceed to the next

command packet duri ng the update, it encount ers the set UPDATE bit and wait unt il

the bit is cleared.

If a set of linked command packets has a lready been created with empty packets at

the end of new transfers, adding to the end of the current linked list is accomplished

by the following steps:

1. Get UPDATE valid (write 1, read back 1)

2. Program attributes for new transfer in next available packet in list

3. Change null pointer (on previous tail of linked list)

4. Release update (clear the UPDATE bit)

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After updating the linked list, the DMA controller is in one of the following

conditions:

1. It can be active and working its way through the linked list. In this case, no

further ste ps are required.

2. The DMA can be idle (done) because it reached the final command packet. If a

full set of linked c ommand p ackets had already been cr eated ahea d of ti me, then

the DCPP registe r points to the most recently programmed command packet,

and the DTBC register would be zero. The DMA can be started on the new

packet by simply clearing the DONE bit and se tting the GO bit in the DGCS

regist er. If a set of co mmand p ackets have not been created ah ead of time, the

DCPP register ca n not be programmed to any valid packet, and needs

programming to the newly programmed packet.

3. The DMA has encountered an error. In this circumstance, see “ D MA E rror

Handling” on page 126 for how to handle DM A errors.

Operation can be considerably simplified by ensuring that sufficient command

packets have been cre ated during syste m initializat ion, probably in a circul ar queue.

In this fa shion, when a new entry is added to the list, it is sim p ly a matter of

programming the next a vailab le entry in the list wit h the new tr ansfer attri bute s and

changing the previously last packe t's NULL bit to zero. The DCPP register is

guaranteed to po int to a valid command packet, so u pon updating t he list, both case s

1 and 2 above can be covered by clearin g the DONE bit and setti ng the GO bit. This

has no eff ect f or case 1 since the DMA is still active , and restarts the DMA for case

If an error has been encountered by the DM A (case 3), setting the GO bit and

clearing the D ONE bit is not be sufficient to restar t the DMA—the error bits in the

DGCS register also has to be cleared before operation can continue.

6.5 FIFO Operation and Bus Ownership

The DMA uses a 256-byte, 64-bit FIFO (DMAFIFO). This supports high

performance DMA transfers. In general, the DMA reads data from the source, and

stores it a s transactions in the FIFO. On the destination side, the DMA requests

ownership of the master and once granted begins transfers. Transfers stop on the

source si de when the FIFO fills, and on the destination si de when the FIFO empties.

6.5.1 PCI-to-VM Eb us Transfers

PCI-to-VMEbus transfers involve the Universe II reading from the PCI bus and

writing to the VMEbus.

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The PCI bus is requested for the current read once 128 bytes are available in the

DMAFIFO. The DMA Channel fills the DMAFIFO using PCI read transactions

with each tra nsaction broken at address boundaries determined by the programmed

PCI aligned burst size (PABS field in the M AST_CTL register, Table 116). This

ensures that the DMA m akes optimal use of the PCI bus by always generating

bursts of 32, 64 or 128 bytes with zero wait states.

The DMA packs read data into the DMAFIFO to the full 64-bit width of the FIFO,

independent of the width of the P CI bus, or the data width of the ensuing VMEbus

transact ion. The PCI read transa ctions contin ue until eithe r the DMA has completed

the full programmed transfer, or there is insufficient room available in the

DMAFIFO for a full tr ansaction. The available space required for anothe r burst read

transaction is again 128 bytes.

When the DMAFIFO fills, the PCI bus is free for other tran saction s (for e x ample,

between other devices on the bus or possibly for use by the Universe II’s VMEbus

Slave Channel). The DMA only resumes read transactions on the PCI bus when the

DMAFIFO has space for another aligned bur st size transaction.

The DMA requests owner ship of the Universe II's VMEbus Master Inter face once

64 bytes of data have been queued in the DMAFIFO (see “VMEbus Requester” on

page 35 on how the VMEbus Master I nte rfac e is sha red be tween t he DMA, the PCI

Targe t Channel, and the Inte rrupt Channel) . The Universe II maintains owne rship of

the Master Interface until one of the following conditions are met:

• DMAFIFO is empty,

• DMA block is complete

Since the VMEbus is typically much slower than the PCI b us, the

DMAFIFO can fill frequently during PCI to VMEbus transfers, though

the depth of the F IFO helps to minimize this situation.

The DMA can prefetch extra read data from the external PCI target. This

means that the DMA m u st only be used with m em ory on the PCI bus

w hich has no adverse side-effects whe n prefetc hed. The U niverse II

prefetches up to the aligned address boundary defined in the PABS field

of the MASC_CTL register. On the VMEbus, the actua l programmed

number of bytes in the DTB C register are written. Prefetching can be

avoided by programming the DM A for transfers that terminate at the

PAB S boundary. If further data is required beyond the boundary, but

before the next boundary, the DTBC register may be programmed to

eight byte transfers. The DMA fetch es the full eight byte s, and nothing

more. Programming the DTBC to less than eight bytes still results in

eight bytes fetched from PCI.

6. DMA Controller
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• DMA is stopped
• a linked list is halted 
• DMA encounters an erro r 
• DMA VM Ebus tenure limit ( VON in the DGCS register)
The DMA can be programmed to li mit its VMEbu s tenure to fi xed block siz es using 
the VON field in the DGCS register (Table 90). With VON enabled, the DMA 
relinquishes ownership of the Master Interface a t defined address boundaries. See 
“DMA VMEbus Ownership” on page 110. 
To further control the DMA’s VMEbus ownership, the VOFF timer in the DGCS 
register  can be used to program the DMA to remain off the VMEbus for a specif ied 
period when VMEbus te nure is relinquished. See “DMA VMEbus Ownership” on 
page 110.
The DMA Channel unpacks the 64-bit data queued in the DMAFIFO to whatever 
the programmed transfe r width is on the VMEbus (D16, D32, or D64). The 
VMEbus Master Interface delivers the data  in the DMAFIFO according to the  
VMEbus cycle type programmed into the DCTL register (Table 85, see 
““Overview” on page 103). The DMA provides da ta to the VMEbus until o ne of the 
following conditions are met:
• DMAFIFO empties
• DMA VM Ebus Tenure Byte Count (VON in the DMA_GCSR register 
Table 90) expires.
If the DMAFIFO empties transfers on the VMEbus stop and, if the cycle being 
generated is a block transfer, then the block is terminated (AS* negated). The 
VMEbus ownership is relinquished by the DM A. The DM A does not re-request 
VMEbus ownership until another eight entries are queued in the DM AFIFO, or the  
DMA Ch annel has  com pl eted the  current Transfer Bloc k on  th e P CI bus  (see 
“VMEbus Release” on page 37 ).
PCI bus transac tions are the full width of the PCI data bus with appropriate byte 
lanes enable d. The maximum VMEbus data width is programmable to 8, 16, 32, or 
64-bit. Byte transfe rs can be only of type DO8 (EO) . Because the PCI bus has a 
more flexible byte lane enabling schem e than the VMEbus, the Universe II can be 
required to generate a variety of VMEbus transaction types to handle the byte 
resolution of the starting and ending addresses (see  “Data Transfer” on page 67).
6.5.2 V M Ebus -to-P CI Transfer s
VMEbus-to-PCI transfers involve the Universe II reading from the VMEbus and 
writing to the PCI bus.

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W ith DMA transfers in this dir ection, the DMA Channel begins to queue data in the

DMAFIFO as soon as there is room for 64 bytes in the DMAFIFO. When this

watermark is re ached, the DMA request s the VMEbus (thr ough the VMEbus Master

Interface ) and begins reading data from the VMEbus. The Universe I I m aintains

VMEbus ownership until one of the following conditions are met:

• DMAFIFO is fu ll

• DMA block is complete

• DMA is stopped

• a linked list is halted

• DMA encounters an error

• VMEbus tenure limit is reached (VON in the DGCS register)

The DMA can be programmed to li mit its VMEbu s tenure to fi xed block siz es using

the VON field in the DGCS register (Table 90). With VON enabled, the DMA will

relinquish ownership of the Master I nterface at define d address boundaries. See

“DMA VMEbus Ownership” on page 110.

To further control the DMA’s VMEbus ownership, the VOFF timer in the DGCS

period when VMEbus te nure is relinquished. See “DMA VMEbus Ownership” on

page 110.

Entries in the DMAFIFO are delivered to the PCI bus as PCI write transactions as

soon as there are 128 bytes available in the DMAFIFO. If the PC I bus responds too

slowly, the DMAFIFO runs the risk of filling before write transactions can begin at

the PCI Master In te rface. Once the DMA FIFO reaches a nearly full state (three

entries rema ining) the DMA requests that the VMEbus Master Interface complete

its pending operations and stop. The pending read operations fill the DMAFIFO.

Once the pending VMEbus reads are completed (or the VON timer expires), the

DMA relinquishes VMEbus ownership and only re -requests the VMEbus Maste r

Interface once 64 by tes again become available i n th e DMAFIFO. If the b u s was

released due to encountering a VON boundary, the bus is not re-requested until the

VOFF timer expires.

PCI bus transac tions are the full width of the PCI data bus with appropriate byte

lanes enable d. The maximum VMEbus data width is programmable to 8, 16, 32, or

64 bits. Byte transfers can be only of type DO8 (EO). Because the PCI bus has a

more flexible byte lane enabling schem e than the VMEbus, the Universe II can be

required to generate a variety of VMEbus transaction types to handle the byte

resolution of the starting and ending addresses (see “Universe II as PCI Target” on

page 72).

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6.6 DMA Interrupts

The Inte rrupt Channel in the Universe II ha ndles a singl e inter rup t sourc ed from the

DMA Channel which it routes to either the VMEbus or P CI bus through the DMA

bits in the LINT_EN and VINT_EN registers. There are six internal DM A sources

of interrupts and these are all route d to this single interrupt. Each of these six

sources can be individually enabled, and are listed in Table 16 below. Setting the

enable bit enables the corresponding interrupt source.

6.7 DMA Channel Interactions with Other

Channels

This se ction de scri bes the impac t tha t t he PCI B us Tar ge t Channel a nd t he VMEbus

Slave Channel can have on the DMA Channel.

Table 16: DMA Interrupt Sources and Enable Bits

Interrupt Sour ce Enable Bit

Stop Request INT_STOP

Halt Request INT_ H ALT

DMA Completion INT_DONE

PCI Target-Abort or Master-Abort INT_LERR

VMEbus Error INT_VERR

Protocol Error INT_M_ERR

Once an enabled DM A interrupt has occur red the corresponding DMA

bit in the LINT_STAT (Table 93) and VINT_STAT (Table 97) registers

are set - regardless of whether the LINT_EN or VINT_EN enable bits

have been set. Each one must be cleared independently. Clearing either

the LINT_STAT or VINT_STAT registers does not clear the other. See

“Interrupt Generation and Handling” on page 129.

The Universe II does not apply PCI 2.1 Specification transaction

ordering requirements to the DMA Controller. Reads and writes

through the DMA Controlle r can occur independently of the other

channels.

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ADOH cycles and RMW cycles through the VMEbus Slave Channel do im pact on

the DMA Channel . Once an external VMEbus mast er locks t h e PCI bus , the DMA

Controller does not perform transfers on the PCI bus until the Universe II is

unlocked (see “VME bus Lock Commands (ADOH Cycles)” on page 49). When an

external VME b us Mas ter begin s a RMW cycle, at som e p oint a read cycle appears

on the PCI bus. Dur ing the time bet ween when th e re ad cy cle occ ur s on t he PCI bus

and when the associated w ri te cycle occurs on the PCI bus , no D MA transfers

occurs on th e PCI bus (se e “VMEbus Read-M odify-Write Cycles (RMW C ycles)”

on page 50).

If t he PCI Tar get Ch annel locks the V MEbus u sin g VOWN, n o DMA tr ansfe rs t akes

place on the VMEbu s (see “Using the VOWN bit” on pa ge 81).

6.8 DMA Error Handling

This section describes how the Universe II responds to err ors involving the DM A,

and how the user c an recover from them. The software source of a DMA error is a

protocol, and the hardware source of a DMA error is a VMEbus error, or PCI bus

Target-Abort or Master-Abort.

6.8.1 DMA Software Respo ns e to Er ror

While the DMA is operating normally, the ACT bit in the DGCS register is set

(Table 90). Once the DMA has terminated, it clea rs this bit, and sets one of six

statu s bits in the same regi ster. The DONE bit will be set if the DMA completed all

its programm ed operations normally. If the DMA is interrupted, either the STOP or

HALT bits are set. If an error has occurred, one of the remaining three bits, LERR,

VERR, or P_ERR, is set. All six forms of DMA terminations can be optionally set

to generate a DMA interrupt by setting the appropriate e nable bit in the DGCS

• LERR is set if the DMA encounters an er ror on the PCI bus (either a

Master-Abort or Target-Abort) : Bits in the PCI_CSR register will indicate

which of these c onditions caused the error.

• VERR is set i f the DMA encounters a bus er ror on t he VMEbus. This is t hrough

a detected assertion of BERR* during a DMA cycle.

• P_ERR is set if the GO bit in the DGCS registe r is set to start th e DMA, and the

DMA has been improperly programmed either because the BM bit in the

PCI_CSR disables P CI bus m astership, or the source and destination start

addresses are not aligned (see “Source and Destination Addresses” on

page 104).

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Whether the error occurs on the destination or source bus, the DMA_C TL register

contains the attributes relevant to the particular DMA transaction. The DTB C

DTBC regist er contains vali d values after an error. The DLA and DVA registers

should not be used for error recovery.

6.8.2 DMA Hardware R espo ns e to Error

When the error conditi on (VMEbus Error , Target- Abort, or Master -Abort) oc curs on

the source bus while the DMA is reading from the source bus, the DMA stops

reading from the source bus. Any data previously queued within the DMAFIFO is

writt en to the destinati on bus. Onc e the DMAFIFO empties, the error status bit is set

and the DMA generates an interrupt (if enabled by INT_LERR or INT_VERR in

the D GCS register—see “DMA Interrupts” on pa ge 125).

When the error conditi on (VMEbus Error , Target- Abort, or Master -Abort) oc curs on

the destination bus while the DM A is writing data to the destination bus, the DMA

stops writing to the destination bus, and it also stops reading from the sour ce bus.

The error bit in the DGCS register is set and an interrupt a sserted (if enable d).

6.8.2.1 Interrupt Generation During Bus Errors

To generate an interrupt from a DMA error, there are two bits in the DGCS register ,

and one bit each in the VINT_EN and LINT_EN registers. I n the DGCS registe r the

INT_LERR bit enables the DMA to generate an interrupt to the Interrupt Channel

after encountering an error on the PCI bus. The INT_VERR enables the DMA to

generate an interrupt to the Interrupt Channel upon encountering an error on the

VMEbus. Upon reaching the Inter rupt Channel, all DMA i nterrupts can be routed to

either the PCI bus or VMEbus by setting the appropriate bit in the enable registers.

All DMA sources of interrupts (Done, Stopped, Halted, VMEbus Error, and PCI

Error) constitute a single interrupt into the Interr upt Channel.

6.8.3 Resuming DMA Transfers

When a DMA erro r occurs (on the source or destina tion bus), the sta tus bits must be

read in o rder to determ ine the source of the erro r. If it is possible to re sume the

transfer, the transfer should be resumed at the address that was in place up to 256

bytes from the current byte count. The original addresses (DLA and DVA) are

required in order to resume the transfer at the appropriate location. However, the

values in the DLA and the DVA registers shou ld not be used to reprogra m the DMA,

because they are not valid once the DMA begins. In direct mode, it is the user’s

responsibility to record the original state of the DVA and DLA registers for error

reco v ery. In Li nked-List mod e, t he user can re fer to the cu rrent Command Packet

stored on the PCI bus (whose location is specified by the DCPP register) for the

location of the DVA and DLA information.

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The DTBC re gister conta ins the number of bytes remaining to transfer on the sour ce

side. The Universe II does not store a count of bytes to transfer on the destination

side. If the error occurr ed on the source side, the n the location of the error is simply

the latest source address plus the byte count . If the error occurr ed on the dest ina tion

side, then one cannot infer specifically where the error occurred, because the byte

count only refers to the number of data queued from the source, not what has been

written to the destination. In this case, the error will have occ urred up to 256 bytes

before: the original address plus the byte count.

Given this background, the following procedure can be implemented to recover

from errors.

1. Read the value contained in the DTBC register.

2. Read the record of the DVA and DLA that is stored on the PCI bus or elsewher e

(not the value stored in the Universe II registers of the sam e name).

3. If the differenc e between the value contained in the DTBC register a nd the

original value is less than 512 bytes (the FIFO depth of the Universe II),

reprogram all the DMA registers with their original values.

4. If the differenc e between the value contained in the DTBC register a nd the

original va lue is greater t han 512 byte s ( the F IFO dept h of the Universe II ), add

512 bytes to the value contained in the DTBC register.

5. Add the difference be tween the original value in the DTBC and the new value

in the DTBC register to the original va lue in the DLA register.

6. Add the difference be tween the original value in the DTBC and the new value

in the DTBC register to the original va lue in the DVA register.

7. Clear the status flags.

8. Restart t he DMA (see “DMA Initiation” on page 109).

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7. Interrupt Generation and Handling

An interrupt is a signal informing a pr ogram t hat an even t (for example, an error)

has occurred. Whe n a program receives an interrupt signal, it temporarily suspends

normal proc essing and diverts the execution of instr uctions to a sub- routine handled

by an interrupt controller. The controller communicates with the host processor and

the device that initiated the interrupt to determine how to handle the interrupt.

Interrupt signals can come from a variety of sources. Interrupt signals generated by

devices (for example, a printer) indicate an event has occurred and are called

hardware interrupts. Interrupt signals generated by pr ograms are called software

interrupts.

This chapter discussed the inte rrupt generation and handling functiona lity of the

Universe II. This chapter discusse s the following topics:

•“Interrupt Generation” on page 131

•“Interrupt Handling” on page 136

7.1 Overview

The Universe II has two types of interrupt capability: it is a generator of interrupts

and an interr upt handler.

The Interrupt Channel handles the prioritization a nd routing of inte rrupt sources to

interrupt outputs on the PCI bus a nd VMEbus. The interrupt sources are:

• the PCI LINT_[7:0] lines

• the VMEbus IRQ*[7:1] lines

• ACFAIL* and SYSFAIL*

• various i nternal events

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These sources can be routed to either the PCI LINT_ [7:0] lines or the VMEbus

IRQ* [ 7:1] lines. Each i nte rrupt source is i ndividua ll y m ask able and c a n be mapped

to various int err upt outp uts. Most inte rrupt sources can be mapped to one part icula r

destination bus. The PCI sources, LINT_[7:0], can only be mapped to the VMEbus

interrupt outputs. The VMEbus sourc es, VIRQ[7:1], are not mapped to the P CI bus

interrupts. How ever, the VIRQ[7:1] bits are status bits which indicate whether or

not a STATUS/ID vector has been acquir ed. This indic ation c an be used to gener ate

an interr upt on the PCI bus. S ome inter nal sources ( for example, e rro r condit ions or

DMA activity) can be mapped to either bus.

Figure 17: Universe Interrupt Circuitry

Figure 17 illustrates the circuitry inside the Universe II Interrupt C hannel. The PCI

hardware interrupts are listed on the left, and the VMEbus interrupt inputs and

outputs a re on the r ight. Inte rnal inter rupts ar e also il lustrated. The figure shows that

the interrupt sources may be mapped a nd enabled. The Internal Interrupt Handler is

a block within the Universe II that detects assertion of the VRIRQ_[7:1] pins and

generates the VME IACK through the VME Master. Upo n complet ion of the IACK

cycle, the Inte rnal Interrupt Handle r notifies the M apping Block which in turn

asserts the loc al LINT_, if en abled. (Whereas the Inter nal Int errupt Ha ndle r implies

a delay between asser tion of an interrupt condition to the Universe I I and the

Universe’s mapping of the interrupt, all other interrupt sources get mapped

immediately to their destination—assertion of LINT_ immediately causes an IRQ,

asserti on of ACFAIL immedi ately caus es an LINT_, etc.)

INT [7:0]

VRIQ[7:1]_

VXIRQ[7:1]_

VRACFAIL_

VRSYSFAIL

and Enabling

Mapping

and Enabling

Mapping

Internal

Interrupt

Handler

Internal

Sources

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7.2 Interrupt Generation

The Universe II has the ability to generate interrupts on both the PCI bus and

VMEbus.

7.2.1 PCI Interrupt Generation

The Universe II expands on the basic P CI specification which pe rmits “single

function” devices to assert only a single interrupt line. Eight PCI inter rupt outputs

provide maximum flexibility, although if full PCI compliancy is require d, all

interrupt sources can be routed to a single PCI interrupt output.

PCI interrupts may be generated from multiple sources:

• VMEbus sources of PCI interrupts

— IRQ*[7:1]

—SYSFAIL*

—ACFAIL*

– internal sources of PCI inte rrupts

—DMA

— VMEbus bus error enc ountered

— PCI Targe t-Abort or Master-Abort encountered

— VMEbus ownership has be en granted while the VOWN bit is set (see

“V ME Loc k Cycles—Exclusive Access to VMEbus Resources” on

page 80)

— Software interrupt

— Mailbox a ccess

— Location monitor access

— VMEbus IACK cycle performed in response to a software interrupt

Each source ca n be individually e nabled in the LINT_EN register (Table 92) and

mapped to a single LINT_ signal through the LINT_MAP0, LINT_MAP1, and

LINT_MAP2 registers (Ta ble 94, Table 95, Table 108). When an interrupt is

received on any of the enabled sources, the Universe II asserts the appropriate

LINT_ pin and sets a matching bit in the LINT_STAT re gister (Table 97). See

Table 18 on page 134 for a list of the enable, mapping and status bits for PCI

interrupt sources.

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The LINT_STAT register shows the status of all sources of PCI interrupts,

independent of whether that source has been enabled. This implies that an interrupt

handling routine m u st mask out those bits in the register that do not correspond to

enabled sources on the active LINT_ pin.

Table 17: Source, Enabling, Mapping, and Status of PCI Interrupt Output

Interrupt Sour ce

Enable Bit in LINT_EN

(Table 92)

Mapping Field in

LI N T_MA P x ( Table 94,

Table 95, Table 108) Status Bit in

LI N T_STAT (Table 93)

ACFAIL* ACFAIL ACFAIL ACFAIL

SYSFAIL* SYSFAIL SYSFAIL SYSFAIL

PCI Software

Interrupt SW_INT SW_INT SW_INT

VMEbus So ftware

IACK SW_IACK SW_IACK SW_IACK

VMEbus Erro r

occur r ed during a

post ed write

VERR VERR VERR

PCI Target-Abort or

Maste r-Abort

occur r ed during a

post ed write

LERR LERR LERR

DMA Event DMA DMA DM A

VMEbus Interrupt

Input VIRQ7-1 VIRQ7-1 VIRQ7-1

Locat ion M onitor LM3 -0 LM3-0 LM3 -0

Mailbo x Acces s MBOX3-0 MBOX3-0 MBOX3-0

VMEbus Owne rship VOWN VOWN VOWN

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Except for SYSFAIL* and ACFAIL*, all sources of PCI interrupts are

edge-sensitive. Enabling of the ACFAIL* or SYSFAIL* sources (ACFAIL and

SYSFAIL bits in the LINT_EN register) causes the status bit and mapped PCI

interrupt pin to assert synchronously with the asser tion of the ACFAIL* or

SYSFAIL* source. The PCI inte rrupt is negated once the ACFAIL or SYSFAIL

status bit is cleared. The status bit cannot be cleared if the source is still active.

Therefore, if SYSFAIL* or ACFAIL* is still asserted while the interrupt is enabled

the interrupt will continue to be asserted. Both of these sources ar e synchronized

and filtered with multiple edges of the PCI clock at the ir inputs.

All other sources of PCI interrupts are edge-sensitive. The VMEbus source f or PCI

interrupts actually comes out of the VMEbus Interrupt Handler block and reflects

acquisition of a VMEbus STATUS/ID. Therefore, even though VMEbus interrupts

externally are level-sensitive as required by the VMEbus Specification, they are

internally ma pped to edge-sensitive interrupts (see “VMEbus Interrupt Handling”

on page 136).

The interrupt source status bit (in the LINT_STAT register) and the mapped LINT_

pin remain asserted with all interrupts. The status bit and the PCI interr upt output

pin are only released when the inte rrupt is cleared by writing a 1 to the appropriate

status bit.

7.2.2 VMEbus Interrupt Generation

This section details the conditions under which the Universe II generates interrupts

to the VMEbus.

Interrupts may be generated on any comb ination of VMEbus interrupt lines

(IRQ*[7:1]) from multipl e sources:

• PCI sources of VMEbus interrupts

—LINT_[7:0]

• Internal sources of VMEbus interrupts

—DMA

— VMEbus bus error enc ountered

— PCI Targe t-Abort or Master-Abort encountered

— Mailbox r eg ister ac cess

— Software interrupt

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Each of these  sources may be individually enabled through the VINT_EN register 
(Table 96) and mapped to a particula r VMEbus Interrupt level using the 
VINT_MAPx registers (Table 98, Table 99, and Table 109). Multiple sources m ay 
be mapped to any VMEbus level. Mapping interrupt sources to level 0 effectively 
disables the  interrupt. 
Once an i nterrupt has  been received f rom any of the sour ces, the Unive rse II sets the  
corresponding status bit in the VINT_STAT register (Table 97), and asserts the 
appropr iate VMEbus interru pt output signal ( if enabled). When a VMEbus int errupt 
handler receives the interrupt, it will perform an IACK cycle at that interrupt level. 
When the Uni verse II decodes that I A CK cy cl e togeth er with IACKIN* assert ed, it 
provides the STATUS/ID previously stored in the STATID register (Table 100), 
unless  it is  configured as  SYSCON in whic h case it d oes not  monitor I ACKIN*. See 
Table 18 for a list of the enable, mapping and status bits for VMEbus interrupt 
sources.
Table 18: Source, Enabling, Mapping, and  Status of VMEbus Interrupt Outputs
Interrupt Sour ce
Enable Bit in VINT_EN
(Table 96)
Mappi ng Fi eld in 
VINT_MAPx
(Table 98, Table 99, 
Table 109)
Status Bit in 
VINT_STAT
(Table 97)
VMEbus So ftware 
Interrupt SW_INT7-1 N/Aa
a. This set of sof t war e in terr upt s cannot be  map ped. That is, set tin g th e SW_INT1 bi t trigg ers  VXI RQ 1,  
setting the SW_INT2 bit trigg er s VXI RQ 2,  etc.
SW_INT7-1
VMEbus Erro r  VERR VERR (Table 99) VERR
PCI Target-Abort or 
Maste r-Abort  LERR LER R (Table 99) LERR
DMA Event DMA DMA (Table 99) DMA
Mailbox Register MBOX3-0 MBOX3-0 (Table 109) MBOX3-0
PCI bus Interrupt 
Input LINT7-0 LIN T7- 0 (Table 109) LIN T7- 0
VMEbus So ftware 
Interrupt
(mappable)
SW_INT SW_INT(Table 99) SW_INT

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For all VMEbus interrupts, the Univer se II interrupter supplies a pre-programmed

8-bit STATUS/ID; a common value for all inter rupt le vels. The upper seven bits are

programmed in the STATID register. The lowest bit is cleared if the source of the

interrupt was the software inter rupt, and is set for all other interrupt sources. If a

software interrupt source and another interrupt sourc e are active and mapped to the

same VMEbus interrupt level, the Universe II gives priority to the software source.

Figure 18: STATUS/ID Provided by Universe II

Once the Universe II has provided the STATUS/ID to an interrupt handler during a

software initiated VMEbus interrupt, it generates an internal interrupt, SW_IACK.

If enable d, this interrupt feeds back to the PCI bus (through one of the LINT_ pins)

to signal a process that the interrupt started through software has been completed.

All VMEbus interrupts generated by the Universe II are RORA, except for the

software interrupts which are ROAK. This m ea ns that if the interrupt source was a

softwar e interrupt, t hen the VMEbus interrupt output is automatic ally negate d when

the Universe II receives the IAC K cycle. However, for any other interrupt, the

VMEbus interrupt output remains asserted until cleared by a register access.

W r it ing 1 to the releva nt bit in the VINT_STAT regist er clear s that inte rr upt sour ce.

However, since PCI interrupts are level-sensitive, if an attempt is made to clea r the

VMEbus interrupt while the LINT_ pin is still asserted, the VMEbus interrupt

remains asserted. For this reason, a VMEbus interrupt handler should clear the

source of the PCI interrupt before clearing the VMEbus interrupt.

Since s oftware inter r upts ar e ROAK, the res pecti ve bi ts i n the VINT_STAT regist er

are cleared automatic ally on comple tion of the IACK cycle, simultane ously with the

negation of the IRQ.

Programmed from

VME_STATUS/ID

Registers

0 if S/W Interrupt Source

1 if Internal or LINT

Interrupt Source

STATUS/ID

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7.3 I nterrupt Handling

The Universe II can handle interrupts from both the PCI bus and the VMEbus.

7.3.1 P C I In te rrup t Handli ng

All eight PCI interrupt lines, LINT_[7:0], can act as inte rrupt inputs to the

Universe II. They are level-sensitive and, if enabled in the VINT_EN register

(Table 96), immediately generate an interrupt to the VMEbus. It is expected that

when a VMEbus interrupt handler receives the Universe II’s STATUS/ID from the

Universe II, the interrupt handle r clears the VMEbus interrupt by first clearing the

source of the interrupt on the P CI bus, and then clearing the VMEbus interrupt (by

writing a 1 to the appropriate bit in the VINT_STAT r egister, Table 97).

Note that since PCI interrupts are level-sensitive, if an attempt is made to clear the

VMEbus interrupt while the LINT_ pin is still asserted, the VMEbus interrupt

remains asserted. Th is causes a second interr upt to be generated to the VMEbu s. For

this r easo n, a VMEbus int err upt h andl er s hould clea r the sou rce of th e PCI inte rrup t

before clea ring the VMEbus interrupt.

7.3.2 VMEbus Interrupt Handling

As a VMEbus interrupt handler, the Universe II can monitor any or all of the

VMEbus interrupt levels. It can also m onitor SYSFAIL* and ACFAIL*, although

IACK cycles are not generated for these inputs. Each interrupt is enabled through

the LINT_EN register (Table 92).

Once enabled, assertion of any of the VMEbus interrupt levels, IRQ[7:1]*, causes

the internal interrupt handler circ uitry to request ownership of the Universe II's

VMEbus Mast er Interf ace on th e le vel progra mmed in the MAST_CTL re gister (se e

“VMEbus Requester” on page 35). This inte rface is shared betwe en several

channels in the Universe II: the P CI Ta rget Channel, the DM A Channel, and the

Interrupt Channel. The Interrupt C hannel has the highest priority over all other

channels and, if an interrupt is pending, assumes ownership of the VMEbus Master

Interface when the previous owner has relinquished ownership.

The Uni verse I I latches the f irst interrupt tha t a ppears on the VMEbus and begins to

process it immediately. If an interr upt at a highe r priority i s asserted on t he VMEbus

before B BSY* is asserte d the Unive rse II pe rforms an int errupt acknowledge f or the

first inte rrupt it det ected. Upon completion of that I ACK cycle , the Uni verse II then

performs IACK cycles for the higher of any remaining active interrupts.

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There may be some la tency between reception of a VMEbus interrupt and

generation of the IACK cycle. This arises because of the latency involved in the

Interrupt Channel gaining control of the VMEbus Master Interface, and because of

possible latency in gaining ownership of the VMEbus if the VMEbus Master

Interface is programmed for release-whe n-done. In addition, the Universe II only

generates an interrupt on the PCI bus once the IACK cycle has complete d on the

VMEbus. Because of these combined latencies (tim e to acquire VMEbus and time

to r un the IACK c ycle), syste ms should be designed t o accommodate a certain worst

case latency from VMEbus interrupt generation to its translation to the PCI bus.

When the Unive rse II recei ves a STATUS/ID in response to an I ACK cycle, it sto res

that value in one of seven registers. These registers, V1_STATID through

V7_STATID (Table 101 to Table 107), store the STATUS/ID correspondin g to each

IACK level (in the STATID field). Once an IACK cycle has been generated and the

resulting STATUS/ID is latched, another IACK cycle is not run on that level until

the level has been c leared by writing a 1 to the corresponding status bit in the

LINT_STAT register (Table 97). If other interrupts (at different levels) a re pending

while the interrupt is waiting to be cleared, IACK cycles are run on those levels in

order of priority and the STATUS/IDs stored in their respective registers.

Once the IACK cycle is complete an d the STATU S/ID s tored, an i nterrupt is

generated to the PCI bus on one of LINT_[7:0] depending on the mapping for that

VMEbus level in the LINT_MAP 0 register. The interrupt is cleared and the

VMEbus interrupt level is re-armed by clearing the correct bit in the LINT_STAT

7.3.2.1 Bus Error During VMEbus IACK Cycle

A bus error encountered on the VMEbus while the Universe II is performing an

IACK cycle is handled by the Uni verse I I in two ways. The first is through the e rror

logs in the VMEbus Master Interface. These logs store address and com mand

information when ever the Universe II encounters a bus error on the VMEbus (see

“Error Handling” on pa ge 147). If the error occurs during an IACK cycle, the

IACK_ bit is set in the V_AMERR register (Table 144). The VMEbus Master

Interface also generates an internal interrupt to the Interrupt Channel indicating a

VMEbus error occurred. This i nternal interrupt can be enable d and mapped to e ither

the VMEbus or PCI bus.

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As well as gener ating an interr upt indicating an erro r during the IACK cycle, the

Universe II also generates an interrupt as though the IACK cycle completed

successfully. If an error oc curs during the fetching of the STATUS/ID, the

Universe II sets the ERR bit in the Vx_STATID register (Table 101 to Table 107),

and generates an interrupt on the appropriate LINT_ pin ( as mapped in the

LINT_MAP0 register, Table 97). The PCI resource , upon receiving the PCI

interrupt, is expected to read the STATUS/ID register, and take appropriate a ctions

if the ERR bit is set. Note that the STATUS/ID cannot be considered valid if the

ERR bit is set in the STATUS/ID register.

It is important to recognize that the IACK cycle error can generate two P CI

interrupts: one through the VMEbus m aster bus error interrupt and another through

the standard PCI interrupt translation. If an e rror occur during acquisition of a

STATUS/ID, the VINT_STAT register (Table 97) shows that both VIRQx, and

VERR are active.

7.3.3 Internal Interrupt Handling

The Univ erse I I’s inte r nal int err upts are route d from se veral p roce sse s in the de vic e.

There is an interrupt f ro m t he VMEbus Master Int erface to indicate a VMEbus

error, anot her from the PCI Master Interf ace to indicate an err or on that bus, anothe r

from the DMA to indicate various conditions in that channel, along with several

others as indicated in Table 19. Table 19 shows to which bus each interrupt source

can be rou ted.

Some sources ca n be mapped t o both buse s, but mappin g interrupts to a

single bus is recom men ded.

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Figure 19 shows the sources of interr upts, and the inte rfaces from which they

originate.

Table 19: Internal Interrupt Routing

Interrupt Sour ce

May be Routed to:

VMEbus PCI Bus

PCI s/w inte rrupt √

VMEbus s /w

interrupt √

IACK cy cl e

complete for s/w

interrupt

√

DMA ev ent √√

Mailbox access √√

Locati on monito r √

PCI Target-Abort

or Mast er -Abort √√

VMEb us bu s er ro r √√

VMEbus bu s

ownership granted √

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Figure 19: Sources of Internal Interrupts

PCI

Target

DMA Channel

PCI

Master

VME

Master

VME

Slave

VMEbus Slave Channel

Interrupt Channel

PCI Bus Slave Channel

PCI Bus

Interface VMEbus

Interface

DMA bidirectional FIFO

coupled read logic

DMA

PCI error

PCI software interrupt

VME error

VME ownership bit

software IACK

VME software interrupt

Interrupt Handler

prefetch read FIFO

posted writes FIFO

coupled path

posted writes FIFO

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7.3.3.1 VMEbus and PCI Software Interrupts

It is possible to interrupt the VMEbus and the PCI bus through software. These

interrupts may be triggered by writing a 1 to the respe ctive enable bits.

Interrupting the VMEbus Through Softwa re

There are two m ethods of triggering software interrupts on the VMEbus. The

second method is provided for compatibility with the original Universe.

1. The first method for interrupting the VMEbus through software involves

writing 1 to one of the SW_INT7-1 bits in the VINT_EN register (Table 96)

while the mask bit is 0.1 This causes an interrupt to be genera ted on the

corresponding IRQ7-1 line. For example , se tting the SW_INT1 bit triggers

VXIRQ1, setting the SW_INT2 bit triggers VXIRQ2, etc .

2. The second method for interrupting the VMEbus through software involves an

extra step. Writing a 1 to the SW_INT bit in the VINT_EN register when this

bit is 0 (Table 96) triggers one interrupt on the VMEbus on the level

programmed in the VINT_MAP1 r egister (Table 99). Notice that this m ethod

requires tha t the user specify in the VINT_MAP1 register to which line the

interr upt is to be generated. When the SW_INT interru pt (method 2) is active at

the same level a s one of SW_INT7-1 interrupts (method 1), the SW_INT

interrupt (method 2) takes priority. While this interrupt source is active, the

SW_INT status bit in the VINT_STAT register is set.

With both methods, the mask bit (SW_INTx or SW_INT) in the VINT_EN register

must be 0 in order for writing 1 to the bit to have any effect.

Regardless of the software interrupt me thod used, when an IACK cycle is se rviced

on the VMEbus, the Universe II can be programmed to generate an interrupt on the

PCI bus by setting the SW_IACK enable bit in the LINT_EN register (see

“Software IACK Interrupt” on page 143).

1. The term “enable” is more meaningful with respect to the other fields in this register, i.e., excluding the

software interrupts. Writing to the software interrupt fields of this register does not enable an interrupt, it

triggers an interrupt.

This method is provided for compatibility with the original Universe

device.

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Interrupting the PCI bus Through Software

On the PCI bus, there is only one method of dir e ctly tr iggeri ng a softwar e interr upt.

(This method is the same as the second method described in “Interrupting the

VMEbus Through Software” on page 141.) Causing a 0 to 1 transition in the

SW_INT in the LINT_EN (Table 92) register ge nerates an interrupt to the PCI bus.

While this interrupt source is active, the SW_INT status bit in LINT_STAT is set.

The SW_INT field in the LINT_MAP1 register (Table 95) determines which

interrupt line is asserted on the PCI interface.

Termination of Software Interrupts

Any software inter rupt can be cleared by clearing the respec tive bit in the VINT_EN

or LINT_EN registe r. However, this method is not recommend for VME bus

software i nterr upts because i t can re sult in a fal se inte rrupt s on tha t bus. These fals e

interrupts are caused because the Universe II does not respond to the inte rrupt

handler’s IACK cycle, and th e handler is l eft wi thout a STATUS/ID for the interrupt.

Since the sof tware interrupt is edge-sensitive, the software interrupt bit in the

VINT_EN or LINT_EN register should be cleared any time between the last

interrupt finishing and the generation of another interrupt. It is recommended that

the appropriate interrupt handler clear this bit once it has completed its operations.

Alternatively, the process generating a software interr upt could clear this bit before

re-asserting it.

Software interrupts on the VMEbus have priority over other interrupts mapped

internally to the same level on the VM Ebus. When a VMEbus interrupt handle r

generates an IACK cycle on a level mapped to both a software interrupt and another

interr upt, the Universe II always provides the STATUS/ID for the soft ware interrupt

(bit zero of the Status/ID is cleared). If there are no other active interrupts on that

level, the interrupt is automatically cleared upon completion of the IACK cycle

(since software interrupts are ROAK).

While the software interrupt STATUS/ID has priority over other interr upt sources,

the user can give other interrupt sources priority over the software interrupt. This is

done by reading the LINT_STAT register (Table 97) when handling a Universe II

interrupt. This register in dicates a ll ac tive inte r rupt sour ces. Us ing this inf ormation,

the interrupt handler can then handle the interrupt sources in any system-defined

order.

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7.3.3.2 Software IACK Interrupt
The Universe II generates an internal interrupt when it provides the softwa re 
STATUS/ID to the VMEbus. This interrupt can only be routed  to a PCI interrupt 
output. A PCI interrupt is generated upon completion of an IACK cycle tha t had 
been initiated by the Universe II’s software interrupt if the following occurs:
• the SW_IACK bit in the LINT_EN register (Table 92) is set
• the SW_IACK field in the LIN T_MAP 1 register (Table 95) is mapped to a 
corresponding PCI interrupt line 
This interrupt could be used by a PCI process to indicate that the software interrupt 
generated to the VMEbus has been received by the device and acknowle dged.
Like other interrupt sources, this interrupt source  can be independently ena bled 
through the LINT_EN register (Table 92) and mapped to a particular LINT_ pin 
using the LINT_MAP1 register (Table 95). A status bit in the LINT_STAT register 
(Table 97) indicates when the interrupt source is active, and is used to clear the  
interrupt once it has been serviced.
7.3.3.3 VMEbus Ownership Interrupt
The VMEbus ownership interrupt is gener ated when the Universe II acquires the 
VMEbus in re sponse to programming of  the VOWN bit in the MAST_CTL regist er 
(Table 116) . This interrupt sour ce can be used to indica te that ownership of the 
VMEbus is ensured during an exclusive access (see “VME Lock 
Cycles—Exclusive Ac cess to VMEbus Resources” on page 80). The interrupt is 
cleared by writing a one to the m atching bit in the LINT_S TAT register (Table 97).
7.3.3.4 DMA Interrupt
The DMA module provides the following possible interrupt sources:
• if the DMA is stopped (INT_STOP)
• if the DMA is halted (INT_HALT)
• if the DMA is done (INT_DONE)
• for PCI Target-Abort or Master-Abort (INT_LERR)
• for VMEbus errors (INT_VERR) 
• if there is a PCI protocol error or if the Universe II is not enabled as PCI master 
(INT_P_ERR)

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All of  these inter rupt sources ar e ORed to a sin gle DMA interrupt out put li ne. When 
an interrupt comes from the  DMA module, software mu st read the DM A status bits 
(Table 90) to discover the originating interrupt source. The DMA interrupt c an be 
mapped to eithe r the VMEbus or one of the PCI interrupt output line s. See “DMA 
Interrupts” on page 125.
7.3.3.5 Mailbox Register Access Interrupts
The Universe II can be programmed to generate  an interrupt on the PCI bus and/or 
the VMEbus when any one of its mailbox registe rs is written to (see “Mailbox 
Registe rs” on page 101). The  user may e nable or disa ble an int errupt response  to the  
access of any mailbox register (Table 92). Each register access may be individually 
mapped to a specific interrupt on the PCI bus (LINT_MAP2, Table 108) a nd/or the 
VMEbus (VINT_MAP2, Table 109). The status of the PCI interrupt and the 
VMEbus are recorde d in the LINT_STAT (Table 93) and VINT_S TAT registers 
(Table 97), respectively.
7.3.3.6 Location Monitors
The Universe II can be programmed to generate  an interrupt on the PCI bus w hen 
one of its four location monitors is accessed (see “Location Monitors” on page 51). 
In order for an inc oming VMEbus transaction to a ctivate the loca tion monitor of the 
Universe II the following criteria must be met:
• location monitor must be enabled
• access must be within 4 kbytes of the location monitor base address (LM _BS, 
Table 138)
• it must be in the specified address space 
When an access to a location monitor is detected, an interrupt m ay be  generated on 
the PCI bus (if the location monitor is enabled). There are  four location monitors:
• VA[4:3] = 00 selects Location Monitor 1,
• VA[4:3] = 01 selects Location Monitor 2,
• VA[4:3] = 10 selects Location Monitor 3, and
• VA[4:3] = 11 selects Loc ation Monitor 4.
An interrupt response to the access of any location monitor  can be enabled or 
disabled with bits in the LINT_EN register (Table 92). Access to ea ch location 
monitor can be individually mapped to a specific interrupt on the PCI  bus 
(LINT_MAP2, Table 108)—not to the VMEbus bus. The status of the PCI interrupt 
is logged in (LM bit of the LINT_STAT, Table 93).

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7.3.3.7 PCI and VMEbus Error Interrupts

Interrupts from VMEbus errors, PCI Target-Aborts or Master-Aborts are genera ted

only when bus errors arise during dec oupled writes. The bus error interrupt (from

either a PCI or VM Ebus error) can be mapped to either a VMEbus or PCI interrupt

output line.

7.3.4 VME64 Auto-ID

The Universe II includ es a power -up option for parti cipation in the VME64 Auto-ID

process . When this option is ena bled, the Uni verse II ge nerates a le vel 2 i nterrupt on

the VMEbus before release of SYS FA IL*. When the level 2 IACK cycle is run by

the system Monarc h, the Universe II responds with the Auto-ID Status/ID, 0xFE,

and enables a ccess to a CR/CSR image at base addr ess 0x00_0000.

When the Monarch detects an Auto-ID STATUS/ID on level 2, it is expected to

access the enabled CR/CSR space of the int errupt er. From there i t completes

identification and configuration of the card. The Monarch functionality is typically

implemented in software on one card in the VMEbus system. See “Automatic Slot

Identification” on page 56.

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8. Error Handling

Errors occur in a system as a result of parity, bus, or internal problems. In order to

handle errors so that they have minimum effects on an application, devices have a

logic module ca lled an error handle r. The error handler logs data about the error

then communicate s the information to another device (for example, a host

processor) that is capable of re solving the error condition.

This chapter discusses the following topics:

•“Errors on Coupled Cycles” on page 148

•“Errors on Decoupled Transa ctions” on page 148

8.1 Overview

There are different conditions under which bus er rors can occur with the

Universe II: during coupled cycles or during decoupled cycles. In a coupled

transaction, the completion status is returned to the transaction master, which can

then take some action. However, in a decoupled transaction, the master is not

involved in the data acknowledgment at the destination bus and higher level

protocols are required.

The error handling provided by the Universe II is described for both coupled and

decoupled transactions.

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8.2 E rrors on Coupled Cycles

During coupled cycles, the Universe II provides immedi ate indica tion of an errored

cycle to the originating bus. VMEbus to PC I transactions terminated with

Target-Abort or Master-A bort are terminated on the VMEbus wit h BERR*. The

R_TA o r R_M A bits in the PCI_ CSR register (Table 38) are set when the

Universe II receives a Target-Abor t or Master-A bort. For PCI to VMEbus

transact ions, a VMEbus BERR* received by the Unive rse II is communicate d to the

PCI master as a Target-Abort and the S_TA bit is set (Table 38). No i n formation is

logged in either direction, nor is an interrupt generated.

8.3 Errors on Decoupled Transactions

During decoupled transactions, there is a possibility that an error in the transaction

can occur. The following sections detail the decoupled transactions supported by

Universe II and the types of error handling supported for these transactions.

8.3.1 Poste d Writes

The Universe II provides the option of performing posted writes in both the PC I

Target Channel and the VMEbus Slave Channel. Once data is written into the

RXFIFO or TXFIFO by the initiating master ( VMEbus or PCI bus resp ectively), the

Universe II provides immediate acknowledgment of the cyc l e’s termination. When

the data in the FIFO is written to the destination slave or target by the Universe II,

the Universe II can receive a bus erro r instead of a normal termination. T he

Universe II handles this situation by logging the errored transactions in one of two

error logs a n d generating an interrupt. Each error log (one for VM Ebus errors and

one for PCI bus e rrors) is comprised of two registers: one for address and one for

command or address space logging.

8.3.1.1 Error Logs

If the error occurs during a poste d w rite to the VMEbus, the Universe II uses the

V_AMERR register (Table 144) to log the A M c ode of the transaction (AMER R

[5:0]). The state of the IACK* signal is logged in the IACK bit, to indicate whether

the error occurred d u ring an IACK cycle. The address of th e errored tran s action is

latched in the V_AERR register (Table 12.2.108). An interrupt is genera ted on the

VMEbus and/or PCI bus depending upon w hether the VERR interrupts are enabled

(see “Interrupt Generation and Handling” on page 129). The remaining entries of

the t ransac tio n are removed from th e FIFO.

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If the error occurs during a posted write to the PCI bus, the Universe II uses the

L_CMDERR registe r (Table 67) to lo g the command in formation f or t he transactio n

(CMDERR [3:0]). The address of the errored transaction is latched in the L_AER R

depending upon whet her the VER R and LER R interrup ts are enabled ( see “Interrupt

Generation and Handling” on page 129).

Under either of the conditions (VMEbus-to-PCI, or PCI-to-VMEbus), the address

that is stored in the log repr esents the most rece nt address the Univer se II gener ated

before the bus error was encountered. For single cycle transactions, the address

represents the address for the a ctual errored transaction. However, for multi-data

beat transa ctions (block transfers on the VM Ebus or burst transactions on the PCI

bus) the log only indicates that an error occurred somewhere after the latched

address. For a VMEbus block transfer, the logged address will represent the start of

the block tr ansfer. In the PCI Target Channel, the Universe II generates block

transfers that do not cross 256-byte boundaries, the err or will have occurred from

the logg ed address up to t he next 256-byte boundary. In the VMEbus Slave Channel,

the error will have occurred anywhere from the logged address up to the next burst

aligned address.

In the case of PCI-initiated transactions, all data from the errored address up to the

end of the initiating transaction is flushed fr om the TXFIFO. Since the Universe II

breaks PCI transacti ons at 256-byte bound aries (or earlie r if the TXF IFO is f ull), the

data is not flushed past this point. If the PCI master is generating bursts tha t do not

cross the 256- byte boundary, then (again) only data up to the en d of th at transa ction

is flushed.

In a posted write from the VMEbus, all data subsequent to the err or in the

transaction is flushed from the R XFIFO. However, the length of a VMEbus

transa ction dif fers from the le ngth of the errored PCI bus transaction. For non-bl ock

transfers, the length always corresponds to one so only the error ed data beat is

flushed. However, if an e rror oc cur s on the PCI bus during a t ransac tion initiated by

a VMEbus block tra nsfer, all data subse quent to the errored da ta beat in the block

transfer is flushed from the RXFIFO. In the case of BLTs, this implie s that

potentially all data up to the next 256-byte boundary m ay be flushed. For MBLTs,

all data up to the next 2-KByte boundary may be flushed.

Once an error is captured in a log, that set of registers is frozen against further errors

until the error is acknowledged. The log is acknowledged and m ade available to

latch another error by clearing the corresponding status bit in the VINT_STAT or

LINT_STAT registers. if a second err or occur before the CPU has the oppor tunity to

acknowledge the first error, another bit in the logs is set to indicate this situation

(M_ERR bit).

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8.3.2 Prefetched Reads

In response to a block read from the VMEbus, the Universe II initiates prefetching

on the PCI bus (if the VMEbus slave image is programmed with this option, see

“VME Slave Image Programming” on page 84). The transaction generated on the

PCI bus is an ali gned memory read transaction with multi ple data be ats extending to

the aligned burst boundary (as programmed by PABS in the MAST_CTL register,

Table 117). Once an acknowledgment is given for the first data beat, an

acknowledgment is sent to the VMEbus initia tor by the assertion of DTACK*.

Therefore, the first data beat of a prefetched read is coupled while all subsequent

read s in the transaction are decou pled.

If an erro r occurs on the PCI bus, the Univers e II does not trans l ate the error

condition into a BERR* on the VMEbus. Indeed, the Universe II does not dire ctly

map the error. By doing nothing, the Universe II forc es the external VMEbus error

timer to expire.

8.3.3 DMA Er rors

The Universe II’s response to a bus error during a transfer controlled by the DMA

Channel is described in “DMA Error Handling” on page 126.

8.3.4 Parity Er ror s

The Universe II both monitors and ge nerates parity informa tion using the PAR

signal. The Universe II monitors PAR when it accepts data as a master during a read

or as a target during a write. The Universe II drives PAR when it provides data as a

target during a read or a master during a write. The Universe II also drives PAR

during the address phase of a transaction when it is a master and monitors PAR

during an addre ss phase when it is the PCI target. In both address and data phases,

the PAR signal provides even parity for C/BE_[3:0] and AD[31:0].

The PERESP and SERR_EN bits in the PCI_C SR register (Table 38) determine

whether or not the Universe II responds to parity errors. Data parity errors are

reported through the assertion of PERR_ if the PERESP bit is se t. Address parity

errors, reported through the SERR_ signal, are reported if both PERESP and

SERR_EN are set. Regard less of the setting of these t w o bits, the D _PE (Detected

Parity Error) bit in the PCI_CS register is set if the Universe II encounters a parity

error as a master or as a target. The D P_D (D ata Parity Detected) b it in the s ame

Universe II detects a parity error while it is PCI master (tha t is, it asserts PERR_

during a rea d transaction or rec eives PERR_ during a write).

If the Universe I I is powered up in a 64-bit PCI environment, then

PAR 64 provides even parity for C/BE_[7:4] and AD[63:32].

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No interrupt s are generated by t h e Universe II eit her as a master o r as a target in

response to parity errors reported during a transaction. Parity errors a re reported by

the Universe II through asse rtion of PERR_ and by setti ng the appropriate bits in the

PCI_CSR register . If PERR_ is asserted to the Universe II while it is PCI master , the

only action it takes is to set the DP_D. Regardless of whether the Universe II is the

master or target of the transaction, and regardle ss which agent asserted P ERR _, the

Universe II does not take any action other than to set bits in the PCI_CSR register.

The Universe II continues with a transaction independe nt of any parity errors

reported during the transaction.

Similarly, address parity err ors are repor ted by the Universe I I (if the SERR_EN bit

and the PERESP bit are set) by asserting the S ERR_ signal for one clock cycle and

setting the S_SERR (Signalled SERR_) bit in the PCI_CSR register. Assertion of

SERR_ can be disabled by clearing the SERR_EN bit in the PCI_CSR register. No

interrupt is generated, and regardle ss of whether assertion of SERR_ is enabled or

not, the Universe II does not respond to the access with DEVSEL_. Typically the

maste r o f the trans action times-o ut with a Master-Abort. As a mas ter, the

Universe II does not monitor SERR_. It is expected that a central resource on the

PCI bus monitors SERR_ and takes appropriate action.

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9. Resets, Clocks and Power-up

Options

This chapter highlights utility functions in the Universe II. This chapter discusses

the following topics:

•“Resets” on page 154

•“Power-Up Options” on page 160

•“Test Modes” on page 166

•“Clocks” on page 167

9.1 Overview

The Universe II has many programmable reset options and power-up options that

impact the functionality of the device.

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9.2 Resets

The Universe II provides a number of pins and registers for reset support. P in

support is summarized in Table 20.

Table 20: Hardware Reset Mechanisms

Interface and

Direction Pin Nam e Lon g Nam e Effectsa

a. A more det ai le d acc ount of the effects of rese t signals is pro vided in “Rese t Im pl em entation Ca ut io ns”

on page 158

VMEbus Inpu t VR SYSRST _ VMEbus Reset

Input Asserts LRST _ on the l ocal bus, resets the

Unive rse II, an d re-config ur es power -up

options.

VMEbus

Output VXSYSRST VMEbus System

Reset Universe II output for SYSRS T* (resets the

VMEbus)

PCI Input PWR RST_ Power- up Re set Resets the Univer se I I and re -c onf i gur es

power - up options.

RST_ PCI Reset Input Resets the Universe II from the PCI bus.

VME_

RESET_ VMEbus Reset

Initiator Causes Universe II to assert VXSYSRST

PCI Output LRST_ PCI Bus Reset

Output Resets PCI resources

JTAG Input TR ST_ JTAG Test Reset Provides asynchronous init ializ ation of the TAP

controller in the Universe II.

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The Universe II is only reset through hardw are. Software can make the Universe II

assert its reset outputs. In order to reset the Universe II thr ough software, the

Universe II reset outputs must be connected to the Universe II reset inputs. For

example, the S W _LRST bit in the MISC_CTL register, which asserts the LR ST_

output, does not reset the Universe II itself unless LR ST_ is looped back to RST_.

As described in “Reset Implementation C autions” on page 158, there ar e potent ial

loopback configurations resulting in permanent rese t.

Table 21: Software Reset Mechanism

Table Name Type Function

MISC_CTL

Table 117

SW_LRST W Software PCI Rese t

0= N o effect

1= I nitiate LRST_

A read always r et urn s 0.

SW_ SYSRST W Software VMEbus SYSRESET

0= N o effect

1=Initiate SYSRST*

A read always r et urns 0

VCSR_SET

Table 163

RESET R/W Bo ar d Rese t

Reads:

0=L RST_ not assert ed

1=L RST_ asserted

Writes:

0=no effect

1=a ssert LRST _

SYSFAIL R/W VMEbus SYSFAIL

Reads:

0=VXSYSFAI L not asserted

1=VXSYSFAI L asserted

Writes:

0=no effect

1=assert VXSYSFAIL

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9.2.1 Universe II Reset Circu itry

Table 22 and Figure 20 shows how to reset various aspects of the Universe II. For

example, it shows that in order to reset the clock servic es (SYSCLK, CLK 64

enables, and PLL divider), PWRRST_ must be asserted.

VCSR_CLR

Table 162

RESET R/W Bo ar d Rese t

Reads:

0=L RST_ not assert ed

1=L RST_ asserted

Writes:

0=no effect

1= negate LRST _

SYSFAIL R/W VMEbus SYSFAIL

Reads:

0=VXSYSFAI L not asserted

1=VXSYSFAI L asserted

Writes:

0=no effect

1=negate VXSYSF AIL

Table 21: Software Reset Mechanism

Table Name Type Function

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PWRRST_ resets all aspec ts of Unive rse II li ste d in column 1 of Table 22. Table 22

also indicates the reset effects that are extended in time. For example, VXSYSRST_

remains asser ted for 256 ms after all initiators are removed—this satisfies VMEbus

Specification (minimum of 200 ms SYSRST*). The ext ernal 64 MHz clock control s

this assertion time. LRST_ is asserte d for 5 ms or more from all sources except

VRSYSRST_.

Table 22: Functions Affected by Reset Initiators

Effect of Reseta,b

a. On PWRRST_, options are loaded from pins. On SYSRST and RST_, options are loaded from values

that were latched at the previous PWRRST_.

b. Refer to Append ix-A to find the effects o f various reset events

Reset Sou rce

Clock Servi ces

SYSCLK

CLK 64 enables

PLL Divider

PWRRST_

VMEbus Services

VMEbus Arbiter

VMEbus Timer

VCSR Registers

PWRRST_, or

VRSYSRST_

General Servic es

Mos t regi st er s

PWRRST_,

RST_ or

VRSYSRST_

Pow er-Up and Reset Sta te Mac hi ne

Pow er-up the device

Reset Registers

PWRRST_, or

VRSYSRST_

VME bus Res et Output

VXSYSR ST_ (as sert ed for mor e th an 20 0 m s)

PWRRST_, or

VME_RESET_, or

SW_S YSRST bit in MISC_CT L register

PCI Bus Reset Ou tput

LRS T_ (a sserted for at least 5 ms)

PWRRST_, or

VRSYSRST_ , or

SW_L R ST bit in MIS C_C TL register, or

RES ET bi t in VCSR_SET regist er c

c. LRST_ may be clea re d by writing 1 to the RESET bit in the CSR_CLR re gister.

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Figure 20: Reset Circuitry

9.2.2 Reset Implementation Cautions

To prevent the Unive r se II f rom resetti ng the PCI bu s, the LRST_ output c a n be left

unconnect ed. Otherwise , LRST_ mu st be grouped wi th othe r PCI re set gener ators to

assert the RST_ signal so that the following conditions are met:

RST_ = LRST_ & reset_sour ce1 & reset_source2 &...

VME Services

Clock Services

General Services

Power-Up and Reset

> 200ms

>= 5ms

PWRRST_

VRSYSRST_

RST_

VME_RESET_

MISC_CTL Register

SW_SYSRST

SW_LRST

VCSR_CLR and

VCSR_SET Registers

RESET LRST_

VXSYSRST_

VOE_

(Power-up, reset registers, assert VOE_)

(VME Arbiter, VMEbus timer, VCSR registers)

(SYSCLK, CLK64 enables, PLL divider)

(Most Registers)

hold for

Notes:

1. On PWRRST_, options are loaded from pins. On SYSRST and RST_,

options are loaded from values that were latched at the previous

PWRRST_.

2. Refer to “Registers” on page 191 to find the effects of various reset

9. Resets, Clocks and Power-up Options

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If the Universe II is the only initiator of PCI rese t, LRST_ can be directly connected

to RST_.

Assertion of VME_RESET_ causes the Universe II to assert VXSYSRST_.

The PWRRST_ input keeps the Universe II in reset until the power supply has

reached a stable level (see Table 22). It must be he ld asserted for over 100

milliseconds after power is stable. Typically this can be achieved through a

resistor /ca pacit or combination (see Figure 21)or under voltage sensing circuits.

Figure 21: Resistor-Capacitor Circu it Ensuring Power-Up Reset Duration

The Universe II supports the VMEbus CSR Bit Clear and Bit Set registers

(Table 162 and Table 163). The VCSR_SET registers allows the user to assert

LRST_ or SYSFAIL by writing to the RESET or SYSFAIL bits. LR ST_ or

SYSFAIL remains asser ted until the corresp onding bit is cleare d in the VCSR_CLR

regist er. The FAIL bit in ea ch of these registers is a stat u s bit and i s set by the

software to in dicate board failure.

Since VME_RESET_ causes assertion of SYSRST*, and since

SYSRST* causes assertion of LRST_, tying both VME_RESET_ and

LRST_ to RST_ will put the Universe II into permanent reset. If

VME_RESET_ is driven by PCI reset logic, ensure that the logic is

designed to break this feedback path.

PWRRST

47 K

10µF

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9.3 Power-Up Options

The Universe II can be aut omatic ally c onfigur ed at power - up to ope rat e in dif f erent

functional modes. These power-up options allow the Universe II to be set in a

particular mode independent of any local intelligence.

Table 23: Power-Up Optionsa

Option Register Field Default Pins

VMEbus Reg ister Access Slave

Image VRAI_CTL EN disabled VA[31]

VAS A16 VA[30:29]

VRAI_BS BS 0x00 VA[28:21]

VMEbus CR/CSR slave image VCSR_CTL LAS memory VA[20]

VCSR_TO TO 0x00 VA[19:15]

Auto-ID MISC_STAT DY4AUTO disabled VD[30]

MISC_CTL V64AUTO disabled VD[29]

VINT_EN SW_INT 0

VINT_STAT SW_INT 0

VINT_MAP1 SW_INT 000

BI-ModeMISC_CTL BI disabled VD[28]

Auto-Syscon Detect MISC_CTL SYSCON enab led VBGIN[3]*

SYSFAIL* Assertion VCSR_SET SYSFAIL asserted VD[27]

VCSR_CLR SYSFAIL

PCI Tar ge t Ima ge LSI0_CT L EN dis abled VA [13]

LAS memory VA[12]

VAS A16 VA[11:10]

LSI0_BS BS 0x0 VA[9:6]

LSI0_BD BD 0x0 VA[5:2]

PCI Register Access PCI_BS0,

PCI_BS1 SP ACE See T able 41 and

Table 42 VA[1]

PCI Bus SizebMISC_STAT LCLSIZE 32-bit REQ64_

PCI CSR M ast er Enable PCI_CS R B M d isabl ed VA[ 14]

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The majority of the Universe II power-up options are loaded from the VMEbus

address and data lines after any PWRRST_ (see Table 23 on page 160). There are

two power-up options that are not initiated by P WRRST_. The first of these is PCI

bus width (a power-up option required by the PCI 2.1 Specification), an d th is is

loaded on any RST_ eve nt from the REQ64_ pin. The second special power-up

option is VMEbus S Y SCON enabling, required by the VMEbus specification. The

SYSCON option is loaded during a SYSRST* event from the BG3IN* signal.

All power-up options are latched from the state of a particular pin or group of pins

on the rising edge of PWRST_. Each of these pins, except REQ64_, has a wea k

internal pull-down to put the Universe II into a default configuration. (REQ64_ has

an internal pull-up). If a non-de fault configuration is required, a pull-up of

approximately 10k Ω is required on the signal. See “PCI Bus Width” on page 164

and the VMEbus Specification.

The Universe II may be restored to t he state i t was in immed iately followin g the

previous power - up without re-asser ting PWRRST_. After SYSRST* or RST_ (with

PWRRST_ negated), the values that were originally latched at the rising edge of

PW RRST_ are re loaded into the U niverse II (e xcept for PCI bus width and

VMEbus SYSCON enabling, which are loaded from their pins).

Table 23 l ists th e power-up options of the Unive rse II , the pins whic h determi ne the

options, a nd the regi ster se ttings tha t ar e se t by this option. Ea ch option is described

in more detail in “Power-up Option Descriptions” on page 161.

9.3.1 Pow er-u p Op tio n Desc rip tions

This section describes each of the groups of power-up options that were listed in

Table 23.

9.3.1.1 VMEbus Register Access Image

The Universe II has several VMEbus slave im ages, each of which can provide a

different map ping of VMEbus cy cles to PCI cycles. All V MEbus slave images are

configur able through a set of VMEbus slave image registers: VSIx_CTL, VSIx_BS,

VSIx_BD, and VSIx_TO.

a. All power-up options ar e l atched only at the rising-edge of PW R R ST_. They are loaded when

PWRRST_, SYSRS T* an d RST_ ar e neg ated.

b. The PCI Bus Size is loaded on any RST_ event (PCI 2.1 Spe cification ).

No VMEbus to PCI transa ction is possible until these registe rs are

programmed.

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The VMEbus Regis ter Access Image (VRAI) power-up option pe rmits access from

the VMEbus to the Universe II internal registers at power-up. The power-up option

allows programming of the VMEbus register access image address space and the

upper five bits of its base address; all other bits are 0 ( see Ta ble 24). Once access is

provided to the registers, then a ll other Universe II f eatures (such as further

VMEbus slave images) can be configured from the VMEbus.

Table 24 shows how the upper bits in the VR AI base address are programm ed for

A16, A24, and A32 VMEbus register access images.

9.3.1.2 VMEbus CR/CSR Slave Image

CR/CSR space is an addres s sp ace introduced in the VME64 Specification. The

CR/CSR spac e on any VMEbus device i s 512 Kbyte s in si ze; the upper re gion of the

512 Kbytes dedicated to register space, and the lower region is dedicated to

configuration ROM. The Universe II maps its internal registers to the upper region

of the CR/CSR space, a nd passes all other a ccesses through to the PCI bus (see

“Registe rs” on page 191).

The VMEbus CR/CSR Slave Image power-up option maps CR/CSR accesses to the

PCI bus. CR/CSR space can be mapped to memory or I/O space with a 5-bit offset.

This allows mapping to any 128 Mbyte page on the PCI bus. As part of this

implementation, ensure that the PCI Master I nterface is enabled through the

MAST_EN bit power-up option or conf igured through a r egister access befor e

accessing configu ratio n ROM.

9.3.1.3 Auto-ID

The re ar e two Aut o- ID me chan is ms pro vi ded by th e Uni ver se II . O ne is the VME64

Specification version which re lies upon use of the C R/CSR space for configuration

of the VMEbus system, and a T undra propriet ary system which use s the IACK daisy

chain for ide nti fying cards in a s y stem. Eit her of these mechanis ms can be enab led

at power-up (see “Automatic Slot Identification” on page 56).

Table 24: VRAI Base Address Power-up Options

VRAI_CTL: VAS BS [31:24] BS [23: 16] BS [15:12]

A1 6 0 0 Power-up Opt ion

VA [2 8: 25]

A24 0 Power-up Option

VA [ 28: 21] 0

A32 P ow er -u p O pt ion

VA [28:21]

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Because VME64 Auto- ID relies upon SYSFAIL to operate correctly, this power-up

option overrides the SYSFAI L power-up option described in “SYSFAIL*

Assertion” on page 163.

9.3.1.4 BI-Mode

BI-Mode (Bus Isola tion Mode) is a mechanism for logically isolating the

Universe II from the VMEbus for diagnostic, maintenance and failure r ecovery

purposes. BI-Mode can be enabled as a power-up option (see “BI-Mode” o n

page 60). When the Universe II has been powered-up in BI-Mode, then any

subsequent SYSRST* or RST_ restores the Universe II to BI-Mode,

9.3.1.5 Auto-Syscon Detect

The VMEbus SYSCON enabling, re quired by the VMEbus Specification, is a

special power-up option in that it does not return to its after-power-up state

following RST_ or SY SRST_. The SYSCON option is loaded during a SY SRST*

event from the VB G3IN* signal.

9.3.1.6 SYSFAIL* Assertion

This powe r-up option cause s the Univ erse I I to assert S YSFAIL* immediatel y upon

entry into r eset. The SYSFAIL* pin is re leased through a register access. Note that

this power-up option is over-ridden if VME64 Auto-ID has been enabled. This

option is used when extensive on-board diagnostics need to be performed before

release of S Y SFAIL*. After completion of diagnostics, SYSFAIL* can be released

through softwa re or through initia tion of the VME6 4 Auto- ID se que nce (if ena ble d,

see “Auto S lot ID: VME64 Specified” on page 56 ).

9.3.1.7 PCI Target Image

The PCI Target Image power -up opt ion provides for default ena bling of a PCI tar get

image (aut omatical ly mapping PCI cycles t o the VMEbus). The default ta rget image

can be mapped with ba se a nd bounds at 256MB r esolution in Memory or I/ O space,

and map PCI tra nsactions to different VMEbus address spaces. Beyond the settings

provided for in this power-up option, the target image possesses its other de fault

conditions: the translation offset is 0, posted writes are disabled, and only 32-bit

(maximum) non-block VM Ebus cycles in the non-privileged data space are

generated.

This option i s typically us ed to acces s permits th e use of Boot ROM on another c ard

in the VMEbus syste m.

9.3.1.8 PCI Register Access

A power-up option determines if the registers are m appe d into Memory or I/O

space.

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9.3.1.9 PCI Bus Width

The PCI Interface can be used as a 32-bit bus or 64-bit bus. The PCI bus width is

determined during a PCI reset (see the PCI 2.1 Specification). The Universe II is

configured a s 32-bit PCI if REQ64_ is high on RST_; it is configure d as 64-bit if

REQ64_ is low. The Universe II has an internal pull-up on REQ64_, so the

Universe I I d efaults t o 32- bit PCI. On a 32 -bit P CI bus, t he Unive rse II drive s all its

64-bit extension bi-direct signals at all times; these signals include: C/BE[7:4]_,

AD[63:32], REQ64_, PAR64 and ACK64_ to unknown values. If used as a 32-bit

interface, the 64-bit pins, AD[63:32], C/BE[7:4], PAR64 and ACK64_ can be left

un-terminated.

9.3.1.10 PCI CSR Image Space

There is a powe r-up option (using the VA[1] pin) that determines the va lue of the

SPACE bit of the PCI_B Sx r egisters. At power-up the SPACE bit of the PCI_BS1

• When the VA pin is sampled low at power-up, the PCI_BS0 register’s SPACE

bit is se t to 1, which signifies I/O space, and the PCI_BS1 r egiste r’s SPACE bit

is set to 0, which signifies Memory space.

• When VA is sampled high at power-up, the P CI _BS0 register ’s SPACE

Once set, this mapping is constant until the next power-up sequence.

See “Memory or I/O Access” on page 95, Table 41 and Table 42.

9.3.2 Power-u p Option Implemen tatio n

In order to implement power-up requirements for the Universe II weak pull-up

resistors are required.

9.3.2.1 Pull-up Requirements

The pull-ups for the general power-up options (if other than default values are

required) must be placed on the VA [31:1] and VD[31:27] lines. During reset, the

Universe II n egates VOE_, putting these s ignals into a high-impe dance sta te . While

VOE_ is negated the pull-ups (or internal pull-downs) bring the option pins (on

A[31:1] and D[31:27]) to their appropriate state.

The internal pull-dow ns are very weak. The leakage cur ren t on many

transceive rs can be sufficient to override these pull-downs. To ensure

proper operation designers must ensure power-up option pins go to the

corre ct state.

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Within two CLK64 periods after PWRRST_ is negated, the Universe II latches the

levels on the option pins, and then negates VOE_ one clock later. This enables the

VMEbus transceivers inwards.

Figure 22: Power-up Opt ions Timing

The power -up options a re subsequent ly loaded into th eir respecti ve register s several

PCI clock periods after PWRRST_, SYSRST* and RST_ have all been negated.

9.3.3 Hardwa re In itial izatio n (Norma l Op erating Mo de )

The Universe II has I/O capabilities that are specific to manufacturing test

functions. These pins are not required in a non-manufacturing test setting. Table 25

shows how these pins must be terminated.

Because of the power-up configur ation, the VMEbus buffers are not

enabled until several CLK64 periods after release of SYSRST*

(approximately 45 ns). Allowing for worst case bac kplane skew of 25

ns, th e Univers e II is not prepared to recei ve a slave access until 70 n s

aft er release of SY SRST*.

Table 25: Manufacturing Pin Requirements for Normal Operating Mode

Pin Name Pin Value

tmode[2] VSS (or pulled-down if board tests are performed, see “Auxiliary Test Modes” on

page 166)

tmode[1]

tmode[0]

pll_testsel VSS

enid VSS

pll_test out No connect

VCOCTL VSS

power-up options

CLK64

VOE_

VA, VD

WRRST_

minimum 100ms

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9.4 Test Modes

The Universe II provides two types of test modes: auxiliary modes (NAND tree

simulation and High Impedance) and JTAG (IEEE 1149.1).

9.4.1 Auxili ary Test Mo des

Two auxiliary test modes are supported: NAND tree and high impedance. The

Universe II has three test m ode input pins (TMODE[2:0]). For normal oper ations

these inputs should be tied to ground (or pulled to ground through resistors).

Table 26 below indicates the 3 operating modes of the Universe II. At reset the

TMODE[2:0] inputs ar e latched by the Universe II to determine the mode of

operation. The Univer se II remains in this mode until the TMODE[2:0] inputs have

changed and a re set event has occurred. PLL_TESTSEL must be high for any test

mode.

For NAND Tree Simulation, the values of the TMODE pins are latched during the

active part of PWRRST_. These pins can cha nge stat e during the NAND Tree tests.

The timers are always accelerated in this mode. All outputs are tristated in this

mode, except for the VXSYSFAIL output pin.

For High Impedance m ode, the values of the TMODE pins are also latched during

the active pa rt of PWRRST_. All outputs are tristated in this mode, except for the

VXSYSFAIL output pin.

Table 26: Test Mode Operation

Op er ation Mode TMODE[2:0] PLL_TESTSEL

Normal Mode 000 0

Accelerate 001 0

PLL Te st 010 1

Scan M ode 011 1

NA ND Tree Simulation 100 1

RAM Test 101 1

High Impedance 110 0/1

Reserved 111 1

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9.4.2 JTAG supp ort

The Universe II includes dedicated user-accessible test logic that is fully compatible

with the IEEE 1149.1 Standard Test Access Port (TAP) and Boundary Scan

Architectur e. This standard was developed by the Test Technology Technical

Committee of IEEE Computer Society and the Joint Test Action Group (JTAG).

The Universe II’s JTAG support includes:

• fiv e-pin JTA G interfa ce (TCK, TDI, TDO , T MS, an d TRST _)

• JTAG TAP controller

• three-bit instruction register

• boundary scan register

• bypass register

• an ID CODE register

The following required public instructions are supported: BY PASS (3'b111),

SAMPLE(3'b100), and EXTES T(3'b000). The optional public instruction

IDCODE(3'b011) selects the IDCODE registe r which returns 32'b01e201d. The

following external pins are not pa rt of the boundary scan r egister: LCLK,

PLL_TESTOUT, PLL_TESTSEL, TMODE[3:0], and VCOCTL.

9.5 Clocks

CLK64 is a 64 MHz clock that is require d by the Uni verse II in or der to s ynchronize

intern al Univ erse II sta te machines and t o produc e t h e VMEbus syst em clock

(VSYSCLK) when the Universe II is system controller (SYSCON). This clock is

specified to have a minimum 50-50 duty cycle with a maximum rise time of 5 ns.

Using a different clock fre quency is not recommended. It will alter

various internal timers and change VME timing.

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10. Signals and Pinout

This chapter discusses the following topics:

•“VMEbus Signals” on page 170

•“PCI Bus Signals” on page 174

•“Pin-out” on page 178

10.1 Overview

The followin g det ai led des cript ion of the Unive r se II signals is or ganiz e d accor ding

to these functional groups:

• VMEbus Signals

•PCI Signals

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10.2 VMEbus Signals

Table 27: VMEbus Signals

CLK64 Input

Refer ence Clock – this 64M H z clock is use d to generate fixe d tim ing parameter s. It req ui re s a 50-5 0 dut y

cycle (±20%) with a 5ns maximum rise time. CLK64 is required to synchronize the internal state machines

of the VM E side of th e Uni ver se II.

VA [31:1] Bidirectional

VMEb us Address Lines 31 to 01 – du ring MBLT transfers , VA 31-01 ser ve as data bits D 63- D33.

VA03-01 ar e us ed t o in di cate i nt errupt level on the VME bus.

VA_DIR Output

VMEb us Address Transce iver Dir ect ion C ontrol – the U niverse I I co ntro ls the direc tion of the addre ss

(VA31- 01, VLWORD_) t r ansc eivers as r equired for mas t er, slave and bus isolation mode s. When t he

Univ ers e II is driving lines on th e VM Ebus, this sign al is driven hig h; when t he VM Ebus is drivin g th e

Universe II, this signal is driven low.

VAM [5:0] Bidirectional

VMEb us Address Modifier Co des – the se codes ind icat e the address spa ce being acc essed (A16 , A24 ,

A32), th e pr ivilege level (u ser, s upervisor ), the cycle t ype (standar d, B LT, MBLT) and the data ty pe

(program, data).

VAM_DIR Output

VMEb us AM C ode D irect ion C ontrol – con trol s the di r ect i on of the A M code transceivers as required for

master, slave and bus isolation modes. When the Universe II is driving lines on the VMEbus, this signal is

driven hig h; when t he VM Ebus is driv ing th e U niver se II, this signa l is driv en l ow.

VAS_ Bidirectional

VMEbus Address Strobe – the falling edge of VAS_ indicates a valid address on the bus. By continuing to

asser t VAS_, owne rs hip of the bu s is maintained during a RMW cycle.

VAS_DIR Output

VMEb us Address Stro be D ire ct ion C ont r ol – cont r ol s the di rec tio n of the ad dr ess strobe transceive r as

requ ired for mast er, slav e and bus isolat i on m od es. When the Uni verse II is driving lines on th e VM Ebus,

this signal is driven hig h; wh en th e VM Ebus is driving the U niverse I I, this signal is driven low.

VBCLR_ Output

VMEb us Bus Clear – requ ests t hat th e cur re nt ow ner release the bu s.

Asserted by the Universe II when configured as SYSCON an d th e arbiter detects a higher level pending

request.

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VBGI[3:0]_ Input

VMEb us Bus Grant Inputs – The VME ar bi te r awa rds use of th e dat a t ra nsf er bus by driving these bu s

gran t lines l ow. The si gn al pro pagates down the bus grant dais y chain and is ei th er accepted by a

requ est er if it requesting at the appropr iate lev el, or pas sed on as a VBGO [ 3: 0] _ to the ne xt boar d i n th e

bus gr ant dai sy chai n.

VBGO[3:0]_ Output

VMEbus Bus Grant Outputs – Only one output is asserted at any time, according to the level at which the

VMEb us is bei ng gra nt ed.

VD[31:0]_ Bidirectional

VMEb us Dat a Li nes – 31 through 0

VD_DIR Output

VMEbus Data Transceiver Direction Control – the Universe II controls the direction of the data (VD [31:0])

transceivers as requi red for m ast er, s la ve and bus iso la tion mod es. When the Universe II is drivi ng lines

on the VMEbus, this signal is driven high; when the VMEbus is driving the Universe II, this signal is driven

low.

VDS[1:0]_ Bidirectional

VMEb us Dat a St ro bes – the level of these signa ls are used to indica te act ive byt e l anes Durin g writ e

cycles, the falling edge indicates valid data on the bus. During read cycles, assertion indicates a request to

a slave to pro vi de data.

VDS_DIR Output

VMEbus Data Strobe Direction Control – controls the direction of the data strobe transceivers as required

for master , slave and bus isolation modes. When the Universe II is driving lines on the VMEbus, this signal

is driven high; when th e VM Ebus is driving the Un iver se I I, th is signal is driven low.

VDTACK_ Bidirectional

VMEb us Dat a Transfer Ac knowledge – VDTA CK _ driven low indic ates t hat th e addr es sed slave ha s

responded to the transfer. The Un iverse II always rescinds DTACK*. It is tristated once the initiating

maste r ne gat es AS *.

VIACK_ Bidirectional

VMEbus Interrupt Acknowledge – Indicates that the cycle just beginning is an interrupt acknowledge cycle.

Table 27: VMEbus Signals (Continued)

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VIACKI_ Input

VMEbus Interrupt Acknowledge In – Input for IACK daisy chain driver. If interrupt acknowledge is at same

leve l as in te rrupt cur re nt ly generate d by the U ni verse II, then the cycl e is accep ted . If inter ru pt

acknowledge is not at same level as current interrupt or Universe II is not generating an interrupt, then the

Univers e II propagates VIACKO_.

VIACKO_ Output

VMEb us Int er rup t Acknowledge Out– Gener at ed by the Un iv er se I I if it receives VI AC KI _ an d is not

currently generating an i nterrupt at the le vel being ackn ow ledged.

VLWORD_ Bidirectional

VMEb us Longwo rd Data Transfer Size Ind icat or – This signal is use d in conjunction w ith the two dat a

strobes VDS [1:0]_ and VA 01 to indicate the number of bytes (1 – 4) in the current transfer. During MBLT

transf er s VLWORD _ serves as data bi t D32.

VOE_ Output

VMEb us Transce iver Out put Enable – U se d to cont ro l transceivers t o isol at e th e Uni ver se II from the

VMEbus during a reset or BI-mode. On power-up, VOE_ is high (to disable the buf fers). VOE_ is negated

during some VMEbus Slave Channel read operations.

VRACFAIL_ Input

VMEb us ACFAIL Input signal – Warns the VM Ebus system of im minent power failur e. Thi s gives the

modules in the system time to shut down in an orderly fashion before power-down. ACF AIL is mapped to a

PCI interrupt .

VRBBSY_ Input

VMEb us Receive Bus Bus y – Allows the Uni ver se II to monitor wh et her the VMEbu s is owned by another

VMEbus mas ter

VRBERR_ Input

VMEbus Receive Bus Error – A low level signal indicates that the addressed slave has not responded, or

is sign al ling an err or.

VRBR[3:0]_ Input

VMEb us Receive Bu s R equ est Li nes – If the Univer se I I is the Syscon, the ar bite r logi c m onitors these

sign als and gene ra te s th e appropriate Bus Gran t signals. Als o m oni t ore d by r equester in ROR m ode.

VRIRQ[7:1]_ Input

VMEbus Receive Interrupts 7 through 1 – These interrupts can be mapped to any of the Universe II’ s PCI

inter ru pt outp ut s. VR IRQ7-1_ are ind i vidually maskable , bu t ca nno t be r ead .

Table 27: VMEbus Signals (Continued)

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VRSYSFAIL_ Input

VMEb us Receive SYS FAI L – Ass er te d by a VMEbus syste m to indicate some sy st em fa ilure.

VRSYSFAIL_ is map ped to a PCI interrupt.

VRSYSRST_ Input

VMEbus Receive System Reset – Causes assertion of LRST_ on the local bus and resets the Universe II.

VSLAVE_DIR Output

VMEb us Slave Direc tion Co ntrol – Transceiver control t hat allo ws th e Uni ver se II to drive DTACK* on the

VMEb us. Wh en t he U niverse II is driving lines on the VM Ebus, this sign al is dri ven hig h; when t he

VMEb us is dr iv ing th e U niver se II, this signa l is driv en low.

VSYSCLK Bidirectional

VMEb us Sy st em C lo ck – Generate d by the U ni v ers e II when it is the Sysco n and moni tored dur in g DY 4

Auto ID sequence

VSCON_DIR Output

Syscon Direction Control – Transceiver control that allows the Universe II to drive VBCLR_ and SYSCLK.

When the Universe II is driving lines on the VMEbus, this signal is driven high; when the VMEbus is driving

the Universe II, this signal is drive n low.

VWRITE_ Bidirectional

VMEb us Writ e signal – Indica te s th e di re ct ion of dat a transfer.

VXBBSY Output

VMEb us Transmit Bus Busy Sign al – Ge ner at ed by the U ni verse I I wh en i t is VMEbus master

VXBERR Output

VMEb us Transmit Bus Error Signal – Gener ated by the Universe I I whe n PCI target gen er at es

Ta rg et-Abort on coupled PCI access from VMEbus.

VXBR [3:0] Output

VMEbus Transmit Bus Request – The Universe II requests the VMEbus when it needs to become

VMEbus mas ter.

VXIRQ [7:1] Output

VMEb us Transmit Inte rrupts – The VMEbus interrupt out puts are indiv idual l y maskable.

Table 27: VMEbus Signals (Continued)

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10.3 PCI Bus Signals

VXSYSFAIL Output

VMEb us Sy st em Fai lure – Asserted by the Univer se I I during r eset and plays a role in VM E64 Auto ID.

VXSYSRST Output

VMEb us Sy st em Reset – The Universe II ou tput for SYSR ST* .

Table 28: PCI Bus Signals

ACK64_ Bidirectional

Acknowledge 64-bit Transfer – It indicates slave can perform a 64-bit transfer when driven by the PCI slave

(target).

AD [ 31:0] Bidirectional

PCI Address/Data Bus – Address and data are multiplexed over these pins providing a 32-bit address and

32-b it dat a bu s.

AD [63: 32] Bidirectional

PCI Address/Dat a Bus – Address and data are mult ip lexed over these pins provi ding 64-bit add re ss and

data capability.

C/BE_ [7:0] Bidirectional

PCI Bus Command and Byte Enable Lines – Command and byte enable information is multiplexed over all

eight C/ BE lin es. C/BE [7:4] _ ar e only used in a 64-bi t PCI bus

DEVSEL_ Bidirectional

PCI Devi ce Select – This si gnal is driven b y the U ni ver se II when it is acc essed as PC I slave.

ENID Input

Enable I D D Tests – Re quire d for ASIC m anuf ac tu ring test, tie to ground for norm al oper ati on.

FRAME_ Bidirectional

Cycl e Fra m e – Thi s signal is driven by the Univer se I I wh en i t is PCI init iato r, and is m oni t or ed by the

Universe II when it is PCI target

GNT_ Input

PCI Gra nt – ind icat es t o th e Univer se II that it has been gra nt ed ow nership of the PC I bus.

Table 27: VMEbus Signals (Continued)

10. Signals and Pinout

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IDSEL Input

PCI Initi aliz at ion D ev ic e Sel ect – Thi s si gn al i s us ed as a chip select during conf igur at i on re ad and write

transactions

LINT[7:0]_ Bid irecti onal (Ope n Dra in)

PCI Inte rrupt In put s – Th ese PCI in terr upt input s can be map ped to any PCI bu s or VME bus interrupt

output.

IRDY_ Bidirectional

Initiator Ready – Is used by the Universe II as PCI mas ter to indicate that is ready to complete a current

data phase.

LCLK Input

PCI Clo ck – Pr ov id es t iming for all transactions on the PC I bus . PCI signal s ar e sampled on the rising

edge of CLK, and all timing par am eters are de fined relative to this signal. The PCI clock frequency of the

Power S pan must be bet ween 25 and 33M Hz. Low er frequen ci es resu lt in inval id VM E tim ing.

LOCK_ Bidirectional

Lock – Used by the Universe II to indicate an exclusive operation with a PCI device. While the Universe II

drives LO C K_, ot her PC I masters are ex cl uded from ac cessing that par ticu la r PCI device. Whe n th e

Univ ers e II sam ples LOC K_, it can be ex cl uded from a par tic ul ar PCI dev ic e.

LRST_ Output

PCI Reset Output – Used to res et PCI re sources.

PAR Bidirectional

Parity – Parity is even across AD [31:0] and C/BE [3:0] (the number of 1s summed across these lines and

PAR equal an even number).

PAR64 Bidirectional

Parity Uppe r DWORD – Parity is even across AD [63:32] and C/BE [7:4] (the number of 1s summed

acro ss t hes e lines and PAR equa l an even numbe r) .

PERR_ Bidirectional

Parity Error – Re por t s par ity error s dur ing al l tra nsa ct io ns. The Univer se I I drives PERR_ hi gh wi th in two

clocks of receiv in g a par ity er r or on inc om ing data, an d holds PERR _ fo r at least one cl ock for ea ch

errore d dat a phase .

Table 28: PCI Bus Signals

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PLL_TESTOUT Output

Manufacturing Test Output—No connect

PLL_TESTSEL Input

Man uf act ur ing Test Sele ct—Tie to ground f or no rmal opera tion

PWRRST_ Input

Power-up Re set – All Universe II circuitry is reset by this input.

REQ_ Output

Bus Request – Used by the Uni ver se II to indicate tha t it requir es t he use of the PCI bus .

REQ64_ Bidirectional

64-Bit Bus R equest — Used to requ est a 64- bit PCI transaction. If the target does not res pond with

ACK 64_, 32- bit oper at i on is assumed.

RST_ Input

PCI Reset Input— Resets the Un iverse II from the PCI bus .

SERR_ Output

System Error – Repor t s address pari ty error s or any ot her system err or.

STOP_ Bidirectional

Stop – Used by the Univer se I I as PCI slave when it wish es to si gnal the PCI ma st er to stop the cur ren t

transaction. As PCI maste r, the Universe II terminates the transaction if it receives STOP_ from the PCI

slave.

TCK Input

JTAG Test Clock Input – Used to clock the Universe II’ s TAP controller. Ti e to any logic level if JTAG is not

used in th e system .

TDI Input

JTAG Test Data Input – Used to serially shift test data and test instructions into the Universe II. Tie to any

logic level if JTAG is not used in the system.

TDO Output

JTAG Test Data Output – Used to serially shift test data and test instructions out of the Universe II

Table 28: PCI Bus Signals

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TMODE [2:0] Input

Te st Mo de Ena b le – U sed for chip test i ng, tie t o gr ound for norm al oper at ion.

TMS Input

JTAG Test Mode Select – Controls the state of the Test Access Port (T AP) controller in the Universe II. T ie

to any logic level if JTAG is not use d in the s ystem.

TRDY_ Bidirectional

Ta rg et Ready – Used by the U niverse I I as PC I slav e to ind icat e th at it is ready to compl et e th e cur r ent

data phase. During a read with Universe II as PCI master , the slave asserts TRDY_ to indicate to the

Un i verse II that valid data i s present on t he data bus .

TRST_ Input

JTAG Tes t Res et – Prov id es as ynchronous initiali zation of the TAP contro ller in the Un iver se I I. Tie to

grou nd i f JTAG is not used i n th e sys t em .

VCOCTL Input

Man uf act ur i ng test i ng – Tie to ground for no r m al o per atio n

VME_RESET_ Input

VMEbus Reset Input — Generates a VME bus system reset.

Table 28: PCI Bus Signals

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10.4 Pin-out

10.4.1 Pin List for 313-pin Plastic BGA P acka ge (P BGA)

A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE

1vd[22] vd[19] vd[9] vd[5] VDD int_[7] VSS lrst_ vrbr_[1] ad[27] ad[58] PLL_

testsel AVSS 1

2vd[18] vd[14] vd[13] vd[6] vd[2] vscon_

DIR vxbbsy ad[61] ad[59] ad[24] PLL_

testout VDD 2

3vd[23] vd[21] vd[20] vd[12] vd[3] int_[5] vbclr_ vrbr_[2] VDD ad[57] lclk VDD vcoctl 3

4vd[26] VDD vd[15] vd[11] vd[4] int_[4] VSS pwrrst_ ad[25] ad[56] perr_ ad[22] 4

5vd[30] vd[24] VDD vd[17] vd[8] VDD ad[63] ad[60] ad[26] vrbr_[0] int_[1] AVDD par64 5

6vd[27] vd[25] vd[16] vd[10] vd[7] vrbbsy_ ad[30] VSS int_[3] ad[23] ad[55] VSS 6

7vrberr_ vd[28] viack_ VDD vd[0] vrbr_[3] vsysclk VDD ad[28] VDD serr_ devsel_ ad[20] 7

8vam_DI

Rvwrite_ vd[29] VDD vd[1] int_[6] par ad[29] VDD ad[21] ad[54] trdy_ 8

9vam[5] VDD vd[31] vam[2] VDD int_[2] VSS ad[62] VDD ad[18] ad[53] VSS VDD 9

10 vam[3] vam[1] vd_DIR vam[4] VSS vxsysfail ad[31] VDD ad[51] VSS ad[52] ad[19] 10

11 vds_[1] tms vam[0] VDD vds_DIR VSS VSS VSS VSS ack64_ VDD ad[50] ad[16] 11

12 voe_ vxberr vds_[0] tck vas_DIR VSS VSS cbe[6] ad[48] ad[49] ad[17] cbe[7] 12

13 tdi tdo trst_ va_DIR VSS VSS VSS VSS VSS cbe[3] tmode[0] vrsysfail

_VSS 13

14 vas_ va[5] va[3] va[1] vlword_ VSS VSS cbe[2] cbe[1] cbe[0] VSS cbe[5] 14

15 va[2] vslave_

DIR VDD vdtack_ va[4] VSS VSS VSS ad[15] VDD ad[14] irdy_ cbe[4] 15

16 va[8] va[10] va[13] va[7] VSS vbgi_[1] ad[0] VSS vrirq_[5] VSS idsel ad[47] 16

17 VDD va[9] va[14] va[6] VDD ad[32] VSS vrirq_[7] VDD frame_ ad[13] VDD gnt_ 17

18 va[12] va[17] va[16] VDD vxirq[3] vbgo_[2] vracfail_ ad[3] VDD ad[45] stop_ req64_ 18

19 va[11] va[18] va[23] VDD vxirq[1] VDD ad[33] ad[2] ad[35] VDD rst_ ad[12] ad[46] 19

20 va[19] va[21] va[22] vrirq_[2] int_[0] vbgo_[0] vrirq_[6] ad[5] ad[39] ad[43] ad[11] ad[44] 20

21 va[15] vrsysrst

_va[28] va[27] vrirq_[4] viacko_ vbgi_[0] VDD ad[38] ad[41] tmode[1] ad[10] enid 21

22 va[20] VDD va[29] vrirq_[1] req_ vxirq[6] ad[1] ad[4] venires_ ad[40] ad[8] ad[42] 22

23 vxsysrst clk64 va[25] vxbr[3] VDD vxirq[5] vbgi_[3] ad[34] ad[36] tmode[2] lock_ VDD viacki_ 23

24 VDD va[30] va[31] vxbr[1] vxirq[2] vbgo_[3] vxbr[2] VSS VSS VDD ad[7] VDD 24

25 va[24] va[26] vrirq_[3] vxbr[0] vxirq[4] vbgo_[1] vbgi_[2] vxirq[7] VDD ad[37] ad[6] VSS ad[9] 25

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10.4.2 361 DBGA Pin List

Table 29: Pin List for 361 Pin DBGA

DBGA_361 Pin DBGA_361 Pin DBGA_361 Pin

E05 vd<20> K02 vrbbsy_ P06 int_<3>

E04 vd<19> J04 int_<7> P04 ad<25>

E06 vd<18> H06 int_<6> V03 ad<57>

G08 vd<17> J01 vscon_dir N06 ad<24>

E03 vd<16> K07 vxsysfail T02 vrbr_<0>

D02 vd<15> K04 vsysclk P05 ad<56>

F04 vd<14> J05 vbclr_ T03 int_<1>

D03 vd<13> K06 ad<31> N04 ad<23>

F02 vd<12> K03 ad<63> R02 pll_testsel

F05 vd<11> K05 vxbbsy W04 lclk

G02 vd<10> L02 par V02 pll_testout

D01 vd<9> L01 lrst_ T04 AVSS

G05 vd<8> L06 ad<30>

E02 vd<7> M07 ad<62>

G03 vd<6> L03 vrbr_<2>

G06 vd<5> N01 vrbr_<1>

G09 vd<4> L04 ad<29>

G01 vd<3> M02 ad<61>

H05 vd<2> L05 ad<28>

E01 vd<1> P02 pwrrst_

H04 vd<0> M04 ad<60>

H02 vrbr_<3> N02 ad<27>

H07 int_<5> M05 ad<59>

J03 int_<4> N03 ad<26>

J02 int_<2> R01 ad<58>

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Table 29: DBGA Pin List (continued)

DBGA_361 Pin DBGA_361 Pin DBGA_361 Pin

T06 AVDD R08 ad<16> P12 req64_

R04 vcoctl N07 ad<48> T14 ad<13>

N10 serr_ Y08 cbe<7> Y15 enid

Y05 perr_ V11 cbe<6> T15 ad<45>

V05 ad<55> W09 cbe<3> V14 stop_

T05 ad<22> P08 vrsysfail_ W17 ad<12>

V07 devsel_ R09 cbe<2> R12 ad<44>

R06 ad<54> W11 tmode<0> W16 rst_

W07 ad<21> T12 cbe<5> V15 ad<11>

W05 par64 Y09 cbe<1> V17 tmode<1>

T08 ad<53> Y11 cbe<4> R13 ad<43>

V06 trdy_ P09 cbe<0> W15 viacki_

P07 ad<20> N16 ad<15> V18 ad<10>

N13 ad<52> V13 irdy_

T09 ad<19> Y12 gnt_

Y04 ad<51> R11 vrirq_<5>

V09 ad<18> W12 ad<47>

Y07 ack64_ P11 frame_

N14 ad<50> Y13 idsel

R07 ad<17> T11 ad<14>

W08 ad<49> W13 ad<46>

10. Signals and Pinout

Universe II VME-to-PCI Bus Bridge Manual 181

80A3010_MA001_03

Table 29: DBGA Pin List (continued)

DBGA_361 Pin DBGA_361 Pin DBGA_361 Pin

Y16 ad<42> K14 vxirq<7> H15 vxbr<1>

R14 ad<9> L15 vracfail_ G10 int_<0>

R16 lock_ L19 vxbr<2> G12 vrirq_<4>

N17 ad<41> K15 ad<0> F18 vrirq_<3>

P13 ad<8> K18 ad<33> F16 vrirq_<2>

T16 ad<40> L14 vbgi_<3> G18 vrirq_<1>

P14 ad<7> J13 vbgi_<2> C16 vxbr<3>

P15 tmode<2> J15 vbgi_<1> G11 va<31>

R18 vme_reset_ K16 vbgi_<0> E19 va<30>

P16 ad<39> K13 vbgo_<3> G17 va<29>

T17 ad<6> K17 vbgo_<2> E18 va<28>

N19 ad<38> J19 vbgo_<1> F15 va<27>

R19 ad<5> J14 vbgo_<0> E17 va<26>

N18 ad<37> H13 ad<32> B17 va<25>

M15 ad<4> J18 vxirq<6>

P18 ad<36> J17 vxirq<5>

T18 ad<3> G15 vxirq<4>

M16 ad<35> J16 vxirq<3>

M18 ad<2> H18 vxirq<2>

M13 ad<34> H14 vxirq<1>

L16 ad<1> G19 req_

L17 vrirq_<7> H16 viacko_

L18 vrirq_<6> G14 vxbr<0>

10. Signals and Pinout

Universe II VME-to-PCI B us Bridge Man ual

182 80A3010_MA001_03

Table 29: DBGA Pin List (continued)

DBGA_361 Pin DBGA_361 Pin DBGA_361 Pin

C17 va<24> F11 vslave_dir E10 vam<2>

D12 clk64 D14 va<5> A07 vam<1>

C13 vrsysrst_ D11 va<4> D06 vam<0>

E16 vxsysrst B11 va<3> B06 vrberr_

F13 va<23> D13 va<2> E09 vam_dir

E15 va<22> E13 va<1> F07 vd_dir

C15 va<21> A12 vas_ C07 vd<31>

D18 va<20> D09 vlword_ A05 vd<30>

D19 va<19> B10 va_dir D05 vd<29>

C12 va<18> E12 tdo B05 vwrite_

B15 va<17> F09 tdi C02 vd<28>

B14 va<16> D08 vas_dir E08 vd<27>

B16 va<15> B09 trst_ B03 vd<26>

D17 va<14> C09 voe_ C05 vd<25>

A15 va<13> A11 tck C04 vd<24>

B13 va<12> A09 vds_<1> E07 viack_

E14 va<11> E11 vds_<0> B04 vd<23>

F12 va<10> F08 vds_dir C03 vd<22>

A13 va<9> B08 vxberr A04 vd<21>

D15 va<8> C08 tms

A16 va<7> A08 vam<5>

C11 va<6> D07 vam<4>

B12 vdtack_ B07 vam<3>

10. Signals and Pinout

Universe II VME-to-PCI Bus Bridge Manual 183

80A3010_MA001_03

Table 30: Grounda, Power and N/Cb

DBGA_

361 Pin

DBGA_

361 Pin DBGA_361 Pin DBGA_361 Pin

DBGA_

361 Pin

A03 Vdd M03 Vdd A14 Vss K12 Vss V08 Vss

A06 Vdd M14 Vdd A17 Vss L07 Vss V19 Vss

A10 Vdd M19 Vdd B02 Vss L08 Vss W02 Vss

C01 Vdd N05 Vdd B18 Vss L09 Vss W10 Vss

C06 Vdd N09 Vdd C18 Vss L10 Vss W18 Vss

C10 Vdd P03 Vdd F06 Vss L11 Vss Y03 Vss

C14 Vdd P17 Vdd F10 Vss L12 Vss Y06 Vss

C19 Vdd R03 Vdd G04 Vss L13 Vss Y14 Vss

D04 Vdd R05 Vdd G16 Vss M06 Vss

D10 Vdd R10 Vdd H08 Vss M08 Vss

D16 Vdd R15 Vdd H09 Vss M09 Vss

F01 Vdd T01 Vdd H10 Vss M10 Vss

F03 Vdd T07 Vdd H11 Vss M11 Vss

F14 Vdd T13 Vdd H12 Vss M12 Vss A01 nc

F17 Vdd T19 Vdd J06 Vss M17 Vss A02 nc

F19 Vdd V04 Vdd J07 Vss N08 Vss A18 nc

G07VddV10VddJ08VssN11VssA19 nc

G13VddV12VddJ09VssN12VssB01 nc

H01 Vdd V16 Vdd J10 Vss N15 Vss B19 nc

H03 Vdd W03 Vdd J11 Vss P01 Vss W01 nc

H17 Vdd W06 Vdd J12 Vss P10 Vss W19 nc

H19 Vdd W14 Vdd K08 Vss P19 Vss Y01 nc

K01 Vdd Y10 Vdd K09 Vss R17 Vss Y02 nc

K19 Vdd Y17 Vdd K10 Vss T10 Vss Y18 nc

M01 Vdd K11 Vss V01 Vss Y19 nc

a. Vdd/VSS pad placements have been based on SSN and Outside location considerations .

b. Route all nc signals out to vias on your board to allow for future migration to Universe II variants

10. Signals and Pinout

Universe II VME-to-PCI B us Bridge Man ual

184 80A3010_MA001_03

Universe II VME-to-PCI Bus Bridge Manual 185

80A3010_MA001_03

11. Electrical Characteristics

This chapter discusses the following topics:

•“DC C haracteristics” on page 185

•“Operating Conditions” on page 187

•“Power Dissipation” on page 188

11.1 DC Characteristic s

11.1.1 Non-PCI Ch arac teri stics

The following table specifies the required DC characteristics of all non PCI signals

pins.

Table 31: Non-PCI Electrical Characteristics

Symbols Parameters Test conditions Min Max

VIH_TTL Voltage Input high 2. 0 V

VIH_CM O S Volt age Input high 0. 7 Vdd

VIL_TTL Voltage Input low 0.8V

VIL_CMOS Voltage Input low 0.3Vdd

VT + _TTL Vol t age Input high

(Schmitt trigger) 2. 0 V

VT+_CMOS Voltage In put high

(Schmitt trigger) 0.7Vdd

VT -_ttl Voltage Input low

(Schmitt trigger) 0.8V

11. Electrical Characteristics

Universe II VME-to-PCI B us Bridge Man ual

186 80A3010_MA001_03

11.1.2 PCI Charac teri stics

The following table s peci fy the required AC and D C characteristics of al l PCI

Universe II signal pins.

VT -_CMOS Voltage Input low

Schmitt tri gge r

0.25Vdd

IIN Input leakage current With no pull-up or pull-down

resist ance (Vin = Vss or Vdd) -5.0µA5.0µA

IIH Inpu t leak age curren t

high Inpu ts wit h pull -d ow n r esi st ance

(Vin = Vdd) 10µA180µA

IIL Inpu t leak age curren t

low Inputs with pul l-up resist ance

(Vin = Vss)

-180µA-10µA

IOZ Tris tate output leakag e Vout = Vdd or Vss -10.0 µA10.0µA

Table 32: AC/DC PCI Electrical Characteristics

Symbols Parameters Condition Min Max Units

VIL V oltage Input low -0.5 0.8 V

VIH Voltage Input high 2.0 Vdd + 0.5 V

IIN Input leakage cu rrent Vin = 2.7V or

0.5V -10 10 µA

IIL Input leakage curre nt low

(Pin with pull-up)

Vin = 0.5V -70 -10 µA

VOL Voltage output low Iout = 3mA, 6mA 0.4 V

VOH Volt age output hi gh Iout = -2mA 2.4 V

IOH (AC)aSwitching cu rrent high 0 < Vout21.4 -44 mA

1.4 < Vout < 2.4 -44 + (Vo ut -1.4) /

0.024 mA

3.1 < Vout < Vdd EqnA mA

(Test point ) Vo ut = 3.1V - 142 mA

Table 31: Non-PCI Electrical Characteristics

Symbols Parameters Test conditions Min Max

11. Electrical Characteristics

Universe II VME-to-PCI Bus Bridge Manual 187

80A3010_MA001_03

11.2 Operating Conditions

The foll owing table spec ifie s r eco mmended op era ting condition for t he Univer se I I .

IOL (AC )bSwitc hi ng cu rr ent high 0 < Vout31.4 95 mA

0.6V dd < Vou t <

0.1Vdd Vout / 0.023 mA

0.71 < Vout < 0 EqnB mA

(Test poi nt) Vo ut = 0.71V 206 mA

ICL Low clamp current -5 Vin2-1 -25 + (Vin +10) /

0.015 mA

SLEW R Output rise slew rate 0. 4V to 2.4V

load 15V/ns

SLEW R Output fa ll slew r ate 2.4V to 0.4V

load 15V/ns

a. Eqn A: Ioh = 11 .9 * (Vout - 5.25) * (Vout + 2.45) for Vdd > Vout > 3.1V

b. Eqn B: Iol = 78.5 * Vout * (4.4 - Vout) for 0V < Vout < 0.71V

Table 33: Operating Conditions

Symbols Parameters Min Max

Frequency

Operation (Mhz)

Vdd DC Supply Voltage (5V ± 10%) 4.5V 5.5V

Ta (Com m e rcial) Ambien t Te m per at ur e 0ºC +70 ºC 25 - 33

Ta (Industrial) Ambi ent Te m per at ur e -40ºC +85ºC 25 - 33

Ta (Extended) Ambient Temperature -55ºC +125ºC 25

Table 32: AC/DC PCI Electrical Characteristics

Symbols Parameters Condition Min Max Units

11. Electrical Characteristics

Universe II VME-to-PCI B us Bridge Man ual

188 80A3010_MA001_03

11.2.1 Absolute Maximum Ratings

11.3 Power Dissipation

Table 34: Absolute Maximum Ratings

Parameter Range

DC Supply Voltage (VSS to VDD) -0.3 to 7.0 V

DC Input Voltag e (VIN) -0.5 to vdd + 0.5V

DC Cur r ent Drain per Pin, Any Single Input or

Output ± 50ma

DC Cur r ent Drain per Pin, Any Par all el ed Out puts ± 100ma

DC Cur r ent D rain VDD and VSS Pi ns ± 75ma

Storage Temperature, (TSTG) -40 ºC t o 125 ºC

Stresses beyond those listed above may cause permane nt damage to the

devices. These are stress ratings only, and functional operation of the

devices at these or any other conditions beyond those indic ated in the

operational se ctions of this doc ume nt is not implied. Exposure to

maximum rating conditions for extended periods m ay affe ct device

reliability.

Table 35: Power Dissipation

Parameter Rating

IDLE

Pow er Dis sipat ion (32-bit PCI) 1.97W

Pow er Dis sipat ion (64-bit PCI) 2.12W

Typical

Pow er Dis sipat ion (32-bit PCI) 2.65W

Pow er Dis sipat ion (64-bit PCI) 3.15W

11. Electrical Characteristics

Universe II VME-to-PCI Bus Bridge Manual 189

80A3010_MA001_03

11.4 Power Sequencing

When designi ng with the Universe II de vice , c are mus t be t aken whe n powering the

device to ensure proper operation. Dur ing power-up, no signals must be applied to

any Universe II signal pins prior to stable power being applied to the device .

In a mixed 3.3V and 5V design, Tundra recommends that 5V power be stable prior

to other devices coming out reset. If other devices come out of r eset before the 5V

power is st able, make ce rtain that no si gnals are dr iven to the Universe II signa l pins

- including possible signals from the VME backplane.

11. Electrical Characteristics

Universe II VME-to-PCI B us Bridge Man ual

190 80A3010_MA001_03

Universe II VME-to-PCI Bus Bridge Manual 191

80A3010_MA001_03

12. Registers

This appendix discusses the follow ing topics:

•“Register Map” on page 192

12.1 Overview

The Universe II Control and Status Registe rs facilitate host system configuration

and allow the user to control Unive rse II operational characteristics. The registers

are divided into three groups:

• PCI Configuration Space

• VMEbus Configuration and Status Registers

• Universe II Device Spec ific Status Registers

Figure 23 below sum marizes the supported register access mechanisms.

Universe II registers have little-endian byte-ordering.

12. Registers

Universe II VME-to-PCI B us Bridge Man ual

192 80A3010_MA001_03

Figure 23: UCSR Access Mechanisms

Bits lis ted as reserve d must be programmed with a value of 0. Reserved bits always

read a value of zero.

12.2 Register Map

Table 36 below lists the Universe II r egisters by address of fse t. The tables f ollowing

the register map (Table 37 to Table 164) provide detailed descriptions of each

Table 36: Universe II Register Map

Offset Register Name Page

0x00 0 P C I Con figu rati on Sp ace ID Regist er PCI_ID Table 37 on

page 202

0x00 4 P CI Configuration Space Co nt ro l and Sta tus

page 203

0x008 P CI Configuration Class Register PCI_CLA SS Ta bl e 39 on

page 207

0x00C PCI Con figuration Mi scellaneo us 0 R egister PCI_M IS C0 Table 40 on

page 208

0x010 PCI Configuration Base Address Register PCI_BS0 Table 41 on

page 209

PCI CONFIGURATION

SPACE

(PCICS)

UNIVERSE DEVICE

SPECIFIC REGISTERS

(UDSR) 4 Kbytes

UCSR Spac

VMEbus Configuration

and Status Registers

(VCSR)

12. Registers
Universe II VME-to-PCI Bus Bridge Manual 193
80A3010_MA001_03
0x014 PCI Configuration Base Address 1 Register PCI_BS1 Ta bl e 42 on 
page 210
0x018- 0x 024 PCI Uni m plem ented
0x028 PCI Reserved
0x02C PCI Reserved
0x03 0 PC I Unim pl em ented
0x034 PCI Reserved
0x038 PCI Reserved
0x03C PCI Con figu rati on M i scellaneo us 1 R egister PCI_MISC1 Tabl e 43 on 
page 212
0x040 -0x 0FF PCI Unim pl em ented
0x10 0 P C I Ta rge t Im age 0 Contro l Reg is ter LSI0 _CTL Table 44 on 
page 213
0x10 4 P CI Target Image 0 Base Addre ss Register LSI 0_ B S Ta bl e 45 on 
page 215
0x108 PCI Target Image 0 Bound Address Register LSI0_BD Table 46 on 
page 216
0x10C PCI Ta rget Image  0 Translation O ffset Re gi st er LSI0_TO Table 47 on 
page 217
0x110 Reserved
0x114 PCI Target Image 1 Control Register LSI1_CTL Table 48 on 
page 218
0x118 PCI Ta rget Im age 1 Base Addre ss  Re gi ster LSI 1_ B S Ta bl e 49 on 
page 220
0x11C PCI Target Image 1 Bound Address Register LSI1_BD Table 50 on 
page 221
0x12 0 P C I Target Im age  1 Translation O ffset  Regi st er LSI1_TO Table 51 on 
page 222
0x124 Reserved
0x12 8 P C I Ta rge t Im age 2 Contro l Reg is ter LSI2 _CTL Table 52 on 
page 223
Table 36: Universe II Register Map  (Continued)
Offset Register Name Page

12. Registers
Universe II VME-to-PCI B us Bridge Man ual
194 80A3010_MA001_03
0x12C PCI Ta rge t Im age  2 Base Address  Regi st er LSI2_BS Tabl e 53 on 
page 225
0x130 PCI Target Image 2 Bound Address Register LSI2_BD Table 54 on 
page 226
0x13 4 P C I Target Im age  2 Translation O ffset  Regi st er LSI2_TO Table 55 on 
page 227
0x138 Reserved
0x13C PCI Ta rge t Im age 3 Contro l Reg is ter LSI3 _C TL Ta ble 56 on 
page 228
0x14 0 P CI Target Image 3 Base Addre ss Register LSI 3_ B S Ta bl e 57 on 
page 230
0x144 PCI Target Image 3 Bound Address Register LSI3_BD Table 58 on 
page 231
0x14 8 P C I Target Im age  3 Translation O ffset  Regi st er LSI3_TO Table 59 on 
page 232
0x14C-0x16C Reserved
0x17 0 S pec ia l Cycle  Cont ro l Reg iste r SCYC_CTL Table 60 on 
page 233
0x17 4 S pecial Cycle P CI Bus  Addr ess Regist er SCY C _ADD R Ta bl e 61 on 
page 234
0x178 Special Cycle Swap/Compare Enable Register SCYC_EN Ta bl e 62 on 
page 235
0x17C Specia l Cycle  Com par e D at a Register SCYC _CM P Ta bl e 63 on 
page 236
0x180 Special Cycle Swap Data Register SCYC_SWP Table 64 on 
page 237
0x184 PCI Mi scellaneous Regist er L MISC Ta bl e 65 on 
page 238
0x18 8 S pec ia l PCI Tar get  Ima ge R egister SLSI Tabl e 66 on 
page 239
0x18C PCI Comm and Error Log  Re gist er L_CMDER R Tabl e 67 on 
page 241
Table 36: Universe II Register Map  (Continued)
Offset Register Name Page

12. Registers
Universe II VME-to-PCI Bus Bridge Manual 195
80A3010_MA001_03
0x19 0 P C I Addre ss Er ro r Log  Re gi ster LAER R Table 68 on 
page 242
0x194-0x19C Reserved
0x1A0 PCI Ta rge t Im age  4 Co nt ro l Reg iste r LSI4 _CTL Table 69 on 
page 243
0x1A4 PCI Ta rget Im age 4 Base Addre ss  Re gi ster LSI 4_ B S Ta bl e 70 on 
page 245
0x1A8 PCI Target Image 4 Bound Address Register LSI4_BD Table 71 on 
page 246
0x1AC PCI Ta rge t Im age  4 Translation O ffset  Regi st er LSI4_TO Tabl e 72 on 
page 247
0x1B0 Reserved
0x1B4 PCI Ta rge t Im age  5 Co nt ro l Reg iste r LSI5 _CTL Table 73 on 
page 248
0x1B8 PCI Ta rget Im age 5 Base Addre ss  Re gi ster LSI 5_ B S Ta bl e 74 on 
page 250
0x1BC PCI Target Image 5 Bound Address Register LSI5_BD Table 75 on 
page 251
0x1C0 PCI Slave  Image 5 Tra nsl at ion O ffset  Regi st er LSI5_ TO Table 76 on 
page 252
0x1C4 Reserved
0x1C8 PCI Ta rge t Im age 6 Contro l Reg iste r LSI6 _CTL Ta bl e 77 on 
page 253
0x1CC PCI Target Image 6 Base Addre ss Register LSI 6_ B S Ta bl e 78 on 
page 255
0x1D0 PCI Target Image 6 Bound Address Register LSI6_BD Table 79 on 
page 256
0x1D4 PCI Ta rget Image  6 Translation O ffset Re gi st er LSI6_TO Table 80 on 
page 257
0x1D8 Reserved
0x1DC PC I Ta rge t Im age 7 Contro l Reg is ter LSI7 _C TL Ta ble 81 on 
page 258
Table 36: Universe II Register Map  (Continued)
Offset Register Name Page

12. Registers
Universe II VME-to-PCI B us Bridge Man ual
196 80A3010_MA001_03
0x1E0 PCI Ta rget Im age 7 Base Addre ss  Re gi ster LSI 7_ B S Ta bl e 82 on 
page 260
0x1E4 PCI Target Image 7 Bound Address Register LSI7_BD Table 83 on 
page 261
0x1E8 PCI Ta rge t Im age 7 Tran sl at io n Offset  Re gist er LSI 7_ TO Table 84 on 
page 262
0x1EC-0x1FC Reserved
0x200 DMA Transfer Control Register DCTL Ta bl e 85 on 
page 263
0x204 DMA Transfer Byte Count Register DTBC Tabl e 86 on 
page 265
0x208 DMA PCI Bus Address Register DLA Table 87 on 
page 266
0x20C Reserved
0x21 0 DMA VMEbus Address Register DVA Table 88 on 
page 267
0x214 Reserved
0x21 8 DM A Comma nd Packet Point er  Regi st er DCPP Tabl e 89 on 
page 268
0x21C Reserved
0x22 0 DMA Gener al  Cont ro l an d Statu s R egister DG C S Table 90 on 
page 269
0x224 DMA Linked List Update Enable Register D_LLUE Table 91 on 
page 273
0x2280x-2FC Reserved
0x30 0 P CI Int errupt Enable Regi ster LINT_EN Ta bl e 92 on 
page 274
0x30 4 P CI Int errupt Status Reg is ter LINT_STAT Table 93 on 
page 277
0x30 8 P C I Interrupt Map 0 Re gi st er LINT_ M AP0 Table 94 on 
page 280
Table 36: Universe II Register Map  (Continued)
Offset Register Name Page

12. Registers
Universe II VME-to-PCI Bus Bridge Manual 197
80A3010_MA001_03
0x30C PCI Interrupt Map 1 Re gi ster LINT_ M AP1 Table 95 on 
page 281
0x310 VMEbus Interrupt Enable Register VINT_EN Ta bl e 96 on 
page 282
0x314 VMEbus Interrupt Status Register VINT_STAT Table 97 on 
page 285
0x318 VMEbus Interrupt Map 0 Register VINT_MAP0 Table 98 on 
page 287
0x31C VMEbus Interrupt Map 1 Register VINT_MAP1 Table 99 on 
page 288
0x32 0 Interrupt Sta tus / ID Out  R egist er STATID Table 100 on 
page 289
0x324 VIRQ1 ST ATUS/ID Register V1_STATID Table 101 on 
page 290
0x328 VIRQ2 ST ATUS/ID Register V2_STATID Table 102 on 
page 291
0x32C VIRQ3 ST ATUS/ID Register V3_STATID Table 103 on 
page 292
0x330 VIRQ4 ST ATUS/ID Register V4_STATID Table 104 on 
page 293
0x334 VIRQ5 ST ATUS/ID Register V5_STATID Table 105 on 
page 294
0x338 VIRQ6 ST ATUS/ID Register V6_STATID Table 106 on 
page 295
0x33C VIRQ7 ST ATUS/ID Register V7_STATID Table 107 on 
page 296
0x34 0 P C I Interrupt Map 2 Re gi st er LINT_ M AP2 Table 108 on 
page 297
0x344 VME Interrupt Map 1 Register VINT_MAP2 Table 109 on 
page 298
0x348 M ailbox 0 R egi st er MBOX 0 Tabl e 110 on 
page 299
Table 36: Universe II Register Map  (Continued)
Offset Register Name Page

12. Registers
Universe II VME-to-PCI B us Bridge Man ual
198 80A3010_MA001_03
0x34C Mailbo x 1 R egi st er MBOX 1 Ta bl e 111 on 
page 300
0x350 M ailbox 2 R egi st er MBOX 2 Tabl e 112 on 
page 301
0x354 M ailbox 3 R egi st er MBOX 3 Tabl e 113 on 
page 302
0x358 Semaphore 0 R egist er SE M A0 Table 114 on 
page 303
0x35C Semaphore 1 R egist er SE M A1 Table 115 on 
page 304
0x360-0x3FC Reserved
0x40 0 Ma st er Co nt rol Register M AST_CTL Table 116 on 
page 305
0x40 4 Miscellaneous Con trol R egist er M ISC _CTL Table 117 on 
page 308
0x40 8 Miscellaneous Status Register MISC _STAT Tabl e 118 on 
page 311
0x40C User AM Cod es R eg i st er  USER_AM Table 119 on  
page 313
0x410-0x4F8 Reserved
0x4FC Universe II Specific Re gister U2SPEC Table 120 on 
page 314
0x500-0xEFC Reserved
0xF00 VMEbus Slave Image 0 Con trol  Regi st er VS I0 _CTL Table 121 on 
page 316
0xF04 VMEbus Slave Image 0 Base Address Register VSI0_BS Table 122 on 
page 318
0xF08 VMEbus Slave Image 0 Bound Address 
Register VSI0_BD Table 123 on 
page 319
0xF0C VMEbus Slave Image 0 Tr anslation O ffset 
Register VSI0_TO Table 124 on 
page 320
0xF10 Reserved
Table 36: Universe II Register Map  (Continued)
Offset Register Name Page

12. Registers
Universe II VME-to-PCI Bus Bridge Manual 199
80A3010_MA001_03
0xF14 VMEbus Slave Image 1 Con trol  Regi st er VS I1 _CTL Table 125 on 
page 321
0xF18 VMEbus Slave Image 1 Base Address Register VSI1_BS Table 126 on 
page 323
0xF1C VME bus Slave Ima ge 1 Bound Addre ss 
Register VSI1_BD Table 127 on 
page 324
0xF20 VMEbus Slave Image 1 Translation O ffset 
Register VSI1_TO Table 128 on 
page 325
0xF24 Reserved
0xF28 VMEbus Slave Image 2 Con trol  Regi st er VS I2 _CTL Table 129 on 
page 326
0xF2C VMEbus Slave Image 2 Base Address Register VSI2_BS Table 130 on 
page 328
0xF30 VMEbus Slave Image 2 Bound Address 
Register VSI2_BD Table 131 on 
page 329
0xF34 VMEbus Slave Image 2 Translation O ffset 
Register VSI2_TO Table 132 on 
page 330
0xF38 Reserved
0xF3C VME bus Slave Ima ge 3 Control Regist er VSI3_CTL Table 133 on 
page 331
0xF40 VMEbus Slave Image 3 Base Address Register VSI3_BS Table 134 on 
page 333
0xF44 VMEbus Slave Image 3 Bound Address 
Register VSI3_BD Table 135 on 
page 334
0xF48 VMEbus Slave Image 3 Translation O ffset 
Register VSI3_TO Table 136 on 
page 335
0xF4C-0xF60 Reserved
0xF64 Location Monitor Control Register LM_CTL Table 137 on 
page 336
0xF68 Location Mo nito r Bas e Addr ess Regist er LM_BS Table 138 on 
page 338
0xF6C Reserved
Table 36: Universe II Register Map  (Continued)
Offset Register Name Page

12. Registers
Universe II VME-to-PCI B us Bridge Man ual
200 80A3010_MA001_03
0xF70 VMEbus Register Access Image Control 
Register VRAI_CTL Table 139 on 
page 339
0xF74 VMEbus Register Access Image Base Address 
Register VRAI_BS Table 140 on 
page 340
0xF78-0xF7C Reserved
0xF80 VMEbus CSR Control Register VCSR_CTL Table 142 on 
page 341
0xF84 VMEbus CSR Translation Of fset Register VCSR_TO Table 143 on 
page 342
0xF88 VME bus AM Code Error Log R egister V_AMERR Table 144 on 
page 343
0xF8C VMEbus Address Error Log Register VAERR Table 145 on 
page 344
0xF90 VMEbus Slave Image 4 Con trol  Regi st er VS I4 _CTL Table 146 on 
page 345
0xF94 VMEbus Slave Image 4 Base Address Register VSI4_BS Table 147 on 
page 347
0xF98 VMEbus Slave Image 4 Bound Address 
Register VSI4_BD Table 148 on 
page 348
0xF9C VMEbus Slave Image 4 Tr anslation O ffset 
Register VSI4_TO Table 149 on 
page 349
0xFA0 Reserved
0xFA 4 VMEbus Slave Image 5 C ontrol Regist er VS I5 _C TL Table 150 on 
page 350
0xF A8 VMEbus Slave Image 5 Base Address Register VSI5_BS Table 151 on 
page 352
0xFAC VME bus  Slav e Ima ge 5 Bound Ad dre ss 
Register VSI5_BD Table 152 on 
page 353
0xFB0 VMEbus  Slave Image 5 Tr anslation O ffset 
Register VSI5_TO Table 153 on 
page 354
0xFB4 Reserved
0xFB8 VMEbus  Slave Image 6 Con trol R egi ster VSI6_CTL Table 154 on 
page 355
Table 36: Universe II Register Map  (Continued)
Offset Register Name Page

12. Registers
Universe II VME-to-PCI Bus Bridge Manual 201
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0xFBC VMEbus Slave Image 6 Base Address Register VSI6_BS Table 155 on 
page 357
0xFC0 VME bus Slave Ima ge 6 Bound Addre ss 
Register VSI6_BD Table 156 on 
page 358
0xFC4 VMEbus Slave Image 6 Tr anslation O ffset 
Register VSI6_TO Table 157 on 
page 359
0xFC8 Reserved
0xFCC V ME bus Slave Image 7 C ontrol Regist er VS I7 _CTL Table 158 on 
page 360
0xFD0 VMEbus Slave Image 7 Base Address Register VSI7_BS Table 159 on 
page 362
0xFD4 VME bus Slave Ima ge 7 Bound Addre ss 
Register VSI7_BD Table 160 on 
page 363
0xFD8 VMEbus Slave Image 7 Tr anslation O ffset 
Register VSI7_TO Table 161 on 
page 364
0xFDC-0xFEC Reserved
0xFF0 VME CR/CSR Reserved
0xFF4 VMEbus CSR Bit Clear Register VCSR_CLR Table 162 on 
page 365
0xFF8 VMEbus CSR Bit Set Register VCSR_SET Table 163 on 
page 366
0xFFC VMEbus CSR Base Address Register VCSR_BS Table 164 on 
page 367
Table 36: Universe II Register Map  (Continued)
Offset Register Name Page

12. Registers

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12.2.1 PCI Configuration Space I D Register (P CI_ ID)

Table 37: PCI Configuration Space ID Register (PCI_ID)

Bits Function

31-24 DID

23-16 DID

15-08 VID

07-00 VID

PCI_ID Descriptio n

Name Type Reset By Reset

State Function

DID[15:0] R all 0 Device ID - Tundra allocated device ide ntifier

VID[ 15 :0 ] R all 10E3 Vendor ID - PCI SIG all ocated vend or ident ifier

12. Registers

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12.2.2 PCI Configu ration Sp ace Co ntro l and S tat us Reg iste r

(PCI_CSR)

Table 38: PCI Configuration Space Control and Status Register (PCI_CSR)

Bits Function

31-24 D_PE S_SERR R_MA R_TA S_TA DEVSEL DP_D

23-16 TFBBC PCI Reserved

15-08 PCI Res erved MFBBC SERR_E

07-00 WAIT PERESP VGAPS MWI_EN SC BM MS IOS

PCI_CSR Description

Name Type Reset By R ese t St ate Function

D_PE R/Write

1 to

Clear

all 0 Detected Parity Error

0=No parity error

1=Parit y error

This bit is always set by the Universe II when

the PCI master interface detects a data parity

error or the PC I tar get in te rface detect s

addr ess or data parit y error s.

S_SERR R/Write

1 to

Clear

all 0 Signalled SERR_

0=SER R _ not asserted

1=SER R _ ass erted.

The Universe II PCI target interface sets this

bit when i t asserts SERR _ to si gnal an

address parity error. SERR_EN must be set

before SERR_ can be ass erted.

R_MA R/Write

1 to

Clear

all 0 Received Master-Abort

0=Master did no t ge ner at e M ast er -Abort

1=Master gener at ed M aster-Abort

The Unive rse II PCI master interfac e sets this

bit when a t ra nsaction it in itiat ed had to be

terminated with a Master-Abort.

12. Registers

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R_TA R/Write

1 to

Clear

all 0 Received Target-Abort

0=Master did no t de tec t Target-Abort

1=Master de tect ed Targe t-A bort.

The Universe II PCI master interface sets this

bit when a t ra nsactio n it initi ated w as

terminated with a Target-Abort.

S_TA R/Write

1 to

Clear

all 0 Si gnalled Tar get - Abor t

0=Target did not terminate transaction with

Target-Abort

1=Target term in at ed t ra nsaction w ith

Target-Abort.

DEVSEL R all 01 Device Selec t Tim ing

The U niver se II is a medium speed devi ce

DP_D R/Write

1 to

Clear

all 0 Master Data Parity Error

0=Master did no t de tec t/ge ner at e data parity

error, 1=Master det ected/generate d dat a

parit y error.

The Universe II PCI master interface sets this

bit if the Parity Error Respons e bit is set, if it

is the m ast er of tra nsactio n in wh ic h it

asser t s PERR _, or the addr ess ed t ar get

asser t s PE R R_.

TFBBC R all 0 Target Fast Back to Back Capable

Unive rs e II can not accept Back to Ba ck

cycles from a different agent.

MFBBC R a ll 0 Master Fast Back to Back Enable

0=no fas t ba ck- t o- back transact i ons

The U niver se II maste r ne ver generate s fast

back t o back transaction s.

SERR_EN R/W all 0 SERR_ Enable

0=Disable SERR_ driver

1=Enabl e SER R_ driver.

Setting this and PERESP allows the

Unive rse II PC I target in terface to report

addr ess parit y er ro rs wit h SERR _.

PCI_CSR Description

Name Type Reset By R ese t St ate Function

12. Registers

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WAIT R all 0 Wait Cycle Control

0=No address/data stepping

PERESP R/W all 0 Parity Error Response

0=Disable

1=Enable

Controls the Universe II response to data and

addr ess parity erro rs. When enabl ed, it

allows the assertion of PERR_ to report data

parit y error s. When this bi t an d SERR _EN

are as ser te d, the Univer se I I ca n re por t

addr ess parity errors on SER R _. Uni ver se II

parit y gen era tion is unaffected by this bit.

VGAPS R all 0 VGA Palette Snoop

0=Disable

The Un iver se II treats palet t e accesses l ike

all other accesses.

MW I_EN R all 0 Memor y Writ e and Invalid ate Enable

0=Disable

The Uni ver se II PCI master in terf ace never

gener at es a M em ory Write an d In vali dat e

command.

SC R all 0 Spe ci al Cycl es

0=Disable

The Universe II PCI target interface never

resp onds to special cycl es.

BM R / W PWR VM E Th i s bit is 1 afte r

re set if th e

VMEbus Address

[14 ] eq uals 1

during power-on

reset.

This bit is

reloaded by “all ”.

Master Enable

0=Disable

1=Enable

For a VMEbus slave imag e to res pond to an

incoming cycle, this bit must be set. If this bit

is cleared while ther e is dat a in th e VM Ebus

Slave Post ed Write FIFO, the dat a w ill be

writte n to the PCI bus but no further data will

be accepted into this FIFO until th e bit is set.

PCI_CSR Description

Name Type Reset By R ese t St ate Function

12. Registers

Universe II VME-to-PCI B us Bridge Man ual

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The Universe II only refuses PCI addresses with parity errors when both the

PERESP and SERR_EN bits are programmed to a value of 1.

MS R/W PW R VM E Th i s bit is 1 af ter

re set if th e

VMEbus Address

[1 3:12 ] eq uals 10

during power-on

reset. This bit is

reloaded by “all ”

Target Memory Enable

0=Disable

1=Enable

IOS R/W PWR VME Th i s bi t is 1 after

re set if th e

VMEbus Address

[1 3:12 ] eq uals 10

during power-on

reset. This bit is

reloaded by “all ”

Target IO Enable

0=Disable

1=Enable

PCI_CSR Description

Name Type Reset By R ese t St ate Function

12. Registers

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12.2.3 PCI Configuration Class Register (PCI_CLASS)

Table 39: PCI Configuration Class Register (PCI_CLASS)

Bits Function

31-24 BASE

23-16 SUB

15-08 PROG

07-00 RID

PCI_CLASS Description

Name Type Reset By Reset

State Function

BASE [7:0 ] R all 06 Base Class Code

The Uni ver se II is defined as a PC I bridge devic e

SUB [7:0] R all 80 Sub Class Code

The U niver se II sub-cl as s is “other bridge device”

PROG [7:0] R all 00 Programming Interface

The Universe II does not have a standardized

regist er - le vel pro gr am ming int erfac e

RID [7:0] R a ll 02 Revision ID

12. Registers

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12.2.4 PCI Configuration Miscellaneous 0 Register (PCI_MISC0)

The Universe II is not a multi-function device.

LTIMER: When the Universe II latency timer is progra mmed for eight clock

periods and FRAME_, IRDY_ and TRDY_ are asserted while GNT_ is not

asserted, FRAME_ is negated on the next clock edge .

Table 40: PCI Configuration Miscellaneous 0 Register (PCI_MISC0)

Bits Function

31-24 BIST C SBIST PCI Reserved CCODE

23-16 MFUNCT LAYOUT

15-08 LTIMER 000

07-0 0 PCI U nim pl em ent ed

PCI_MISC 0 Description

Name Type Reset By Reset

State Function

BISTC R all 0 The Universe II is not BIST Capable

SBIST R all 0 Start BIST

The Universe II is not BIST capable

CCOD E R all 0 C omplet io n C ode

The Universe II is not BIST capable

MFUNCT R all 0 Mu ltifunction Device

0=No

1=Yes

The Univer se II is not a multi-fu n ct io n devic e.

LAYOUT R all 0 C onfigur at ion Space Layout

LTIMER [7:3] R/W all 0 L atency Timer: The latency timer has a resolution

of eight clocks

12. Registers

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12.2.5 PCI Configurati on Base Add ress Register (PCI_BS 0)

This register specifies the 4 Kbyte aligned base address of the 4 Kbyte Universe II

A power -up opti on determines if the re gisters ar e mapped into Memory or I/O spa ce

in relation to this base address. (See “Power-Up Options” on page 160). If mapped

into Me mory spac e, the use r is fr ee to l ocate the reg is ters a ny wh er e in the 32-bit

address space . If PCI_BS0 is mapped to Memory space, PCI_BS1 is mapped to I/O

space; if P CI_ BS0 is mapped to I/O space, then PCI_BS1 is mapped to M em ory

space.

• When the VA[1] pin is samp led low at power-up, the PCI_BS0 register’s

SPACE bit is set to 1, which signifies I/O space, and the PCI_BS1 register’s

SPACE bit is set to 0, which signifies memory space .

• When VA[1] is sampled high at power-up, the PCI_BS0 register’s SPAC E

A write must o ccur to this reg ister before the Universe II Device Spec ific Regis t ers

can be accessed. This write can be perform ed with a PCI configuration transaction

or a VMEbus register access.

Table 41: PCI Configuration Base Address Register (PCI_BS0)

Bits Function

31-24 BS

23-16 BS

15-08 BS 0000

07-000000000SPACE

PCI_BS0 Description

Name Type Reset By Reset

State Function

BS[31:1 2] R/W a ll 0 Base Add ress

SPACE R all Power-up

Option PCI Bus Address Space

0=Memory

1=I/O

12. Registers

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12.2.6 PCI Configuration Base Address 1 Register (PCI_BS1)

This register specifies the 4 KByte aligned base a ddress of the 4 KByte Universe II

A power -up option dete rmines the value of the SPACE bit. This determines whe ther

the registers are mapped into Memory or I/O space in relation to this base address.

(See “Power-Up Options” on page 160). If mapped into Memory space, the user is

free to loc ate the Universe registers anywhere in the 32-bit address spac e. If

PCI_B S0 is mapped to Memory space, PCI_BS1 is mapped to I/O s pace; if

PCI_BS0 is mapped to I/O space, then PCI_BS1 is mapped to Memory space.

• When the VA[1] pin is samp led low at power-up, the PCI_BS0 register’s

SPACE bit is set to “1”, which signifies I/O space, and the PCI_BS1 register’s

SPACE bit is set to “0” , which signifies memory spa ce.

• When VA[1] is sampled high at power-up, the PCI_B S0 register’s SPAC E

regist er’s bit is set t o “0”, whi ch sign if ies Memo ry space, and th e PCI_BS1

A write must o ccur to this register b efore the Univers e II Device Specif ic Regist ers

can be accessed. This write can be perform ed with a PCI configuration transaction

or a VMEbus register access.

Table 42: PCI Configuration Base Address 1 Register (PCI_BS1)

Bits Function

31-24 BS

23-16 BS

15-08 BS 0000

07-000000000SPACE

PCI_BS1 Description

Name Type Res et By Reset

State Function

BS[31:12] R/W all 0 Base Address

SPACE R all Power-up

Option PCI Bus Addr es s Space

0=Memory

1=I/O

12. Registers

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The SPACE bit in this register is an inversion of the SPACE field in PCI_BS0.

12. Registers

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212 80A3010_MA001_03

12.2.7 PCI Configuration Miscellaneous 1 Register (PCI_MISC1)

The MIN_GNT parameter assumes the Universe II master is transfer ring an aligned

burst size of 64 bytes to a 32-bit target with no wait states. This would require

roughly 20 clocks (at a clock frequency of 33 MHz, this is about 600 ns).

MIN_GNT is set to three, or 750 ns.

Table 43: PCI Configuration Miscellaneous 1 Register (PCI_MISC1)

Bits Function

31-24 MAX_LAT [7:0}

23-1 6 M IN_ GNT [7:0}

15-08 INT_PIN [7:0}

07-0 0 INT_LI NE [7:0 }

PCI_MISC 1 Description

Name Type Reset By Reset

State Function

MAX_LAT[7:0] R all 0 Maximum Latency: This device has no special

latenc y re qui r em ent s

MIN_GNT[7:0] R all 0 000 0011 Mini m um G ran t: 250 ns

INT_PIN[7:0] R all 00000001 Interrupt Pin: Universe II pin INT_ [0] has a PCI

compli ant I/O buffer

INT_LINE[7:0] R/W all 0 I nt er rup t Line : us ed by some PCI sys te m s to

recor d inte rrupt routing informa tion

12. Registers

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12.2.8 PCI Target Image 0 Con trol (LS I0_CTL)

Table 44: PCI Target Image 0 Control (LSI0_CTL)

Bits Function

31-24 EN PWEN Reserved

23-16 VDW Reserved VAS

15-08 Reserved PGM Reserved SUPER Reserved VCT

07-00 Reserved LAS

LSI0_CTL Description

Name Type Reset By Reset

State Function

EN R/W all Power-up

Option Image Enable

0=Disable

1=Enable

PWEN R/W all 0 Posted Write Enable

0=Disable

1=Enable

VDW R/W a ll 10 VMEbus Maximum Datawidth

00= 8-b i t data wi dt h

01= 16 bit dat a w idth

10= 32- bi t data width

11=64-bit data width

VAS R/W all Power-up

Option VMEbus Address Space

000=A16

001=A24

010=A32

011= Rese rv ed

100=Reserved

101=CR/CSR

110=User1

111=User2

12. Registers

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214 80A3010_MA001_03

In the PCI Tar get Image Control regist er , sett ing the VCT bit will only have ef fect if

the VAS bits are programmed for A24 or A32 space and the VDW bits are

programmed for 8- bit, 16-bit, or 32-bit.

If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for

64-bit, the Universe II may pe rform MBLT transfers independent of the state of the

VCT bit.

The setting of the PWEN bit is ignored if the LAS bit is progr amme d for PCI Bus

I/O Space, forcing all transactions through this image to be coupled.

PGM R/W all 0 Prog ram/Data AM Code

0=Data

1=Program

SUPER R/W all 0 Su per visor/User AM Code

0=Non-Privileged

1=Supervisor

VCT R/W a ll 0 VM Eb us Cy cle Type

0=No BLTs on VMEbus

1=Single BLTs on VMEbus

LAS R/W all Power-up

Option PCI Bus Memory Space

0=PCI Bus Memory Space

1=PCI Bus I/O Space

LSI0_CTL Description

Name Type Reset By Reset

State Function

12. Registers

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12.2.9 PCI Targ et Imag e 0 Base Ad dress Register (LSI0_ BS )

The bas e address speci fies the l owest ad dress in t he address rang e t hat will b e

decoded.

The base address for PCI Targe t Image 0 and PCI Targe t Image 4 have a 4 Kbyte

resolution. PCI Target Images 1, 2, 3, 5, 6, and 7 have a 64 Kbyte resolution.

Table 45: PCI Target Image 0 Base Address Register (LSI0_BS)

Bits Function

31-24 BS

23-16 BS

15-08 BS Reserved

07-00 Reserved

LSI0_BS Description

Name Type Reset By Reset

State Function

BS[3 1:28] R/W all Power-up

Option Base Address

BS[2 7:12] R/W all 0 Base Add re ss

12. Registers

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216 80A3010_MA001_03

12.2.10 PCI Target Image 0 Bou nd Addr ess Register (LSI0 _BD)

The addresses decoded in a slave image are those which are greater than or equal to

the base address and less than the bound register. If the bound address is 0, then the

addresses decoded are those greate r than or equal to the base address.

The bound address for PCI Target Im age 0 and PCI Targe t Image 4 have a 4Kbyte

resolution. PCI Target Images 1, 2, 3, 5, 6, and 7 have a 64Kbyte resolution.

Table 46: PCI Target Image 0 Bound Address Register (LSI0_BD)

Bits Function

31-24 BD

23-16 BD

15-08 BD Reserved

07-00 Reserved

LSI0_BD Description

Name Type Reset By Reset

State Function

BD[31:28] R /W all Pow er-up

Option Bound Address

BD[27:12] R/W all 0 Bound Address

12. Registers

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12.2.11 PCI Target Imag e 0 Translation Offse t (LSI0_TO)

The tra nslation of fset for PCI Targe t Image 0 and PCI Target I mage 4 have a 4Kbyte

resolution. PCI Target Images 1, 2, 3, 5, 6, and 7 have a 64Kbyte resolution.

Address bi ts [31 :12] generate d on the VMEbus in r esponse t o an i mage decode ar e a

two’s complement addition of address bits [31:12] on the PCI Bus and bits [ 31:12]

of the image’s translation offset.

Table 47: PCI Target Image 0 Translation Offset (LSI0_TO)

Bits Function

31-24 TO

23-16 TO

15-08 TO Reserved

07-00 Reserved

LSI0_TO Description

Name Type Reset By Reset

State Function

TO[31:12] R /W al l 0 Tra nsl at ion O ffset

12. Registers

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218 80A3010_MA001_03

12.2.12 PCI Target Imag e 1 Con trol (LS I1_CTL)

Table 48: PCI Target Image 1 Control (LSI1_CTL)

Bits Function

31-24 EN PWEN Reserved

23-16 VDW Reserved VAS

15-08 Reserved PGM Reserved SUPER Reserved VCT

07-00 Reserved LAS

LSI1_C TL Description

Name Type Reset By Reset

State Function

EN R/W all 0 Image Enable

0=Disable

1=Enable

PWEN R/W all 0 Posted Write Enable

0=Disable

1=Enable

VDW R/W all 10 VMEbus Maximum Datawidth

00=8-bit data width

01=16 bit data w i dth

10=32 -b it data w i dt h

11=64-bit data w i dt h

VAS R/W all 0 VMEbus Addres s Space

000=A16

001=A24

010=A32

011= Reserved

100=Reserved

101=CR/CSR

110=User1

111=User2

12. Registers

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In the PCI Tar get Image Control regist er , sett ing the VCT bit will only have ef fect if

the VAS bits are programmed for A24 or A32 space and the VDW bits are

programmed for 8- bit, 16-bit, or 32-bit.

If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for

64-bit, the Universe II may pe rform MBLT transfers independent of the state of the

VCT bit.

The setting of the PWEN bit is ignored if the LAS bit is progr amme d for PCI Bus

I/O Space, forcing all transactions through this image to be coupled.

PGM R/W all 0 Program/Data AM Code

0=Data

1=Program

SUPER R/W all 0 Supervisor/User AM Code

0=Non-Privileged

1=Supervisor

VCT R/W all 0 VMEbus Cycle Type

0=no BLTs on V ME bus

1=BLTs on VMEb us

LAS R/W all 0 PCI Bus Memory Space

0=PCI Bus Memory Space

1=PCI Bus I/O Space

LSI1_C TL Description

Name Type Reset By Reset

State Function

12. Registers

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220 80A3010_MA001_03

12.2.13 PCI Target Image 1 Base Ad dress Register (LS I1_BS )

The bas e add res s specifi es the lo west add ress in t he address rang e t hat will b e

decoded.

Table 49: PCI Target Image 1 Base Address Register (LSI1_BS)

Bits Function

31-24 BS

23-16 BS

15-08 Reserved

07-00 Reserved

LSI1_BS Description

Name Type Reset By Reset

State Function

BS[31:16] R/W all 0 Base Address

12. Registers

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12.2.14 PCI Target Image 1 Bou nd Addr ess Register (LSI1 _BD)

The addresses decoded in a slave image are those which are greater than or equal to

the base address and less than the bound register. If the bound address is 0, then the

addresses de coded are those greater than or equal to the base address.

The bound address for PCI Target Im age 0 and PCI Targe t Image 4 have a 4Kbyte

resolution. PCI Target Images 1, 2, 3, 5, 6, and 7 have a 64Kbyte resolution.

Table 50: PCI Target Image 1 Bound Address Register (LSI1_BD)

Bits Function

31-24 BD

23-16 BD

15-08 Reserved

07-00 Reserved

LSI1_BD Description

Name Type Reset By Reset

State Function

BD[31:16] R/W all 0 Bound Address

12. Registers

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222 80A3010_MA001_03

12.2.15 PCI Target Imag e 1 Tran sl ation Offset (LSI1_TO)

Address bi ts [31 :16] generate d on the VMEbus in r esponse t o an i mage decode are a

two’s complement addition of address bits [31:16] on the PCI Bus and bits [ 31:16]

of the image’s translation offset.

Table 51: PCI Target Image 1 Translation Offset (LSI1_TO)

Bits Function

31-24 TO

23-16 TO

15-08 Reserved

07-00 Reserved

LSI1_TO Description

Name Type Reset By Reset

State Function

TO[31:16] R /W all 0 Transl at i on offset

12. Registers

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12.2.16 PCI Target Imag e 2 Con trol (LS I2_CTL)

Table 52: PCI Target Image 2 Control (LSI2_CTL)

Bits Function

31-24 EN PWEN Reserved

23-16 VDW Reserved VAS

15-08 Reserved PGM Reserved SUPER Reserved VCT

07-00 Reserved LAS

LSI2_C TL Description

Name Type Reset By Reset

State Function

EN R/W all 0 Image Enable

0=Disable

1=Enable

PWEN R/W all 0 Posted Write Enable

0=Disable

1=Enable

VDW R/W a ll 10 VMEbus Maximum Datawidth

00= 8-b i t data wi dt h

01= 16 bit dat a w idth

10= 32- bi t data width

11=64-bit data width

VAS R /W all 0 VMEbus Ad dre ss Space

000=A16

001=A24

010=A32

011= Rese rv ed

100=Reserved

101=CR/CSR

110=User1

111=User2

12. Registers

Universe II VME-to-PCI B us Bridge Man ual

224 80A3010_MA001_03

In the PCI Tar get Image Control regist er , sett ing the VCT bit will only have ef fect if

the VAS bits are programmed for A24 or A32 space and the VDW bits are

programmed for 8- bit, 16-bit, or 32-bit.

If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for

64-bit, the Universe II may pe rform MBLT transfers independent of the state of the

VCT bit.

The setting of the PWEN bit is ignored if the LAS bit is progr amme d for PCI Bus

I/O Space, forcing all transactions through this image to be coupled.

PGM R/W a ll 0 Pr og ram/Data AM Code

0=Data

1=Program

SUPER R/W all 0 Su per visor/User AM Code

0=Non-Privileged

1=Supervisor

VCT R/W a ll 0 VM Eb us Cy cle Type

0=no BLTs on VMEbu s

1=BLTs on VMEbus

LAS R/W all 0 PCI Bus Memory Space

0=PCI Bus Memory Space

1=PCI Bus I/O Space

LSI2_C TL Description

Name Type Reset By Reset

State Function

12. Registers

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12.2.17 PCI Target Image 2 Base Ad dress Register (LS I2_BS )

The bas e address speci fies the l owest ad dress in t he address rang e t hat will b e

decoded.

Table 53: PCI Target Image 2 Base Address Register (LSI2_BS)

Bits Function

31-24 BS

23-16 BS

15-08 Reserved

07-00 Reserved

LSI2_BS Description

Name Type Reset By Reset

State Function

BS[3 1:16] R/W all 0 Base Add re ss

12. Registers

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226 80A3010_MA001_03

12.2.18 PCI Target Image 2 Bou nd Addr ess Register (LSI2 _BD)

The addresses decoded in a slave image are those which are greater than or equal to

the base address and less than the bound register. If the bound address is 0, then the

addresses de coded are those greater than or equal to the base address.

Table 54: PCI Target Image 2 Bound Address Register (LSI2_BD)

Bits Function

31-24 BD

23-16 BD

15-08 Reserved

07-00 Reserved

LSI2_BD Description

Name Type Reset By Reset

State Function

BD[31:16] R/W all 0 Bound Address

12. Registers

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12.2.19 PCI Target Imag e 2 Translation Offse t (LSI2_TO)

Address bi ts [31 :16] generate d on the VMEbus in r esponse t o an i mage decode ar e a

two’s complement addition of address bits [31:16] on the PCI Bus and bits [ 31:16]

of the image’s translation offset.

Table 55: PCI Target Image 2 Translation Offset (LSI2_TO)

Bits Function

31-24 TO

23-16 TO

15-08 Reserved

07-00 Reserved

LSI2_TO Description

Name Type Reset By Reset

State Function

TO[31:16] R /W all 0 Transl at ion offset

12. Registers

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12.2.20 PCI Target Imag e 3 Con trol (LS I3_CTL)

Table 56: PCI Target Image 3 Control (LSI3_CTL)

Bits Function

31-24 EN PWEN Reserved

23-16 VDW Reserved VAS

15-08 Reserved PGM Reserved SUPER Reserved VCT

07-00 Reserved LAS

LSI3_C TL Description

Name Type Reset By Reset

State Function

EN R/W all 0 Image Enable

0=Disable

1=Enable

PWEN R/W all 0 Posted Write Enable

0=Disable

1=Enable

VDW R/W a ll 10 VMEbus Maximum Datawidth

00= 8-b i t data wi dt h

01= 16 bit dat a w idth

10= 32- bi t data width

11=64-bit data width

VAS R /W all 0 VMEbus Ad dre ss Space

000=A16

001=A24

010=A32

011= Rese rv ed

100=Reserved

101=CR/CSR

110=User1

111=User2

12. Registers

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In the PCI Tar get Image Control regist er , sett ing the VCT bit will only have ef fect if

the VAS bits are programmed for A24 or A32 space and the VDW bits are

programmed for 8- bit, 16-bit, or 32-bit.

If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for

64-bit, the Universe II may pe rform MBLT transfers independent of the state of the

VCT bit.

The setting of the PWEN bit is ignored if the LAS bit is progr amme d for PCI Bus

I/O Space, forcing all transactions through this image to be coupled.

PGM R/W a ll 0 Pr og ram/Data AM Code

0=Data

1=Program

SUPER R/W all 0 Su per visor/User AM Code

0=Non-Privileged

1=Supervisor

VCT R/W a ll 0 VM Eb us Cy cle Type

0=no BLTs on VMEbu s

1=BLTs on VMEbus

LAS R/W all 0 PCI Bus Memory Space

0=PCI Bus Memory Space

1=PCI Bus I/O Space

LSI3_C TL Description

Name Type Reset By Reset

State Function

12. Registers

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12.2.21 PCI Target Image 3 Base Ad dress Register (LS I3_BS )

The bas e add res s specifi es the lo west add ress in t he address rang e t hat will b e

decoded.

Table 57: PCI Target Image 3 Base Address Register (LSI3_BS)

Bits Function

31-24 BS

23-16 BS

15-08 Reserved

07-00 Reserved

LSI3_BS Description

Name Type Reset By Reset

State Function

BS[31:16] R/W all 0 Base Address

12. Registers

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12.2.22 PCI Target Image 3 Bou nd Addr ess Register (LSI3 _BD)

The addresses decoded in a slave image are those which are greater than or equal to

the base address and less than the bound register. If the bound address is 0, then the

addresses decoded are those greate r than or equal to the base address.

Table 58: PCI Target Image 3 Bound Address Register (LSI3_BD)

Bits Function

31-24 BD

23-16 BD

15-08 Reserved

07-00 Reserved

LSI3_BD Description

Name Type Reset By Reset

State Function

BD[31:16] R/W all 0 Bound Address

12. Registers

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12.2.23 PCI Target Imag e 3 Tran sl ation Offset (LSI3_TO)

Address bi ts [31 :16] generate d on the VMEbus in r esponse t o an i mage decode are a

two’s complement addition of address bits [31:16] on the PCI Bus and bits [ 31:16]

of the image’s translation offset.

Table 59: PCI Target Image 3 Translation Offset (LSI3_TO)

Bits Function

31-24 TO

23-16 TO

15-08 Reserved

07-00 Reserved

LSI3_TO Description

Name Type Reset By Reset

State Function

TO[31:16] R /W all 0 Transl at i on offset

12. Registers

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12.2.24 Spec ial Cycle Con tro l Reg ister (SCYC_C TL )

The special cycle generator generates an ADOH or RMW cycle for the 32-bit PCI

Bus address which matches the programmed addre ss in SCYC_ADDR, in the

address space specifi ed in the LAS field of the SCYC_CTL regis ter. A

Read -Modi fy-Wri te command is i nitiated b y a read to the specified addr es s.

Address-Only cycles are initiated by either read or write cycles.

Table 60: Special Cycle Control Register (SCYC_CTL)

Bits Function

31-24 Reserved

23-16 Reserved

15-08 Reserved

07-00 Reserved LAS SCYC

SCYC_CTL Desc ript ion

Name Type Reset By Reset

State Function

LAS R/W all 0 PCI Bus Address Space

0=PCI Bus Memory Space

1=PCI Bus I/O Space

For a RM W cycl e only.

SCYC R/W all 0 Special Cycle

00=Disable

01=RMW

10=ADOH

11=Reserved

12. Registers

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12.2.25 Special Cycle PCI Bus Address Register (SC YC_ADDR)

This register designates the special cycle address. This address must appear on the

PCI Bus during the address phase of a transfer for the Specia l Cycle Generator to

perform its function. Whenever the addresses match, the Universe II does not

respond with ACK64_.

Table 61: Special Cycle PCI Bus Address Register (SCYC_ADDR)

Bits Function

31-24 ADDR

23-16 ADDR

15-08 ADDR

07-00 ADDR Reserved

SCYC_ADDR Description

Name Type Reset By Reset

State Function

ADDR

[31:2]

R/W all 0 Address

12. Registers

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12.2.26 Spec ia l Cycle Swap /C omp are E na ble R egister (SCYC_EN)

The bits enabled in this register determine the bits that are involved in the compare

and swap operations for VME RMW cycles.

Table 62: Special Cycle Swap/Compare Enable Register (SCYC_EN)

Bits Function

31-24 EN

23-16 EN

15-08 EN

07-00 EN

SCYC_EN Description

Name Type Reset By Reset

State Function

EN [31: 0] R/W all 0 Bit Enab le

0=Disable

1=Enable

12. Registers

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12.2.27 Spec ial Cycle Comp are Data Register (S CY C_CM P)

The data returned from the read portion of a VM Ebus RM W is compared with the

conten ts of this register. SCYC_EN is used to cont rol whic h bi t s are compared.

Table 63: Special Cycle Compare Data Register (SCYC_CMP)

Bits Function

31-24 CMP

23-16 CMP

15-08 CMP

07-00 CMP

SCYC_CMP Description

Name Type Reset By Reset

State Function

CMP[31:0] R/W a ll 0 The dat a r etu rn ed fro m the VM Ebus is compared

with th e contents of thi s re gi st er.

12. Registers

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12.2.28 Special Cycle Swap Data Register (SCYC_SWP)

If enabled bits matched with the value in the compare register, then the contents of

the swap data r egister is written back to VME. SCYC_EN is used to control whic h

bits are written back to VME.

Table 64: Special Cycle Swap Data Register (SCYC_SWP)

Bits Function

31-24 SWP

23-16 SWP

15-08 SWP

07-00 SWP

SCYC_SWP Description

Name Type Reset By Reset

State Function

SWP[31: 0] R/W all 0 Swap da ta

12. Registers

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12.2.29 PCI Mis cel laneous Register (LM I SC)

This register can only be set at configuration or afte r disabling all PC I Target

Images.

The Universe II uses CWT to determine how long to hold ownership of the

VMEbus after processi ng a coupled transaction. The ti mer is restarted each time the

Universe II processes a coupled transaction. If this timer expires, the PCI Slave

Channel releases the VMEbus.

Table 65: PCI Miscellaneous Register (LMISC)

Bits Function

31-24 CRT[3:0] Reserved CWT

23-16 Reserved

15-08 Reserved

07-00 Reserved

SLSI Description

Name Type Reset By Reset

State Function

CRT[3:0] R/W all 000 CRT

This field is provided for backward compatibility with

the Un iv ers e I. It has no effect on th e operation of

the Un iv ers e II.

CWT [2:0] R/W all 000 Coupled Window Timer

000=Disable - release after first coupled transaction

001=16 PCI Clocks

010=32 PCI Clocks

011=64 PCI Clocks

100= 12 8 PC I Clocks

101= 25 6 PC I Clocks

110=512 PCI Cloc ks

others= Reserved

Device behavior is unpredictable if C WT is changed during coupled

cy cle activity.

12. Registers

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12.2.30 Spec ia l PCI Target Image (SLS I)

This r egister fu l ly s pecifie s an A32 capable special PCI Target Image . The base is

programmable to a 64 Mbyte alignment, and the size is fixed at 64 Mbytes.

Incoming address lines [31:26] (in Mem ory or I/O) must match this field for the

Universe II to decode the access. This special PCI Target Im age has lower priority

than any other PCI Target Image.

Table 66: Special PCI Target Image (SLSI)

Bits Function

31-24 EN PWEN Reserved

23-16 VDW Reserved

15-08 PGM SUPER

07-00 BS Reserved LAS

SLSI Description

Name Type Reset By Reset

State Function

EN R/W all 0 Image Enable

0=Disable

1=Enable

PWEN R/W all 0 Posted Write Enable

0=Disable

1=Enable

VDW [3:0] R/W all 0 VMEbus Maximum Data width

Each of the fo ur bit s specifies a dat a w idt h fo r the

corresponding 16 MByte region. Low order bits

correspond to the lower addre ss r egi ons.

0=16-bit

1=32-bit

PGM [3:0] R/W all 0 Program/Data AM Code

Each of the fo ur bit s spe cif ie s Pro gr am /Da ta AM

code for the corresponding 16 MByte region. Low

orde r bit s cor re spond to the lo w er addr ess regions.

0=Data

1=Program

12. Registers

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This r egister fu l ly s pecifie s an A32 capable special PCI Target Image . The base is

programmable to a 64 Mbyte alignment, and the size is fixed at 64 Mbytes.

Incoming address lines [31:26] (in Mem ory or I/O) must match this field for the

Universe II t o decode the access. This speci al PCI Target Image has lower priority

than any other PCI Target Image.

The 64 Mbytes of the SLSI is partitione d into four 16 Mbyte re gions, numbered 0 to

3 ( 0 is at the l owest addres s). PCI addr ess bits [25:24] are us ed to select regions. The

top 64 Kbyte of each region is mapped to VMEbus A16 space, and the rest of each

16 Mbyte region is mapped to A24 space.

The user can use the PGM, SUPER and VDW fie lds to specif y the AM code and the

maximum port size for each region. The PGM field is ignored for the portion of

each region mapped to A16 space.

No block transfer AM codes are generated.

SUPER [3:0] R/W a ll 0 Su per visor/User AM Code

Each of the fo ur bit s spe cif ie s Supervisor /Us er AM

code for the corresponding 16 MByte region. Low

orde r bit s cor re spond to the lo w er addr ess regions.

0=Non-Privileged

1=Supervisor

BS [5:0] R /W all 0 Base Address

Specif ie s a 64 M B yte al i gned base address f or this

64 MByte image.

LAS R/W all 0 PCI Bus Address Space

0=PCI Bus Memory Space

1=PCI Bus I/O Space

SLSI Description

Name Type Reset By Reset

State Function

12. Registers

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12.2.31 PCI Comman d E rro r Log Register (L_CMDERR)

The Universe II PCI Master Interface is responsible for logging errors under the

following conditions:

• a posted write transaction results in a target abort,

• a posted write transaction results in a master abort, or

• a maximum retry counter expires during retr y of posted write transaction.

This registe r logs the command information.

Table 67: PCI Command Error Log Register (L_CMDERR)

Bits Function

31-24 CMDERR M_ERR Reserved

23-16 L_STAT Reserved

15-08 Reserved

07-00 Reserved

L_CMDERR Description

Name Type Reset By Reset

State Function

CMDERR

[3:0] R all 0111 PCI Command Error Log

M_ERR R all 0 Mu ltiple Error Occu rred

0=S in gle er ror, 1= At leas t on e er ror has occurr ed

since t he l ogs we re frozen.

L_STAT R/W all 0 PCI Error Log Sta tus

Reads:

0=logs invalid

1=logs are vali d and error log ging halted

Writes:

0=no effect

1=c lear s L_STAT and enables er ro r logging

12. Registers

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12.2.32 PCI Address Erro r Log (LAE RR)

The star ting address of an err ored PCI transa ction is logged in t his registe r under the

following conditions:

• a posted write transaction results in a target abort,

• a posted write transaction results in a master abort, or

• a maximum retry counter expires during retr y of posted write transaction.

Contents are qualified by bit L_STAT of the L_CMD ERR register.

Table 68: PCI Address Error Log (LAERR)

Bits Function

31-24 LAERR

23-16 LAERR

15-08 LAERR

07-00 LAERR Reserved

LAERR Description

Name Type Reset By Reset

State Function

LAERR

[31:2] R all 0 P CI Address Error Log

12. Registers

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12.2.33 PCI Target Imag e 4 Con trol Regi ster (LSI4_ CTL )

Table 69: PCI Target Image 4 Control Register (LSI4_CTL)

Bits Function

31-24 EN PWEN Reserved

23-16 VDW Reserved VAS

15-08 Reserved PGM Reserved SUPER Reserved VCT

07-00 Reserved LAS

LSI4_C TL Description

Name Type Reset By Reset

State Function

EN R/W all 0 Image Enable

0=Disable

1=Enable

PWEN R/W all 0 Posted Write Enable

0=Disable

1=Enable

VDW R/W a ll 10 VMEbus Maximum Datawidth

00= 8-b i t data wi dt h

01= 16 bit dat a w idth

10= 32- bi t data width

11=64-bit data width

VAS R /W all 0 VMEbus Ad dre ss Space

000=A16

001=A24

010=A32

011= Rese rv ed

100=Reserved

101=CR/CSR

110=User1

111=User2

12. Registers

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244 80A3010_MA001_03

In the PCI Tar get Image Control regist er , sett ing the VCT bit will only have ef fect if

the VAS bits are programmed for A24 or A32 space and the VDW bits are

programmed for 8- bit, 16-bit, or 32-bit.

If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for

64-bit, the Universe II may pe rform MBLT transfers independent of the state of the

VCT bit.

The setting of the PWEN bit is ignored if the LAS bit is progr amme d for PCI Bus

I/O Space, forcing all transactions through this image to be coupled.

PGM R/W a ll 0 Pr og ram/Data AM Code

0=Data

1=Program

SUPER R/W all 0 Su per visor/User AM Code

0=Non-Privileged

1=Supervisor

VCT R/W a ll 0 VM Eb us Cy cle Type

0=no BLTs on VMEbu s

1=BLTs on VMEbus

LAS R/W all 0 PCI Bus Memory Space

0=PCI Bus Memory Space

1=PCI Bus I/O Space

LSI4_C TL Description

Name Type Reset By Reset

State Function

12. Registers

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12.2.34 PCI Target Image 4 Base Ad dress Register (LS I4_BS )

The bas e address speci fies the l owest ad dress in t he address rang e t hat will b e

decoded.

The bas e address speci fies the l owest ad dress in t he address rang e t hat will b e

decoded.

Table 70: PCI Target Image 4 Base Address Register (LSI4_BS)

Bits Function

31-24 BS

23-16 BS

15-08 BS Reserved

07-00 Reserved

LSI4_BS Description

Name Type Reset By Reset

State Function

BS[3 1:12] R/W all 0 Base Add re ss

12. Registers

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12.2.35 PCI Target Image 4 Bou nd Addr ess Register (LSI4 _BD)

The addresses decoded in a slave image are those which are greater than or equal to

the base address and less than the bound register. If the bound address is 0, then the

addresses de coded are those greater than or equal to the base address.

The bound address for PCI Target Im age 0 and PCI Targe t Image 4 have a 4Kbyte

resolution. PCI Target Images 1, 2, 3, 5, 6, and 7 have a 64Kbyte resolution.

Table 71: PCI Target Image 4 Bound Address Register (LSI4_BD)

Bits Function

31-24 BD

23-16 BD

15-08 BD Reserved

07-00 Reserved

LSI4_BD Description

Name Type Reset By Reset

State Function

BD[31:12] R/W all 0 Bound Address

12. Registers

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12.2.36 PCI Target Imag e 4 Translation Offse t (LSI4_TO)

Address bi ts [31 :12] generate d on the VMEbus in r esponse t o an i mage decode ar e a

two’s complement addition of address bits [31:12] on the PCI Bus and bits [ 31:12]

of the image’s translation offset.

Table 72: PCI Target Image 4 Translation Offset (LSI4_TO)

Bits Function

31-24 TO

23-16 TO

15-08 TO Reserved

07-00 Reserved

LSI4_TO Description

Name Type Reset By Reset

State Function

TO[31:12] R/W all 0 T ranslation offset

12. Registers

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12.2.37 PCI Target Imag e 5 Con trol Regi ster (LSI5_ CTL )

Table 73: PCI Target Image 5 Control Register (LSI5_CTL)

Bits Function

31-24 EN PWEN Reserved

23-16 VDW Reserved VAS

15-08 Reserved PGM Reserved SUPER Reserved VCT

07-00 Reserved LAS

LSI5_C TL Description

Name Type Reset By Reset

State Function

EN R/W all 0 Image Enable

0=Disabl

1=Enable

PWEN R/W all 0 Posted Write Enable

0=Disable

1=Enable

VDW R/W a ll 10 VMEbus Maximum Datawidth

00= 8-b i t data wi dt h

01= 16 bit dat a w idth

10= 32- bi t data width

11=64-bit data width

VAS R /W all 0 VMEbus Ad dre ss Space

000=A16

001=A24

010=A32

011= Rese rv ed

100=Reserved

101=CR/CSR

110=User1

111=User2

12. Registers

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In the PCI Tar get Image Control regist er , sett ing the VCT bit will only have ef fect if

the VAS bits are programmed for A24 or A32 space and the VDW bits are

programmed for 8- bit, 16-bit, or 32-bit.

If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for

64-bit, the Universe II may pe rform MBLT transfers independent of the state of the

VCT bit.

The setting of the PWEN bit is ignored if the LAS bit is progr amme d for PCI Bus

I/O Space, forcing all transactions through this image to be coupled.

PGM R/W a ll 0 Pr og ram/Data AM Code

0=Data

1=Program

SUPER R/W all 0 Su per visor/User AM Code

0=Non-Privileged

1=Supervisor

VCT R/W a ll 0 VM Eb us Cy cle Type

0=no BLTs on VMEbu s

1=BLTs on VMEbus

LAS R/W all 0 PCI Bus Memory Space

0=PCI Bus Memory Space

1=PCI Bus I/O Space

LSI5_C TL Description

Name Type Reset By Reset

State Function

12. Registers

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12.2.38 PCI Target Image 5 Base Ad dress Register (LS I5_BS )

The bas e add res s specifi es the lo west add ress in t he address rang e t hat will b e

decoded.

Table 74: PCI Target Image 5 Base Address Register (LSI5_BS)

Bits Function

31-24 BS

23-16 BS

15-08 Reserved

07-00 Reserved

LSI5_BS Description

Name Type Reset By Reset

State Function

BS[31:1 6] R/ W all 0 Base Addres s

12. Registers

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12.2.39 PCI Target Image 5 Bou nd Addr ess Register (LSI5 _BD)

The addres ses decoded in a slave image are those which are g reater than or

equal to the base address and less than the bound register. If the bound address

is 0, then the addresses decoded are those greater than or equal to the base

address.

The bound address for PCI Target Im age 0 and PCI Targe t Image 4 have a 4Kbyte

resolution. PCI Target Images 1, 2, 3, 5, 6, and 7 have a 64Kbyte resolution.

Table 75: PCI Target Image 5 Bound Address Register (LSI5_BD)

Bits Function

31-24 BD

23-16 BD

15-08 Reserved

07-00 Reserved

LSI5_BD Description

Name Type Reset By Reset

State Function

BD[31:16] R/W all 0 Bound Address

12. Registers

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12.2.40 PCI Target Imag e 5 Translation Offse t (LSI5_TO)

Address bi ts [31 :16] generate d on the VMEbus in r esponse t o an i mage decode are a

two’s complement addition of address bits [31:16] on the PCI Bus and bits [ 31:16]

of the i mage’s tran slation offset.

Table 76: PCI Target Image 5 Translation Offset (LSI5_TO)

Bits Function

31-24 TO

23-16 TO

15-08 Reserved

07-00 Reserved

LSI5_TO Description

Name Type Reset By Reset

State Function

TO[31:16] R /W all 0 Transl at i on offset

12. Registers

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12.2.41 PCI Target Imag e 6 Con trol Regi ster (LSI6_ CTL )

Table 77: PCI Target Image 6 Control Register (LSI6_CTL)

Bits Function

31-24 EN PWEN Reserved

23-16 VDW Reserved VAS

15-08 Reserved PGM Reserved SUPER Reserved VCT

07-00 Reserved LAS

LSI6_C TL Description

Name Type Reset By Reset

State Function

EN R/W all 0 Image Enable

0=Disable

1=Enable

PWEN R/W all 0 Posted Write Enable

0=Disable

1=Enable

VDW R/W a ll 10 VMEbus Maximum Datawidth

00= 8-b i t data wi dt h

01= 16 bit dat a w idth

10= 32- bi t data width

11=64-bit data width

VAS R /W all 0 VMEbus Ad dre ss Space

000=A16

001=A24

010=A32

011= Rese rv ed

100=Reserved

101=CR/CSR

110=User1

111=User2

12. Registers

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254 80A3010_MA001_03

In the PCI Tar get Image Control regist er , sett ing the VCT bit will only have ef fect if

the VAS bits are programmed for A24 or A32 space and the VDW bits are

programmed for 8- bit, 16-bit, or 32-bit.

If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for

64-bit, the Universe II may pe rform MBLT transfers independent of the state of the

VCT bit.

The setting of the PWEN bit is ignored if the LAS bit is progr amme d for PCI Bus

I/O Space, forcing all transactions through this image to be coupled.

PGM R/W a ll 0 Pr og ram/Data AM Code

0=Data

1=Program

SUPER R/W all 0 Su per visor/User AM Code

0=Non-Privileged

1=Supervisor

VCT R/W a ll 0 VM Eb us Cy cle Type

0=no BLTs on VMEbu s

1=BLTs on VMEbus

LAS R/W all 0 PCI Bus Memory Space

0=PCI Bus Memory Space

1=PCI Bus I/O Space

LSI6_C TL Description

Name Type Reset By Reset

State Function

12. Registers

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12.2.42 PCI Target Image 6 Base Ad dress Register (LS I6_BS )

The bas e address speci fies the l owest ad dress in t he address rang e t hat will b e

decoded.

Table 78: PCI Target Image 6 Base Address Register (LSI6_BS)

Bits Function

31-24 BS

23-16 BS

15-08 Reserved

07-00 Reserved

LSI1_BS Description

Name Type Reset By Reset

State Function

BS[3 1:16] R/W all 0 Base Add re ss

12. Registers

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12.2.43 PCI Target Image 6 Bou nd Addr ess Register (LSI6 _BD)

The addresses decoded in a slave image are those which are greater than or equal to

the base address and less than the bound register. If the bound address is 0, then the

addresses decoded are those greate r than or equal to the base address.

The bound address for PCI Target Im age 0 and PCI Targe t Image 4 have a 4Kbyte

resolution. PCI Target Images 1, 2, 3, 5, 6, and 7 have a 64Kbyte resolution.

Table 79: PCI Target Image 6 Bound Address Register (LSI6_BD)

Bits Function

31-24 BD

23-16 BD

15-08 Reserved

07-00 Reserved

LSI6_BD Description

Name Type Reset By Reset

State Function

BD[31:16] R/W all 0 Bound Address

12. Registers

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12.2.44 PCI Target Imag e 6 Translation Offse t (LSI6_TO)

Address bi ts [31 :16] generate d on the VMEbus in r esponse t o an i mage decode ar e a

two’s complement addition of address bits [31:16] on the PCI Bus and bits [ 31:16]

of the i mage’s tran slation offset.

Table 80: PCI Target Image 6 Translation Offset (LSI6_TO)

Bits Function

31-24 TO

23-16 TO

15-08 Reserved

07-00 Reserved

LSI6_TO Description

Name Type Reset By Reset

State Function

TO[31:16] R /W all 0 Transl at ion offset

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12.2.45 PCI Target Imag e 7 Con trol Regi ster (LSI7_ CTL )

Table 81: PCI Target Image 7 Control Register (LSI7_CTL)

Bits Function

31-24 EN PWEN Reserved

23-16 VDW Reserved VAS

15-08 Reserved PGM Reserved SUPER Reserved VCT

07-00 Reserved LAS

LSI7_C TL Description

Name Type Reset By Reset

State Function

EN R/W all 0 Image Enable

0=Disable

1=Enable

PWEN R/W all 0 Posted Write Enable

0=Disable

1=Enable

VDW R/W a ll 10 VMEbus Maximum Datawidth

00= 8-b i t data wi dt h

01= 16 bit dat a w idth

10= 32- bi t data width

11=64-bit data width

VAS R /W all 0 VMEbus Ad dre ss Space

000= A16 , 00 1= A24, 010=A32, 011= Re ser ved,

100= Reserved, 101=C R /CS R , 110=U se r1 ,

111=User2

PGM R/W a ll 0 Pr og ram/Data AM Code

0=Data

1=Program

SUPER R/W all 0 Su per visor/User AM Code

0=Non-Privileged

1=Supervisor

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In the PCI Tar get Image Control regist er , sett ing the VCT bit will only have ef fect if

the VAS bits are programmed for A24 or A32 space and the VDW bits are

programmed for 8- bit, 16-bit, or 32-bit.

If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for

64-bit, the Universe II may pe rform MBLT transfers independent of the state of the

VCT bit.

The setting of the PWEN bit is ignored if the LAS bit is progr amme d for PCI Bus

I/O Space, forcing all transactions through this image to be coupled.

VCT R/W a ll 0 VM Eb us Cy cle Type

0=no BLTs on VMEbu s

1=BLTs on VMEbus

LAS R/W all 0 PCI Bus Memory Space

0=PCI Bus Memory Space

1=PCI Bus I/O Space

LSI7_C TL Description

Name Type Reset By Reset

State Function

12. Registers

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12.2.46 PCI Target Image 7 Base Ad dress Register (LS I7_BS )

The base address specifies the lowest address in the addre ss range that is decoded.

Table 82: PCI Target Image 7 Base Address Register (LSI7_BS)

Bits Function

31-24 BS

23-16 BS

15-08 Reserved

07-00 Reserved

LSI7_BS Description

Name Type Reset By Reset

State Function

BS[31:16] R/W all 0 Base Address

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12.2.47 PCI Target Image 7 Bou nd Addr ess Register (LSI7 _BD)

The addresses decoded in a slave image are those which are greater than or equal to

the base address and less than the bound register. If the bound address is 0, then the

addresses de coded are those greater than or equal to the base address.

The bound address for PCI Target Im age 0 and PCI Targe t Image 4 have a 4Kbyte

resolution. PCI Target Images 1, 2, 3, 5, 6, and 7 have a 64Kbyte resolution.

Table 83: PCI Target Image 7 Bound Address Register (LSI7_BD)

Bits Function

31-24 BD

23-16 BD

15-08 Reserved

07-00 Reserved

LSI7_BD Description

Name Type Reset By Reset

State Function

BD[31:16] R/W all 0 Bound Address

12. Registers

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12.2.48 PCI Target Imag e 7 Translation Offse t (LSI7_TO)

Address bi ts [31 :16] generate d on the VMEbus in r esponse t o an i mage decode are a

two’s complement addition of address bits [31:16] on the PCI Bus and bits [ 31:16]

of the i mage’s tran slation offset.

Table 84: PCI Target Image 7 Translation Offset (LSI7_TO)

Bits Function

31-24 TO

23-16 TO

15-08 Reserved

07-00 Reserved

LSI7_TO Description

Name Type Reset By Reset

State Function

TO[31:16] R /W all 0 Transl at i on offset

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12.2.49 DMA Transfer Control Regis ter (DCTL )

This regist er is pr ogrammed from eithe r bus or is progr ammed by the DMAC when

it loads the com mand packet.

The D MA only accesses PCI Bus Memory space.

Table 85: DMA Transfer Control Register (DCTL)

Bits Function

31-24 L2V Reserved

23-16 VDW Reserved VAS

15-08 PGM SUPER Reserved NO_

VINC

VCT

07-00 LD64EN Reserved

DCTL Description

Name Type Reset By Reset

State Function

L2V R/W all 0 Direction

0=Transfer from VMEbus to PCI Bus

1=Transfer from PCI Bus to VMEbus

VDW R/W all 0 VMEbus Maximum Datawidth

00= 8-b i t data wi dt h

01= 16 bit dat a w idth

10= 32- bi t data width

11=64-bit data width

VA S R/W all 0 VMEbus Ad dre ss Space

000=A16

001=A24

010=A32

011= Rese rv ed

100=Reserved

101=Reserved

110=User1

111=User2

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The VCT bit determines whether or not the Universe II VME Master will generate

BLT transfers. The value of this bit only has meaning if the address space is A24 or

A32 and the data width is not 64 bits. If the data width i s 64 bits the Universe II may

perform MBLT transfers independent of the sta te of the VCT bit.

PGM R/W all 0 Pr og ram/Data AM Code

00=Data

01=Program

othe rs = Re ser ved

SUPER R/W a ll 0 Supervisor/User AM Code

00=Non-Privileged

01=Supervisor

othe rs = Re ser ved

NO_VINC R/W all 0 VMEbus Non-Incrementing Mode (Non-Inc Mode)

0=disabled

1=enabled

VCT R/W all 0 VMEb us Cy cle Type

0=no BLTs on VMEbu s

1=BLTs on VMEbus

LD64EN R/W all 1 En able 64-bit PCI Bus Transactio ns

0=Disable

1=Enable

DCTL Description

Name Type Reset By Reset

State Function

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12.2.50 DMA Transfer Byte Count Register (DTBC)

This regist er specif ies the number of bytes to be moved by the DMA before the star t

of the DMA transfe r, or the number of remaining bytes in the transfer w hile the

DMA is active. This register is progra mm ed from either bus or is programmed by

the DMA Controller when it loads a command packet from a linked-list.

In direct m ode the user must reprogram the DTBC registe r before each transfer.

When using the DMA to perform linked-list transfers, it is essential that the DTBC

undefined behaviors may occur.

Table 86: DMA Transfer Byte Count Register (DTBC)

Bits Function

31-24 Reserved

23-16 DTBC

15-08 DTBC

07-00 DTBC

DTBC Description

Name Type Reset By Reset

State Function

DTBC

[23:0]

R/W a ll 0 DMA Transfer Byte Count

12. Registers

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12.2.51 DMA PCI Bus Addr ess Reg iste r (DLA)

This registe r is programmed from either bus or by the DMA Controller when it

loads a command packet. In direct mode th e user must reprogram the DLA register

before each transfer. In linked-list mode, this register is only updated when the

DMA is stopped, halted, or at the completion of processing a command packet.

After a Bus Err or, a Target-A bort, or a Master-Abort, the value in the DLA register

must not be used to reprogram the DMA because it has no usable infor mation. Some

offset from its original value must be used.

Address bits [2:0] must be programmed the same as those in the DVA.

Table 87: DMA PCI Bus Address Register (DLA)

Bits Function

31-24 LA

23-16 LA

15-08 LA

07-00 LA

DLA Descriptio n

Name Type Reset By Reset

State Function

LA[31:3 ] R/W a ll 0 PCI Bus Addr ess

LA[2:0] R/W all 0 PCI Bus Address

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12.2.52 DMA VME bu s Add res s R egister (DVA)

This registe r is programmed from eithe r bus or is programmed by the DMA

Controlle r when it loads a command packet. I n direct m ode the us er must reprogram

the DVA register before each transfer. In linked-list operation, this register is only

updated when the DM A is stopped, halted, or at the completion of processing a

command packet.

After a bus e rror, a Target-A bort, or a Master-Abort, the value in the DVA register

must not be used to reprogram the DMA because it has no usable infor mation. Some

offset from its original value must be used.

Address bits [2:0] must be programmed the same as those in the DLA.

Table 88: DMA VMEbus Address Register (DVA)

Bits Function

31-24 VA

23-16 VA

15-08 VA

07-00 VA

DVA Description

Name Type Reset By Reset

State Function

VA[31:0] R/W all 0 VMEbus Address

12. Registers

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12.2.53 DMA Command Packet Pointer (DCPP)

This registe r contains the pointer into the current c ommand packet. Initially it is

programmed to the st arting packet of the l inke d-list, and is updated wit h the address

to a new command p acket at the comp letion of a pack et.

The packets must be aligned to a 32-byte address.

Table 89: DMA Command Packet Pointer (DCPP)

Bits Function

31-24 DCPP

23-16 DCPP

15-08 DCPP

07-00 DCPP Reserved

DCPP Description

Name Type Reset By Reset

State Function

DCPP

[31:5] R/W all 0 DMA Command Packe t Pointer

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12.2.54 DMA Gen eral Con trol /Sta tus Reg ister (DGCS )

Table 90: DMA General Control/Status Register (DGCS)

Bits Function

31-24 GO STOP_

REQ

HALT_

REQ

0 CHAIN 0 0 0

23-16 Reserved VON VOFF

15-08 ACT STOP HALT 0 DONE LERR VERR P_ERR

07-00 0 INT_

STOP

INT_

HALT

0INT_

DONE

INT_

LERR

INT_

VERR

INT_

P_ERR

DGCS Descriptio n

Name Type Reset By Reset

State Function

GO W/Read 0

always all 0 DMA Go Bit

0=No effect

1=Enable DMA Transfers

STOP_

REQ

W/Read 0

always all 0 D M A Stop R equ est

0=No effect

1=Stop DM A transfer wh en al l buffered dat a has

been writ te n

HALT_

REQ W/Read 0

always all 0 DMA Halt Req uest

0=No effect

1=Halt the DMA transfer at the co mpletion of the

current command packet

CHAIN R/W all 0 DMA Chaining

0=DMA Direct Mode

1=DM A Linked List mo de

12. Registers

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VON [2:0] R/W all 0 VMEbus “On” counter

000=Un til done

001=2 56 by te s

010=5 12 by te s

011=1024 bytes

100=2048 bytes

101=4096 bytes

110=8192 bytes

111=163 84 bytes

others= R eserved

VOFF [3:0] R/W all 0 VMEbus “Off” Counter

0000=0µs

0001=16µs

0010=32µs

0011=64µs

0100=128µs

0101=256µs

0110=512µs

0111=1024µs

1000=2µs

1001=4µs

1010=8µs

others= R eserved

ACT R all 0 DMA Active Status Bit

0=Not Acti ve

1=Active

STOP R/Wr ite 1

to Cle ar all 0 DMA Stopped Statu s Bit

0=Not Stopped

1=Stopped

HALT R/Writ e 1

to Cle ar all 0 DMA Halted Status Bit

0=Not Halted

1=Halted

DGCS Descriptio n

Name Type Reset By Reset

State Function

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DONE R/Wr ite 1

to Cle ar all 0 DMA Done Status Bit

0=Not Complete

1=Complete

LERR R/Writ e 1

to Cle ar all 0 DMA PCI Bus Error Status Bit

0=No Error

1=Error

VERR R/Write 1

to Cle ar all 0 DMA VMEbus Error Status Bit

0=No Error

1=Error

P_ERR R/Write 1

to Cle ar all 0 DMA Programming Protocol Error Status Bit

Asserted if P CI master interface disab le d or lowe r

three bits of PCI and VME address es di ffer

0=No Error

1=Error

INT_ STOP R/ W all 0 Inte rrupt w hen S topped

0=Disable

1=Enable

INT_HALT R/W all 0 Interrupt when Halted

0=Disable

1=Enable

INT_

DONE

R/W all 0 Inte rr upt w hen Done

0=Disable

1=Enable

INT_ LER R R/W al l 0 Interr upt on LERR

0=Disable

1=Enable

INT_ VERR R /W all 0 Interrupt on VER R

0=Disable

1=Enable

INT_P_

ERR

R/W all 0 Interrupt on Master Enable Error

0=Disable

1=Enable

DGCS Descriptio n

Name Type Reset By Reset

State Function

12. Registers

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ST OP, HALT , DONE, LERR, VERR, and P_ERR must be cleared before the GO bit

is enabled.

12. Registers

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12.2.55 DMA Li nked List Update Enable Register (D_LL UE )

The PCI Resour ce must r ead bac k a l ogic 1 in the UPDATE fiel d before pr oceeding

to modify the linked list. Af ter the Linke d List has been modifie d the PCI Resourc e

must cle ar t he UPDATE field by wri ting a l ogic 0. The Unive rse I I does not pre ve nt

an external master, from the PCI bus or the VMEbus, from writing to the other

DMA registers (see “Linked-list Updating” on page 120).

Table 91: DMA Linked List Update Enable Register (D_LLUE)

Bits Function

31-24 UPDATE Reserved

23-16 Reserved

15-08 Reserved

07-00 Reserved

D_LLUE Description

Name Type Reset By Reset

State Function

UPDATE R/W all 0 DM A Linked List Up dat e Enable

0=PCI Resource not Updating Linked List

1=PCI R esource U pd at in g Li nke d Li st

12. Registers

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12.2.56 PCI Inter rup t Enabl e Reg ister (LIN T_EN )

Table 92: PCI Interrupt Enable Register (LINT_EN)

Bits Function

31-24 Reserved

23-16 LM3 LM2 LM1 LM0 MBOX3 MBOX2 MBOX1 MBOX0

15-08 ACFAIL SYSFAIL SW_INT SW_

IACK

Reserved VERR LERR DMA

07-00 VIRQ7 VIRQ6 VIRQ5 VIRQ4 VIRQ3 VIRQ2 VIRQ1 VOWN

LINT_EN Description

Name Type Reset By Reset

State Function

LM3 R/W all 0 Location Monitor 3

0=L M 3 In te rrupt Di sabled

1=LM3 Interrupt Enabled

LM2 R/W all 0 Location Monitor 2

0=L M 2 In te rrupt Di sabled

1=LM2 Interrupt Enabled

LM1 R/W all 0 Location Monitor 1

0=L M 1 In te rrupt Di sabled

1=LM1 Interrupt Enabled

LM0 R/W all 0 Location Monitor 0

0=L M 0 In te rrupt Di sabled

1=LM0 Interrupt Enabled

MBOX 3 R/W al l 0 Mailbox 3

0=MBOX3 In te rrupt D isabled

1=MBOX3 In terr upt Enabled

MBOX 2 R/W al l 0 Mailbox 2

0=MBOX2 In te rrupt D isabled

1=MBOX2 In terr upt Enabled

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MBOX 1 R/W al l 0 Mailbox 1

0=MBOX1 In te rrupt D isabled

1=MBOX1 In terr upt Enabled

MBOX0 R/W all 0 Ma ilbox 0

0=MBOX0 In te rrupt D isabled

1=MBOX0 In terr upt Enabled

ACFAIL R/W all 0 ACFAIL In terrupt

0=ACFAIL Interrupt Disab led

1=ACFAIL Interrupt Enabled

SYSFAIL R/W all 0 S YSFAIL Interrupt

0=SYSFAIL Interrupt Disabled

1=SYSFAIL Interru pt Enabled

SW_INT R/W all 0 Local Software In terrupt

0 =PCI Soft war e Interrupt D i s a bled

1 =PC I So ftwa re Interr u p t En abled

A zero-to-one tr ansiti on will cause the PCI software

inter ru pt to be asserted . Subs equ ent zer oi ng of

this bit will c ause the interr upt to be masked, but will

not clear the PCI Software Interru p t Status bit .

SW_IAC K R/W all 0 “VME Soft war e IACK”

0 =“VM E Softw are IACK” Inte rrupt Disabl ed

1 =“VME Software IACK” Interrupt Enabled

VERR R/W all 0 PCI VERR Interrupt

0 =PCI VERR Inte rrupt Disable d

1=PCI VERR Interr upt Enabl ed

LERR R/W all 0 PCI LERR Interru pt

0 =PCI LERR Interrupt Disabled

1 =PCI LER R I nt er rupt En abl ed

DMA R/W all 0 P CI DMA Interr u p t

0=PCI DMA Interrupt Disabled

1=PCI DMA Interrupt Enabled

LINT_EN Description

Name Type Reset By Reset

State Function

12. Registers

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Bits VIRQ7-VIRQ1 enable the Universe II to respond as a VME Interrupt Handler

to interrupts on the VIRQ[x] lines. When a VIRQ x interrupt is enabled, and the

corresponding VIRQ[x] pin is asserted, the Universe II reque sts the VMEbus and

performs a VME IACK cycle for that interrupt level. When the interrupt

acknowledge cycle co mpletes, the STATUS/ID is store d in the corresponding

VINT_ID registe r, the VIRQx bit of the LINT_STAT register is set, and a PCI

interrupt is generated. The Universe II does not acquire further interrupt

STATUS/ID vectors at the same interrupt level until the VIRQx bit in the

LINT_STAT register is cleared.

The other bits enable the respective inter n al or external sources to interrupt the PCI

side.

VIRQ7-VIRQ

1R/W all 0 VIRQx Interrupt

0=VIRQx Interrupt Disabled

1 =VI RQx Interrupt Enabl ed

VOWN R/W all 0 VOWN Interrupt

0=VOWN Interrupt Dis abled

1=VOWN Interrupt Enable d

LINT_EN Description

Name Type Reset By Reset

State Function

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12.2.57 PCI Interrupt Status Register (LINT_STAT)

Status bits indicated as “R/Write 1 to Clear” are edge sensitive: the status is latched

when the inte rrupt event occurs. These status bits can be cleared inde pendently of

the sta te of the interrup t source b y writi ng a “1” to the st atus regi ster. C learing t he

status bit does not imply the source of the interrupt is cleared. However, ACFAIL

and SYSFAIL a re level-sensitive. Clearing ACFAIL or SYSFAIL while their

respective pins are still asserted will have no effect.

Table 93: PCI Interrupt Status Register (LINT_STAT)

Bits Function

31-24 Reserved

23-16 LM3 LM2 LM1 LM0 MBOX3 MBOX2 MBOX1 MBOX0

15-08 ACFAIL SYSFAIL SW_INT SW_

IACK Reserved VERR LERR DMA

07-00 VIRQ7 VIRQ6 VIRQ5 VIRQ4 VIRQ3 VIRQ2 VIRQ1 VOWN

LINT_STAT Description

Name Type Reset By Reset

State Function

LM3 R/Write

1 to

Clear

all 0 Location Monito r 3 Stat us/ Cl ear

0=n o Loc at io n M oni t or 3 Inter ru pt,

1=L ocation Mo ni to r 3 Int err upt active

LM2 R/Write

1 to

Clear

all 0 Location Monito r 2 Stat us/ Cl ear

0=n o Loc at io n M oni t or 2 Inter ru pt,

1=L ocation Mo ni to r 2 Int err upt active

LM1 R/Write

1 to

Clear

all 0 Location Monito r 1 Stat us/ Cl ear

0=n o Loc at io n M oni t or 1 Inter ru pt,

1=L ocation Mo ni to r 1 Int err upt active

LM0 R/Write

1 to

Clear

all 0 Location Monito r 0 Stat us/ Cl ear

0=n o Loc at io n M oni t or 0 Inter ru pt,

1=L ocation Mo ni to r 0 Int err upt active

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MBOX3 R/Write

1 to

Clear

all 0 M ailbox 3 Sta tus/ C lear

0=no Mailbox 3 Interrupt,

1=Mailbox 3 In te rr upt act ive

MBOX2 R/Write

1 to

Clear

all 0 M ailbox 2 Sta tus/ C lear

0=no Mailbox 2 Interrupt,

1=Mailbox 2 In te rr upt act ive

MBOX1 R/Write

1 to

Clear

all 0 M ailbox 1 Sta tus/ C lear

0=no Mailbox 1 Interrupt,

1=Mailbox 1 In te rr upt act ive

MBOX0 R/Write

1 to

Clear

all 0 M ailbox 0 Sta tus/ C lear

0=no Mailbox 0 Interrupt,

1=Mailbox 0 In te rr upt act ive

ACFAIL R/Write

1 to

Clear

all 0 ACFAIL In terr upt Stat us/ C lear

0=no ACFA IL Interrupt,

1 =AC FAIL Interr u pt acti v e

SYSFAIL R/Write

1 to

Clear

all 0 SYSFAIL Interrup t Status/Clear

0=no SYSFAIL Interrupt,

1=SYSFAIL Interru pt active

SW_INT R/Write

1 to

Clear

all 0 Local So ftwar e Inte rrupt St at us/C l ear

0=no PCI Software Interrupt,

1 =PC I So ftwa re Interr u p t acti ve

SW_IACK R/Write

1 to

Clear

all 0 “ VM E Soft w ar e IACK” Status/C lear

0=no “VME Software IACK” Interrupt,

1=“VME Software IACK” Interrupt active

VERR R/Write

1 to

Clear

all 0 Local VERR Interrupt Status/ Cle ar

0= Local VERR Interrupt m asked ,

1= Local V ER R Interr upt act ive

LERR R/Write

1 to

Clear

all 0 Local LERR Interr upt St at u s/Cl ear

0=Local LERR Interrupt masked,

1= Local LERR Inter r upt activ e

LINT_STAT Description

Name Type Reset By Reset

State Function

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DMA R/Write

1 to

Clear

all 0 Local DMA I nt errupt Status/Cl ear

0=Local DMA Interrupt masked,

1=Local DMA Interrupt active

VIRQ7-VIRQ

1R/Write

1 to

Clear

all 0 VIRQx Interr up t Stat us/C l ea r

0=VIRQx Interrupt masked,

1=VIRQx Interrup t activ e

VOWN R/Write

1 to

Clear

all 0 VOWN I nt er rup t Stat us /Cl ear

0=no VOWN Interrupt masked,

1=VOWN Interrupt active

LINT_STAT Description

Name Type Reset By Reset

State Function

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12.2.58 PCI Interrupt Map 0 Register (LINT_MAP0)

This register maps various interr upt sources to one of the eight PCI interrupt pins.

For example, a value of 000 maps the corresponding interrupt source to LINT_ [0].

Table 94: PCI Interrupt Map 0 Register (LINT_MAP0)

Bits Function

31-24 Reserved VIRQ7 Reserved VIRQ6

23-16 Reserved VIRQ5 Reserved VIRQ4

15-08 Reserved VIRQ3 Reserved VIRQ2

07-00 Reserved VIRQ1 Reserved VOWN

LINT_MAP0 Description

Name Type Reset By Reset

State Function

VIRQ7-VIRQ

1R/W all 0 PCI interrupt destinat io n (L INT[7: 0] ) for VIRQx

VO WN R / W all 0 VME bus owner sh ip bit inte rr upt m ap to PC I

interrupt

12. Registers

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12.2.59 PCI Interrupt Map 1 Register (LINT_MAP1)

This register maps various interr upt sources to one of the e ight PCI interrupt pins.

For example, a value of 000 maps the corresponding interrupt source to LINT_ [0].

Table 95: PCI Interrupt Map 1 Register (LINT_MAP1)

Bits Function

31-24 Reserved ACFAIL Reserved SYSFAIL

23-16 Reserved SW_INT Reserved SW_IACK

15-08 Reserved VERR

07-00 Reserved LERR Reserved DMA

LINT_MAP1 Description

Name Type Reset By Reset

State Function

ACFAIL R/W all 0 ACFAIL interrupt destination

SYSFAIL R/W all 0 SYSFAIL interrupt destination

SW_INT R/W all 0 P CI software interrupt de stination

SW_IAC K R/W all 0 VMEbus Software IAC K inte rrupt destinatio n

VERR R/W all 0 VMEbus Error interrupt destination

LERR R/W all 0 PCI Bus Error interr upt des tin a tion

DMA R/W all 0 DMA interrupt destina tio n

12. Registers

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12.2.60 VMEbus Interrupt Enable Register (VINT_EN)

This register enables the various sources of VMEbus interrupts.

SW_INT can be enabled with the VME64AUTO power-up option.

Table 96: VMEbus Interrupt Enable Register (VINT_EN)

Bits Function

31-24 SW_

INT7 SW_

INT6 SW_

INT5 SW_

INT4 SW_

INT3 SW_

INT2 SW_

INT1 Reserved

23-16 Reserved MBOX3 MBOX2 MBOX1 MBOX0

15-08 Reserved SW_INT Reserved VERR LERR DMA

07-00 LINT7 LINT6 LINT5 LINT4 LINT3 LINT2 LINT1 LINT0

VINT_EN Description

Name Type Reset By Reset

State Function

SW_IN T7 R/ W all 0 VME Software 7 I nt errup t Mas k

0=VME Software 7 Interru pt masked ,

1=V M E Sof twa re 7 Int er ru pt enabl ed

A zero-to-one transi tion will cause a VME level 7

interrupt to be generated. Subsequent zeroing of

this bit will c ause the interr upt to be masked, but will

not clear the VME So ftware 7 In terrupt Status bit.

SW_IN T6 R/ W all 0 VME Software 6 I nt errup t Mas k

0=VME Software 6 Interru pt masked ,

1=V M E Sof twa re 6 Int er ru pt enabl ed

A zero-to-one transi tion will cause a VME level 6

interrupt to be generated. Subsequent zeroing of

this bit will c ause the interr upt to be masked, but will

not clear the VME So ftware 6 In terrupt Status bit.

SW_IN T5 R/ W all 0 VME Software 5 I nt errup t Mas k

0=VME Software 5 Interru pt masked ,

1=V M E Sof twa re 5 Int er ru pt enabl ed

A zero-to-one transi tion will cause a VME level 5

interrupt to be generated. Subsequent zeroing of

this bit will c ause the interr upt to be masked, but will

not clear the VME So ftware 5 In terrupt Status bit.

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SW_IN T4 R/ W all 0 VME Software 4 I nt errup t Mas k

0=VME Software 4 Interru pt masked ,

1=V M E Sof twa re 4 Int er ru pt enabl ed

A zero-to-one transi tion will cause a VME level 4

interrupt to be generated. Subsequent zeroing of

this bit will c ause the interr upt to be masked, but will

not clear the VME So ftware 4 In terrupt Status bit.

SW_IN T3 R/ W all 0 VME Software 3 I nt errup t Mas k

0=VME Software 3 Interru pt masked ,

1=V M E Sof twa re 3 Int er ru pt enabl ed

A zero-to-one transi tion will cause a VME level 3

interrupt to be generated. Subsequent zeroing of

this bit will c ause the interr upt to be masked, but will

not clear the VME So ftware 3 In terrupt Status bit.

SW_IN T2 R/ W all 0 VME Software 2 I nt errup t Mas k

0=VME Software 2 Interru pt masked ,

1=V M E Sof twa re 2 Int er ru pt enabl ed

A zero-to-one transi tion will cause a VME level 2

interrupt to be generated. Subsequent zeroing of

this bit will c ause the interr upt to be masked, but will

not clear the VME So ftware 2 In terrupt Status bit.

SW_IN T1 R/ W all 0 VME Software 1 I nt errup t Mas k

0=VME Software 1 Interru pt masked ,

1=V M E Sof twa re 1 Int er ru pt enabl ed

A zero-to-one transi tion will cause a VME level 1

interrupt to be generated. Subsequent zeroing of

this bit will c ause the interr upt to be masked, but will

not clear the VME So ftware 1 In terrupt Status bit.

MBO X3 R/W al l 0 Mailbox 3 Mask

0=MBOX3 In te rr upt m ask ed,

1=MBOX3 In te rrupt enabled

MBO X2 R/W al l 0 Mailbox 2 Mask

0=MBOX2 In te rr upt m ask ed,

1=MBOX2 In te rrupt enabled

MBO X1 R/W al l 0 Mailbox 1 Mask

0=MBOX1 In te rr upt m ask ed,

1=MBOX1 In te rrupt enabled

VINT_EN Description

Name Type Reset By Reset

State Function

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MBO X0 R/W al l 0 Mailbox 0 Mask

0=MBOX0 In te rr upt m ask ed,

1=MBOX0 In te rrupt enabled

SW_INT R/W all Power-up

Option “VME Software Interrupt” Mask

0 = VME Software Interru p t mask ed

1 =VME Software In terr up t ena bl ed

A zero -to- one transition cause s the VM E sof t w ar e

interrupt to be asserted. Subsequent zeroing of this

bit causes the inte rrupt to be masked and the

VMEbus interrupt negated, but does not clear the

VME software interr upt st at us bit.

VERR R/ W all 0 VERR Inter r upt Ma sk

0 =PCI VERR Interrupt masked

1=PCI VERR Interrupt enabled

LERR R/W all 0 LERR Inte rrupt Mask

0 =PCI LERR I nter rup t masked

1 =PCI LERR I nt er rup t enabl ed

DMA R/W all 0 DMA Interr upt Mask

0=PCI DMA Interrupt mask ed

1=P C I DMA I nt errup t en abl ed

LINT7-LINT0 R/W all 0 PCI Interrupt Mask

0=LINTx Inte rrupt m asked

1 =L I N Tx Interrupt enabled

VINT_EN Description

Name Type Reset By Reset

State Function

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12.2.61 VMEbus Interrupt Status Register (VINT_STAT)

This register maps PCI Bus interrupt sources to one of the seven VMEbus interr upt

pins. A value of 001 maps the corresponding interrupt source to VI RQ*[1], a value

of 002 maps to VIRQ *[2], etc. A value of 000 effectively ma sks the interrupt since

there is no corresponding VIRQ*[0].

Table 97: VMEbus Interrupt Status Register (VINT_STAT)

Bits Function

31-24 SW_

INT7 SW_

INT6 SW_

INT5 SW_

INT4 SW_

INT3 SW_

INT2 SW_

INT1 Reserved

23-16 Reserved MBOX3 MBOX2 MBOX1 MBOX0

15-08 Reserved SW_INT Reserved VERR LERR DMA

07-00 LINT7 LINT6 LINT5 LINT4 LINT3 LINT2 LINT1 LINT0

VINT_STAT D esc ript io n

Name Type Reset By Reset

State Function

SW_INT7 R/Write

1 to

clear

all 0 VME Software 7 Interrupt Sta tus/ Cle ar

0=no VME Sof tw ar e 7 Inte rrupt ,

1=VME Software 7 Interrupt active

SW_INT6 R/Write

1 to

clear

all 0 VME Software 6 Interrupt Sta tus/ Cle ar

0=no VME Sof tw ar e 6 Inte rrupt ,

1=VME Software 6 Interrupt active

SW_INT5 R/Write

1 to

clear

all 0 VME Software 5 Interrupt Sta tus/ Cle ar

0=no VME Sof tw ar e 5 Inte rrupt ,

1=VME Software 5 Interrupt active

SW_INT4 R/Write

1 to

clear

all 0 VME Software 4 Interrupt Sta tus/ Cle ar

0=no VME Sof tw ar e 4 Inte rrupt ,

1=VME Software 4 Interrupt active

SW_INT3 R/Write

1 to

clear

all 0 VME Software 3 Interrupt Sta tus/ Cle ar

0=no VME Sof tw ar e 3 Inte rrupt ,

1=VME Software 3 Interrupt active

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SW_INT2 R/Write

1 to

clear

all 0 VME Software 2 Interrupt Sta tus/ Cle ar

0=no VME Sof tw ar e 2 Inte rrupt ,

1=VME Software 2 Interrupt active

SW_INT1 R/Write

1 to

clear

all 0 VME Software 1 Interrupt Sta tus/ Cle ar

0=no VME Sof tw ar e 1 Inte rrupt ,

1=VME Software 1 Interrupt active

MBOX3 R/Write

1 to

clear

all 0 Mailbox 3 St atus/ C l ear

0=no Mailbox 3 Interrupt,

1=Mai lb ox 3 I nt errupt active

MBOX2 R/Write

1 to

clear

all 0 Mailbox 2 St atus/ C l ear

0=no Mailbox 2 Interrupt,

1=Mai lb ox 2 I nt errupt active

MBOX1 R/Write

1 to

clear

all 0 Mailbox 1 St atus/ C l ear

0=no Mailbox 1 Interrupt,

1=Mai lb ox 1 I nt errupt active

MBOX0 R/Write

1 to

clear

all 0 Mailbox 0 St atus/ C l ear

0=no Mailbox 0 Interrupt,

1=Mai lb ox 0 I nt errupt active

SW_INT R/Write

1 to

Clear

all Power-up

Option VME Software Interrupt Status/Clear

0=VME Software Interrupt inactive,

1=VME Software Interrupt active

VERR R/Write

1 to

Clear

all 0 VERR Interrupt Stat us/ Cl ear

0=VME VERR Inte rrupt m ask ed,

1=VME VERR Inte rrupt ena bl ed

LERR R/Write

1 to

Clear

all 0 LERR Interrupt Status/Cl ear

0=VME LERR I nterrupt masked,

1=VME LERR I nterrupt enabled

DMA R/Write

1 to

Clear

all 0 DM A I nt errup t Stat us /Clear

0=VME DMA Interrupt masked,

1=VME DMA Interrupt enabled

LINT7-LINT0 R/Write

1 to

Clear

all 0 LINTx Interrupt Status/Clear

0=LINTx Interrupt masked,

1=LINTx Interrup t en abl ed

VINT_STAT D esc ript io n

Name Type Reset By Reset

State Function

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12.2.62 VM E Interr up t Map 0 Register (VINT _M AP 0)

Table 98: VME Interrupt Map 0 Register (VINT_MAP0)

Bits Function

31-24 Reserved LINT7 Reserved LINT6

23-16 Reserved LINT5 Reserved LINT4

15-08 Reserved LINT3 Reserved LINT2

07-00 Reserved LINT1 Reserved LINT0

VINT_MAP0 Description

Name Type Reset By Reset

State Function

LINT7-LINT0

[2:0] R/W all 0 VMEbus destinat i on of PC I Bu s inte rr upt source

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12.2.63 VME I nterr up t Map 1 Register (VINT _M AP 1)

This r egiste r maps VMEbus inter rupt sources to one of the seven VMEbus inte rrupt

pins. A value of 001 maps the corresponding interrupt source to VI RQ*[1], a value

of 010 maps to VIRQ *[2], etc. A value of 000 effectively ma sks the interrupt since

there is no corresponding VIRQ*[0].

SW_INT is set to 010 with the VME64AUTO power-up option.

Table 99: VME Interrupt Map 1 Register (VINT_MAP1)

Bits Function

31-24 Reserved

23-16 Reserved SW_INT

15-08 Reserved VERR

07-00 Reserved LERR Reserved DMA

VINT_MAP1 Description

Name Type Reset By Reset

State Function

SW_INT R/W all Power-up

Option VMEbus Softw ar e int er rup t de st inat io n

VERR R/W all 0 VMEbus Error interrupt destination

LERR R/W all 0 PCI Bus Error interr upt des tin a tion

DMA R/W all 0 DMA interrupt destina tio n

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12.2.64 Interrupt STATUS/ID Out Register (STATID)

When the Universe II responds to an interrupt acknowledge cycle on VM Ebus it

returns an 8- bit STATUS/ID. STATI D [7:1] can be written by software to uniquely

identify the V MEbus module within the system. STATID [ 0] is a value of 0 if the

Universe II is generating a software interrupt (SW_IACK) at the same level as the

interrupt acknowledge cycle, otherwise it is a value of 1.

The reset state is designed to support the VME64 Auto ID STATUS/ID value.

Table 100: Interrupt STATUS/ID Out Register (STATID)

Bits Function

3 1 -24 S TATID [7 :0]

23-16 Reserved

15-08 Reserved

07-00 Reserved

Name Type Reset By Reset

State Function

STATID [7:1 ] R/W all 1111111 Bits [7 :1 ] o f th e STATUS/ID byte are re tu rn e d whe n

the Univ er se I I resp onds to a VMEb us IA C K cycle.

STATID [0] R all See below 0 = the Universe II is generating a SW_IACK at the

same level as the interrupt acknowledge cycle.

1 = the Universe II is not generating a SW_IACK at

the same level as the interr upt ack nowle d ge cycle.

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12.2.65 VIRQ1 S TATUS/ID Regi ster (V 1_STATI D)

The Vx_STATID registers are read-only r egisters that hold the 8-bit VMEbus

STATUS/ID th at is acquired wh en the Universe II performs a IACK cycle for a

given interrupt level.

The Univer se II is enable d a s the in terr upt h andl er f or a g iven inte r rupt le vel via the

VIRQx bits of the LINT_EN register. Once a vector for a given level is acquired,

the Universe II does not perform a subsequent interrupt acknowledge cycle at that

level until the corresponding VIRQx bit in the LINT_STAT register is cleared.

The acqui siti on of a l evel x STATUS/ID by the Unive r se II upda tes the S TATUS/ID

field of the corresponding Vx_STATID registe r and generation of a PCI interrupt . A

VMEbus error during the acquisition of the STATUS/ID vector sets the ERR bit,

which means the STATUS/ID field may not contain a valid vector.

Table 101: VIRQ1 STATUS/ID Register (V1_STATID)

Bits Function

31-24 Reserved

23-16 Reserved

15-08 Reserved ERR

07-00 STAT ID [7:0]

V1_STATID Description

Name Type Reset By Reset

State Function

ERR R all 0 Error Status Bit

0=S TATUS/ID w as acqui r ed w ith out bus error

1=b us er r or oc cur r ed during ac quisi t i on of the

STATUS/ID

STATID [7:0] R all 0 STATUS/ID acquired duri ng IACK cycle for level 1

VM Ebus i nte r rup t

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12.2.66 VIRQ2 S TATUS/ID Regi ster (V2_S TAT ID)

The Vx_STATID registers are read-only r egisters that hold the 8-bit VMEbus

STATUS/ID that is acqu ir ed when the Uni verse II p erforms a IAC K cycle for a

given interrupt level.

The Univer se II is enable d a s the in terr upt h andl er f or a g iven inte r rupt le vel via the

VIRQx bits of the LINT_EN register. Once a vector for a given level is acquired,

the Universe II does not perform a subsequent interrupt acknowledge cycle at that

level until the corresponding VIRQx bit in the LINT_STAT register is cleared.

The acq uisit ion of a level x STATUS/ID by the Unive rse II up dat es the STATUS/ID

field of the corresponding Vx_STATID registe r and generation of a PCI interrupt . A

VMEbus error during the acquisition of the STATUS/ID vector sets the ERR bit,

which means the STATUS/ID field may not contain a valid vector.

Table 102: VIRQ2 STATUS/ID Register (V2_STATID)

Bits Function

31-24 Reserved

23-16 Reserved

15-08 Reserved ERR

0 7 -00 S TATID [7 :0]

V2_STATID Description

Name Type Reset By Reset

State Function

ERR R all 0 Error Status Bit

0=S TATUS/ID w as acqui r ed w ith out bus error

1=b us er r or oc cur r ed during ac quisi t i on of the

STATUS/ID

STATID [7:0] R all 0 STATUS/ID acquired duri ng IACK cycle for level 1

VM Ebus i nte r rup t

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12.2.67 VIRQ3 S TATUS/ID Regi ster (V 3_STATI D)