DS04-27205-7Ea
FUJITSU MICROELECTRONICS
DATA SHEET
Copyright©1995-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2006.5
ASSP Power Supplies
BIPOLAR
Switching Regulator Controller
MB3782
■DESCRIPTION
The FUJITSU MICROELECTRONICS MB3782 is a PWM-type switching regulator controller, designed with open-
collector output for connection to external drive transistors and coils, providing a selection of three types of output
voltage: step-up, step-down or inverting (inverting output is available on one circuit only).
The MB3782 features identical oscillator output waveforms to enable completely synchronous operation and
prevent the occurrence of low-frequency beat between channels.
Also, the MB3782 features low power dissipation (2.1 mA Typ) and a built-in standby mode (10 µA), making
possible the configuration of a wide variety of high-efficiency, stable power supplies, even with the use of battery
power. The MB37 82 is an id eal p ower sup ply for high -p erfor man ce portable devices suc h as vi deo ca mcor de rs
and cameras.
■FEATURES
• Wide voltage range (3.6 V to 18 V)
• Low power dissipation (operating mode: 2.1 mA (Typ), standby mode: 10 µA (Max)
• Wide range of oscillator frequencies, high-frequency capability (1 kHz to 500 kHz)
• On-chip timer-latch type short detection circuit
• On-chip undervoltage lockout circuit
• On-chip 2.50 V reference voltage circuit (1.25 V output available at RT pin)
• Dead time adjustment over full duty cycle range
• On-chip standby mode (power on/off function)
• One type of package (SOP-20pin : 1 type)
■APPLICATIONS
• LCD monitor/panel
• Surveillance camera etc.
MB3782
2
■PIN ASSIGNMENT
■PIN DESCRIPTION
(Continued)
Pin No. Pin Name I/O Description
1V
REF O2.50 V (typ) voltage output: provides load current up to 3 mA,
for use as error amplifier reference input and for dead time
setting.
2C
T—Oscillator timing capacity connection: should be used in the
capacity range 150 pF to 15000 pF.
3R
T—Oscillator timing resistor connection: should be used in the
resistance range 5.1 kΩ to 100 kΩ. This pin can also provide
output at voltage level VREF/2, for use as error amplifier
reference input.
4 +IN1 I Error amplifier 1 non-inverting input pin.
5 –IN1 I Error amplifier 1 inverting input pin.
6FB1O
Error amplifier 1 output pin: connect resistor and capacitor
between this pin and the –IN1 pin to set gain and adjust
frequency characteristics.
7DTC1*1IOUT1 dead time setting pin: VREF voltage is divided by an
ex ternal resistor and applied to set dead time. Also , a capacitor
may be connected between this pin and the GND pin to perform
soft start operations.
VCC
CTL
− IN3
FB3
DTC3
OUT3
SCP
− IN2
FB2
DTC2
VREF
CT
RT
+ IN1
− IN1
FB1
DTC1
PUT1
GND
OUT2
TOP VIEW
(FPT-20P-M01)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
MB3782
3
(Continued)
*1: DTC = Dead Time Control
*2: SCP = Short Circuit Protection
Pin No. Pin Name I/O Description
8VOUT1O
Open collector type output pin with an emitter connected to
GND.
Output current may be up to 50 mA.
9 GND — Ground pin
10 OUT2 O Open collector type output pin with an emitter connected to
GND. Output current may be up to 50 mA.
11 DTC2*1IUsed to set OUT2 pin dead time. VREF voltage is divided by an
ex ternal resistor and applied to set dead time. Also , a capacitor
may be connected between this pin and the GND pin to perform
soft start operations.
12 FB2 O Error amplifier 2 output pin: connect resistor and capacitor
between this pin and the –IN2 pin to set gain and adjust
frequency characteristics.
13 –IN2 I Error amplifier 2 inverting input pin.
14 SCP*2—
Time constan t setti ng ca pac ito r conne cti on for timer-latch
type short prevention circuit: a capacitor should be connected
between this pin and the GND pin. For details, see “■ Setting
the Time Constant for the Timer-Latch Type Short Prevention
Circuit.”
15 OUT3 O Open collector type output pin for emitter connected to GND.
Output current may be up to 50 mA.
16 DTC3*1IUsed to set OUT3 pin dead time. VREF voltage is divided by an
ex ternal resistor and applied to set dead time. Also , a capacitor
may be connected between this pin and the GND pin to perform
soft start operations.
17 FB3 O Error amplifier 3 output pin: connect resistor and capacitor
between this pin and the –IN3 pin to set gain and adjust
frequency characteristics.
18 –IN3 I Error amplifier 3 inverting input pin.
19 CTL I Power supply control pin: low level places the IC in standby
mode and reduces power consumption to 10 µA or lower. Input
level may be driven by TTL or CMOS.
20 VCC — Power supply pin: voltage range is 3.6 V to 18 V.
MB3782
4
■BLO C K DIAGR AM
16
17
14
18
11
12
13
7
6
5
4
3 2 1 20 19
9
8
10
15
GND
OUT1
OUT2
OUT3
+ IN1
- IN1
FB1
DTC1
- IN2
FB2
DTC2
- IN3
FB3
DTC3
SCP
SR
Latch U.V.L.O.
V
REF
CLTV
CC
V
REF
C
T
R
T
1.25 V 2.5 V
-
+
-
++
+
-
+
+
-
+
-+
+
-
Error Amp 1 Ch.1
Ch.2
Ch.3
Error Amp 2
Error Amp 3
1.25 V
1.25 V
2.1 V
SCP Comp. -
-
-
+
1 µA
Triangular wave
oscillator
Reference
voltage
source
Power on/off
control
circuit
PWM Comp.1
PWM Comp.2
PWM Comp.3
MB3782
5
■FUNCTIONAL DESCRIPTIONS
1. Reference Voltage Source
The reference voltage source uses the voltage provided at the VCC pin (pin 20) to generate a temperature-
compensated reference voltage (≅ 2.50 V), which is used as the operating power supply f or the internal circuits
of the IC. The reference voltage source can be output through the VREF pin (pin 1).
2. Triangular Wave Oscillator
By connecting a timing capacitor and resistor respectively to the CT pin (pin 2) and RT pin (pin 3), the oscillator
can provide a triangular wav eform at any desired frequency.
The waveform ha s an amp litude of 1.3 V to 1.9 V, and can be c onnected to the no n-inver ting i nput of the on-
chip PWM comparator and also output through the CT pin (pin 2).
3. Error Amp s
The error amps are amplifiers that detect the output voltage of the switching regulator and send the PWM control
signal. The common-mode input voltage range is 1.05 V to 1.45 V, so that the voltage applied to the non-inverting
input pin as a ref erence voltage should be either the voltage obtained b y dividing the IC ref erence voltage output
(recomm ended value: VREF/2) or th e voltage obt ain ed from th e RT pin (pin 3) (1.25 V) . The non-inverting in put
for the error amps 1 and 2 is internally connected to VREF/2 voltage.
Also, a f eedback transistor and capacitor can be connected between the error amp output pin and inverting input
pin to provide any desired level of loop gain, enabling stable phase compensation.
4. Timer Latch (S-R Latch) Type Short Prevention Circuit
The time r-latch type shor t pr eventio n circui t detects the outp ut levels from each of the error amps. Whe never
one or more error amps produces an output level of 2.1 V or higher, the timer circuit is activated star ting the
charging of the external protection enabler capacitor.
If the error amp output voltage does not return to normal range before the v oltage in this capacitor reaches the
transistor’ s base-emitter junction voltage (VBE (≅ 0.65 V)), the latch circuit will operate to turn the output transistor
off and at the same time set the dead time to 100%.
Once the prevention circuit is activated, the power must be switched on again to resume normal operation.
5. Low Input Voltage Fa ult Prevention Circuit (Under Voltage Lock-Out (UVLO) function)
When power is s witched on, excess power or momentary drops in power line current can cause operating faults
in the controller IC, which can in turn lead to damage or deterioration in systems.
The low input voltage fault prevention circuit detects the internal reference voltage level with respect to the power
supply voltage level and acts to reset the latch circuit, thereby turning the output transistor off and at the same
time setting the dead time to 100% and holding the SCP pin (pin 14) at “low.” Operation returns to normal when
the power supply voltage reaches or exceeds the UVLO threshold voltage level.
6. P WM Comp arator
The PWM comparator is a voltage comparator with one inv erting and two non-inv erting inputs, which acts as a
voltage to pulse width conv erter controlling the on-time of the output pulse according to the input voltage level.
When the tr iangul ar wavefor m pro duced by the oscillator is lower than eit her the er ror amp o utput or the DTC
pin voltage, the output transistor is switched on.
It is also possible to use the DTC terminal to provide a soft start function.
7. Output Transistor
The output is open-collector type, with the emitter of the output transistor connected to the GND pin. The power
transistor for external switching can carry a base current of up to 50 mA.
8. Power Supply Control
Pow er supply on/off control is enabled through the CTL pin (pin 19). (In standby mode, power supply current is
10 µA or less.)
MB3782
6
■ABSOLUTE MAXIMUM RATINGS
*1: For operation in conditions where Ta > +25°C, and the SOP version should be derated by 7.4 mW/°C.
*2: When mounted on a 4 cm-square dual-sided epoxy board.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■RECOMMENDED OPERATING CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
Parameter Symbol Condition Rating Unit
Min Max
Power supply voltage VCC ——20V
Error amp input voltage VIN —–0.3 +10V
Dead time control input voltage Vdt — –0.3 +2.8 V
Contr ol inp ut voltage VCTL — –0.3 +20 V
Collector output voltage VOUT ——20V
Collector output current IOUT ——75mA
Allowable loss PD*1Ta ≤ +25°CSOP Version —740*
2mW
Operating ambient temperature Ta — –30 +85 °C
Storage temperature Tstg — –55 +125 °C
Parameter Symbol Condition Value Unit
Min Typ Max
Power supply voltage VCC — 3.6 6.0 18.0 V
Error amp input voltage VIN —1.05—1.45V
Control input voltage VCTL —0—18V
Collector output voltage V OUT ———18V
Collector output current IOUT —0.3—50mA
Reference voltage output current IREF —–3–10mA
Timing capacitance CT— 150 — 15000 pF
Timing resistance RT— 5.1 — 100 kΩ
Oscillator frequency fOSC — 1 — 500 kHz
Operating ambient temperature Ta — –30 +25 +85 °C
MB3782
7
■ELECTRICAL CHARACTERISTICS (VCC = 6 V, Ta = +25°C)
(Continued)
Parameter Symbol Conditions Value Unit
Min Typ Max
Reference voltage
Output voltage VREF IOR = –1 mA 2.45 2.50 2.55 V
Output voltage
temperature variation VRTC Ta = –30°C to +85°C–2±0.2 +2 %
Input stability Line VCC = 3.6 V to 18 V — 2 10 mV
Load stability Load IOR = –0.1 mA to –1 mA — 1 7.5 mV
Short output current IOS VREF = 2 V –30 –10 –3 mA
Undervol tage lock
out circuit (UVLO)
Threshold voltage VtH IOR = –0.1 mA — 2.72 — V
VtL IOR = –0.1 mA — 2.60 — V
Hysteresis width VHYS IOR = –0.1 mA 80 120 — mV
Reset voltage (VCC)VR—1.51.9—V
Short circuit protection
(SCP)
Input t hreshold voltag e VtPC — 0.60 0.65 0.70 V
Input standby voltage VSTB No pul l- up — 50 100 mV
Input latch voltage VIN No pull-up — 50 100 mV
Input source current Ibpc — –1.4 –1.0 –0.6 µA
Comparator threshol d
voltage VtC Pin 6, pin 12, pin 17 — 2.1 — V
Triangula r wave
oscillator
Oscillator frequency fOSC CT = 330 pF, RT = 15 kΩ160 200 240 kHz
Frequency deviation fdev CT = 330 pF, RT = 15 kΩ—±5—%
Frequency deviation (VCC)fdV VCC = 3.6 V to 18 V — ±1—%
Frequency deviation (Ta) fdT Ta = –30°C to +85°C–4—+4%
Dead time controller
(DTC)
Input t hreshold voltag e Vt0 Duty cycle = 0 % 1.05 1.3 — V
Vt100 Duty cycle = 100 % — 1.9 2.25 V
ON duty cycle Dtr Vdt = VR/1.45 V 55 65 75 %
Input bias current Ibdt ——0.21µA
Latch mode sink current Idt Vdt = 2.5 V 150 500 — µA
Latch input voltage Vdt Idt = 100 µA——0.3V
MB3782
8
(Continued) (VCC = 6 V, Ta = +25°C)
Notes : •Voltage control on channel 1 may be positive or negative.
•The non-inv erting input to the error amps on channel 2 and channel 3 is internally connected to VREF/2,
and therefore voltage control is positive only.
•VREF/2 output can be obtained from the RT pin.
Parameter Symbol Conditions Value Unit
Min Typ Max
Error amps
Input offset voltage VIO VOUT = 1.6 V –6 — +6 mV
Input offset current IIO VOUT = 1.6 V –100 — +100 nA
Input bias current IBVOUT = 1.6 V –500 –100 — nA
Common mode input
voltage range VICR VCC = 3.6 V to 18 V 1.05 — 1.45 V
Voltage gain Av — 70 80 — d B
Frequency bandwidth BW Av = 0 dB — 0.8 — MHz
Common mode rej ec tio n
ratio CMRR — 60 80 — dB
Maximum output voltage
range VOM+—
VREF
–0.3 ——V
VOM-——0.70.9V
Output sink current IOM+VOUT = 1.6 V — 1.0 — mA
Output source current IOM-VOUT = 1.6 V — –60 — µA
PWM
comparator
Input t hreshold voltag e Vt0 Duty cycle = 0 % 1.05 1.3 — V
Vt100 Duty cycle = 100 % — 1.9 2.25 V
Input sink current IIN+ Pin 6, pin 12, pin 17 — 1.0 — mA
Input source current IIN- Pin 6, pin 12, pin 17 — –60 — µA
Control
block
Input OFF conditions VOFF ———0.7V
Input ON conditions VON —2.1——V
Control pin current ICTL VCTL = 10 V — 200 400 µA
Output
block
Output leak current Leak VOUT = 18 V — — 10 µA
Output saturation voltage VSAT IOUT = 50 mA — 1.1 1.4 V
Entire
device
Standby current ICCS VCTL = 0 V — — 10 µA
Average feed current ICCaVCTL = VCC, no output load — 2.1 3.2 mA
MB3782
9
■SETTING THE TIME CONSTANT FOR THE TIMER-LATCH TYPE SHORT PREVENTION
CIRCUIT
Figure 1 shows the configuration of the protection latch circuit.
The output lines from the error amps are each connected to the inverting input lines of the short protection
comparat or, whi ch con stantly co mpares them with the reference voltage o f approximately 2 .1 V con nected to
the non-inverting input.
When load conditions in the switching regulator are stabilized, there is no variation in the output from the error
amps, and th erefore the short prevention controls ar e held in equili briu m. In this situat ion, voltage at the SCP
pin (pin 14) is held at approximately 50 mV.
When lo ad conditions c hange rapidly, as in the case of a load s hor t, high potential signal (greater than 2.1V )
from the error amps is input to the inverting signal input of the short protection comparator, and the short protection
comparator outputs a “low” le vel signal. The transistor Q1 is consequently switched off, so that short protection
capacitor C PE e x ternally connected to the SCP pin voltage is then charged according to the following f ormulas.
VPE = 50 mV + tPE × 10–6/CPE
0.65 = 50 mV + tPE × 10–6/CPE
CPE = tPE/0.6 (µF)
When the shor t pr otection capacit or is ch arged to a level of a pproximately 0.65 V, t he SR latch is set and the
low input voltage fault pre vention circuit is enabled, turning the output drive transistor off. At the same time, the
dead time is set to 100% and the SCP pin (pin 14) is held “low. ” This closes the S-R latch input and then discharges
the capacitor CPE
-
-
-
+
14
1 µA
CPE SR
Latch U.V.L.O.
2.50 V
Out
PWM
Comp.
Q3Q1
S.C.P.Comp.
Error Amp 1
Error Amp 2
Error Amp 3
2.1 V
Figure 1 Protection Latch Circuit
MB3782
10
■SETTING OUTPUT VOLTAGE
The following diagrams show the connections used to set the output voltage.
Because the power supply to the error amps is provided by the same reference voltage circuit used for the other
internal circuits, the common-mode input voltage range is set at 1.05 V to 1.45 V.
The reference voltage input to the +IN and -IN pins should be set at 1.25 V (VREF/2). The method of connection
for channel 1 is different from channel 2 and channel 3. In addition, channel 1 is capable of picking up both
positive and negative voltages, while channel 2 and channel 3 can pick up only positive output voltages.
RNF
R2R
+
−
R1R
VREF
V0 +V0 + = 2R2
VREF × (R1 + R2)
pin 6
Figure 2 Error amp (channel 1) connection: Output voltage VO pos itive
RNF
R2R
+
R1R
VREF
2×R2
VREF × (R1 + R2) + VREF
pin 6
V0 −
−
V0 − = −
Figure 3 Error amp (channel 1) connection: Output voltage VO positive
MB3782
11
The non-inver ting inpu t to the error amps on channel 2 and channel 3 is inter nally connected to VREF/2, and
therefore cannot be configured for inverting output.
ch.1 ch.2 ch.3
Step up ●●●
Step down ●●●
Inverting ●××
RNF
R2
+
−
R1
V0 + = R2
1.25 × (R1 + R2)
pin 12,17
V0 +
1.25 V
Figure 4 Error amp (ch annel 2, channel 3) connection
MB3782
12
■USING THE RT PIN
The triangular waves, as shown in Figure 5, act to set the oscillator frequency by charging and discharging the
capacitor connected to the CT pin using the current value of the resistor connected to the RT pin.
In addition, when voltage level VREF/2 is output to ex ternal circuits from the RT pin, care must be taken in making
the external circuit connections to adjust for the fact that I1 is increased by the value of the current I2 to the
external circuits in determining the oscillator frequency (see Figure 6).
21
VREF
2
RTCT
ICTIRT
ICT = IRT
=VREF
2RT
Triangular wave oscillator
Figure 5 No VREF/2 connection to external circuits from RT pin
21
VREF
2
RTCT
ICTIRT
ICT = IRT
= I1 + I2
Triangular wave generator
I1
IRT
= + I2
VREF
2RT
To external circuits
Figure 6 VREF/2 connection to external circuits from RT pin
MB3782
13
■TREATMENT OF UNUSED ERROR AMPS
Any error amps that are not used should be handled as follows.
Note that failure t o apply pr oper tre atment to error amps will cause the SCP c ircuit to activate and dis able the
switching regulator output.
1. Error Amp (channel 1) Not In Use
2. Error Amp (channel 2) Not In Use
3. Error Amp (channel 3) Not In Use
9
7
5
4
3
1
GND
DTC1
– IN1
VREF
+ IN1
RT
Note: Pin 6 and pin 8 shoud be left open.
913
11
1
GND
DTC2
– IN2
VREF
Note: Pin 10 and pin 12 shoud be left open.
1
9
18
16
GND
DTC3
– IN3
VREF
Note: Pin 15 and pin 17 shoud be left open.
MB3782
14
■TREATMENT OF UNUSED SCP PIN
When the timer latch short protection circuit is not used, the SCP pin (pin 14) should be connected to the GND
by the shortest possible path.
14
SCP
MB3782
15
■TEST CIRCUIT
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
330 pF
150 kΩ
TEST
INPUT
TEST
INPUT
CPF
OUTPUT
INPUT
TEST 4.7 kΩ
VCC
CTL
4.7 kΩ
OUTPUT
OUTPUT
4.7 kΩ
MB3782
16
■TIMING CHART (INTERMAL WAVEFORMS)
2.1 V
1.9 V
1.6 V
1.3 V
tPE
"High"
"Low"
"High"
"Low"
0.6 V
0 V
"High"
"Low"
2.1 V
0 V
3.6V
0V
CT pin wavefoms
Short protection
comparator reference input
Error amp output
PWM comparator output
Dead time,PWM input voltage
Output transistor-collector
waveforms
SCP pin waveforms
Short protection comparator output
Control pin voltage (VCTL: minimum value)
Power ON
Power supply voltage (VCC: minimum)
Power OFF
Protection enable time tPE ≅ 0.6 × 106 × CPE (µs)
Dead time 100 %
MB3782
17
■EXAMPLE OF APPLICATION
MB3782
8
OUT1
5−IN1
4+IN1
6FB1
0.033 µF 150 k
Ω
−IN2
FB2
0.033 µF 150 k
Ω
12
13
−IN3
FB3
0.033 µF 150 k
Ω
17
18
CT
RT
SCP
14
2
39
GND
1.8 kΩ
1.8 kΩ
4.7 kΩ
820 pF
0.1
µ
F
8.2 kΩ
1
VREF 7
DTC1 DTC2 DTC3
20
VCC CTL
11 16 19
V IN (6V)
CTL
4.7 kΩ
1.8 kΩ10 kΩ
10 kΩ
4.7kΩ
2.4 kΩ
10 kΩ
4.7 kΩ
1 µF
1 µF
1 µF
5.6 kΩ
9.1 kΩ
16 kΩ
OUT3
15
VO−
(−5V)
330 Ω
330 Ω
120 µH
10
OUT2
VO+
(+5V)
330 Ω
330 Ω
220 µF
120 µH
VO+
(+12V)
120 µH
3.9 kΩ100 Ω
220 µF
5.6 µH
+
−
+
−
MB3782
18
■ TYPICAL CHARACTERISTICS CURVES
(Continued)
5.0
0
2.5
Reference voltage vs. Power supply voltage
Ta = +25˚C
04 8 12 16 20
Power supply voltage V
CC
(V)
Reference voltage V
REF
(V)
Average feed current vs. Power supply voltage
Power supply voltage V
CC
(V)
Timing capacitance C
T
(pF)
04 8 12 16 20
3.0
0
1.5
Ta = +25˚C
2.51
2.50
2.49
2.48
2.47
2.46
2.45
- 40 - 20 0 + 20 + 40 + 60 + 80 + 100
Reference voltage V
REF
(V)
V
CC
= V
CTL
= 6 V
I
OR
= -1 mA
1.6
2.0
1.8
1.4
1.2
1.0
0.8 10
2
2.2
10
3
10
4
Reference voltage vs. Operating ambient temperature
Operating ambient temperature Ta (˚C)
Triangular wave maximum amplitude voltage vs. Timing capacitance
V
CC
= 6 V
R
T
= 15 kΩ
Ta = +25˚C
3.0
2.0
1.0
0
100 500 1 k 5 k 10 k 50 k 100 k 500 k
Ta = +25˚C
V
CC
= 6 V
2.0
1.5
1.0
0.5
001020304050
Sink current I
OL
(mA)
Collector saturation voltage vs. Sink current
Collector saturation voltagre V
OL
(V)
Error amp maximum output voltage amplitude (V)
Error amp maximum output voltage amplitude vs. Frequency
Fequency f (Hz)
Ta = +25˚C
V
CC
= 6 V
Average feed current (mA)
Triangular wave maximum
amplitude voltage (V)
MB3782
19
(Continued)
1 M
100 k
10 k
1 k1 k 5 k 10 k 50 k 100 k 500 k
CT = 150 pF
CT = 1500 pF
CT = 15000 pF
100
10
1102103104105
Triangular wave period vs. Timing capacitance
Timing capacitance CT (pF)
Oscillator frequency vs. Timing resistance
Timing resistance RT (Ω)
Oscillator frequency fOSC (Hz)
Triangular wave period (µs)
10
0
-10
-
40
-
20 0 +20 +40 +60 +80 +100 +120
VCC = 6 V
Ta = +25˚C
Frequency variation vs. Operating ambient temperature
Operating ambient temperature Ta (˚C)
Frequency variation fDT (%)
100
80
60
40
20
05 k 10 k 50 k 100 k 500 k 1 M
ON duty cycle vs. Oscillator frequency
Oscillator frequency (Hz)
Reference voltage vs. Control input voltage
Control input voltage VCTL (V)
Reference voltage VREF (V)
5.0
2.5
0012345
ON duty Cycle Dtr (%)
Control input current ICTL (µA)
500
250
0048121620
Control input current vs. Control input voltage
Control input voltage VCTL (V)
VCC = 6 V
RT = 15 kΩ
Ta = +25˚C
VCC = 6 V
CT = 330 pF
RT = 15 kΩ
VCC = 6 V
CT = 1330 pF
RT = 15 kΩ
Ta = +25˚C
VCC = 6 V
CT = +25˚C VCC = 6 V
CT = +25˚C
MB3782
20
(Continued)
OUT
6
5
IN
4
+
-
-+
4.7 kΩ4.7 kΩ
240 kΩ
CNF
VREFVREF
4.7 kΩ4.7 kΩ
10 µF
Error amp
10 100 1 k 10 k 100 k 1 M
-40
-20
0
20
40
-180
-90
0
90
180
φ
CNF = 470 pF
AV
AV
φ
CNF = 4700 pF
-40
-20
0
20
40
-180
-90
0
90
180
10 100 1 k 10 k 100 k 1 M
Frequenncy f (Hz)Frequenncy f (Hz)
Voltage gain and phase vs. FrequenncyVoltage gain and phase vs. Frequenncy
Voltage gain AV (dB)
Phase ϕ (deg)
Phase ϕ (deg)
Voltage gain AV (dB)
Test Circuit
10 100 1 k 10 k 100 k 1 M
Frequenncy f (Hz)
10 100 1 k 10 k 100 k 1 M
Frequenncy f (Hz)
-180
-90
0
90
180
-40
-20
0
20
40
Voltage gain AV (dB)
Phase ϕ (deg)
-40
-20
0
20
40
Voltage gain AV (dB)
-180
-90
0
90
180
Phase ϕ (deg)
Voltage gain and phase vs. FrequenncyVoltage gain and phase vs. Frequenncy
AV
φφ
CNF = 0.047 pF
CNF = open
AV
MB3782
21
(Continued)
-30 -20 -10 0 +10+20 +30 +40 +50 +60 +70 +80 +85
0
200
400
600
800
740
1000
1110
1200
Allowable loss PD (mW)
Allowable loss vs. Operating ambient temperature
Operating ambient temperature Ta (˚C)
SOP version
MB3782
22
■CONCERNING EQUIVALENT SERIES RESISTANCE AND STABILITY OF SMOOTHING
CAPACITORS
In DC/DC converters, the equivalent series resistance value (ESR) of smoothing capacitors has a major influence
on loop phase characteristics.
The ESR is a means by which phase characteristics approximate phase relationships to ideal capacitors in high-
frequency bands (see Graph 1), thus improving system stability . At the same time, the use of smoothing capacitors
with low ESR redu ces system stability, s o that care must be taken when usi ng semiconduc tor electrolytic ca-
pacitors (OS-CONTM*) or tantalum capacitors with low ESR.
* : OS-CON is a trademark of Sanyo Electric Co., Ltd.
Tr L
D
Rc
RL
C
VIN
Figure 7 Basic circuit for step-down voltage DC/DC converter
1
2
2
10 100 1 k 10 k 100 k
− 60
− 40
− 20
0
20
Gain (dB)
Gain vs. frequency
Phase (deg)
Frequency f (Hz)
Phase vs. frequency
Frequency f (Hz)
10 100 1 k 10 k 100 k
0
− 90
− 180
2
1
1: Rc = 0 Ω
: Rc = 31 mΩ2
1: Rc = 0 Ω
: Rc = 31 mΩ
Graph 1 Gain and phase vs. frequency
MB3782
23
• Reference dat a
Chang ing the smooth ing c apacitor from an alum inum ele ctrolyt ic ca pacitor (RC ≅ 1.0 Ω) to a lower-ESR semi-
conductor electrolytic capacitor (OS-CONTM: RC ≅ 0.2 Ω) decreases the phase margin (see Graphs 2, 3).
V out V0 +
CNF
FB –
+
– IN
+ IN
R1
R2VIN
VREF/2
Error amp
AV and phase characteristics
measured between these points
Figure 8 Measurement of DC/DC Capacitor AV and Phase (φ) Characteristics
+
−
Gain (dB)
DC/DC converter + 5 V output Gain and Phase vs. Frequency
Frequency f (Hz)
Phase (deg)
Aluminum electrolytic
capacitor
220 µF (16 V)
RC ≅ 1.0 Ω
: fosc = 1 kHz
10 100 1 k 10 k 100 k
− 40
− 20
0
20
40
60
Av φ
62°
Vcc = 10 V
RL = 25 Ω
Cp = 0.1 µF
− 90
0
− 180
90
180 V0 +
+
−
Gain (dB)
10
− 40
− 20
0
20
40
60
Frequency f (Hz)
100 1 k 10 k 100 k
Phase (deg)
− 90
0
− 180
90
180
DC/DC converter + 5 V output Gain and Phase vs. Frequency
Vcc = 10 V
RL = 25 Ω
Cp = 0.1 µF
OS-CONTM
22 µF (16 V)
RC ≅ 0.2 Ω
: fosc = 1 kHz
Av
φ
27°
Graph 2
Graph 3
MB3782
24
■NOTES ON USE
• Take account of common impedance when designing the earth line on a printed wiring board.
• Take measures against static electricity.
- For semiconductors, use antistatic or conductive containers.
- When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container.
- The work table, tools and measuring instruments must be grounded.
- The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series.
• Do not apply a negative voltage
- Applying a negative voltage of −0.3 V or less to an LSI may generate a parasitic transistor, resulting in
malfunction.
■ORDERING INFORMATION
■RoHS Compliance Information of Lead (Pb) Free version
The LS I products of Fujits u Microele ctronic s with “E1 ” are com pliant wit h RoHS Dir ective , and has o bser ved
the standard of lead, cadmium, mercury, Hexa valent chromium, polybrominated biphenyls (PBB) , and polybro-
minated diphenyl ethers (PBDE) .
The product that conforms to this standard is added “E1” at the end of the part number.
■MARKING FORMAT (Lead Free version)
Part number Package Remarks
MB3782PF-❏❏❏ 20 pin plastic SOP
(FPT-20P-M01) Conven tion al version
MB3782PF-❏❏❏E1 20 pin plastic SOP
(FPT-20P-M01) Lead Free version
INDEX
MB3782
XXXX XXX
E1
Lead Free version
SOP-20
MB3782
25
■LABELING SAMPLE (Lead free version)
2006/03/01
ASSEMBLED IN JAPAN
G
QC PASS
(3N) 1MB123456P-789-GE1
1000
(3N)2 1561190005 107210
1,000
PCS
0605 - Z01A
1000
1/1
1561190005
MB123456P - 789 - GE1
MB123456P - 789 - GE1
MB123456P - 789 - GE1
Pb
Lead Free version
Lead free mark
JEITA logo JEDEC logo
MB3782
26
■MB3782PF-❏❏❏E1 RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL
[Temperature Profile for FJ Standard IR Reflow]
(1) IR (infrared reflow)
(2) Manual soldering (partial heating method )
Conditions : Temperature 400 °C Max
Times : 5 s max/pin
Item Condition
Mounting Method IR (infrared reflow) , Manual soldering (partial heating method)
Mounting tim es 2 times
Storage period
Before opening Please use it within two years after
Manufacture.
From opening to the 2nd
reflow Less than 8 days
When the storage period after
opening was exceeded Please processes within 8 days
after baking (125 °C, 24H)
Storage conditions 5 °C to 30 °C, 70%RH or less (the lowest possible humidity)
260 °C
(e)
(d')
(d)
255 °C
170 °C
190 °C
RT (b)
(a)
(c)
to
Note : Temperature : the top of the package body
(a) Te mperat ure Incr ease grad ient : Average 1 °C/s to 4 °C/s
(b) Preliminary heating : Temperature 170 °C to 190 °C, 60s to 180s
(c) Tem perat ure Increas e grad ient : Average 1 °C/s to 4 °C/s
(d) Actual heating : Temperature 260 °C Max; 255 °C or more, 10s or less
(d’) : Temperature 230 °C or more, 40s or less
or
Temperature 225 °C or more, 60s or less
or
Temperature 220 °C or more, 80s or less
(e) Cooling : Natural cooling or forced cooling
H rank : 260 °C Max
MB3782
27
■PACKAGE DIMENSION
20-pin plastic SOP Lead pitch 1.27 mm
Package width
×
package length
5.3 × 12.7 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 2.25 mm MAX
Weight 0.28 g
Code
(Reference) P-SOP20-5.3×12.7-1.27
20-pin plastic SOP
(FPT-20P-M01)
(FPT-20P-M01)
C
2002 FUJITSU LIMITED F20003S-c-7-7
0.13(.005) M
Details of "A" part
7.80±0.405.30±0.30
(.209±.012) (.307±.016)
–.008
+.010
–0.20
+0.25
12.70
INDEX
1.27(.050)
0.10(.004)
1 10
1120
0.47±0.08
(.019±.003)
–0.04
+0.03
0.17
.007 +.001
–.002
"A" 0.25(.010)
(Stand off)
0~8˚
(Mounting height)
2.00 +0.25
–0.15
.079 +.010
–.006
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10 +0.10
–0.05
–.002
+.004
.004
.500
*1
*2
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen,
Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD.
151 Lorong Chuan, #05-08 New Tech Park,
Singapore 556741
Tel: +65-6281-0770 Fax: +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm.3102, Bund Center, No.222 Yan An Road(E),
Shanghai 200002, China
Tel: +86-21-6335-1560 Fax: +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road
Tsimshatsui, Kowloon
Hong Kong
Tel: +852-2377-0226 Fax: +852-2376-3269
http://cn.fujitsu.com/fmc/tw
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-
ing the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited Strategic Business Development Dept.
