ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
1 of 42
ITG-3050
Product Specification
Revision 1.3
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
2 of 42
CONTENTS
1 DOCUMENT INFORMATION ..................................................................................................................... 4
1.1 REVISION HISTORY ................................................................................................................................. 4
1.2 PURPOSE AND SCOPE ............................................................................................................................ 5
1.3 PRODUCT OVERVIEW.............................................................................................................................. 5
1.4 SOFTWARE SOLUTIONS .......................................................................................................................... 5
1.5 APPLICATIONS ........................................................................................................................................ 7
2 FEATURES ................................................................................................................................................. 8
2.1 SENSORS ............................................................................................................................................... 8
2.2 DIGITAL OUTPUT .................................................................................................................................... 8
2.3 DATA PROCESSING ................................................................................................................................ 8
2.4 CLOCKING .............................................................................................................................................. 8
2.5 POWER .................................................................................................................................................. 8
2.6 PACKAGE ............................................................................................................................................... 8
3 ELECTRICAL CHARACTERISTICS .......................................................................................................... 9
3.1 SENSOR SPECIFICATIONS ....................................................................................................................... 9
3.2 ELECTRICAL SPECIFICATIONS................................................................................................................ 10
3.3 ELECTRICAL SPECIFICATIONS, CONTINUED ............................................................................................ 11
3.4 ELECTRICAL SPECIFICATIONS, CONTINUED ............................................................................................ 12
3.5 I2C TIMING CHARACTERIZATION ............................................................................................................ 13
3.6 ABSOLUTE MAXIMUM RATINGS .............................................................................................................. 14
4 APPLICATIONS INFORMATION ............................................................................................................. 15
4.1 PIN OUT AND SIGNAL DESCRIPTION ....................................................................................................... 15
4.2 TYPICAL OPERATING CIRCUIT ............................................................................................................... 16
4.3 BILL OF MATERIALS FOR EXTERNAL COMPONENTS ................................................................................. 16
4.4 RECOMMENDED POWER-ON PROCEDURE .............................................................................................. 17
5 FUNCTIONAL OVERVIEW ....................................................................................................................... 18
5.1 BLOCK DIAGRAM .................................................................................................................................. 18
5.2 OVERVIEW ........................................................................................................................................... 18
5.3 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING .................................. 18
5.4 PRIMARY I2C SERIAL COMMUNICATIONS INTERFACE............................................................................... 19
5.5 SECONDARY I2C SERIAL INTERFACE (FOR 3RD-PARTY ACCELEROMETERS) ............................................... 19
5.6 3RD PARTY ACCELEROMETER CIRCUIT CONFIGURATIONS ........................................................................ 22
5.7 INTERNAL CLOCK GENERATION ............................................................................................................. 22
5.8 CLOCK OUTPUT .................................................................................................................................... 23
5.9 SENSOR DATA REGISTERS ................................................................................................................... 23
5.10 FIFO ................................................................................................................................................... 23
5.11 INTERRUPTS ......................................................................................................................................... 23
5.12 DIGITAL-OUTPUT TEMPERATURE SENSOR ............................................................................................. 23
5.13 BIAS AND LDO ..................................................................................................................................... 23
5.14 CHARGE PUMP ..................................................................................................................................... 23
6 DIGITAL INTERFACE ............................................................................................................................... 24
6.1 I2C SERIAL INTERFACE ......................................................................................................................... 24
7 SERIAL INTERFACE CONSIDERATIONS .............................................................................................. 28
7.1 ITG-3050 SUPPORTED INTERFACES ..................................................................................................... 28
7.2 LOGIC LEVELS ...................................................................................................................................... 28
8 ASSEMBLY ............................................................................................................................................... 31
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
3 of 42
8.1 ORIENTATION OF AXES ......................................................................................................................... 31
8.2 PACKAGE DIMENSIONS: ........................................................................................................................ 32
8.3 PCB DESIGN GUIDELINES:.................................................................................................................... 33
8.4 ASSEMBLY PRECAUTIONS ..................................................................................................................... 34
8.5 PACKAGE MARKING SPECIFICATION ...................................................................................................... 37
8.6 TAPE & REEL SPECIFICATION ................................................................................................................ 38
8.7 LABEL .................................................................................................................................................. 39
8.8 PACKAGING .......................................................................................................................................... 40
9 RELIABILITY ............................................................................................................................................ 41
9.1 QUALIFICATION TEST POLICY ................................................................................................................ 41
9.2 QUALIFICATION TEST PLAN ................................................................................................................... 41
10 ENVIRONMENTAL COMPLIANCE ...................................................................................................... 42
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
4 of 42
1 Document Information
1.1 Revision History
Revision
Date
Revision
Description
04/15/2011
1.0
Initial Release
05/19/2011
1.1
Sec. 1.4 Provided additional information to software solution section
Sec. 3.2 Added CLKOUT Digital Output specification
Sec. 8.4.3 Clarified Trace Routing Precautions
05/25/2011
1.2
Sec. 4.1 Specified CLKIN and FSYNC to be connected to GND if unused.
Sec. 4.4 Modified TVDDR value for consistency with Electrical
Characteristics
08/25/2011
1.3
Sec. 1.4 Clarified upgrade path to InvenSense’s MPU and IMU product
families and integration with software solutions.
Sec. 5.6 Added section describing and providing diagrams for the 3rd party
Accelerometer circuit configurations
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
5 of 42
1.2 Purpose and Scope
This document is a product specification, providing a description, specifications, and design related
information for the ITG-3050.
1.3 Product Overview
The ITG-3050 is a single-chip, digital output, 3-Axis MEMS gyro IC which features a 512-byte FIFO and a
secondary I2C sensor bus that interfaces to 3rd party digital accelerometers. The combination of FIFO and
dedicated sensor bus allows the ITG-3050 to directly acquire data from an off-chip accelerometer without
intervention from an external processor. This both lowers the traffic on the primary (application processor)
bus interface and saves power by allowing the system processor to burst read sensor data from the ITG-
3050’s FIFO and then go into a low-power sleep mode while the device collects more data.
The ITG-3050 features a 3-axis digital gyro with programmable full-scale ranges of ±250, ±500, ±1000, and
±2000 degrees/sec (dps or °/sec), which is useful for precision tracking of both fast and slow motions. Rate
noise performance sets the industry standard at 0.01 dps/√Hz, providing the highest-quality user experience
in pointing, gaming, user interface, and other motion-based applications. Factory-calibrated initial sensitivity
reduces production-line calibration requirements.
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, a precision clock
with 1% drift from -40°C to 85°C, an embedded temperature sensor, programmable interrupts, and a low
5.9mA supply current. The ITG-3050 comes with an I2C serial interface, a VDD operating range of 2.1 to
3.6V, and a VLOGIC interface voltage from 1.71V to 3.6V.
By leveraging its patented and volume-proven Nasiri-Fabrication platform, which integrates MEMS wafers
with companion CMOS electronics through wafer-level bonding, InvenSense has driven the ITG-3050
package size down to a revolutionary footprint of 4x4x0.9mm (QFN), while providing the highest
performance, lowest noise, and the lowest cost semiconductor packaging to address a wide range of
handheld consumer electronic devices. The device provides the highest robustness by supporting 10,000g
shock in operation. The highest cross-axis isolation is achieved by design from its single silicon integration.
1.4 Software Solutions
This section describes the MotionApps™ software solutions included with the InvenSense MPU (Motion
Processing Unit) and IMU (Inertial Measurement Unit) product families.
Please note that the products within the IDG, IXZ, and ITG gyroscope families do not include these
software solutions. The MPU and IMU product families are pin compatible with the digital IDG, IXZ, and
ITG families, and provide a simple swap and replace upgrade path to integrate InvenSense’s software
solutions.
The MotionApps Platform is a complete software solution that in combination with the InvenSense IMU and
MPU MotionProcessor families delivers robust, well-calibrated 6-axis and/or 9-axis sensor fusion data
using its field proven and proprietary MotionFusion™ engine. Solution packages are available for
smartphones and tablets as well as for embedded microcontroller-based devices.
The MotionApps Platform provides a turn-key solution for developers and accelerates time-to-market. It
consists of complex 6/9-axis sensor fusion algorithms, robust multi-sensor calibration, a proven software
architecture for Android and other leading operating systems, and a flexible power management scheme.
The MotionApps Platform is integrated within the middleware of the target OS (the sensor framework), and
also provides a kernel device driver to interface with the physical device. This directly benefits application
developers by providing a cohesive set of APIs and a well-defined sensor data path in the user-space.
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
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The table below describes the MotionApps software solutions included with the InvenSense MPU and IMU
product families.
InvenSense MotionProcessor Devices and Included MotionApps Software
Included Software
Feature
MotionApps
Embedded
MotionApps
MotionApps
Lite
Embedded
MotionApps
Lite
None
Part Number
MPU-3050
MPU-6050
IMU-3000
ITG-3050
Processor Type
Mobile
Application
Processor
8/16/32-bit
Microcontroller
Mobile
Application
Processor
8/16/32-bit
Microcontroller
N/A
Applications
Smartphones,
tablets
TV remotes,
health/fitness,
toys, other
embedded
Smartphones,
tablets
TV remotes,
health/fitness,
toys, other
embedded
N/A
6-Axis MotionFusion
Yes
Yes
No
9-Axis MotionFusion
Yes
No
No
Gyro Bias Calibration
Yes
Yes
No
3rd Party Compass Cal
API
Yes
No
No
Gyro-Assisted Compass
Calibration (Fast Heading)
Yes
No
No
Magnetic Anomaly
Rejection
(Improved Heading)
Yes
No
No
The table below lists recommended documentation for the MotionApps software solutions.
Software Documentation
Platform
MotionApps and MotionApps Lite
Embedded MotionApps and
Embedded MotionApps Lite
Software
Documentation
Installation Guide for Linux and Android
MotionApps Platform, v1.9 or later
Embedded MotionApps Platform
User Guide, v3.0 or later
MPL Functional Specifications
Embedded MPL Functional
Specifications
For more information about the InvenSense MotionApps Platform, please visit the Developer’s Corner or
consult your local InvenSense Sales Representative.
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
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1.5 Applications
Motion-enabled game controllers
Handheld gaming
Handset User Interface
Motion-based Digital TV and Set Top Box remote controls
Location based services, points of interest, and dead reckoning
Improved camera image quality through image stabilization
Health and sports monitoring
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
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2 Features
The ITG-3050 triple-axis MEMS gyroscope includes a wide range of features:
2.1 Sensors
X-, Y-, Z-Axis angular rate sensors (gyros) on one integrated circuit
Digital-output temperature sensor
External sync signal connected to the FSYNC pin supports image, video and GPS
synchronization
Secondary I2C interface directly connects to a digital 3-axis 3rd-party accelerometer
Factory calibrated scale factor
High cross-axis isolation via proprietary MEMS design
10,000g shock tolerant
2.2 Digital Output
Fast Mode (400kHz) I2C serial interface
16-bit ADCs for digitizing sensor outputs
Angular rate sensors (gyros) with user-programmable full-scale-range of ±250°/sec, ±500°/sec,
±1000°/sec, or ±2000°/sec.
2.3 Data Processing
When used together with a 3rd-party digital 3-axis accelerometer, the ITG-3050 collects the
accelerometer data via a dedicated sensor interface, while synchronizing data sampling at a user
defined rate. The total data set obtained by the ITG-3050 includes 3-axis gyroscope data, 3-axis
accelerometer data, temperature data, and the one bit external sync signal connected to the
FSYNC pin. The ITG-3050 also downloads the results calculated by the digital 3-axis 3rd party
accelerometer internal registers.
FIFO buffers complete data set, reducing timing requirements on the system processor and
saving power by letting the processor burst read the FIFO data, and then go into a low-power
sleep mode while the ITG-3050 collects more data.
Programmable interrupt
Programmable low-pass filters
2.4 Clocking
On-chip timing generator clock frequency ±1% drift over full temperature range
Optional external clock inputs of 32.768kHz or 19.2MHz
1MHz clock output to synchronize with digital 3-axis accelerometer
2.5 Power
VDD supply voltage range of 2.1V to 3.6V
Flexible VLOGIC reference voltage allows for multiple I2C interface voltage levels
Power consumption with all three axis active: 5.9mA
Sleep mode: 5μA
Each axis can be individually powered down
2.6 Package
4x4x0.9mm QFN plastic package
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
9 of 42
3 Electrical Characteristics
3.1 Sensor Specifications
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VLOGIC = 2.5V, TA=25°C.
Parameter
Conditions
Min
Typical
Max
Unit
Notes
GYRO SENSITIVITY
Full-Scale Range
FS_SEL=0
±250
º/s
4, 7
FS_SEL=1
±500
4, 7
FS_SEL=2
±1000
4, 7
FS_SEL=3
±2000
4, 7
Gyro ADC Word Length
16
bits
3
Sensitivity Scale Factor
FS_SEL=0
FS_SEL=1
FS_SEL=2
FS_SEL=3
131
65.5
32.8
16.4
LSB/(º/s)
1
3
3
3
Sensitivity Scale Factor Tolerance
25°C
-6
±2
+6
%
1
Sensitivity Scale Factor Variation Over
Temperature
-40°C to +85°C
±2
%
8
Nonlinearity
Best fit straight line; 25°C
0.2
%
6
Cross-Axis Sensitivity
2
%
6
GYRO ZERO-RATE OUTPUT (ZRO)
Initial ZRO Tolerance
25°C
±20
º/s
1
ZRO Variation Over Temperature
-40°C to +85°C
±0.03
º/s/ºC
8
Power-Supply Sensitivity (1-10Hz)
Sine wave, 100mVpp; VDD=2.2V
0.2
º/s
5
Power-Supply Sensitivity (10 - 250Hz)
Sine wave, 100mVpp; VDD=2.2V
0.2
º/s
5
Power-Supply Sensitivity (250Hz -
100kHz)
Sine wave, 100mVpp; VDD=2.2V
4
º/s
5
Linear Acceleration Sensitivity
Static
0.1
º/s/g
6
GYRO NOISE PERFORMANCE
FS_SEL=0
Total RMS Noise
DLPFCFG=2 (100Hz)
0.1
º/s-rms
1
Low-frequency RMS noise
Bandwidth 1Hz to10Hz
0.033
º/s-rms
1
Rate Noise Spectral Density
At 10Hz
0.01
º/s/√Hz
3
GYRO MECHANICAL FREQUENCIES
X-Axis
30
33
36
kHz
1
Y-Axis
27
30
33
kHz
1
Z-Axis
24
27
30
kHz
1
GYRO START-UP TIME
DLPFCFG=0
ZRO Settling
to ±1º/s of Final
50
ms
5
TEMPERATURE SENSOR
Range
Sensitivity
Untrimmed
-30 to 85
280
ºC
LSB/ºC
2
2
Room-Temperature Offset
35°C
-13200
LSB
1
Linearity
Best fit straight line (-30°C to +85°C)
±1
°C
2
TEMPERATURE RANGE
Specified Temperature Range
-40
85
ºC
2
Notes:
1. Tested in production
2. Based on characterization of 30 parts over temperature on evaluation board or in socket
3. Based on design, through modeling, and simulation across PVT
4. Typical. Randomly selected part measured at room temperature on evaluation board or in socket
5. Based on characterization of 5 parts over temperature
6. Tested on 20 parts at room temperature
7. Part is characterized to Full-Scale Range. Maximum ADC output is [216 / (Sensitivity x 2)]
Example: For Sensitivity of 131 LSB/(º/s), [216 / (131 x 2)] = ±250 º/s.
8. Based on characterization of 48 parts on evaluation board or in socket
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
10 of 42
3.2 Electrical Specifications
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VLOGIC = 2.5V, TA = 25°C.
Parameters
Conditions
Min
Typical
Max
Units
Notes
VDD POWER SUPPLY
Operating Voltage Range
2.1
3.6
V
2
Power-Supply Ramp Rate
Monotonic ramp. Ramp
rate is 10% to 90% of the
final value (see Figure in
Section 4.4)
0
5
ms
2
Normal Operating Current
5.9
mA
1
Sleep Mode Current
5
µA
4
VLOGIC REFERENCE VOLTAGE
(must be regulated)
Voltage Range
VLOGIC must be ≤VDD at
all times
1.71
VDD
V
3, 5
Power-Supply Ramp Rate
Monotonic ramp. Ramp
rate is 10% to 90% of the
final value
1
ms
3, 5
Normal Operating Current
(see Figure in Section 4.4)
Does not include pull up
resistor current draw as
that is system dependent
100
µA
4
START-UP TIME FOR REGISTER
READ/WRITE
20
100
ms
4
I2C ADDRESS
AD0 = 0
AD0 = 1
1101000
1101001
1
DIGITAL INPUTS (SDI, SCLK,
FSYNC, AD0, /CS, CLKIN)
VIH, High Level Input Voltage
VIL, Low Level Input Voltage
CI, Input Capacitance
0.7*VLOGIC
< 5
0.3*VLOGIC
V
V
pF
4
4
6
DIGITAL OUTPUT (INT)
VOH, High Level Output Voltage
VOL1, LOW-Level Output Voltage
VOL.INT1, INT Low-Level Output Voltage
Output Leakage Current
tINT, INT Pulse Width
RLOAD=1MΩ
RLOAD=1MΩ
OPEN=1, 0.3mA sink
current
OPEN=1
LATCH_INT_EN=0
0.9*VLOGIC
100
50
0.1*VLOGIC
0.1
V
V
V
nA
µs
2
2
2
3
3
DIGITAL OUPUT (CLKOUT)
VOH, High Level Output Voltage
VOL1, Low Level Output Voltage
RLOAD=1MΩ
RLOAD=1MΩ
0.9*VDD
0.1*VDD
V
V
2
2
Notes:
1. Tested in production
2. Based on characterization of 30 parts over temperature on evaluation board or in socket
3. Typical. Randomly selected part measured at room temperature on evaluation board or in socket
4. Based on characterization of 5 parts over temperature
5. Refer to Section 4.4 for the recommended power-on procedure
6. Guaranteed by design
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
11 of 42
3.3 Electrical Specifications, continued
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VLOGIC = 2.5V, TA=25°C.
Parameters
Conditions
Typical
Units
Notes
Primary I2C I/O (SCL, SDA)
VIL, LOW Level Input Voltage
-0.5V to 0.3*VLOGIC
V
1
VIH, HIGH-Level Input Voltage
0.7*VLOGIC to VLOGIC +
0.5V
V
1
Vhys, Hysteresis
0.1*VLOGIC
V
1
VOL1, LOW-Level Output Voltage
3mA sink current
0 to 0.4
V
1
IOL, LOW-Level Output Current
VOL = 0.4V
VOL = 0.6V
3
5
mA
mA
1
1
Output Leakage Current
100
nA
2
tof, Output Fall Time from VIHmax to VILmax
Cb bus capacitance in
pf
20+0.1Cb to 250
ns
1
CI, Capacitance for Each I/O pin
< 10
pF
3
Secondary I2C I/O (AUX_CL,
AUX_DA)
AUX_VDDIO=0
VIL, LOW-Level Input Voltage
-0.5V to 0.3*VLOGIC
V
1
VIH, HIGH-Level Input Voltage
0.7*VLOGIC to
VLOGIC + 0.5V
V
1
Vhys, Hysteresis
0.1*VLOGIC
V
1
VOL1, LOW-Level Output Voltage
VLOGIC > 2V; 1mA sink
current
0 to 0.4
V
1
VOL3, LOW-Level Output Voltage
VLOGIC < 2V; 1mA sink
current
0 to 0.2*VLOGIC
V
1
IOL, LOW-Level Output Current
VOL = 0.4V
VOL = 0.6V
1
1
mA
mA
1
1
Output Leakage Current
100
nA
2
tof, Output Fall Time from VIHmax to VILmax
Cb bus capacitance in
pF
20+0.1Cb to 250
ns
1
CI, Capacitance for Each I/O pin
< 10
pF
3
Secondary I2C I/O (AUX_CL,
AUX_DA)
AUX_VDDIO=1
VIL, LOW-Level Input Voltage
-0.5 to 0.3*VDD
V
1
VIH, HIGH-Level Input Voltage
0.7*VDD to VDD+0.5V
V
1
Vhys, Hysteresis
0.1*VDD
V
1
VOL1, LOW-Level Output Voltage
1mA sink current
0 to 0.4
V
1
IOL, LOW-Level Output Current
VOL = 0.4V
VOL = 0.6V
1
1
mA
mA
1
1
Output Leakage Current
100
nA
2
tof, Output Fall Time from VIHmax to VILmax
Cb bus cap. in pF
20+0.1Cb to 250
ns
1
CI, Capacitance for Each I/O pin
< 10
pF
3
Notes:
1. Based on characterization of 5 parts over temperature.
2. Typical. Randomly selected part measured at room temperature on evaluation board or in socket
3. Guaranteed by design
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
12 of 42
3.4 Electrical Specifications, continued
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VLOGIC = 2.5V, TA=25°C.
Parameters
Conditions
Min
Typical
Max
Units
Notes
INTERNAL CLOCK SOURCE
CLK_SEL=0,1,2,3
Sample Rate, Fast
DLPFCFG=0
SAMPLERATEDIV = 0
8
kHz
3
Sample Rate, Slow
DLPFCFG=1,2,3,4,5, or 6
SAMPLERATEDIV = 0
1
kHz
3
Reference Clock Output
CLKOUTEN = 1
1.024
MHz
3
Clock Frequency Initial Tolerance
CLK_SEL=0, 25°C
-5
+5
%
1
CLK_SEL=1,2,3; 25°C
-1
+1
%
1
Frequency Variation over Temperature
CLK_SEL=0
-15 to +10
%
2
CLK_SEL=1,2,3
+/-1
%
2
PLL Settling Time
CLK_SEL=1,2,3
1
ms
4
EXTERNAL 32.768kHz CLOCK
CLK_SEL=4
External Clock Frequency
32.768
kHz
4
External Clock Jitter
Cycle-to-cycle rms
1 to 2
µs
4
Sample Rate, Fast
DLPFCFG=0
SAMPLERATEDIV = 0
8.192
kHz
4
Sample Rate, Slow
DLPFCFG=1,2,3,4,5, or 6
SAMPLERATEDIV = 0
1.024
kHz
4
Reference Clock Output
CLKOUTEN = 1
1.0486
MHz
4
PLL Settling Time
1
ms
4
EXTERNAL 19.2MHz CLOCK
CLK_SEL=5
External Clock Frequency
19.2
MHz
4
Sample Rate, Fast
DLPFCFG=0
SAMPLERATEDIV = 0
8
kHz
4
Sample Rate, Slow
DLPFCFG=1,2,3,4,5, or 6
SAMPLERATEDIV = 0
1
kHz
4
Reference Clock Output
CLKOUTEN = 1
1.024
MHz
4
PLL Settling Time
1
ms
4
Notes:
1. Tested in production
2. Based on characterization of 30 parts over temperature on evaluation board or in socket
3. Typical. Randomly selected part measured at room temperature on evaluation board or in socket
4. Based on design, through modeling, and simulation across PVT
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
13 of 42
3.5 I2C Timing Characterization
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VLOGIC = 1.8V±5%, 2.5V±5%, 3.0V±5%, or 3.3V±5%,
TA=25°C.
Parameters
Conditions
Min
Typical
Max
Units
Notes
I2C TIMING
I2C FAST-MODE
fSCL, SCL Clock Frequency
0
400
kHz
1
tHD.STA, (Repeated) START Condition
Hold Time
0.6
µs
1
tLOW, SCL Low Period
1.3
µs
1
tHIGH, SCL High Period
0.6
µs
1
tSU.STA, Repeated START Condition
Setup Time
0.6
µs
1
tHD.DAT, SDA Data Hold Time
0
µs
1
tSU.DAT, SDA Data Setup Time
100
ns
1
tr, SDA and SCL Rise Time
Cb bus cap. from 10 to
400pF
20+0.1
Cb
300
ns
1
tf, SDA and SCL Fall Time
Cb bus cap. from 10 to
400pF
20+0.1
Cb
300
ns
1
tSU.STO, STOP Condition Setup Time
0.6
µs
1
tBUF, Bus Free Time Between STOP and
START Condition
1.3
µs
1
Cb, Capacitive Load for each Bus Line
< 400
pF
3
tVD.DAT, Data Valid Time
0.9
µs
1
tVD.ACK, Data Valid Acknowledge Time
0.9
µs
1
Notes:
1. Based on characterization of 5 parts over temperature on evaluation board or in socket
2. S = Start Condition, P = Stop Condition, Sr = Repeated Start Condition
3. Guaranteed by design
I2C Bus Timing Diagram
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
14 of 42
3.6 Absolute Maximum Ratings
Stress above those listed as Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these conditions is not implied.
Exposure to the absolute maximum ratings conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
Parameter
Rating
Supply Voltage, VDD
-0.5V to +6V
VLOGIC Input Voltage Level
-0.5V to VDD + 0.5V
REGOUT
-0.5V to 2V
Input Voltage Level (CLKIN, AUX_DA, AD0,
FSYNC, INT, SCL, SDA)
-0.5V to VDD + 0.5V
CPOUT (2.1V ≤ VDD ≤ 3.6V )
-0.5V to 30V
Acceleration (Any Axis, unpowered)
10,000g for 0.3ms
Operating Temperature Range
-40°C to +105°C
Storage Temperature Range
-40°C to +125°C
Electrostatic Discharge (ESD) Protection
1.5kV (HBM); 200V (MM)
Latch-up
JEDEC Class II (2),125°C
Level B, ±60mA
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
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4 Applications Information
4.1 Pin Out and Signal Description
Pin Number
Pin Name
Pin Description
1
CLKIN
External reference clock input. Connect to GND if not used.
6
AUX_DA
Interface to a 3rd party accelerometer, SDA pin. Logic levels are set to be
either VDD or VLOGIC. See Section 6 for more details.
7
AUX_CL
Interface to a 3rd party accelerometer, SCL pin. Logic levels are set to be
either VDD or VLOGIC. See Section 6 for more details.
8
VLOGIC
Digital I/O supply voltage. VLOGIC must be ≤ VDD at all times.
9
AD0
I2C Slave Address LSB
10
REGOUT
Regulator filter capacitor connection
11
FSYNC
Frame synchronization digital input. Connect to GND if not used.
12
INT
Interrupt digital output (totem pole or open-drain)
13
VDD
Power supply voltage and Digital I/O supply voltage
18
GND
Power supply ground
19
RESV
Reserved. Do not connect.
20
CPOUT
Charge pump capacitor connection
21
RESV
Reserved. Do not connect.
22
CLKOUT
1MHz clock output for 3rd-party accelerometer synchronization
23
SCL
I2C serial clock
24
SDA
I2C serial data
2, 3, 4, 5, 14,
15, 16, 17
NC
Not internally connected. May be used for PCB trace routing.
7 8 9 10 11 12
AUX_CL
VLOGIC
AD0
REGOUT
FSYNC
INT
13
18
17
16
15
14
NC
NC
NC
VDD
NC
GND
6
1
2
3
4
5
NC
NC
NC
AUX_DA
NC
CLKIN
24 23 22 21 20 19
RESV
CPOUT
RESV
CLKOUT
SCL
SDA
ITG-3050
QFN Package (Top View)
24-pin, 4mm x 4mm x 0.9mm Orientation of Axes of Sensitivity
and Polarity of Rotation
ITG-3050
+Z
+X+Y
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
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4.2 Typical Operating Circuit
Typical Operating Circuit
AD0
7 8 9 10 11 12
13
18
17
16
15
14
6
1
2
3
4
5
24 23 22 21 20 19
ITG-3050
CLKIN
GND
GND
GND
FSYNC
INT
GND
VDD
SCL
SDA
C3
2.2nF
C1
0.1µF
C2
0.1µF
GND
VLOGIC
C4
10nF
AUX_CL
AUX_DA
CLKOUT
4.3 Bill of Materials for External Components
Component
Label
Specification
Quantity
Regulator Filter Capacitor
C1
Ceramic, X7R, 0.1µF ±10%, 2V
1
VDD Bypass Capacitor
C2
Ceramic, X7R, 0.1µF ±10%, 4V
1
Charge Pump Capacitor
C3
Ceramic, X7R, 2.2nF ±10%, 50V
1
VLOGIC Bypass Capacitor
C4
Ceramic, X7R, 10nF ±10%, 4V
1
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
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4.4 Recommended Power-on Procedure
TVLGR
VLOGIC
VDD
TVDDR
All Voltages at 0V
Power-Up Sequencing
1. TVDDR is VDD rise time: Time for VDD to
rise from 10% to 90% of its final value
2. TVDDR is ≤5ms
3. TVLGR is VLOGIC rise time: Time for
VLOGIC to rise from 10% to 90% of its
final value
4. TVLGR is ≤1ms
5. TVLG-VDD is the delay from the start of
VDD ramp to the start of VLOGIC rise
6. TVLG-VDD is 0ms; VLOGIC amplitude
must always be ≤VDD amplitude
7. VDD and VLOGIC must be monotonic
ramps
90%
10%
90%
10%
TVLG - VDD
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
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5 Functional Overview
5.1 Block Diagram
CLOCK ITG-3050
Charge
Pump
AD0
SCL
SDA
Temp
Sensor ADC
ADCZ Gyro Signal
Conditioning
ADCY Gyro Signal
Conditioning
ADCX Gyro Signal
Conditioning
FSYNC
22
1
8
9
23
24
11
Primary
I2C Serial
Interface
Secondary
I2C Serial
Interface
Config
Register
Clock
CPOUT
Secondary
Interface
Bypass
Mux
7
6
AUX_CL
AUX_DA
INT
12
Sensor
Register
20
OTP
FIFO
Interrupt
Status
Register
VDD
Bias & LDO
GND REGOUT
13 18 10
VLOGIC
8
CLKIN
CLKOUT
5.2 Overview
The ITG-3050 is comprised of the following key blocks / functions:
Three-axis MEMS rate gyroscope sensors with 16-bit ADCs and signal conditioning
Primary I2C serial communications interfaces
Secondary I2C serial interface for 3rd party accelerometer
Clocking
Sensor Data Registers
FIFO
Interrupts
Digital-Output Temperature Sensor
Bias and LDO
Charge Pump
5.3 Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning
The ITG-3050 consists of three independent vibratory MEMS rate gyroscopes, which detect rotation about
the X, Y, and Z axes. When the gyros are rotated about any of the sense axes, the Coriolis Effect causes a
vibration that is detected by a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered
to produce a voltage that is proportional to the angular rate. This voltage is digitized using individual on-chip
16-bit Analog-to-Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro sensors
may be digitally programmed to ±250, ±500, ±1000, or ±2000 degrees per second (dps). ADC sample rate is
programmable from 8,000 samples per second, down to 3.9 samples per second, and user-selectable low-
pass filters enable a wide range of cut-off frequencies.
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Revision: 1.3
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5.4 Primary I2C Serial Communications Interface
The ITG-3050 has a primary I2C serial primary interface. ITG-3050 always acts as a slave when
communicating to the system processor. The logic level for communications to the master is set by the
voltage on the VLOGIC pin. The LSB of the of the I2C slave address is set by pin 9 (AD0).
The I2C protocol is described in more detail in Section 6.
Note: When VDD is low, the primary I2C interface pins become low impedance and thus can load the serial
bus. This is a concern if other devices are active on the bus during this time.
5.5 Secondary I2C Serial Interface (for 3rd-party Accelerometers)
The ITG-3050 has a secondary I2C bus for communicating to an off-chip 3-axis digital output accelerometer.
This bus has two operating modes: I2C Master Mode, where the ITG-3050 acts as a master to an external
accelerometer connected to the secondary I2C bus; and Pass-Through Mode, where the ITG-3050 directly
connects the primary and secondary I2C buses together, to allow the system processor to directly
communicate with the external accelerometer.
Secondary I2C Bus Modes of Operation:
I2C Master Mode: allows the ITG-3050 to directly access the data registers of an external digital
accelerometer. In this mode, the ITG-3050 directly obtains sensor data from accelerometers without
intervention from the system applications processor. In I2C master mode, the ITG-3050 can be
configured to perform burst reads, returning the following data from the accelerometer:
X accelerometer data (2 bytes)
Y accelerometer data (2 bytes)
Z accelerometer data (2 bytes)
Pass-Through Mode: allows an external system processor to act as master and directly
communicate to the external accelerometer connected to the secondary I2C bus pins (AUX_DA and
AUX_CL). This is useful for configuring the accelerometers, or for keeping the ITG-3050 in a low-
power mode, when only accelerometers are to be used. In this mode, the secondary I2C bus control
logic (3rd-party accelerometer Interface block) of the ITG-3050 is disabled, and the secondary I2C
pins AUX_DA and AUX_CL (Pins 6 and 7) are connected to the main I2C bus (Pins 23 and 24)
through analog switches.
In the pass through mode the system processor can still access ITG-3050 data through the I2C
interface.
Secondary I2C Bus IO Logic Levels
The logic levels of the secondary I2C bus can be programmed to be either VDD or VLOGIC (see Sections 6
and 7).
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
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Secondary I2C Bus Internal Pull-up Configuration
I2C Master Mode Equivalent Circuit: The simplified equivalent circuit diagram below shows the ITG-
3050 auxiliary I²C interface while in master mode. It should be noted that the AUX_CL pin is an
output only and is driven by a CMOS output buffer which does not require a pull-up resistor. The
AUX_DA pin is open drain and an internal pull-up resistor is used. The CMOS output buffer and the
pull up resistor can be powered from VDD or VLOGIC. Please refer to Section 7.2 for more details.
P
N
ITG-3050
VLOGIC/VDD
AUX_CL
AUX_DA
PULLUP
Equivalent
~2.5k Ohm
ITG-3050 I2C Master Mode auxiliary I2C interface equivalent circuit
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
21 of 42
Pass-Through Mode Equivalent Circuit: The simplified equivalent circuit diagram below shows the
ITG-3050 I²C interface during pass-through mode. Internal analog switches are used to connect the
primary and auxiliary I²C interfaces together (SCL to AUX_CL through a buffer and SDA to AUX_DA
pins through a level shifter).
ITG-3050
VLOGIC/VDD
AUX_CL
AUX_DA
SCL
SDA
Analog
switch
Analog
switch
Level
Shifter
Circuit
VLOGIC/VDD
ITG-3050 Pass-Through Mode Equivalent Circuit
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
22 of 42
5.6 3rd Party Accelerometer Configurations
There are two options for connecting a 3rd party accelerometer to the system comprised of the ITG-3050 and
the application processor.
5.6.1 3rd Party Accelerometer on ITG-3050 Auxiliary I2C Bus
The diagram below shows the accelerometer connected to the Auxiliary I2C bus of the ITG-3050. In this
configuration, the application processor can communicate to the accelerometer directly by putting the ITG-
3050 into Pass-Through Mode. Alternatively, the ITG-3050 can collect the accelerometer data and send it to
the application processor.
For further information regarding I2C Master Mode and Pass-Through Mode, please refer to Section 5.5.
This configuration is useful since it provides a pin-compatible upgrade path to the MPU-3000 or IMU-3000
family of products, which feature an on-board Digital Motion Processor for MotionProcessing. The upgrade
provides access to the software solutions described in Section 1.4.
Digital
Accelerometer ITG-3050 Applications
Processor
I2C I2C
5.6.2 3rd Party Accelerometer Connected to ITG-3050 Primary I2C Interface
The diagram below shows the accelerometer connected to the Primary I2C Bus of the ITG-3050. In this
configuration, the applications processor can directly address the accelerometer via the I2C bus. However,
an upgrade to the MPU-3000 or IMU-3000 family of products will require a new board layout.
Digital
Accelerometer
ITG-3050 Applications
Processor
I2C
5.7 Internal Clock Generation
The ITG-3050 has a flexible clocking scheme, allowing for a variety of internal or external clock sources for
the internal synchronous circuitry. This synchronous circuitry includes the signal conditioning and ADCs,
various control circuits, and registers. An on-chip PLL provides flexibility in the allowable inputs for
generating this clock.
Allowable internal sources for generating the internal clock are:
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
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An internal relaxation oscillator
Any of the X, Y, or Z gyros (MEMS oscillators with a drift of only ±1% over temperature)
Allowable external clocking sources are:
32.768kHz square wave
19.2MHz square wave
Which source to select for generating the internal synchronous clock depends on the availability of external
sources and the requirements for power consumption and clock accuracy. Most likely, these requirements
will vary by mode of operation. For example, in a mode where the gyros are active, selecting the gyros as
the clock source provides for a more-accurate clock source.
There are also start-up conditions to consider. When the ITG-3050 first starts up, the device operates off of
its internal clock, until programmed to operate from another source. This allows the user, for example, to
wait for the MEMS oscillators to stabilize before they are selected as the clock source.
5.8 Clock Output
In addition, the ITG-3050 provides a clock output, which allows the device to operate synchronously with an
external digital 3-axis accelerometer. Operating synchronously provides for higher-quality data, since the
sampling instant for the sensor data can be set to be coincident for all sensors.
5.9 Sensor Data Registers
The sensor data registers contain the latest gyro and temperature data. They are read-only registers, and
are accessed via the Serial Interface. Data from these registers may be read anytime, however, the interrupt
function may be used to determine when new data is available.
5.10 FIFO
The ITG-3050 contains a 512-byte FIFO register that is accessible via the Serial Interface. The FIFO
configuration register determines what data goes into it, with possible choices being gyro data,
accelerometer data, temperature readings, and FSYNC input. A FIFO counter keeps track of how many
bytes of valid data are contained in the FIFO. The FIFO register supports burst reads. The interrupt function
may be used to determine when new data is available.
5.11 Interrupts
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include
the INT pin configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that
can trigger an interrupt are (1) Clock generator locked to new reference oscillator (used when switching clock
sources); (2) new data is available to be read (from the FIFO and Data registers); and (3) the ITG-3050 did
not receive an acknowledge from the accelerometer on the Secondary I2C bus. The interrupt status can be
read from the Interrupt Status register.
5.12 Digital-Output Temperature Sensor
An on-chip temperature sensor and ADC are used to measure the ITG-3050 die temperature. The readings
from the ADC can be read from the FIFO or the Sensor Data registers.
5.13 Bias and LDO
The bias and LDO section generates the internal supply and the reference voltages and currents required by
the ITG-3050. Its two inputs are an unregulated VDD of 2.1V to 3.6V and a VLOGIC logic reference supply
voltage of 1.71V to VDD. The LDO output is bypassed by a 0.1µF capacitor at REGOUT.
5.14 Charge Pump
An on-board charge pump generates the high voltage required for the MEMS oscillators. Its output is
bypassed by a 2.2nF capacitor at CPOUT.
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
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6 Digital Interface
6.1 I2C Serial Interface
The internal registers and memory of the ITG-3050 can be accessed using the I2C interface.
Serial Interface
Pin Number
Pin Name
Pin Description
8
VLOGIC
Digital I/O supply voltage. VLOGIC must be VDD at all
times.
9
AD0
I2C Slave Address LSB
23
SCL
I2C serial clock
24
SDA
I2C serial data
6.1.1 I2C Interface
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the
lines are open-drain and bi-directional. In a generalized I2C interface implementation, attached devices can
be a master or a slave. The master device puts the slave address on the bus, and the slave device with the
matching address acknowledges the master.
The ITG-3050 always operates as a slave device when communicating to the system processor, which thus
acts as the master. SDA and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is
400kHz.
The slave address of the ITG-3050 is b110100X which is 7 bits long. The LSB bit of the 7 bit address is
determined by the logic level on pin AD0. This allows two ITG-3050s to be connected to the same I2C bus.
When used in this configuration, the address of the one of the devices should be b1101000 (pin AD0 is logic
low) and the address of the other should be b1101001 (pin AD0 is logic high). The I2C address is stored in
WHO_AM_I register.
I2C Communications Protocol
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is
defined as a HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is
considered to be busy until the master puts a STOP condition (P) on the bus, which is defined as a LOW to
HIGH transition on the SDA line while SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
SDA
SCL S
START condition STOP condition
P
START and STOP Conditions
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Data Format / Acknowledge
I2C data bytes are defined to be 8 bits long. There is no restriction to the number of bytes transmitted per
data transfer. Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the
acknowledge signal is generated by the master, while the receiver generates the actual acknowledge signal
by pulling down SDA and holding it low during the HIGH portion of the acknowledge clock pulse.
If a slave is busy and is unable to transmit or receive another byte of data until some other task has been
performed, it can hold SCL LOW, thus forcing the master into a wait state. Normal data transfer resumes
when the slave is ready, and releases the clock line (refer to the following figure).
DATA OUTPUT BY
TRANSMITTER (SDA)
DATA OUTPUT BY
RECEIVER (SDA)
SCL FROM
MASTER
START
condition
clock pulse for
acknowledgement
acknowledge
not acknowledge
1 2 8 9
Acknowledge on the I2C Bus
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address
followed by an 8th bit, the read/write bit. The read/write bit indicates whether the master is receiving data from
or is writing to the slave device. Then, the master releases the SDA line and waits for the acknowledge
signal (ACK) from the slave device. Each byte transferred must be followed by an acknowledge bit. To
acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of the SCL line.
Data transmission is always terminated by the master with a STOP condition (P), thus freeing the
communications line. However, the master can generate a repeated START condition (Sr), and address
another slave without first generating a STOP condition (P). A LOW to HIGH transition on the SDA line while
SCL is HIGH defines the stop condition. All SDA changes should take place when SCL is low, with the
exception of start and stop conditions.
SDA
START
condition
SCL
ADDRESS R/W ACK DATA ACK DATA ACK STOP
condition
S P
1 7 8 9 1 7 8 9 1 7 8 9
Complete I2C Data Transfer
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
26 of 42
To write the internal ITG-3050 registers, the master transmits the start condition (S), followed by the I2C
address and the write bit (0). At the 9th clock cycle (when the clock is high), the ITG-3050 acknowledges the
transfer. Then the master puts the register address (RA) on the bus. After the ITG-3050 acknowledges the
reception of the register address, the master puts the register data onto the bus. This is followed by the ACK
signal, and data transfer may be concluded by the stop condition (P). To write multiple bytes after the last
ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the
ITG-3050 automatically increments the register address and loads the data to the appropriate register. The
following figures show single and two-byte write sequences.
Single-Byte Write Sequence
Burst Write Sequence
To read the internal ITG-3050 registers, the master sends a start condition, followed by the I2C address and
a write bit, and then the register address that is going to be read. Upon receiving the ACK signal from the
ITG-3050, the master transmits a start signal followed by the slave address and read bit. As a result, the
ITG-3050 sends an ACK signal and the data. The communication ends with a not acknowledge (NACK)
signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high at the
9th clock cycle. The following figures show single and two-byte read sequences.
Single-Byte Read Sequence
Burst Read Sequence
Master
S
AD+W
RA
DATA
P
Slave
ACK
ACK
ACK
Master
S
AD+W
RA
DATA
DATA
P
Slave
ACK
ACK
ACK
ACK
Master
S
AD+W
RA
S
AD+R
NACK
P
Slave
ACK
ACK
ACK
DATA
Master
S
AD+W
RA
S
AD+R
ACK
NACK
P
Slave
ACK
ACK
ACK
DATA
DATA
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
27 of 42
I2C Terms
Signal
Description
S
Start Condition: SDA goes from high to low while SCL is high
AD
Slave I2C address
W
Write bit (0)
R
Read bit (1)
ACK
Acknowledge: SDA line is low while the SCL line is high at the 9th clock cycle
NACK
Not-Acknowledge: SDA line stays high at the 9th clock cycle
RA
ITG-3050 internal register address
DATA
Transmit or received data
P
Stop condition: SDA going from low to high while SCL is high
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
28 of 42
7 Serial Interface Considerations
7.1 ITG-3050 Supported Interfaces
The ITG-3050 supports I2C communications on both its primary (microprocessor) serial interface and its
secondary (accelerometer) interface.
7.2 Logic Levels
The ITG-3050 I/O logic levels are set to be either VDD or VLOGIC, as shown in the table below.
I/O Logic Levels vs. AUX_VDDIO (Secondary I2C Bus IO Level)
AUX_VDDIO
MICROPROCESSOR LOGIC LEVELS
(Pins: SDA, SCL, AD0, CLKIN, INT, FSYNC)
ACCELEROMETER LOGIC LEVELS
(Pins: AUX_DA, AUX_CL)
0
VLOGIC
VLOGIC
1
VLOGIC
VDD
Notes:
1. CLKOUT has logic levels that are always referenced to VDD
2. The power-on-reset value for AUX_VDDIO is 0.
VLOGIC may be set to be equal to VDD or to another voltage, such that at all times VLOGIC is VDD.
When AUX_VDDIO is set to 0 (its power-on-reset value), VLOGIC is the power supply voltage for both the
microprocessor system bus and the accelerometer secondary bus, as shown in the figure of Section 7.2.1.
When AUX_VDDIO is set to 1, VLOGIC is the power supply voltage for the microprocessor system bus and
VDD is the supply for the accelerometer secondary bus, as shown in the figure of Section 7.2.2.
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
29 of 42
7.2.1 AUX_VDDIO = 0
The figure below shows logic levels and voltage connections for AUX_VDDIO = 0. Note: Actual configuration
will depend on the type of 3rd-party accelerometer used.
ITG-3050
3rd Party
Accel
SDA
AUX_CL SCL
AUX_DA
VDD_IO
VDD
VDD
SA0
CS
INT 2
INT 1
System
Processor
CLKIN
SYSTEM BUS
VLOGIC
VLOGIC
VLOGIC
VDD
VDD
VLOGIC
(0V - VLOGIC)
CLKOUT
SCL
SDA
INT
FSYNC
VLOGIC
AD0 (0V - VLOGIC)
(0V - VLOGIC)
(0V - VLOGIC)
(0V - VLOGIC)
(0V - VLOGIC)
Notes:
1. AUX_VDDIO is bit 7 in Register 24, and determines the IO voltage levels of AUX_DA and AUX_CL (0 = set
output levels relative to VLOGIC)
2. CLKOUT is always referenced to VDD
3. Other ITG-3050 logic IO are always referenced to VLOGIC
(0V - VLOGIC)
(0V - VLOGIC)
(0V - VLOGIC)
(0V - VLOGIC)
0V - VDD
(0V, VLOGIC)
No connect
(0V, VLOGIC)
SCL
SDA
I/O Levels and Connections for AUX_VDDIO = 0
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
30 of 42
7.2.2 AUX_VDDIO = 1
When AUX_VDDIO is set to 1 by the user, VLOGIC is the power supply voltage for the microprocessor
system bus and VDD is the power supply for the accelerometer secondary bus, as shown in the figure below.
This is useful when interfacing to a 3rd-party accelerometer where there is only one supply for both the logic
and analog sections of the 3rd party accelerometer.
ITG-3050
3rd Party
Accel
SDA
AUX_CL SCL
AUX_DA
VDD
VDD
ADDR
INT 2
INT 1
System
Processor
CLKIN
SYSTEM BUS
VLOGIC
VDD
Configuration 1 Configuration 2
1.8V±5%
2.5V±5% 3.0V±5%
3.0V±5%
Voltage/
Configuration
VLOGIC
VLOGIC
VDD
VDD
VLOGIC
CLKOUT
SCL
SDA
INT
FSYNC
VLOGIC
AD0
(0V - VLOGIC)
(0V - VLOGIC)
(0V - VLOGIC)
(0V - VLOGIC)
AUX_VDDIO 1 1
Notes:
1. AUX_VDDIO is bit 7 in Register 24, and determines the IO voltage levels of AUX_DA and
AUX_CL (1 = set output levels relative to VDD)
2. CLKOUT is always referenced to VDD
3. Other ITG-3050 logic IO are always referenced to VLOGIC
4. Third-party accelerometer logic levels are referenced to VDD; setting INT1 and INT2 to open-
drain configuration provides voltage compatibility when VDD ≠ VLOGIC.
When VDD = VLOGIC, INT1 and INT2 may be set to push-pull outputs, and the external pull-up
resistors will not be needed.
(0V - VLOGIC)
(0V - VLOGIC)
0V - VDD
0V - VDD
0V - VDD
DIO
(0V, VLOGIC)
0V - VDD
VLOGIC
(0V - VLOGIC)
(0V - VLOGIC)
SCL
SDA
I/O Levels and Connections for Two Example Power Configurations (AUX_VDDIO = 1)
Note: Actual configuration will depend on the type of 3rd-party accelerometer used.
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
31 of 42
8 Assembly
This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems
(MEMS) gyros packaged in Quad Flat No leads package (QFN) surface mount integrated circuits.
8.1 Orientation of Axes
The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1
identifier in the figure.
Orientation of Axes of Sensitivity and Polarity of Rotation
ITG-3050
+Z
+X+Y
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
32 of 42
8.2 Package Dimensions:
SYMBOLS DIMENSIONS IN MILLIMETERS
MIN NOM MAX
A 0.85 0.90 0.95
A1 0.00 0.02 0.05
b 0.18 0.25 0.30
c--- 0.20 REF. ---
D 3.90 4.00 4.10
D2 2.95 3.00 3.05
E 3.90 4.00 4.10
E2 2.75 2.80 2.85
e--- 0.50 ---
f (e-b) 0.20 0.25 0.32
L 0.30 0.35 0.40
L1 0.35 0.40 0.45
I 0.20 0.25 0.30
R 0.05 --- 0.10
s 0.05 --- 0.15
S1 0.15 0.20 0.25
R
S
S
A1
A
E
D
PIN 1 IDENTIFIER IS A LASER
MARKED FEATURE ON TOP c
E2
L1 (12x)
D2 L(12x)
b
e
f
S1
I
PIN 1 IDENTIFIER
C 0.16
On 4 corner lead dim.
1
6
712
13
18
1924
1
6
712
13
18
19 24
S1
I
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
33 of 42
8.3 PCB Design Guidelines:
The Pad Diagram using a JEDEC type extension with solder rising on the outer edge is shown below. The
Pad Dimensions Table shows pad sizing (mean dimensions) recommended for the ITG-3050 product.
JEDEC type extension with solder rising on outer edge
PCB Lay-out Diagram
SYMBOLS
DIMENSIONS IN MILLIMETERS
NOM
Nominal Package I/O Pad Dimensions
e
Pad Pitch
0.50
b
Pad Width
0.25
L
Pad Length
0.35
L1
Pad Length
0.40
D
Package Width
4.00
E
Package Length
4.00
D2
Exposed Pad Width
3.00
E2
Exposed Pad Length
2.80
I/O Land Design Dimensions (Guidelines )
D3
I/O Pad Extent Width
4.80
E3
I/O Pad Extent Length
4.80
c
Land Width
0.35
Tout
Outward Extension
0.40
Tin
Inward Extension
0.05
L2
Land Length
0.80
L3
Land Length
0.85
PCB Dimensions Table (for PCB Lay-out Diagram)
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
34 of 42
8.4 Assembly Precautions
8.4.1 Gyroscope Surface Mount Guidelines
InvenSense MEMS Gyros sense rate of rotation. In addition, gyroscopes sense mechanical stress coming
from the printed circuit board (PCB). This PCB stress can be minimized by adhering to certain design rules:
When using MEMS gyroscope components in plastic packages, PCB mounting and assembly can cause
package stress. This package stress in turn can affect the output offset and its value over a wide range of
temperatures. This stress is caused by the mismatch between the Coefficient of Linear Thermal Expansion
(CTE) of the package material and the PCB. Care must be taken to avoid package stress due to mounting.
Traces connected to pads should be as symmetric as possible. Maximizing symmetry and balance for pad
connection will help component self alignment and will lead to better control of solder paste reduction after
reflow.
Any material used in the surface mount assembly process of the MEMS gyroscope should be free of
restricted RoHS elements or compounds. Pb-free solders should be used for assembly.
8.4.2 Exposed Die Pad Precautions
The ITG-3050 has very low active and standby current consumption. The exposed die pad is not required for
heat sinking, and should not be soldered to the PCB. Failure to adhere to this rule can induce performance
changes due to package thermo-mechanical stress. There is no electrical connection between the pad and
the CMOS.
8.4.3 Trace Routing
Routing traces or vias under the gyro package such that they run under the exposed die pad is prohibited.
Routed active signals may harmonically couple with the gyro MEMS devices, compromising gyro response.
These devices are designed with the drive frequencies as follows: X = 33±3kHz, Y = 30±3kHz, and
Z=27±3kHz. To avoid harmonic coupling don’t route active signals in non-shielded signal planes directly
below, or above the gyro package. Note: For best performance, design a ground plane under the e-pad to
reduce PCB signal noise from the board on which the gyro device is mounted. If the gyro device is stacked
under an adjacent PCB board, design a ground plane directly above the gyro device to shield active signals
from the adjacent PCB board.
8.4.4 Component Placement
Do not place large insertion components such as keyboard or similar buttons, connectors, or shielding boxes
at a distance of less than 6 mm from the MEMS gyro. Maintain generally accepted industry design practices
for component placement near the ITG-3050 to prevent noise coupling and thermo-mechanical stress.
8.4.5 PCB Mounting and Cross-Axis Sensitivity
Orientation errors of the gyroscope mounted to the printed circuit board can cause cross-axis sensitivity in
which one gyro responds to rotation about another axis. For example, the X-axis gyroscope may respond to
rotation about the Y or Z axes. The orientation mounting errors are illustrated in the figure below.
.
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
35 of 42
Package Gyro Axes ( ) Relative to PCB Axes ( ) with Orientation Errors (Θ and Φ)
ITG-3050
Φ
ΘX
Y
Z
The table below shows the cross-axis sensitivity of the gyroscope for a given orientation error.
Cross-Axis Sensitivity vs. Orientation Error
Orientation Error
(θ or Φ)
Cross-Axis Sensitivity
(sinθ or sinΦ)
0%
0.5º
0.87%
1.75%
The specification for cross-axis sensitivity in Section 3.1 includes the effect of the die orientation error with
respect to the package.
8.4.6 MEMS Handling Instructions
MEMS (Micro Electro-Mechanical Systems) are a time-proven, robust technology used in hundreds of
millions of consumer, automotive and industrial products. MEMS devices consist of microscopic moving
mechanical structures. They differ from conventional IC products, even though they can be found in similar
packages. Therefore, MEMS devices require different handling precautions than conventional ICs prior to
mounting onto printed circuit boards (PCBs).
The ITG-3050 gyroscope has been qualified to a shock tolerance of 10,000g. InvenSense packages its
gyroscopes as it deems proper for protection against normal handling and shipping. It recommends the
following handling precautions to prevent potential damage.
Do not drop individually packaged gyroscopes, or trays of gyroscopes onto hard surfaces. Components
placed in trays could be subject to g-forces in excess of 10,000g if dropped.
Printed circuit boards that incorporate mounted gyroscopes should not be separated by manually
snapping apart. This could also create g-forces in excess of 10,000g.
8.4.7 ESD Considerations
Establish and use ESD-safe handling precautions when unpacking and handling ESD-sensitive devices.
Store ESD sensitive devices in ESD safe containers until ready for use. The Tape-and-Reel moisture-
sealed bag is an ESD approved barrier. The best practice is to keep the units in the original moisture
sealed bags until ready for assembly.
Restrict all device handling to ESD protected work areas that measure less than 200V static charge.
Ensure that all workstations and personnel are properly grounded to prevent ESD.
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
36 of 42
8.4.8 Reflow Specification
Qualification Reflow: The ITG-3050 gyroscope was qualified in accordance with IPC/JEDEC J-STD-020D.01.
This standard classifies proper packaging, storage and handling in order to avoid subsequent thermal and
mechanical damage during the solder reflow attachment phase of assembly. The classification specifies a
sequence consisting of a bake cycle, a moisture soak cycle in a temperature humidity oven, followed by
three solder reflow cycles and functional testing for qualification. All temperatures refer to the topside of the
QFN package, as measured on the package body surface. The peak solder reflow classification temperature
requirement is (260 +5/-0°C) for lead-free soldering of components measuring less than 1.6 mm in thickness.
Production Reflow: Check the recommendations of your solder manufacturer. For optimum results,
production solder reflow processes should reduce exposure to high temperatures, and use lower ramp-up
and ramp-down rates than those used in the component qualification profile shown for reference below.
Production reflow should never exceed the maximum constraints listed in the table and shown in the figure
below. These constraints were used for the qualification profile, and represent the maximum tolerable ratings
for the device.
Maximum Temperature IR / Convection Solder Reflow Curve Used for Qualification
Temperature Set Points for IR / Convection Reflow Corresponding to Figure Above
Step
Setting
CONSTRAINTS
Temp (°C)
Time (sec)
Rate (°C/sec)
A
Troom
25
B
TSmin
150
C
TSmax
200
60 < tBC < 120
D
TLiquidus
217
r(TLiquidus-TPmax) < 3
E
TPmin [255°C, 260°C]
255
r(TLiquidus-TPmax) < 3
F
TPmax [ 260°C, 265°C]
260
tAF < 480
r(TLiquidus-TPmax) < 3
G
TPmin [255°C, 260°C]
255
10< tEG < 30
r(TPmax-TLiquidus) < 4
H
TLiquidus
217
60 < tDH < 120
I
Troom
25
Note: For users TPmax must not exceed the classification temperature (260°C).
For suppliers TPmax must equal or exceed the classification temperature.
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
37 of 42
8.4.9 Storage Specifications
The storage specification of the ITG-3050 gyroscope conforms to IPC/JEDEC J-STD-020D.01 Moisture
Sensitivity Level (MSL) 3.
Calculated shelf-life in moisture-sealed bag
12 months -- Storage conditions: <40°C and <90% RH
After opening moisture-sealed bag
168 hours -- Storage conditions: ambient ≤30°C at 60%RH
8.5 Package Marking Specification
InvenSense
ITG-3050
X X X X X X-X X
X X Y Y W W X
Lot traceability code
Foundry code
Package Vendor Code
Rev Code
Y Y = Year Code
W W = Work Week
TOP VIEW
Package Marking Specification
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
38 of 42
8.6 Tape & Reel Specification
Tape Dimensions
Reel Outline Drawing
Reel Dimensions and Package Size
PACKAGE
SIZE
REEL (mm)
L
V
W
Z
4x4
330
100
13.2
2.2
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
39 of 42
Tape and Reel Specification
Reel Specifications
Quantity Per Reel
5,000
Reels per Box
1
Boxes Per Carton (max)
3
Pieces per Carton (max)
15,000
8.7 Label
Package Orientation
Pin 1
User Direction of
Feed
Cover Tape
(Anti-Static)
Carrier Tape
(Anti-Static)
Label
Reel
Terminal Tape
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
40 of 42
8.8 Packaging
Moisture Barrier Bag
With Labels
ESD Anti-static Label
Moisture-Sensitivity
Caution Label
Tape & Reel
Barcode Label
Reel in Box
Box with Tape & Reel Label
Moisture-Sensitivity Caution Label
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
41 of 42
9 Reliability
9.1 Qualification Test Policy
Before InvenSense products are released for production, they complete a series of qualification tests. The
Qualification Test Plan for the ITG-3050 followed the JEDEC JESD47G.01 Standard, “Stress-Test-Driven
Qualification of Integrated Circuits.” The individual tests are described below.
9.2 Qualification Test Plan
Accelerated Life Tests
TEST
Method/Condition
Lot
Quantity
Sample
/ Lot
Acc /
Reject
Criteria
High Temperature
Operating Life (HTOL/LFR)
JEDEC JESD22-A108C, Dynamic,
3.63V biased, Tj>125°C
[read-points 168, 500, 1000 hours]
3
77
(0/1)
Highly Accelerated Stress
Test (1) (HAST)
JEDEC JESD22-A118
Condition A, 130°C, 85%RH, 33.3 psia., unbiased, [read-
point 96 hours]
3
77
(0/1)
High Temperature Storage
Life (HTS)
JEDEC JESD22-A103C, Cond. A, 125°C,
Non-Biased Bake
[read-points 168, 500, 1000 hours]
3
77
(0/1)
Device Component Level Tests
TEST
Method/Condition
Lot
Quantity
Sample
/ Lot
Acc /
Reject
Criteria
ESD-HBM
JEDEC JESD22-A114F, (1.5KV)
1
3
(0/1)
ESD-MM
JEDEC JESD22-A115-A, (200V)
1
3
(0/1)
Latch Up
JEDEC JESD78B Class II (2), 125°C;
Level B ±60mA
1
6
(0/1)
Mechanical Shock
JEDEC JESD22-B104C,
Mil-Std-883H, method 2002.5,
Cond. E, 10,000g’s, 0.2ms,
±X, Y, Z 6 directions, 5 times/direction
3
30
(0/1)
Vibration
JEDEC JESD22-B103B, Variable Frequency
(random), Cond. B, 5-500Hz,
X, Y, Z 4 times/direction
3
5
(0/1)
Temperature Cycling (TC) (1)
JEDEC JESD22-A104D Condition N,
[-40°C to +85°C], Soak Mode 2 [5’], 100 cycles
3
77
(0/1)
Board Level Tests
TEST
Method/Condition
Lot
Quantity
Sample
/ Lot
Acc /
Reject
Criteria
Board Mechanical Shock
JEDEC JESD22-B104C,
Mil-Std-883H, method 2002.5,
Cond. E, 10000g’s, 0.2ms,
+-X, Y, Z 6 directions, 5 times/direction
1
5
(0/1)
Board
Temperature Cycling (TC) (1)
JEDEC JESD22-A104D Condition N,
[ -40°C to +85°C], Soak Mode 2 [5’], 100 cycles
1
40
(0/1)
(1) Tests are preceded by MSL3 Preconditioning in accordance with JEDEC JESD22-A113F
ITG-3050 Product Specification
Document Number: PS-ITG-3050-00
Revision: 1.3
Release Date: 08/25/2011
42 of 42
10 Environmental Compliance
The ITG-3050 is RoHS and Green compliant.
The ITG-3050 is in full environmental compliance as evidenced in report HS-ITG-3050, Materials Declaration
Data Sheet.
Environmental Declaration Disclaimer:
InvenSense believes this environmental information to be correct but cannot guarantee accuracy or completeness. Conformity
documents for the above component constitutes are on file. InvenSense subcontracts manufacturing and the information contained
herein is based on data received from vendors and suppliers, which has not been validated by InvenSense.
This information furnished by InvenSense is believed to be accurate and reliable. However, no responsibility is assumed by InvenSense
for its use, or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to
change without notice. InvenSense reserves the right to make changes to this product, including its circuits and software, in order to
improve its design and/or performance, without prior notice. InvenSense makes no warranties, neither expressed nor implied, regarding
the information and specifications contained in this document. InvenSense assumes no responsibility for any claims or damages arising
from information contained in this document, or from the use of products and services detailed therein. This includes, but is not limited
to, claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by
implication or otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information
previously supplied. Trademarks that are registered trademarks are the property of their respective companies. InvenSense sensors
should not be used or sold in the development, storage, production or utilization of any conventional or mass-destructive weapons or for
any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment,
transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime
prevention equipment.
InvenSense is a registered trademark of InvenSense, Inc. ITG-3050™, MPU™, MotionProcessing Unit™, MotionProcessor™,
MotionApps™, MotionFusion™, Digital Motion Processor™, and DMP are trademarks of InvenSense, Inc.
©2011 InvenSense, Inc. All rights reserved.