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1. General description
74HC1G08-Q100 and 74HCT1G08-Q100 are high-speed, Si-gate CMOS devices. They
provide a 2-input AND function.
The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.
The HCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
The standard output currents are half of those of the 74HC08-Q100 and 74HCT08-Q100.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
74HC1G08-Q100; 74HCT1G08-Q100
2-input AND gate
Rev. 2 — 16 August 2012 Product data sheet
Table 1. Ordering information
Type number Package
Tem perature range Name Description Version
74HC1G08GW-Q100 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads;
body width 1.25 mm SOT353-1
74HCT1G08GW-Q100
74HC1G08GV-Q100 40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753
74HCT1G08GV-Q100
74HC_HCT1G08_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 16 August 2012 2 of 12
NXP Semiconductors 74HC1G08-Q100; 74HCT1G08-Q100
2-input AND gate
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
6. Pinning information
6.1 Pinning
Table 2. Marking codes
Type number Marking[1]
74HC1G08GW-Q100 HE
74HCT1G08GW-Q100 TE
74HC1G08GV-Q100 H08
74HCT1G08GV-Q100 T08
Fig 1. Logic symbol Fig 2. IEC logic symbol
mna113
B
AY
2
14
mna114
24
&
1
Fig 3. Lo gic diagram
mna115
B
A
Y
Fig 4. Pin con f ig ura t io n
74HC1G08-Q100
74HCT1G08-Q100
BV
CC
A
GND Y
aaa-003473
1
2
3
5
4
74HC_HCT1G08_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 16 August 2012 3 of 12
NXP Semiconductors 74HC1G08-Q100; 74HCT1G08-Q100
2-input AND gate
6.2 Pin description
7. Functional description
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Above 55 C the value of Ptot derates linearly with 2.5 mW/K.
Table 3. Pin description
Symbol Pin Description
B 1 data input
A 2 data input
GND 3 ground (0 V)
Y 4 data output
VCC 5 supply voltage
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level
Input Output
ABY
LLL
LHL
HLL
HHH
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). [1]
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V or VI>V
CC + 0.5 V - 20 mA
IOK output clamping current VO<0.5 V or VO>V
CC + 0.5 V - 20 mA
IOoutput current 0.5 V < VO <V
CC +0.5V - 12.5 mA
ICC supply current - 25 mA
IGND ground current 25 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C[2] - 200 mW
74HC_HCT1G08_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 16 August 2012 4 of 12
NXP Semiconductors 74HC1G08-Q100; 74HCT1G08-Q100
2-input AND gate
9. Recommended operating conditions
10. Static characteristics
Table 6. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 74HC1G08-Q100 74HCT1G08-Q100 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0- V
CC V
VOoutput voltage 0 - VCC 0- V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise
and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - - 139 - - 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 7. Static characteristics
Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb =25
C.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max
74HC1G08-Q100
VIH HIGH-level input
voltage VCC = 2.0 V 1.5 1.2 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - V
VIL LOW-level input
voltage VCC = 2.0 V - 0 .8 0 .5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 V
VOH HIGH-level output
voltage VI= VIH or VIL
IO= 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - V
IO= 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - V
IO= 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - V
IO= 2.0 mA; VCC = 4.5 V 4.13 4.32 - 3.7 - V
IO= 2.6 mA; VCC = 6.0 V 5.63 5.81 - 5.2 - V
VOL LOW-level output
voltage VI= VIH or VIL
IO= 20 A; VCC = 2.0 V - 0 0.1 - 0.1 V
IO= 20 A; VCC = 4.5 V - 0 0.1 - 0.1 V
IO= 20 A; VCC = 6.0 V - 0 0.1 - 0.1 V
IO= 2.0 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V
IO= 2.6 mA; VCC = 6.0 V - 0.16 0.33 - 0.4 V
IIinput leakage current VI=V
CC or GND; VCC = 6.0 V - - 1.0 - 1.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =6.0V --10- 20 A
CIinput capacitance - 1.5 - - - pF
74HC_HCT1G08_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 16 August 2012 5 of 12
NXP Semiconductors 74HC1G08-Q100; 74HCT1G08-Q100
2-input AND gate
11. Dynamic characteristics
74HCT1G08-Q100
VIH HIGH-level input
voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V
VIL LOW-level input
voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V
VOH HIGH-level output
voltage VI= VIH or VIL
IO= 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - V
IO= 2.0 mA; VCC = 4.5 V 4.13 4.32 - 3.7 - V
VOL LOW-level output
voltage VI= VIH or VIL
IO= 20 A; VCC = 4.5 V - 0 0.1 - 0.1 V
IO= 2.0 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V
IIinput leakage current VI=V
CC or GND; VCC = 5.5 V - - 1.0 - 1.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V --10- 20 A
ICC additional supply
current per input; VCC = 4.5 V to 5.5 V;
VI=V
CC 2.1 V; IO=0A - - 500 - 850 A
CIinput capacitance - 1.5 - - - pF
Table 7. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb =25
C.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max
Table 8. Dynamic characteristics
GND = 0 V; tr = tf
6.0 ns; All typical values are measured at Tamb =25
C. For test circuit see Figure 6
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max
74HC1G08-Q100
tpd propagation delay A and B to Y; see Figure 5 [1]
VCC = 2.0 V; CL= 50 pF - 25 115 - 135 ns
VCC = 4.5 V; CL=50pF - 9 23 - 27 ns
VCC = 5.0 V; CL=15pF - 7 - - - ns
VCC = 6.0 V; CL=50pF - 8 20 - 23 ns
CPD power dissipation
capacitance VI=GNDtoV
CC [2] -19- - -pF
74HCT1G08-Q100
tpd propagation delay A and B to Y; see Figure 5 [1]
VCC = 4.5 V; CL=50pF - 11 23 - 27 ns
VCC = 5.0 V; CL=15pF - 11 - - - ns
74HC_HCT1G08_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 16 August 2012 6 of 12
NXP Semiconductors 74HC1G08-Q100; 74HCT1G08-Q100
2-input AND gate
[1] tpd is the same as tPLH and tPHL.
[2] CPD is used to determine the dynamic power dissipation PD(W).
PD=C
PD VCC2fi+(CLVCC2fo)where:
fi= input frequency in MHz
fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in Volts
(CLVCC2fo) = sum of outputs
12. Waveforms
CPD power dissipation
capacitance VI=GNDtoV
CC 1.5 V [2] -21- - -pF
Table 8. Dynamic characteristics …continu ed
GND = 0 V; tr = tf
6.0 ns; All typical values are measured at Tamb =25
C. For test circuit see Figure 6
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max
For 74HC1G08-Q100: VM = 0.5 VCC; VI = GND to VCC
For 74HCT1G08-Q100: VM = 1.3 V; VI = GND to 3.0 V Test data is given in Table 8. Definitions for test circuit:
CL = Load capacitance including jig and probe
capacitance
RT = Termination resistance should be equal to the
output impedance Zo of the pulse generator
Fig 5. The input (A and B) to output (Y) propagation
delays Fig 6. Test circuit for measuring switch ing times
mna116
A, B input
Y output
t
PHL
t
PLH
V
M
V
M
mna101
V
CC
V
I
V
O
RTCL
PULSE
GENERATOR DUT
74HC_HCT1G08_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 16 August 2012 7 of 12
NXP Semiconductors 74HC1G08-Q100; 74HCT1G08-Q100
2-input AND gate
13. Package outline
Fig 7. Package outline SOT353-1 (TSSOP5)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(1) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.1
01.0
0.8 0.30
0.15 0.25
0.08 2.25
1.85 1.35
1.15 0.65
e1
1.3 2.25
2.0 0.60
0.15 7°
0°
0.1 0.10.30.425
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.46
0.21
SOT353-1 MO-203 SC-88A 00-09-01
03-02-19
wM
bp
D
Z
e
e1
0.15
13
54
θ
A
A2
A1
Lp
(A3)
detail X
L
HE
E
c
vMA
X
A
y
1.5 3 mm0
scale
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1
1.1
74HC_HCT1G08_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 16 August 2012 8 of 12
NXP Semiconductors 74HC1G08-Q100; 74HCT1G08-Q100
2-input AND gate
Fig 8. Package outline SOT753 (SC-74A)
74HC_HCT1G08_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 16 August 2012 9 of 12
NXP Semiconductors 74HC1G08-Q100; 74HCT1G08-Q100
2-input AND gate
14. Abbreviations
15. Revision history
Table 9. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
TTL Transistor-Transistor Logic
HBM Human Body Model
ESD ElectroStatic Discharge
MM Machine Model
DUT Device Under Test
Table 10. Revision history
Document ID Release
date Dat a sheet status Change notice Supersedes
74HC_HCT1G08_Q100 v.2 20120816 Product data sheet - 74HC_HCT1G08_Q100 v.1
Modifications: •Added pin 1 location note (Table 2)
74HC_HCT1G08_Q100 v.1 20120605 Product data sheet - -
74HC_HCT1G08_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 16 August 2012 10 of 12
NXP Semiconductors 74HC1G08-Q100; 74HCT1G08-Q100
2-input AND gate
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full informatio n see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggreg ate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with t heir
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the obj ective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74HC_HCT1G08_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 16 August 2012 11 of 12
NXP Semiconductors 74HC1G08-Q100; 74HCT1G08-Q100
2-input AND gate
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC1G08-Q100; 74HCT1G08-Q100
2-input AND gate
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 16 August 2012
Document identifier : 74HC _H CT 1G 08 _Q1 00
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 9
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
17 Contact information. . . . . . . . . . . . . . . . . . . . . 11
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12