ANALOG LC?M0S DEVICES Octal 8-Bit D/A Converter AD7228 REV. A 1.1 Scope. This specification covers the detail requirements for an octal CMOS digital-to-analog converter. 1.2 Part Number. The complete part number per Table 1 of this specification is as follows: Device Part Number? -1 AD7228T(X)/883B -2 AD7228U(X)/883B NOTE 1To complete the part number substitute the package identifier as shown in paragraph 1.2.3. 1.2.3 Case Outline. See Appendix 1 of General Specification ADI-M-1000: package outline: (X) Package Description Q Q-24 24-Pin Cerdip, 0.3 Width E E-28A 28-Contact LCC 1.3 Absolute Maximum Ratings. (T,=+25C unless otherwise noted) Vpp tO GND 2... ccc ee tee teen nee tenet n nee 0.3 Vto +17 V Vpp t0 Vag occ cc ce ee ee ee eee eee ee te eee en ene ee eras +0.3 V to +24 V Digital Input Voltage 2.2... eee ee eee cnet teen en eeeee 0.3 V, Vpp VagrtOGND 0... eee ete ene ne eee rete teeta ene -0.3 V, Vpp Vout to GND! Ce ewe wee ee ee ee eee we eee ee meee eee ee Vss> Vopp Power Dissipation Up to +75C occ eee eee te teen ene e ee een ete eeneee 1000 mW Derates above +75C . 0. cee eee ee een ee eee tence eens 2.0 mW/C Operating Temperature Range ........ 0... ccs eee ee ee ee eee eee 55C to +125C Thermal Resistance (65): Case 1(Q-24) 2. cece ce cece e ene ee eens See MIL-M-38510, Appendix C Case 3 (E-28A) 2... ccc cc eee eee teen ete eeneee See MIL-M-38510, Appendix C Storage Temperature . 0.2.00... cee eee eee eee eee eee 65C to +125C Lead Temperature (Soldering 10 sec) 2.6... ce ce tee cnet eee een enaee +300C Junction Temperature 2.0.0.0... cee ee eee eee ne ene t ene ee naae +175C NOTE 1Qutrputs may be shorted to any voltage in the range Vgg to Vpp provided that the power dissipation of the package is not exceeded. Typical short circuit for a short ta Vgz is 50 mA. DIGITAL-TO-ANALOG CONVERTERS 8-85 DIGITAL-TO-ANALOG CONVERTERS aAD7228 SPECIFICATIONS Table 1. Design Sub Test Symbol Device Min Max Group Test Condition Units Total Unadjusted Error? TUE -1,2 -2 +2 1 Vpp = 15 V +10%, LSB | -1 -2 +2 2,3 Vrer = +10 V | 2 -l. 44 2,3 (Single Supply Only) | -2 -1 +1 4 Total Unadjusted Error TUE -1 -2 +2 13, 14,15 | Dual Supply Only LSB | -2 -1 41 Relative Accuracy RA -1,2 -l +1 1 LSB -1 1 +1 2,3 -2 -0.5 +0.5 2,3 -2 -0.5 +0.5 12 Differential Nonlinearity DNL ~1,2 -1 +1 1, 2,3 Guaranteed Monotonic LSB , (Single Supply Only) Differential Nonlinearity DNL -1,2 -1 +] 13, 14,15 | Dual Supply Only LSB . Full-Scale Error? Ag -1,2 -1 +] 1 mV -l 1 +1 2,3 -2 -0.5 +0.5 2,3 -2 0.5 +0.5 12 Zero Code Error Azce 1,2 25 +25 1 mV ~l 30 +30 2,3 -2 ~20 +20 2,3 -2 -15 +15 12 Load Resistance R, -1,2 2 1, 2,3 Vout = +10 V kD (Dual Supply & Single Supply) Reference Input Voltage Range Veer -1,2 2 10 1, 2,3 , v Reference Input Resistance Riw -1,2 2 1, 2,3 Dual Supply Only kQ Reference Input Capacitance* Cy, (REF) -1,2 500 13, 14,15 | Dual and Single Supply pF Digital Input High Voltage Vinn -1,2 2.4 1, 2,3 Dual Supply Only v Digital Input Low Voltage Vint -1,2 0.8 1, 2,3 Input Coding Is Binary v Digital Input Leakage Current litc -1,2 -1 +1 1, 2,3 pA Digital Input Capacitance Cy -1,2 8 13, 14, 15 pF Voltage Output Slew Rate SR -1,2 2 13, 14,15 | Dual and Single Supply Vips Voltage Output Settling Time ts -1,2 13, 14, 15 Positive Full-Scale Change 5 Dual and Single Supply ps Negative Full-Scale Change -1,2 5 Dual Supply 7 Single Supply Power Supply Current Ipp -1,2 16 1 Dual Supply Only mA 22 2,3 Igs ~1,2 14 1 20 2,3 Function Tests -1,2 7 Address to WR Setup Time t -1,2 9,10,11 | Dual and Single Supply ns Address to WR Hold Time ty -1,2 9,10, 11 | See Figure 2 and Note 7 Data Valid to WR Setup Time ts -1,2 70 9 100 10, 11 Data Valid to WR Hold Time te -1,2 10 9, 10, 11 ns 8-86 DIGITAL-TO-ANALOG CONVERTERS REV. AAD7228 Design Sub . Test Symbol Device | Min Max Group Test Condition Units Write Pulse Width ts -1,2 95 9 ns 150 10, 11 NOTES 1 5C<T,<+125C, Dual Supply unless otherwise specified. R, = 2k, C, = 100 pF unless otherwise stated. Parameters in subgroups 13, 14, 15 are characterized at initial design and after any subsequent redesigns. 2 Includes zero code error, relative accuracy and full-scale error. Calculated after zero code error has been adjusted out. *Occurs when each DAC is loaded with all Is. *Vaer = +10 V; settling time to + 1/2 LSB. Subgroup 7 tests are for the purpose of verifying the truth table. | 7AIl input rise and fall times measured from 10% to 90% of +5 V, tq = te = Sas. Timing ference level is ViNH + Vine. 1.3.1 Recommended Operating Conditions. Operating Voltage Range for Dual Supply Positive Supply (Vpp) 6... ce cee teen e ee eter e eee +10.8 V to +16.5 V Negative Supply (Vgg) 6. ee eee eee tee ete nn teee -4.5 Vito -5.5V Reference Voltage (Vapp)) . 1. eee tebe eee eee +2.0 V to +10.0 V Operating Voltage Range for Single Supply Positive Supply (Vpp) . 6.0.62. cece eee eee enter eee eres +13.5 V to +16.5 V Negative Supply (Vss)_ .. 0. 00-00 -- Lee enn eet eee eee ete ee eee e ee eee OV Reference Voltage (Vapp)) oe cece eee ee eet e eet e keen eee aee +10 V NOTE Vour must be less than Vpp by 3.5 V to ensure correct operation. 3.2.1 Functional Block Diagram and Terminal Assignments. Veer Vop 1 9} Vou Cwm Po4oProO MsB DATA t (a BIT) LSB a2 CONTROL al LOGIC AD7228 ao Vss GND REV. A DIGITAL-TO-ANALOG CONVERTERS 8-87 DIGITAL-TO-ANALOG CONVERTERS aAD7228 Q Package (Cerdip) E Package (LCC) 25 WA 24 OBO 23 DB1 22 NC 2t DBZ 20 OB3 19 DB4 wd Voo [1 | 24| Ao Voure | 23) A1 Vourr [3 | 22] a2 Voura tf 21| Wa Yours 5 Yours 6 verte 20] DBO {LSB} Ve 7 Vours L6 AD7228 19 | DB1 Cc AD7228 Vours J (Not to Seale} 18 | p82 vee : (Not to Seete) Vours fe 17 | DBa Voure 10 Voun [3 | 16 | OB4 Vous 17 Vsg | 10 15] DBS Veer [77 [14] oa6 enn [12 [13] 087 mse) Nc = NOCONNECT Table 2. Truth Table AD7228 Control Inputs WR | A2 | Al | AO | Operation H Xx x Xx No Operation Device Not Selected L L L L DAC | Transparent L L L DAC 1 Latched L L L H DAC 2 Transparent L L H L DAC 3 Transparent L L H H DAC 4 Transparent L H L L DAC 5 Transparent L H L H DAC 6 Transparent L H H L DAC 7 Transparent L H H H DAC 8 Transparent H = High State L = Low State X = Dont Care a_" aa A2 _ 1-0F-8 DECODER TODAC1LATCH TO DAC 2LATCH TODAC3LATCH TO DAC 4LATCH TODACS5LATCH TODACBLATCH TO DAC? LATCH TO DAC8 LATCH Figure 1. Input Control Logic 8-88 DIGITAL-TO-ANALOG CONVERTERS aff foe ADDAESS. x K NOTE: THE SELECTED INPUT LATCH IS TRANSPARENT WHILE WA IS LOW, THUS INVALID DATA DURING THIS TIME CAN CAUSE SPURIOUS OUTPUTS Figure 2. Write Cycle Timing Diagram REV. AAD7228 REV. A 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (80). 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). EDGE CONNECTIONS 2x250mA 4 * a Q ~ > e > +10V -5V 0 +18V TEST POINTS DATA TO INITIALIZE, APPLY THE FOLLOWING WAVEFORMS: EACH PULSE OF AO SHOULD BE AT LEAST 50ps. DATA = 15V wl LS LE Lt s J Ll es WR J THIS SEQUENCE ENSURES ALL DACS ARE LOADED. Burn-in Conditions DIGITAL-TO-ANALOG CONVERTERS 8-&9 DIGITAL-TO-ANALOG CONVERTERS a