LT3032 Series
1
3032ff
For more information www.linear.com/LT3032
TYPICAL APPLICATION
FEATURES DESCRIPTION
Dual 150mA
Positive/Negative Low Noise
Low Dropout Linear Regulator
The LT
®
3032 is a dual, low noise, positive and negative low
dropout voltage linear regulator. Each regulator delivers
up to 150mA with a typical 300mV dropout voltage. Each
regulator’s quiescent current is low (30µA operating and
<3µA in shutdown) and well-controlled in dropout, making
it an excellent choice for battery-powered circuits.
Another key feature of the LT3032 is low output noise.
Adding an external 10nF bypass capacitor to each regulator
reduces output noise to 20µVRMS/30µVRMS over a 10Hz to
100kHz bandwidth. The LT3032 is stable with minimum
output capacitors of 2.2µF. The regulators do not require
the addition of ESR as is common with other regulators.
The regulators are offered as adjustable output devices with
an output voltage down to the ±1.22V reference voltage or
in fixed voltages of ±3.3V, ±5V, ±12V and ±15V. Internal
protection circuitry includes reverse-output protection,
current limiting and thermal limiting.
The LT3032 is available in a unique low profile 14-lead
4mm × 3mm × 0.75mm DFN package with exposed back-
side pads for each regulator, allowing optimum thermal
performance.
Dual Polarity Low Noise 150mA Power Supply
APPLICATIONS
n Low Noise: 20µVRMS (Positive) and
30µVRMS (Negative)
n Low Quiescent Current: 30µA/Channel
n Wide Input Voltage Range: ±2.3V to ±20V
n Output Current: ±150mA
n Low Shutdown Current: <3µA Total (Typical)
n Low Dropout Voltage: 300mV/Channel
n Fixed Output Voltages: ±3.3V, ±5V, ±12V, ±15V
n Adjustable Outputs from ±1.22V to ±20V
n No Protection Diodes Needed
n Stable with 2.2µF Output Capacitors
n Stable with Ceramic, Tantalum or Aluminum Capacitors
n Starts into Reverse Output Voltage
n Current Limit and Thermal Limit
n Low Profile 14-Lead 4mm × 3mm × 0.75mm
DFN Package
n Battery-Powered Instruments
n Bipolar Power Supplies
n Low Noise Power Supplies
L, LT, LTC , LT M , Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Analog Devices, Inc. All other trademarks are the property of their
respective owners.
10µF 10µF
10µF
0.01µF
0.01µF
10µF
5.4V TO
20V
5V OUT AT 150mA
20µVRMS NOISE
–5V OUT AT –150mA
30µVRMS NOISE
–5.4V TO
–20V
<0.25V = OFF
>2V = ON SHDNP
SHDNN
OUTPINP
INN
LT3032-5
BYPP
GND
BYPN
OUTN
3032 TA01
OUTP
100µV/DIV
OUTN
100µV/DIV
20µVRMS
30µVRMS
1mS/DIV 3032 TA02a
10Hz to 100kHz Output Noise
LT3032 Series
2
3032ff
For more information www.linear.com/LT3032
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
INP Pin Voltage .......................................................±20V
INN Pin Voltage ....................................................... ±20V
OUTP Pin Voltage....................................................±20V
OUTN Pin Voltage (Note 3) .....................................±20V
INP Pin to OUTP Pin Differential Voltage ................±20V
OUTN Pin to INN Pin Differential Voltage
(Note 3) ..........................................................–0.5V, 20V
ADJP Pin Voltage ......................................................±7V
ADJN Pin Voltage
(with Respect to INN Pin, Note 3) ..................–0.5V, 20V
BYPP Pin Voltage ................................................... ±0.5V
BYPN Pin Voltage
(with Respect to INN Pin) ........................................±20V
SHDNP Pin Voltage .................................................±20V
SHDNN Pin Voltage
(with Respect to INN Pin, Note 3) ..................–0.5V, 35V
SHDNN Pin Voltage
(with Respect to GND Pin) ..............................–20V, 15V
Output Short-Circuit Duration .......................... Indefinite
Operating Junction Temperature Range (Note 2)
E, I Grades ......................................... –40°C to 125°C
MP-Grade .......................................... –55°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
(Note 1)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
INP
NC
SHDNP
BYPN
SHDNN
INN
ADJN/NC
††
OUTP
NC†/ADJP
BYPP
GND
GND
INN
OUTN
TOP VIEW
DE14MA PACKAGE
14-LEAD (4mm × 3mm) PLASTIC DFN
15
GND
16
INN
TJMAX = 125°C, θJA = 30°C/W TO 43°C/W*, θJC = 10°C/W*
*SEE APPLICATIONS INFORMATION FOR MORE DETAIL
†PIN 2: NC FOR LT3032-3.3/LT3032-5/LT3032-12/LT3032-15, ADJP FOR LT3032
††PIN 8: NC FOR LT3032-3.3/LT3032-5/LT3032-12/LT3032-15, ADJN FOR LT3032
EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PINS 4, 5 ON PCB
EXPOSED PAD (PIN 16) IS INN, MUST BE SOLDERED TO PINS 6, 9 ON PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3032EDE#PBF LT3032EDE#TRPBF 3032 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3032IDE#PBF LT3032IDE#TRPBF 3032 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3032MPDE#PBF LT3032MPDE#TRPBF 3032 14-Lead (4mm × 3mm) Plastic DFN –55°C to 125°C
LT3032EDE-3.3#PBF LT3032EDE-3.3#TRPBF 03233 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3032IDE-3.3#PBF LT3032IDE-3.3#TRPBF 03233 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3032MPDE-3.3#PBF LT3032MPDE-3.3#TRPBF 03233 14-Lead (4mm × 3mm) Plastic DFN –55°C to 125°C
LT3032EDE-5#PBF LT3032EDE-5#TRPBF 30325 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3032IDE-5#PBF LT3032IDE-5#TRPBF 30325 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3032MPDE-5#PBF LT3032MPDE-5#TRPBF 30325 14-Lead (4mm × 3mm) Plastic DFN –55°C to 125°C
LT3032EDE-12#PBF LT3032EDE-12#TRPBF 30322 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3032IDE-12#PBF LT3032IDE-12#TRPBF 30322 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3032MPDE-12#PBF LT3032MPDE-12#TRPBF 30322 14-Lead (4mm × 3mm) Plastic DFN –55°C to 125°C
http://www.linear.com/product/LT3032#orderinfo
LT3032 Series
3
3032ff
For more information www.linear.com/LT3032
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum INP Operating Voltage LT3032 ILOAD = 150mA l1.8 2.3 V
Minimum INN Operating Voltage LT3032 ILOAD = –150mA l–2.3 –1.6 V
Regulated Output Voltage
(Notes 4, 10)
LT3032-3.3 VINP = 3.8V, ILOAD = 1mA
4.3V ≤ VINP ≤ 20V, 1mA ≤ ILOAD ≤ 150mA
l
3.250
3.200
3.300
3.300
3.350
3.400
V
V
LT3032-3.3 VINN = –3.8V, ILOAD = –1mA
–4.3V ≥ VINN ≥ –20V, –1mA ≥ ILOAD ≥ –150mA
l
–3.250
–3.200
–3.300
–3.300
–3.350
–3.400
V
V
LT3032-5 VINP = 5.5V, ILOAD = 1mA
6V ≤ VINP ≤ 20V, 1mA ≤ ILOAD ≤ 150mA
l
4.925
4.850
5.00
5.00
5.075
5.150
V
V
LT3032-5 VINN = –5.5V, ILOAD = –1mA
–6V ≥ VINN ≥ –20V, –1mA ≥ ILOAD ≥ –150mA
l
–5.075
–5.150
–5.00
–5.00
–4.925
–4.850
V
V
LT3032-12 VINP = 12.5V, ILOAD = 1mA
13V ≤ VINP ≤ 20V, 1mA ≤ ILOAD ≤ 150mA
l
11.82
11.64
12.00
12.00
12.18
12.36
V
V
LT3032-12 VINN = –12.5V, ILOAD = –1mA
–13V ≥ VINN ≥ –20V, –1mA ≥ ILOAD ≥ 150mA
l
–12.18
–12.36
–12.00
–12.00
–11.82
–11.64
V
V
LT3032-15 VINP = 15.5V, ILOAD = 1mA
16V ≤ VINP ≤ 20V, 1mA ≤ ILOAD ≤ 150mA
l
14.775
14.550
15.00
15.00
15.225
15.450
V
V
LT3032-15 VINN = –15.5V, ILOAD = –1mA
–16V ≥ VINN ≥ –20V, –1mA ≥ ILOAD ≥ 150mA
l
–15.225
–15.450
–15.00
–15.00
–14.775
–14.550
V
V
ADJP Pin Voltage
(Notes 4, 5)
LT3032 VINP = 2V, ILOAD = 1mA
2.3V ≤ VINP ≤ 20V, 1mA ≤ ILOAD ≤ 150mA
l
1.202
1.184
1.22
1.22
1.238
1.256
V
V
ADJN Pin Voltage
(Notes 4, 5, 10)
LT3032 VINN = –2V, ILOAD = –1mA
–2.3V ≤ VINN ≤ –20V, –1mA ≤ ILOAD ≤ –150mA
l
–1.238
–1.256
–1.22
–1.22
–1.202
–1.184
V
V
Line Regulation (Note 5) LT3032-3.3 OUTP ΔVINP = 3.8V to 20V, ILOAD = 1mA
OUTN ΔVINN = –3.8V to –20V, ILOAD = –1mA
l
l
1
9
6
30
mV
mV
LT3032-5 OUTP ΔVINP = 5.5V to 20V, ILOAD = 1mA
OUTN ΔVINN = –5.5V to –20V, ILOAD = –1mA
l
l
1
15
6
50
mV
mV
LT3032-12 OUTP ΔVINP = 12.5V to 20V, ILOAD = 1mA
OUTN ΔVINN = –12.5V to –20V, ILOAD = –1mA
l
l
1.5
13
15
75
mV
mV
LT3032-15 OUTP ΔVINP = 15.5V to 20V, ILOAD = 1mA
OUTN ΔVINN = –15.5V to 20V, ILOAD = –1mA
l
l
2
10
20
75
mV
mV
LT3032 ADJP ΔVINP = 2V to 20V, ILOAD = 1mA
ADJN ΔVINN = –2V to –20V, ILOAD = –1mA
l
l
1
1
6
12
mV
mV
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3032EDE-15#PBF LT3032EDE-15#TRPBF 03215 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3032IDE-15#PBF LT3032IDE-15#TRPBF 03215 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LT3032MPDE-15#PBF LT3032MPDE-15#TRPBF 03215 14-Lead (4mm × 3mm) Plastic DFN –55°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
ORDER INFORMATION
LT3032 Series
4
3032ff
For more information www.linear.com/LT3032
PARAMETER CONDITIONS MIN TYP MAX UNITS
Load Regulation (Notes 5, 13) LT3032-3.3 OUTP VINP = 4.3V, ΔILOAD = 1mA to 150mA –5 mV
LT3032-3.3 OUTN VINN = –4.3V, ΔILOAD = –1mA to –150mA 10 mV
LT3032-5 OUTP VINP = 6V, ΔILOAD = 1mA to 150mA –9 mV
LT3032-5 OUTN VINN = –6V, ΔILOAD = –1mA to –150mA 15 mV
LT3032-12 OUTP VINP = 13V, ΔILOAD = 1mA to 150mA –20 mV
LT3032-12 OUTN VINN = –13V, ΔILOAD = –1mA to –150mA 20 mV
LT3032-15 OUTP VINP = 16V, ΔILOAD = 1mA to 150mA –25 mV
LT3032-15 OUTN VINN = –16V, ΔILOAD = –1mA to –150mA 27 mV
LT3032 ADJP VINP = 2.3V, ΔILOAD = 1mA to 150mA
VINP = 2.3V, ΔILOAD = 1mA to 150mA
l
–1.5 –7
–15
mV
mV
LT3032 ADJN VINN = –2.3V, ΔILOAD = –1mA to –150mA
VINN = –2.3V, ΔILOAD = –1mA to –150mA
l
1.5 7
15
mV
mV
Dropout Voltage
VINP = VOUTP(NOMINAL)
(Notes 6, 7)
ILOAD = 1mA l0.09 0.20 V
ILOAD = 10mA l0.15 0.27 V
ILOAD = 50mA 0.21 V
ILOAD = 150mA 0.27 V
Dropout Voltage
VINN = VOUTN(NOMINAL)
(Notes 6, 7)
ILOAD = –1mA l0.10 0.20 V
ILOAD = –10mA l0.15 0.27 V
ILOAD = –50mA 0.21 V
ILOAD = –150mA 0.30 V
GND Pin Current
VINP = VOUTP(NOMINAL), VINN = 0V
(Notes 6, 8, 9)
ILOAD = 0mA (LT3032, LT3032-3.3, LT3032-5)
ILOAD = 0mA (LT3032-12, LT3032-15)
ILOAD = 1mA (LT3032, LT3032-3.3, LT3032-5)
ILOAD = 1mA (LT3032-12, LT3032-15)
ILOAD = 10mA
ILOAD = 50mA
ILOAD = 150mA
l
l
l
l
l
l
l
–25
–50
–70
–80
–350
–1.3
–4
–65
–120
–120
180
–500
–1.8
–7
µA
µA
µA
µA
µA
mA
mA
GND Pin Current
VINN = VOUTN(NOMINAL), VINP = 0V
(Notes 6, 8, 9, 10)
ILOAD = 0mA (LT3032, LT3032-3.3, LT3032-5)
ILOAD = 0mA (LT3032-12, LT3032-15)
ILOAD = –1mA (LT3032, LT3032-3.3, LT3032-5)
ILOAD = –1mA (LT3032-12, LT3032-15)
ILOAD = –10mA
ILOAD = –50mA
ILOAD = –150mA
l
l
l
l
l
l
l
30
50
85
90
300
0.75
2
70
130
180
180
600
1.5
5
µA
µA
µA
µA
µA
mA
mA
ADJP Pin Bias Current LT3032 (Notes 5, 9) 30 100 nA
ADJN Pin Bias Current LT3032 (Notes 5, 9) –30 –100 nA
Shutdown Threshold SHDNP VOUTP = Off to On
SHDNP VOUTP = On to Off
SHDNN VOUTN = Off to On (Positive)
SHDNN VOUTN = Off to On (Negative)
SHDNN VOUTN = On to Off (Positive)
SHDNN VOUTN = On to Off (Negative)
l
l
l
l
l
l
0.25
–2.8
0.25
0.7
0.6
1.4
–1.9
1.4
–1.9
2
2
–0.25
V
V
V
V
V
V
SHDNP Pin Current (Note 9) VSHDNP = 0V
VSHDNP = 20V
–1
1
1
4
µA
µA
SHDNN Pin Current
(Note 9)
VSHDNN = 0V
VSHDNN = 15V
VSHDNN = -15V
–1
6
–3
1
15
–9
µA
µA
µA
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
LT3032 Series
5
3032ff
For more information www.linear.com/LT3032
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3032 is tested and specified under pulse load conditions
such that TJ ≅ TA. The LT3032E is 100% tested at TA = 25°C. Performance
of the LT3032E over the full –40°C to 125°C operating junction
temperature range is assured by design, characterization, and correlation
with statistical process controls. The LT3032I regulators are guaranteed
over the full –40°C to 125°C operating junction temperature range.
Note 3: Parasitic diodes exist internally between the INN pin and the OUTN,
ADJN, and SHDNN pins. These pins cannot be pulled more than 0.5V
below the INN pin during fault conditions, and must remain at a voltage
more positive than the INN pin during operation.
Note 4: Operating conditions are limited by maximum junction
temperature. Specifications do not apply for all possible combinations of
input voltages and output currents. When operating at maximum input
voltages, the output current ranges must be limited. When operating at
maximum output currents, the input voltage ranges must be limited.
Note 5: The LT3032 is tested and specified for these conditions with the
ADJP pin tied to the OUTP pin and the ADJN pin tied to the OUTN pin.
Note 6: To satisfy requirements for minimum input voltage, the LT3032 is
tested and specified for these conditions with an external resistor divider
(two 250k resistors) from OUTP/OUTN to the corresponding ADJP/ADJN
pin to give an output voltage of ±2.44V. The external resistor divider adds
a 5µA DC load on the output. The LT3032-12/LT3032-15 have higher
internal resistor divider current, resulting in higher GND pin current at
light/no load.
Note 7: Dropout voltage is the minimum input-to-output voltage
differential needed to maintain regulation at a specified output current. In
dropout, output voltage equals:
VINP/INN – VDROPOUT
For lower output voltages, dropout voltage is limited by the minimum
input voltage specification under some output voltage/load conditions;
see curves for Minimum INN Voltage and Minimum INP Voltage in Typical
Performance Characteristics. LT C is unable to guarantee Maximum
Dropout Voltage specifications at 50mA and 150mA due to production
test limitations with Kelvin-Sensing the package pins. Please consult the
Typical Performance Characteristics for curves of Dropout Voltage as a
function of Output Load Current and Temperature.
Note 8: GND pin current is tested with VINP = VOUTP(NOMINAL) or VINN =
VOUTN(NOMINAL) and a current source load. This means the device is tested
while operating in its dropout region. This is the worst-case GND pin
current. GND pin current decreases slightly at higher input voltages.
Note 9: Positive current flow is into the pin. Negative current flow is out of
the pin.
Note 10: For input-to-output differential voltages from INN to OUTN
greater than –7V, a –50µA load is needed to maintain regulation.
Note 11: Reverse output current is tested with the INP pin grounded and
the OUTP pin forced to the nominal output voltage. This current flows into
the OUTP pin and out the GND pin.
Note 12: Positive side current limit is tested at VINP = 2.3V or
VOUTP(NOMINAL) + 1V (whichever is more positive). Negative side current
limit is tested at VINN = –2.3V or VOUTN(NOMINAL) – 1V (whichever is more
negative).
Note 13: LTC is unable to guarantee load regulation specifications on
fixed voltage versions of the LT3032 due to production test limitations
with Kelvin-Sensing the package pins. Please consult the Typical
Performance Characteristics for curves of Load Regulation as a function of
Temperature.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Quiescent Current in Shutdown VINP = 6V, VSHDNP = 0V, VINN = 0V
VINN = –6V, VSHDNN = 0V, VINP = 0V (LT3032, LT3032-3.3,
LT3032-5)
VINN = VOUT(NOMINAL) –1V, VSHDNN = 0V, VINP = 0V
(LT3032-12/ LT3032-15)
l
l
l
0.1
–3
10
8
–10
20
µA
µA
µA
Output Voltage Noise (10Hz to 100kHz) COUTP = 10µF, CBYPP 0.01µF, ILOAD = 150mA
COUTN = 10µF, CBYPN 0.01µF, ILOAD = –150mA
20
30
µVRMS
µVRMS
Ripple Rejection
VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz
VINP to VOUTP = 1.5V (Average), ILOAD = 100mA
VINN to VOUTN = –1.5V (Average), ILOAD = –100mA
50
46
68
54
dB
dB
Current Limit (Note 12) VINP = 7V, VOUTP = 0V
VINN = –7V, VOUTN = 0V
VINP = 2.3V or VOUTP(NOMINAL) + 1V, ΔVOUTP = –0.1V
VINN = –2.3V or VOUTP(NOMINAL) – 1V, ΔVOUTN = 0.1V
l
l
170
170
400
350
mA
mA
mA
mA
INP Reverse Leakage Current VINP = –20V, VOUTP = 0V l–1 mA
INN Reverse Leakage Current VINN = 20V, VOUTN, VADJN, VSHDNN = Open Circuit l1 mA
Reverse Output Current
(Notes 5, 11)
LT3032-3.3
LT3032-5
LT3032-12
LT3032-15
LT3032
VOUTP = 3.3V, VINP < 3.3V
VOUTP = 5V, VINP < 5V
VOUTP = 12V, VINP < 12V
VOUTP = 15V, VINP < 15V
VOUTP = VADJP = 1.22V, VINP < 1.22V
10
10
25
25
5
20
20
50
50
10
µA
µA
µA
µA
µA
LT3032 Series
6
3032ff
For more information www.linear.com/LT3032
TYPICAL PERFORMANCE CHARACTERISTICS
INN-to-OUTN
Dropout Voltage INP Quiescent Current INN Quiescent Current
INP-to-OUTP
Typical Dropout Voltage
INN-to-OUTN
Typical Dropout Voltage
INP-to-OUTP
Dropout Voltage
LOAD CURRENT (mA)
500
450
400
350
300
250
200
150
100
50
0
DROPOUT VOLTAGE (mV)
3032 G01
0 20 40 60 80 100 120 140 160
TJ = 125°C
TJ = 25°C
LOAD CURRENT (mA)
0
500
450
400
350
300
250
200
150
100
50
0
3032 G02
–40 –80 –120 –160
DROPOUT VOLTAGE (mV)
TJ = 125°C
TJ = 25°C
TEMPERATURE (°C)
–50
DROPOUT VOLTAGE (mV)
050 75
3032 G03
–25 25 100 125
IL = 150mA
IL = 50mA
IL = 10mA
IL = 1mA
500
450
400
350
300
250
200
150
100
50
0
TEMPERATURE (°C)
–50
DROPOUT VOLTAGE (mV)
050 75
3032 G04
–25 25 100 125
500
450
400
350
300
250
200
150
100
50
0
IL = 150mA
IL = 10mA
IL = 1mA
IL = 50mA
TEMPERATURE (°C)
–50
QUIESCENT CURRENT (µA)
100
3032 G05
0 50
70
50
60
40
30
20
10
0–25 25 75 125
IL = 0 (FIXED VOLTAGES)
IL = 5µA (ADJUSTABLE)
VSHDNP = VINP = 6V
(5V, ADJ)
VSHDNP = VINP = VOUTP(NOMINAL) +1V
(12V, 15V)
VSHDNP = 0V, VINP = 6V
TEMPERATURE (°C)
–60
–50
–40
–30
–20
–10
0
3032 G06
QUIESCENT CURRENT (µA)
IL = 0 (FIXED VOLTAGES)
IL = –5µA (ADJUSTABLE)
–50 –25 0 25 50 75 100 125
VSHDNN = VINN = VOUTN(NOMINAL) –1V
(12V, 15V)
VSHDNN = VINN = –6V
(5V, ADJ)
VSHDNN = 0V, VINN = –6V
LT3032-5 OUTP Output VoltageLT3032-3.3 OUTP Output Voltage LT3032-3.3 OUTN Output Voltage
TEMPERATURE (°C)
–50
OUTP OUTPUT VOLTAGE (V)
100
3032 G52
0 50
5.100
5.075
5.050
5.025
5.000
4.975
4.950
4.925
4.900 –25 25 75 125
IL = 1mA
TEMPERATURE (°C)
–50
OUTP OUTPUT VOLTAGE (V)
100
3032 G70
0 50
3.360
3.345
3.330
3.315
3.300
3.285
3.270
3.255
3.240 –25 25 75
125
IL = 1mA
TEMPERATURE (°C)
–50
OUTN OUTPUT VOLTAGE (V)
25
3032 G71
–25 0 50
–3.360
–3.345
–3.330
–3.315
–3.300
–3.285
–3.270
–3.255
–3.240 75 100
125
IL = –1mA
LT3032 Series
7
3032ff
For more information www.linear.com/LT3032
LT3032-5 OUTN Output Voltage LT3032-12 OUTP Output Voltage
LT3032 ADJP Pin Voltage
TEMPERATURE (°C)
–50
ADJP PIN VOLTAGE (V)
100
3032 G07
0 50
1.240
1.235
1.230
1.225
1.220
1.215
1.210
1.205
1.200 –25 25 75 125
IL = 1mA
TEMPERATURE (°C)
–50
OUTN OUTPUT VOLTAGE (V)
25
3032 G53
–25 0 50
–5.100
–5.075
–5.050
–5.025
–5.000
–4.975
–4.950
–4.925
–4.900 75 100 125
IL = –1mA
LT3032 ADJN Pin Voltage
TEMPERATURE (°C)
–1.240
–1.235
–1.230
–1.225
–1.220
–1.215
–1.210
–1.205
–1.200
3032 G08
ADJN PIN VOLTAGE (V)
IL = –1mA
–50 –25 0 25 50 75 100 125
TYPICAL PERFORMANCE CHARACTERISTICS
TEMPERATURE (°C)
–50
OUTP OUTPUT VOLTAGE (V)
100
3032 G58
0 50
12.24
12.18
12.12
12.06
12.00
11.94
11.88
11.82
11.76 –25 25 75
125
IL = 1mA
TEMPERATURE (°C)
–50
100
0 50
–12.18
–12.12
–12.06
–12.00
–11.94
–11.88
–11.82
–11.76 –25 25 75
IL = –1mA
LT3032-12 OUTN Output Voltage
LT3032-15 OUTP Output Voltage LT3032-15 OUTN Output Voltage
TEMPERATURE (°C)
–50
OUTP OUTPUT VOLTAGE (V)
100
3032 G60
0 50
15.300
15.225
15.150
15.075
15.000
14.925
14.850
14.775
14.700 –25 25 75
125
IL = 1mA
TEMPERATURE (°C)
–50
OUTN OUTPUT VOLTAGE (V)
100
3032 G61
0 50
–15.300
–15.225
–15.150
–15.075
–15.000
–14.925
–14.850
–14.775
–14.700 –25 25 75
125
IL = –1mA
LT3032-3.3
INP Quiescent Current
LT3032-3.3
INN Quiescent Current
INPUT VOLTAGE (V)
0
INP QUIESCENT CURRENT (µA)
400
350
300
250
200
150
100
50
08
3032 G72
21 3 5 7 9
46
10
VSHDN = VIN
TJ = 25°C
RL = ∞
VSHDN = 0V
INN VOLTAGE (V)
–80
–70
–60
–50
–40
–30
–20
–10
–0
3032 G73
INN QUIESCENT CURRENT (µA)
0 –2 –4 –6 –8 –10 –12 –14 –16 –18
–20
TJ = 25°C
RL = ∞
VSHDNN = VINN
VSHDNN = 0V
LT3032 Series
8
3032ff
For more information www.linear.com/LT3032
TYPICAL PERFORMANCE CHARACTERISTICS
LT3032-3.3
Positive Side GND Pin Current
INPUT VOLTAGE (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
GND PIN CURRENT (mA)
3032 G74
0123456 7 8 9
10
TJ = 25°C
VIN = VSHDN
*FOR VOUT = 3V
RL = 22Ω
IL = 150mA*
RL = 33Ω
IL = 100mA*
RL = 66Ω
IL = 50mA*
LT3032 INP Quiescent Current
INP VOLTAGE (V)
0 2 6 10 14 18
INP QUIESCENT CURRENT (µA)
30
25
20
15
10
5
04 8 12 16
3032 G09
20
TJ = 25°C
RL = 250k
VSHDNP = VINP
VSHDNP = 0V
LT3032-15 INN Quiescent CurrentLT3032-15 INP Quiescent Current
INN VOLTAGE (V)
0
INN QUIESCENT CURRENT (µA)
–80
–70
–60
–50
–40
–30
–20
–10
0–16
3032 G65
–4–2 –6 –10 –14 –18
–8 –12 –20
TJ = 25°C
RL = ∞
VSHDNN = 0V
VSHDNN = VINN
INP VOLTAGE (V)
0
INP QUIESCENT CURRENT (µA)
400
350
300
250
200
150
100
50
016
3032 G64
42 6 10 14 18
812
20
TJ = 25°C
RL = ∞
VSHDNP = 0V
VSHDNP = VINP
LT3032 INN Quiescent Current
INN VOLTAGE (V)
–40
–35
–30
–25
–20
–15
–10
–5
–0
3032 G10
INN QUIESCENT CURRENT (µA)
0 –2 –4 –6 –8 –10 –12 –14 –16 –18 –20
TJ = 25°C
RL = 250k
IL = –5µA VSHDNN = VINN
VSHDNN = 0V
LT3032-5 INP Quiescent Current LT3032-5 INN Quiescent Current
LT3032-12 INN Quiescent Current
LT3032-12 INP Quiescent Current
INP VOLTAGE (V)
0
INP QUIESCENT CURRENT (µA)
400
350
300
250
200
150
100
50
016
3032 G54
42 6 10 14 18
812 20
VSHDNP = VINP
TJ = 25°C
RL = ∞
VSHDNP = 0V
INN VOLTAGE (V)
–60
–50
–40
–30
–20
–10
–0
3032 G55
INN QUIESCENT CURRENT (µA)
0 –2 –4 –6 –8 –10 –12 –14 –16 –18 –20
TJ = 25°C
RL = ∞
VSHDNN = VINN
VSHDNN = 0V
INP VOLTAGE (V)
0
INN QUIESCENT CURRENT (µA)
–80
–70
–60
–50
–40
–30
–20
–10
0–16
3032 G63
–4–2 –6 –10 –14 –18
–8 –12
–20
TJ = 25°C
RL = ∞
VSHDNN = 0V
VSHDNN = VINN
INP VOLTAGE (V)
0
INP QUIESCENT CURRENT (µA)
400
350
300
250
200
150
100
50
016
3032 G62
42 6 10 14 18
812
20
TJ = 25°C
RL = ∞
VSHDNP = 0V
VSHDNP = VINP
LT3032 Series
9
3032ff
For more information www.linear.com/LT3032
LT3032
Negative Side GND Pin Current
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
3032 G12
GND PIN CURRENT (mA)
0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10
RL = 12.2Ω
IL = –100mA*
RL = 24.4Ω
IL = –50mA*
RL = 122Ω
IL = –10mA*
TJ = 25°C; VSHDNN = VINN;
*FOR VOUTN = –1.22V
RL = 8.07Ω
IL = –150mA*
INN VOLTAGE (V)
TYPICAL PERFORMANCE CHARACTERISTICS
LT3032-15
Positive Side GND Pin Current
INP VOLTAGE (V)
0
GND PIN CURRENT (mA)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
016
3032 G68
42 6 10 14 18
812
20
TJ = 25°C
VSHDNP = VINP
*FOR VOUTP = 15V
RL = 100Ω
*IL = 150mA
RL = 150Ω
*IL = 100mA
RL = 300Ω
*IL = 50mA
LT3032
Positive Side GND Pin Current
INP VOLTAGE (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
GND PIN CURRENT (mA)
3032 G11
0123456 7 8 9 10
RL = 8.07Ω
IL = 150mA*
RL = 12.2Ω
IL = 100mA*
RL = 24.4Ω
IL = 50mA*
TJ = 25°C
VINP = VSHDNP
*FOR VOUTP = 1.22V
LT3032-15
Negative Side GND Pin Current
INN VOLTAGE (V)
0
GND PIN CURRENT (mA)
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0–16
3032 G69
–4–2 –6 –10 –14 –18
–8 –12
–20
TJ = 25°C
VSHDNN = VINN
*FOR VOUTN = –15V RL = 100Ω
*IL = –150mA
RL = 300Ω, *IL = 50mA
RL = 1.5k, *IL = –10mA
RL = 150Ω
*IL = –100mA
LT3032-12
Negative Side GND Pin Current
INN VOLTAGE (V)
0
GND PIN CURRENT (mA)
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0–16
3032 G67
–4–2 –6 –10 –14 –18
–8 –12
–20
TJ = 25°C
VSHDNN = VINN
*FOR VOUTN = –12V
RL = 80Ω
*IL = –150mA
RL = 120Ω
*IL = –100mA
RL = 240Ω
*IL = –50mA
RL = 1.2k, *IL = –10mA
LT3032-12
Positive Side GND Pin Current
INP VOLTAGE (V)
0
GND PIN CURRENT (mA)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
016
3032 G66
42 6 10 14 18
812
20
TJ = 25°C
VSHDNP = VINP
*FOR VOUTP = 12V RL = 80Ω
*IL = 150mA
RL = 120Ω
*IL = 100mA
RL = 240Ω
*IL = 50mA
LT3032-5
Positive Side GND Pin Current
LT3032-5
Negative Side GND Pin Current
LT3032-3.3
Negative Side GND Pin Current
INP VOLTAGE (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
GND PIN CURRENT (mA)
3032 G56
0123456 7 8 9 10
RL = 33.3Ω
IL = 150mA*
RL = 50Ω
IL = 100mA*
RL = 100Ω
IL = 50mA*
TJ = 25°C
VINP = VSHDNP
*FOR VOUTP = 5V
INN VOLTAGE (V)
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
3032 G57
GND PIN CURRENT (mA)
0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10
TJ = 25°C
VSHDNN = VINN
*FOR VOUTN = –5V RL = 33.3Ω
IL = 150mA*
RL = 50Ω
IL = –100mA*
RL = 100Ω
IL = –50mA*
RL = 500Ω
IL = –10mA*
INN VOLTAGE (V)
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
3032 G75
GND PIN CURRENT (mA)
0 –1 –2 –3 –4 –5 –6 –7 –8 –9
–10
TJ = 25°C
VSHDNN = VINN
*FOR VOUTN = –3.3V
RL = 22Ω
IL = 150mA*
RL = 33Ω
IL = –100mA*
RL = 66Ω
IL = –50mA*
RL = 330Ω
IL = –10mA*
LT3032 Series
10
3032ff
For more information www.linear.com/LT3032
TYPICAL PERFORMANCE CHARACTERISTICS
SHDNN Pin Input Current
10
8
6
4
2
0
–2
–4
–6
–8
–10
3032 G19
SHDNN PIN INPUT CURRENT (µA)
SHDNN PIN VOLTAGE (V)
–10 –8 –6 –4 –2 0 2 4 6 8 10
TJ = 25°C
POSITIVE CURRENT
FLOWS INTO THE PIN
SHDNN Pin Input Current ADJP Pin Bias Current
12
9
6
3
0
–3
–6
–9
3032 G20
SHDNN PIN INPUT CURRENT (µA)
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
VSHDNN = 15V
VSHDNN = –15V
VINN = –15V
POSITIVE CURRENT
FLOWS INTO THE PIN
TEMPERATURE (°C)
–50
ADJP PIN BIAS CURRENT (nA)
050 75
3032 G21
–25 25 100 125
140
120
100
80
60
40
20
0
SHDNN Pin Thresholds SHDNP Pin Input Current SHDNP Pin Input Current
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
3032 G16
SHDNN PIN VOLTAGE (V)
ON
ON
OFF
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
SHDNP PIN VOLTAGE (V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
SHDNP PIN INPUT CURRENT (µA)
3032 G17
0123456 7 8 9 10
TEMPERATURE (°C)
–50 100
3032 G18
0 50
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0–25 25 75 125
SHDNP PIN INPUT CURRENT (µA)
VSHDNP = 20V
Positive Side GND Pin Current
vs ILOAD
Negative Side GND Pin Current
vs ILOAD SHDNP Pin Threshold
POSITIVE LOAD CURRENT (mA)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
GND PIN CURRENT (mA)
3032 G13
0 20 40 60 80 100 120 140 160
VINP = VOUTP(NOMINAL) + 1V
TJ = 25°C
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
3032 G14
GND PIN CURRENT (mA)
0 –40 –60–20 –80 –120 –140–100 –160
VINN = VOUTN(NOMINAL) – 1V
TJ = –50°C
TJ = 25°C
TJ = 125°C
NEGATIVE LOAD CURRENT (mA) TEMPERATURE (°C)
–50
SHDNP PIN THRESHOLD (V)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0050 75
3032 G15
–25 25 100 125
IL = 1mA
ON
OFF
LT3032 Series
11
3032ff
For more information www.linear.com/LT3032
Reverse OUTP Pin Current INP-to-OUTP Ripple Rejection INP-to-OUTP Ripple Rejection
TEMPERATURE (°C)
–50
REVERSE OUTP CURRENT (µA)
45
40
35
30
25
20
15
10
5
0050 75
3032 G28
–25 25 100 125
(LT3032-3.3/LT3032-5)
(LT3032-12/LT3032-15)
(LT3032)
VINP = 0V
VOUTP = VADJP =1.22V (LT3032)
VOUTP = 5V (LT3032-5)
VOUTP = 12V (LT3032-12)
VOUTP = 15V (LT3032-15)
FREQUENCY (Hz)
INP-TO-OUTP RIPPLE REJECTION (dB)
80
70
60
50
40
30
20
10
010 1k 10k 1M
3032 G29
100 100k
IL = 150mA
VINP = VOUTP(NOMINAL) +
1.5V + 50mVRMS RIPPLE
CBYPP = 0
COUTP = 2.2µF
COUTP = 10µF
FREQUENCY (Hz)
INP-TO-OUTP RIPPLE REJECTION (dB)
80
70
60
50
40
30
20
10
010 1k 10k 1M
3032 G30
100 100k
IL = 150mA
VINP = VOUTP(NOMINAL) +
1.5V + 50mVRMS RIPPLE
COUTP = 10µF
CBYPP = 0.01µF
CBYPP = 100pF
CBYPP = 1000pF
TYPICAL PERFORMANCE CHARACTERISTICS
Negative Side Current Limit Reverse OUTP Pin Current
TEMPERATURE (°C)
–600
–500
–400
–300
–200
–100
0
3032 G26
NEGATIVE SIDE CURRENT LIMIT (mA)
–50 –25 0 25 50 75 100 125
VINN = –7V
VOUTN = 0V
OUTP PIN VOLTAGE (V)
100
90
80
70
60
50
40
30
20
10
0
REVERSE OUTP PIN CURRENT (µA)
3032 G27
0246810 12 14 16 18 20
TJ = 25°C, VINP = 0V
CURRENT FLOWS
INTO OUTP PIN
VOUTP = VADJP (LT3032)
LT3032
LT3032-5
LT3032-15
LT3032-12
LT3032-3.3
Negative Side Current Limit
INN-TO-OUTN DIFFERENTIAL VOLTAGE (V)
0
–600
–500
–400
–300
–200
–100
0
3032 G25
–4 –8 –12 –16 –20
NEGATIVE SIDE CURRENT LIMIT (mA)
∆VOUTN = 100mV
Positive Side Current Limit Positive Side Current Limit
500
450
400
350
300
250
200
150
100
50
0
INP-TO-OUTP DIFFERENTIAL VOLTAGE (V)
0
POSITIVE SIDE CURRENT LIMIT (mA)
245
3032 G23
1367
VOUTP = 0V
500
450
400
350
300
250
200
150
100
50
0
POSITIVE SIDE CURRENT LIMIT (mA)
3032 G24
VINP = 7V
VOUTP = 0V
TEMPERATURE (°C)
–50 0 50 75
–25 25 100 125
ADJN Pin Bias Current
–70
–60
–50
–40
–30
–20
–10
0
3032 G22
ADJN PIN BIAS CURRENT (nA)
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
LT3032 Series
12
3032ff
For more information www.linear.com/LT3032
TYPICAL PERFORMANCE CHARACTERISTICS
Negative Load Regulation OUTP Noise Spectral Density
TEMPERATURE (°C)
60
50
40
30
20
10
0
3032 G37
LOAD REGULATION (mV)
LT3032-5
LT3032-15
LT3032-12
LT3032
VINN = VOUTN(NOMINAL) – 1V
IL = –1mA TO –150mA
–50 –25 0 25 50 75 100 125
LT3032-3.3
FREQUENCY (Hz)
10 1k 10k 100k
3032 G38
100
10
1
0.1
0.01
OUTP NOISE SPECTRAL DENSITY (µV/√Hz)
CBYPP = 1000pF
CBYPP = 100pF
COUTP = 10µF
IL = 150mA
CBYPP = 0.01µF
VOUTP = 5V
VOUTP = VADJP
VOUTP = VADJP
VOUTP = 5V
OUTN Noise Spectral Density
FREQUENCY (Hz)
0.1
OUTN NOISE SPECTRAL DENSITY (µV/√Hz)
1
10 1k 10k 100k
3032 G39
0.01 100
10
COUTN = 10µF
IL = –150mA
CBYPN = 1000pF
CBYPN = 0
VOUTN = –5V
VOUTN = VADJN
CBYPN = 0.01µF
CBYPN = 100pF
LT3032 Minimum INP Pin Voltage LT3032 Minimum INN Pin Voltage
TEMPERATURE (°C)
–50
MINIMUM INP PIN VOLTAGE (V)
050 75
3032 G34
–25 25 100 125
IL = 150mA
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
IL = 1mA
VOUTP = 1.22V
TEMPERATURE (°C)
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
3032 G35
MINIMUM INN PIN VOLTAGE (V)
IL = –150mA
IL = –1mA
–50 –25 0 25 50 75 100 125
NOTE: THE SHDNN PIN THRESHOLD
MUST BE MET TO ENSURE
DEVICE OPERATION
Positive Load Regulation
TEMPERATURE (°C)
0
–10
–20
–30
–40
–50
–60
–70
3032 G36
LOAD REGULATION (mV)
–50 –25 0 25 50 75 100 125
VINP = VOUTP(NOMINAL) +1V
∆IL = 1mA TO 150mA
LT3032
LT3032-5
LT3032-12
LT3032-3.3
LT3032-15
INN-to-OUTN Ripple Rejection
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
INN-TO-OUTN RIPPLE REJECTION (dB)
80
70
60
50
40
30
20
10
0
3032 G31
IL = –150mA
VINN = VOUTN(NOMINAL) – 1.5V +
50mVRMS RIPPLE
CBYPN = 0
COUTN = 10µF
COUTN = 1µF
INP-to-OUTP Ripple Rejection INN-to-OUTN Ripple Rejection
TEMPERATURE (°C)
–50
INP-TO-OUTP RIPPLE REJECTION (dB)
100
3032 G32
0 50
68
66
64
62
60
58
56
54
52 –25 25 75 125
VINP = VOUTP(NOMINAL) +
1.5V + 0.5VP-P RIPPLE
AT f = 120Hz
IL = 150mA
TEMPERATURE (°C)
60
58
56
54
52
50
48
46
44
3032 G33
INN-TO-OUTN RIPPLE REJECTION (dB)
VINN = VOUTN(NOMINAL) – 1.5V +
0.5VP-P RIPPLE AT f = 120Hz
IL = –150mA
–50 –25 0 25 50 75 100 125
LT3032 Series
13
3032ff
For more information www.linear.com/LT3032
TYPICAL PERFORMANCE CHARACTERISTICS
OUTN, 10Hz to 100kHz
Output Noise, CBYPN = 0
1ms/DIVCOUTN = 10µF
ILOAD = –150mA
VOUTN = –5V
VOUTN
200µV/DIV
3032 G46
OUTP 10Hz to 100kHz Output Noise
CBYPP = 0.01µF
1ms/DIVCOUTP = 10µF
IL = 150mA
VOUTP = 5V
VOUTP
100µV/DIV
3032 G45
OUTP 10Hz to 100kHz Output Noise
CBYPP = 0
1ms/DIVCOUTP = 10µF
IL = 150mA
VOUTP = 5V
VOUTP
100µV/DIV
3032 G44
OUTN, 10Hz to 100kHz Output
Noise, CBYPN = 0.01µF
OUTP Transient Response
CBYPP = 0
VOUTN
100µV/DIV
1ms/DIVCOUTN = 10µF
ILOAD = –150mA
VOUTN = –5V
3032 G47
TIME (µs)
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
OUTP VOLTAGE
DEVIATION (V)
150
100
50
0
LOAD CURRENT
(mA)
3032 G48
0 400 800 1200 1600 2000
VOUTP = 5V
VINP = 6V
CINP = 10µF
COUTP = 10µF
OUTN RMS Noise
vs Load Current (10Hz to 100kHz)
140
120
100
80
60
40
20
0
LOAD CURRENT (mA)
OUTN RMS NOISE (µVRMS)
–0.01
3032 G43
LT3032
LT3032-5
LT3032-3.3
LT3032-12
LT3032-15
–1 –10 –1k–0.1
LT3032
LT3032-5
LT3032-12
LT3032-15
LT3032-3.3
–100
CBYPN = 0
CBYPN = 0.01µF COUTN = 10µF
OUTN RMS Noise
vs Bypass Capacitor
CBYPN (pF)
10
OUTN RMS NOISE (µVRMS)
250
200
150
100
50
0
LT3032-5
100 1k 10k
3032 G42
COUTN = 10µF
IL = –150mA
f = 10Hz TO 100kHz
LT3032
LT3032-15
LT3032-12
LT3032-3.3
OUTP RMS Noise
vs Load Current (10Hz to 100kHz)
LOAD CURRENT (mA)
0.01
OUTP RMS NOISE (µVRMS)
350
300
250
200
150
100
50
00.1 1
3032 G41
10 100 1k
LT3032
LT3032-5
LT3032-3.3
LT3032-12
LT3032-15
COUTP = 10µF
CBYPP = 0
CBYPP = 0.01µF
LT3032-3.3
LT3032-5
LT3032
LT3032-12
LT3032-15
OUTP RMS Noise
vs Bypass Capacitor
CBYPP (pF)
10
OUTP RMS NOISE (µVRMS)
350
300
250
200
150
100
50
0100 1k 10k
3032 G40
COUTP = 10µF
IL = 150mA
f = 10Hz TO 100kHz
LT3032
LT3032-5
LT3032-3.3
LT3032-15
LT3032-12
LT3032 Series
14
3032ff
For more information www.linear.com/LT3032
PIN FUNCTIONS
OUTP (Pin 1): Positive Output. This output supplies power
to the positive side load. A minimum output capacitor
of 2.2µF is required to prevent oscillations. Larger out-
put capacitors are required for applications with large
transient loads to limit peak voltage transients. See the
Applications Information section for more information
on output capacitance, bypass capacitance, and reverse
output characteristics.
ADJP (Pin 2, Adjustable Part Only): Positive Adjust. This
is the input to the positive side error amplifier. This pin
is internally clamped to ±7V. It has a typical bias current
of 30nA which flows into the pin (see curve of ADJP Pin
Bias Current vs Temperature in the Typical Performance
Characteristics). The ADJP pin voltage is 1.22V referenced
to ground and the output voltage range is 1.22V to 20V.
BYPP (Pin 3): Positive Bypass. The BYPP pin is used to
bypass the reference of the positive side regulator to achieve
low noise performance. The BYPP pin is clamped internally
to ±0.6V (one VBE). A small capacitor from OUTP to this pin
will bypass the reference to lower the output voltage noise.
A maximum value of 0.01µF is used for reducing output
voltage noise to a typical 20µVRMS over the 10Hz to 100kHz
bandwidth. If not used, this pin must be left unconnected.
GND (Pins 4, 5, Exposed Pad Pin 15): Ground. One of
the DFN’s exposed backside pads (Pin 15) is an electrical
connection to ground. To ensure proper electrical and
thermal performance, solder Pin 15 to the PCB’s ground
and tie directly to Pins 4 and 5. Connect the bottom of
the positive and negative output voltage setting resistor
dividers directly to Pins 4 and 5 for optimum load regula-
tion performance.
INN (Pin 6, 9, Exposed Pad Pin 16): Negative Input. The
DFN package’s second exposed backside pad (Pin 16) is
an electrical connection to INN. To ensure proper electri-
cal and thermal performance, solder Pin 16 to the PCB’s
negative input supply and tie directly to Pins 6 and 9.
Power is supplied to the negative side of the LT3032
through the INN pins. A bypass capacitor is required on
this pin if it is more than six inches away from the main
input filter capacitor. In general, the output impedance of
a battery rises with frequency, so it is advisable to include
a bypass capacitor in battery-powered circuits. A bypass
capacitor in the range of 1µF to 10µF is sufficient.
TYPICAL PERFORMANCE CHARACTERISTICS
OUTP Transient Response
CBYPP = 0.01µF
TIME (µs)
0.04
0.02
0
–0.02
–0.04
OUTP VOLTAGE
DEVIATION (V)
150
100
50
0
LOAD CURRENT
(mA)
3032 G49
0 40 80 120 160 200
VOUTP = 5V
VINP = 6V
CINP = 10µF
COUTP = 10µF
OUTN Transient Response
CBYPN = 0
OUTN Transient Response
CBYPN = 0.01µF
TIME (µs)
0.2
0.1
0
–0.2
–0.1
0
–50
–150
–100
OUTN VOLTAGE
DEVIATION (V)
LOAD CURRENT
(mA)
3032 G50
0 100 200 300 400 500 600 700 800 900 1k
VOUTN = –5V
VINN = –6V
CINN = 10µF
COUTN = 10µF
TIME (µs)
0.04
0.06
0.02
0
–0.02
–0.04
–0.06
–50
0
–100
–150
OUTN VOLTAGE
DEVIATION (V)
LOAD CURRENT
(mA)
3032 G51
0 50 100 150 200 250 300 350 400 450 500
VOUTN = –5V
VINN = –6V
CINN = 10µF
COUTN = 10µF
LT3032 Series
15
3032ff
For more information www.linear.com/LT3032
OUTN (Pin 7): Negative Output. This output supplies power
to the negative side load. A minimum output capacitor
of 1µF is required to prevent oscillations. Larger output
capacitors are required for applications with large tran-
sient loads to limit peak voltage transients. A parasitic
diode exists between OUTN and INN; OUTN can not be
pulled more negative than INN during normal operation,
or more than 0.5V below INN during a fault condition. See
the Applications Information section for more information
on output capacitance and bypass capacitors.
ADJN (Pin 8, Adjustable Part Only): Negative Adjust. This
is the input to the negative side error amplifier. The ADJN
pin has a typical bias current of 30nA that flows out of the
pin. The ADJN pin voltage is –1.22V referenced to ground,
and the output voltage range is –1.22V to –20V. A parasitic
diode exists between ADJN and INN. The ADJN pin cannot
be pulled more negative than INN during normal operation,
or more than 0.5V below INN during a fault condition.
SHDNN (Pin 10): Negative Shutdown. The SHDNN pin puts
the negative side into a low power shutdown state. The
SHDNN pin is referenced to ground for regulator control,
allowing the negative side to be driven by either positive
or negative logic. The negative output will be off if the
SHDNN pin is within ±0.8V(typical) of ground. Pulling the
SHDNN pin more than –1.9V or +1.4V(typical) will turn the
negative output on. The SHDNN pin can be driven by 5V
logic or open-collector logic with a pull-up resistor. The
pull-up resistor is required to supply the pull-up current of
the open-collector device, normally several microamperes,
and the SHDNN pin current, typically 3µA out of the pin
(for negative logic) or 6µA into the pin (for positive logic).
If unused, the SHDNN pin must be connected to INN. The
negative output will be shut down if the SHDNN pin is open
circuit. A parasitic diode exists between SHDNN and INN,
the SHDNN pin cannot be pulled more negative than INN
during normal operation, or more than 0.5V below INN
during a fault condition.
PIN FUNCTIONS
BYPN (Pin 11): Negative Bypass. The BYPN pin is used
to bypass the reference of the negative side regulator to
achieve low noise performance. A small capacitor from
OUTN to this pin will bypass the reference to lower the
output voltage noise. A maximum value of 0.01µF is used
for reducing output voltage noise to a typical 30µVRMS
over the 10Hz to 100kHz bandwidth. If not used, this pin
must be left unconnected.
SHDNP (Pin 12): Positive Shutdown. The SHDNP pin puts
the positive side into a low power shutdown state. The
positive output will be off when the SHDNP pin is pulled
below 0.6V(typical). The SHDNP pin can be driven by 5V
logic or open-collector logic with a pull-up resistor. The
pull-up resistor is required to supply the pull-up current
of the open-collector device, normally several microam-
peres, and the SHDNP pin current, typically 1µA into the
pin. If unused, the SHDNP pin must be connected to INP.
The positive output will be shut down if the SHDNP pin
is open circuit. The SHDNP pin can be tied directly to the
SHDNN pin and both pins driven directly by positive logic
for a single point control of both outputs.
NC (Pin 13/Pins 2, 8 for Fixed Voltage Devices): No
Connect. The No Connect pin has no connection to inter-
nal circuitry and may be tied to INP, GND, INN, SHDNP,
SHDNN, OUTP, OUTN, floated, or tied to any other point.
INP (Pin 14): Positive Input. Power is supplied to the
positive side of the LT3032 through the INP pin. A bypass
capacitor is required on this pin if it is more than six inches
away from the main input filter capacitor. In general, the
output impedance of a battery rises with frequency, so
it is advisable to include a bypass capacitor in battery-
powered circuits. A bypass capacitor in the range of 1µF
to 10µF is sufficient.
LT3032 Series
16
3032ff
For more information www.linear.com/LT3032
The LT3032 is a dual 150mA positive and negative low noise
low dropout linear regulator with micropower quiescent
current and shutdown. It supplies ±150mA at a dropout
of 300mV. Output voltage noise can be lowered on the
positive side to 20µVRMS and to 30µVRMS on the negative
side over the 10Hz to 100kHz bandwidth with the addition
of 0.01µF reference bypass capacitors. Additionally, the
reference bypass capacitors improve transient response,
lowering the settling time for transient load conditions.
Quiescent current is 25µA for the positive side and –30µA
for the negative side (45µA each for the LT3032-12/
LT3032-15), typically dropping to less than 3µA total in
shutdown. In addition to the low quiescent current, the
LT3032 incorporates several protection features which
make it ideal for use in battery-powered systems. If the
load is common mode between the two outputs, it does
not matter which output starts first; either output can be
pulled to the opposing side of ground and the regulator
will still start and operate.
Setting Output Voltage
The adjustable LT3032 has output voltage ranges of 1.22V
to 20V for the positive side and –1.22V to –20V for the
negative side. The output voltages are set by the ratio of
two external resistor dividers as shown in Figure 1. The
LT3032 servos the outputs to maintain the voltages at the
ADJP and ADJN pins to 1.22V and –1.22V, respectively.
The current in the bottom resistor of each divider (R1P
or R1N) is equal to 1.22V/R1 and the current in the top
resistor (R2P or R2N) is equal to the current in the bottom
resistor plus the respective ADJP/ADJN pin bias current.
The bias current for ADJP and ADJN is 30nA at 25°C,
flowing into the pin for ADJP and flowing out of the pin
for ADJN. The output voltages can then be calculated us-
ing the formulas shown in Figure 1. The value of R1P or
R1N should be less than 250k to minimize errors in the
resultant output voltage caused by the ADJP/ADJN pin
bias current. Note that in shutdown the respective output
is turned off and the divider current will be zero. Curves
of ADJP Pin Voltage, ADJN Pin Voltage, ADJP Pin Bias
Current, and ADJN Pin Bias Current (all vs Temperature)
appear in the Typical Performance Characteristics.
The LT3032 is tested and specified with the ADJP/ADJN
pin tied to the respective OUTP/OUTN pin and a ±5µA DC
load (unless otherwise specified) for an output voltage
of ±1.22V. Specifications for output voltages greater than
this will be proportional to ±1.22V; (VOUT/±1.22V). For
example, load regulation for an output current change
of 1mA to 150mA is –2mV typical at VOUTN = –1.22V. At
VOUTN = –12V, load regulation is:
(–12V/–1.22V)•(–2mV) = –19.6mV
Bypass Capacitors and Low Noise Performance
The LT3032 provides reasonable noise performance
without reference bypass capacitors from OUTP/OUTN
to the corresponding BYPP/BYPN pin. Using the LT3032
with the addition of reference bypass capacitors lowers
output voltage noise. Good quality low leakage capacitors
are recommended. These capacitors bypass the internal
references for the positive and negative sides of the LT3032,
providing low frequency noise poles. The noise poles
provided by the bypass capacitors decrease the output
voltage noise to as low as 20µVRMS for the positive side
and 30µVRMS for the negative side with the use of 0.01µF
bypass capacitors.
The BYPP pin and BYPN pin are high impedance nodes
and leakage into or out of these pins affects the reference
voltage. The BYPP pin operates at approximately 74mV at
Figure 1. Setting Output Voltages
APPLICATIONS INFORMATION
LT3032
OUTP VOUTP
VOUTN
R2P
R1P
R1N
R2N
ADJP
GND
ADJN
OUTN
3032 F01
+
+
VOUTP =1.22V 1+R2P
R1P
+IADJP
( )
R2P
( )
VADJP =1.22V
IADJP =30nA at 25°C
OUTPUT RANGE =1.22V TO 20V
VOUTN =–1.22V 1+R2N
R1N
+IADJN
( )
R2N
( )
VADJN =–1.22V
IADJN =–30nA at 25°C
OUTPUT RANGE =–1.22V TO – 20V
LT3032 Series
17
3032ff
For more information www.linear.com/LT3032
APPLICATIONS INFORMATION
25°C during normal operation where the BYPN pin oper-
ates at approximately –60mV. DC leakages on the order
of 1µA into or out of these pins can throw off the internal
reference by 20% or more.
Output Capacitance and Transient Response
The LT3032 requires output capacitors for stability. It
is designed to be stable with most low ESR capacitors
(typically ceramic, tantalum or low ESR electrolytic). A
minimum output capacitor of 2.2μF with an ESR of 3Ω
or less is recommended to prevent oscillations on each
output. The LT3032 is a micropower device and output
transient response is a function of output capacitance.
Larger values of output capacitance decrease peak devia-
tions and provide improved transient response for larger
load current changes. Additional capacitors, used to de-
couple individual components powered by the LT3032,
increase the effective output capacitor value. When using
bypass capacitors (for low noise operation), larger values
of output capacitors are needed. For 100pF of bypass ca-
pacitance, 3.3µF of output capacitance is recommended.
With a 330pF bypass capacitor or larger, a 4.7µF output
capacitor is recommended. The shaded region of Figure 2
defines the range over which the LT3032 is stable. The
minimum ESR needed is defined by the amount of bypass
capacitance used, while the maximum ESR is 3Ω. These
requirements are applicable to both the positive and nega-
tive linear regulator.
Give extra consideration to the use of ceramic capacitors.
Ceramic capacitors are manufactured with a variety of di-
electrics, each with different behavior across temperature
and applied voltage. The most common dielectrics used
are specified with EIA temperature characteristic codes of
Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are
good for providing high capacitances in a small package,
but they tend to have strong voltage and temperature
coefficients as shown in Figures 3 and 4. When used with
a 5V regulator, a 16V 10μF Y5V capacitor can exhibit an
effective value as low as 1μF to 2μF for the DC bias voltage
applied and over the operating temperature range. The X5R
and X7R dielectrics result in more stable characteristics
and are more suitable for use as the output capacitor.
The X7R type has better stability across temperature,
while the X5R is less expensive and is available in higher
values. Care still must be exercised when using X5R and
X7R capacitors. The X5R and X7R codes only specify
operating temperature range and maximum capacitance
change over temperature. Capacitance change due to DC
bias with X5R and X7R capacitors is better than Y5V and
Z5U capacitors, but can still be significant enough to drop
capacitor values below appropriate levels. Capacitor DC
bias characteristics tend to improve as component case
size increases, but expected capacitance at operating
voltage should be verified in situ for a given application.
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress. In
a ceramic capacitor, the stress can be induced by vibra-
tions in the system or thermal transients. Tapping on the
ceramic bypass capacitor with a pencil generated the noise
shown in Figure 5. Similar vibration induced behavior can
masquerade as increased output voltage noise.
OUTPUT CAPACITANCE (µF)
1
ESR (Ω)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
03 10
1762 F02
2 4 5 67 8 9
STABLE REGION
CBYP = 330pF
CBYP ≥ 3300pF
CBYP = 100pF
CBYP = 0
Figure 2. Stability
LT3032 Series
18
3032ff
For more information www.linear.com/LT3032
Stability and Input Capacitance
Low ESR, ceramic input bypass capacitors are acceptable
for applications without long input leads. However, applica-
tions connecting a power supply to an LT3032’s circuit’s
INP/INN and GND pins with long input wires combined
with low ESR, ceramic input capacitors are prone to voltage
spikes, reliability concerns and application-specific board
oscillations. The input wire inductance found in many
battery-powered applications, combined with the low ESR
ceramic input capacitor, forms a high-Q LC resonant tank
circuit. In some instances this resonant frequency beats
against the output current dependent LDO bandwidth and
interferes with proper operation. Simple circuit modifica-
tions/solutions are then required. This behavior is not
indicative of LT3032 instability, but is a common ceramic
input bypass capacitor application issue.
The self-inductance, or isolated inductance, of a wire is
directly proportional to its length. Wire diameter is not a
major factor on its self-inductance. For example, the self-
inductance of a 2-AWG isolated wire (diameter = 0.26”) is
about half the self-inductance of a 30-AWG wire (diameter
= 0.01”). One foot of 30-AWG wire has about 465nH of
self-inductance.
One of two ways reduces a wire’s self-inductance. One
method divides the current flowing towards the LT3032
between two parallel conductors. In this case, the farther
apart the wires are from each other, the more the self-
inductance is reduced; up to a 50% reduction when placed
a few inches apart. Splitting the wires basically connects
two equal inductors in parallel, but placing them in close
proximity gives the wires mutual inductance adding to
the self-inductance. The second and most effective way
to reduce overall inductance is to place both forward and
return current conductors (the input and GND wires) in
very close proximity. Two 30-AWG wires separated by only
0.02”, used as forward– and return– current conductors,
reduce the overall self-inductance to approximately one-
fifth that of a single isolated wire.
APPLICATIONS INFORMATION
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
3032 F03
20
0
–20
–40
–60
–80
–100 04810
2 6 12 14
X5R
Y5V
16
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
Figure 3. Ceramic Capacitor DC Bias Characteristics
TEMPERATURE (°C)
–50
40
20
0
–20
–40
–60
–80
–100 25 75
3032 F04
–25 0 50 100 125
Y5V
CHANGE IN VALUE (%)
X5R
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
Figure 4. Ceramic Capacitor Temperature Characteristics
OUTPUT SET TO 5V 3032 F05
Figure 5. Noise Resulting From Tapping on a Ceramic Capacitor
LT3032 Series
19
3032ff
For more information www.linear.com/LT3032
APPLICATIONS INFORMATION
If wiring modifications are not permissible for the applica-
tions, including series resistance between the power supply
and the input of the LT3032 also stabilizes the application.
As little as 0.1Ω to 0.5Ω, often less, is effective in damp-
ing the LC resonance. If the added impedance between
the power supply and the input is unacceptable, adding
ESR to the input capacitor also provides the necessary
damping of the LC resonance. However, the required ESR
is generally higher than the series impedance required.
Thermal Considerations
The power handling capability of the device is limited by
the maximum rated junction temperature (125°C). The
power dissipated by the device is made up of the follow-
ing components:
1. Output current of each side multiplied by the respective
input/output voltage differential: (IOUT)(VIN to VOUT),
and
2. GND pin current for each side multiplied by its input
voltage: (IGND)(VIN)
The GND pin current of each side is found by examining
the GND Pin Current curves in the Typical Performance
Characteristics. Total power dissipation equals the sum
for both channels of the components listed above.
The LT3032 has internal thermal limiting designed to pro-
tect each side of the regulator during overload conditions.
For continuous normal conditions, the maximum junction
temperature rating of 125°C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
The LT3032 is a surface mount device and heat sinking is
accomplished by using the heat spreading capabilities of
the PC board and its copper traces. Copper board stiffen-
ers and plated through-holes can also be used to spread
the heat generated by power devices.
Note that the exposed pads (Pins 15 and 16) are elect-
rically connected to ground (GND) and the negative input
(INN) respectively.
The following table lists thermal resistance as a function
of copper area on a fixed board size. All measurements
were taken in still air on a 4-layer FR-4 board with 1oz
solid internal planes and 2oz external trace planes with a
total finished board thickness of 1.6mm.
Table 3. DE Package, 14-Lead DFN
COPPER AREA
BOARD AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
TOPSIDE* BACKSIDE
2500mm22500mm22500mm232°C/W
1000mm22500mm22500mm233°C/W
225mm22500mm22500mm238°C/W
100mm22500mm22500mm243°C/W
*Device is mounted on topside
For further information on thermal resistance and using
thermal information, refer to JEDEC standard JESD51,
notably JESD51-12.
PCB layers, copper weight, board layout and thermal vias
affect the resultant thermal resistance. This table provides
thermal resistance numbers for best-case 4-layer boards
with 1oz internal and 2oz external copper. Modern, mul-
tilayer PCBs may not be able to achieve quite the same
level performance as found in this table.
LT3032 Series
20
3032ff
For more information www.linear.com/LT3032
APPLICATIONS INFORMATION
Calculating Junction Temperature
Example: Given a positive output voltage of 3.3V, a posi-
tive input voltage of 4V to 6V, output current range from
10mA to 150mA, negative output voltage of –3.3V, negative
input voltage of –5V to –6V, a negative output current of
–100mA, and a maximum ambient temperature of 50°C,
what will the maximum junction temperature be for a
2500mm2 board with topside copper of 1000mm2?
The power in each side equals:
PSIDE = (VIN(MAX) – VOUT)(IOUT(MAX))+(VIN(MAX)•IGND)
where,
IOUTP(MAX) = 150mA
VINP(MAX) = 6V
IGND at (IOUTP = 150mA, VINP = 6V) = 3.7mA
IOUTN(MAX) = –100mA
VINN(MAX) = –6V
IGND at (IOUTN = –100mA, VINN = –6V) = –1.5mA
The total power equals:
PTOTAL = PPOSITIVE + PNEGATIVE
So,
PPOSITIVE = 150mA(6V – 3.3V) + 3.7mA(6V) = 0.43W
PNEGATIVE = –100mA(–6V+3.3V)–1.5mA(–6V) =
0.28W
PTOTAL = 0.43W + 0.28W = 0.71W
Junction Temperature equals:
TJ = TA + PTOTAL • θJA (using tables)
TJ = 50°C + 0.71W • 33°C/W = 73.4°C
In this case, the junction temperature is below the maxi-
mum rating, ensuring reliable operation.
Protection Features
The LT3032 incorporates several protection features that
make it ideal for use in battery-powered circuits. In ad-
dition to the normal protection features associated with
monolithic regulators, such as current limiting and thermal
limiting, the LT3032 is protected against reverse input
voltages and reverse output voltages on both channels.
Current limit protection and thermal overload protection
protect the device against current overload conditions at
the outputs of the part. For normal operation, the junction
temperature should not be allowed to exceed 125°C.
The positive input of the LT3032 withstands 20V reverse
voltage. The negative input also withstands reverse volt-
age, but the negative input may not be more than 0.5V
(one VBE) higher than the OUTN and SHDNN pins. This
provides protection against batteries that are plugged in
backwards.
The outputs of the LT3032 can be pulled to opposing volt-
ages without damaging the part. The outputs may be pulled
to the opposing polarity with a load that is common mode
between the two and one regulator starts before the other;
in this condition, it does not matter which regulator started
first. Both sides are capable of having the output pulled to
the opposing polarity and both will still start and operate.
If an input is left open circuit or grounded, the corre-
sponding output can be pulled to its opposing polarity by
as much as 20V. The output will act like an open circuit;
no current will flow into or out of the pin. If the input is
powered by a voltage source, the output will source the
short-circuit current and will protect itself by thermal
limiting. In this case, grounding the respective SHDNP/
SHDNN pin will turn off that side of the LT3032 and stop
the output from sourcing current.
The ADJP pin can be pulled above or below ground by
±7V without damage to the device. If the input is left open
circuit or grounded, the ADJP pin acts like an open circuit
when pulled below ground and like a large resistor (typically
100k) in series with a diode when pulled above ground.
LT3032 Series
21
3032ff
For more information www.linear.com/LT3032
APPLICATIONS INFORMATION
In situations where the ADJP pin is connected to a resistor
divider that would pull the ADJP pin above its 7V clamp
voltage if the output is pulled high, the ADJP pin input
current must be limited to less than 5mA. For example, a
resistor divider is used to provide a 1.5V output from the
1.22V reference and the output is forced to 20V. The top
resistor of the divider must be chosen to limit the current
into the ADJP pin to less than 5mA when the ADJP pin is
at 7V. The 13V difference between OUTP and ADJP divided
by the 5mA maximum current into the ADJP pin yields a
minimum top resistor value of 2.6k.
In circuits where a backup battery is required on the posi-
tive output, several different input/output conditions can
occur. The output voltage may be held up while the input
is either pulled to ground, pulled to some intermediate
voltage or is left open circuit. Current flow back into OUTP
follows the curve shown in Figure 6.
If the INP pin is forced below the OUTP pin or the OUTP
pin is pulled above the INP pin, input current typically
drops to less than 2µA. This can happen if the device is
connected to a discharged (low voltage) battery and the
output is held up by a backup battery or a second regula-
tor circuit. The state of the SHDNP pin has no effect on
the reverse output current if OUTP is pulled above INP.
Figure 6. Reverse Output Current
OUTP PIN VOLTAGE (V)
100
90
80
70
60
50
40
30
20
10
0
REVERSE OUTP PIN CURRENT (µA)
3032 F06
0246810 12 14 16 18 20
TJ = 25°C, VINP = 0V
CURRENT FLOWS
INTO OUTP PIN
VOUTP = VADJP (LT3032)
LT3032
LT3032-5
LT3032-15
LT3032-12
LT3032-3.3
Like many IC power regulators, the negative side of the
LT3032 has safe operating area (SOA) protection. The safe
operating area protection activates when the differential
voltage between INN and OUTN is greater than -7V. The
SOA protection decreases current limit as a function of
the voltage differential between INN and OUTN and keeps
the power transistor inside a safe operating region for all
values of forward input-to-output voltage. The protection
is designed to provide some output current at all values
of INN to OUTN differential voltage up to the Absolute
Maximum Rating. A 50µA load is required to maintain
regulation for INN to OUTN differential voltages greater
than –7V. When in shutdown, protection circuitry remains
active and will cause the output to rise slightly at zero load.
A small pre-load is needed for zero output, if desired (see
graph of Quiescent Current vs Input Voltage in Typical
Performance Characteristics).
When power to the negative side is first turned on, as the
input voltage rises, OUTN follows INN, allowing the regula-
tor to start into very heavy loads. During start-up, as the
INN voltage is rising, the differential voltage between INN
and OUTN is small, allowing the negative side to supply
large output currents. With a high INN voltage, a problem
can occur wherein removal of an output short will not al-
low the output voltage to fully recover. Other regulators,
such as the LT1175, LT1964, and LT3080 also exhibit this
phenomenon, so it is not unique to the LT3032.
The problem occurs with a heavy output load when the INN
voltage is high and the OUTN voltage is low. Common situ-
ations are immediately after the removal of a short-circuit
or when the SHDNN pin is pulled high after the INN pin
has already been turned on. The load line for such a load
may intersect the output current curve at two points. If
this happens, there are two stable operating points for the
negative side of the LT3032. With this double intersection,
the INN supply may need to be cycled down to zero and
brought up again to make OUTN recover.
LT3032 Series
22
3032ff
For more information www.linear.com/LT3032
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT3032#packaging/ for the most recent package drawings.
3.00 ±0.10
(2 SIDES)
4.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
1.65 ± 0.101.65 ± 0.10
BOTTOM VIEW—EXPOSED PAD
0.75 ±0.05
R = 0.125
TYP
R = 0.05
TYP
3.00 REF
17
148
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DE14MA) DFN 0317 REV C
PIN 1 NOTCH
R = 0.20 OR
0.25 × 45°
CHAMFER
3.00 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.10 ±0.05
0.70 ±0.05
3.50
±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.25 ± 0.05
0.50 BSC
1.78 ±0.10
0.10 TYP
0.10 TYP
1.07
±0.10
1.07
±0.05
0.51 TYP
0.50 BSC
1.78 ±0.05
1.65 ± 0.05
0.78 ±0.05 0.88 ±0.05
1.65 ± 0.05 0.51 TYP
0.78 ±0.050.88 ±0.05
DE14MA Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1731 Rev C)
LT3032 Series
23
3032ff
For more information www.linear.com/LT3032
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 08/10 Updated all applicable sections to add fixed voltage ±5V option. 1-7, 9-14
B 01/11 Swapped OUTN and INN pins in Absolute Maximum Ratings.
Revised values in SHDNN and SHDNP descriptions in Pin Functions.
Revised quiescent current for the positive side up to 25µA in Applications Information.
2
12, 13
14
C 09/11 Updated to add 12V and 15V options. 1-12, 21
D 03/12 Added MP-Grade to Order Information and Absolute Maximum Ratings. 2, 3
E 08/14 Added ±3.3V option. 1-8, 10-12,
21, 24
F 04/17 Updated Package Description. 22
LT3032 Series
24
3032ff
For more information www.linear.com/LT3032
LINEAR TECHNOLOGY CORPORATION 2010
LT 0417 REV F • PRINTED IN USA
www.linear.com/LT3032
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LT3032
INP
10µF
10µF
3032 TA02
536k
536k
95.3k
250k
OUTP
5.5V TO
20V
–5.5V TO
–20V OUTNINN
ADJP
BYPP
BYPN
ADJN
GND
SHDNP
SHDNN
0.01µF
0.01µF
5V TO 15V
AT 150mA
–5V TO –15V
AT –150mA
ON
OFF
±5V to ±15V Tracking Supply
TYPICAL APPLICATION