NXP Semiconductors Data Sheet: Technical Data Document Number MPC5748G Rev. 4, 02/2017 MPC5748G MPC5748G Microcontroller Data Sheet Features * 2 x 160 MHz Power Architecture(R) e200Z4 Dual issue, 32-bit CPU - Single precision floating point operations - 8 KB instruction cache and 4 KB data cache - Variable length encoding (VLE) for significant code density improvements * 1 x 80 MHz Power Architecture(R) e200Z2 Single issue, 32-bit CPU - Using variable length encoding (VLE) for significant code size footprint reduction * End to end ECC - All bus masters, for example, cores generate single error correction, double error detection (SECDED) code for every bus transaction - SECDED covers 64-bit data and 29-bit address * Memory interfaces - 6 MB on-chip flash supported with the flash controller - 3 x flash page buffers (3 port flash controller) - 768 KB on-chip SRAM across three RAM ports * Clock interfaces - 8-40 MHz external crystal (FXOSC) - 16 MHz IRC (FIRC) - 128 KHz IRC (SIRC) - 32 KHz external crystal (SXOSC) - Clock Monitor Unit (CMU) - Frequency modulated phase-locked loop (FMPLL) - Real Time Counter (RTC) * System Memory Protection Unit (SMPU) with up to 32 region descriptors and 16-byte region granularity * 16 Semaphores to manage access to shared resource * Interrupt controller (INTC) capable of routing interrupts to any CPU * Multiple crossbar switch architecture for concurrent access to peripherals, flash, and RAM from multiple bus masters * Boot Assist Flash (BAF) supports internal flash programming via a serial link (LIN / SCI) * Analog - Two analog-to-digital converters (ADC), one 10-bit and one 12-bit - Three analogue comparators - Cross Trigger Unit to enable synchronization of ADC conversions with a timer event from the eMIOS or from the PIT * Communication - Four Deserial Peripheral Interface (DSPI) - Six Serial Peripheral interface (SPI) - 18 serial communication interface (LIN) modules - Eight enhanced FlexCAN3 with FD support - Four inter-IC communication interface (IIC) - One USB OTG Controller (USB_0) and One USB SPH Controller (USB_1) with ULPI Interface. - ENET complex (10/100 Ethernet) that supports Multi queue with AVB support, 1588, and MII/ RMII - 2 x ENET with L2 switch - Secure Digital Hardware Controller (uSDHC) - Dual-channel FlexRay Controller * Audio - 3 x Synchronous Audio Interface (SAI) - Fractional clock dividers (FCD) operating in conjunction with the SAIs * Configurable I/O domains supporting FLEXCAN, LINFlex, Ethernet, USB, MLB, uSDHC and general I/O * Supports wake-up from low power modes via the WKPU controller * On-chip voltage regulator (VREG) * Debug functionality - e200Z2 core:NDI per IEEE-ISTO 5001-2008 Class3+ - e200Z4 core(s): NDI per IEEE-ISTO 5001-2008 Class 3+ * 32-channels eDMA controller with multiple transfer request sources using DMAMUX NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. * Timer - 16 Periodic Interrupt Timers (PITs) - Three System Timer Module (STM) - Four Software WatchDog Timers (SWT) - 96 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels * Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) and 1149.7 (cJTAG) * Security - Hardware Security Module (HSMv2) - Password and Device Security (PASS and TDM) supporting advanced censorship and life-cycle management - One Fault Collection and Control Unit (FCCU) to collect faults and issue interrupts * Functional Safety - ISO26262 ASIL compliance * Multiple operating modes - Includes enhanced low power operation MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 2 NXP Semiconductors Table of Contents 1 Block diagram.................................................................................... 4 6.3.5 Flash memory AC timing specifications................... 41 2 Family comparison.............................................................................4 6.3.6 Flash read wait state and address pipeline control 3 Ordering parts.....................................................................................8 4 5 6 settings ...................................................................... 42 3.1 Determining valid orderable parts ..........................................8 6.4 Communication interfaces.......................................................42 3.2 Ordering Information ............................................................. 9 6.4.1 DSPI timing............................................................... 42 General............................................................................................... 9 6.4.2 FlexRay electrical specifications............................... 48 4.1 Absolute maximum ratings..................................................... 9 6.4.2.1 FlexRay timing...................................... 48 4.2 Recommended operating conditions....................................... 11 6.4.2.2 TxEN......................................................49 4.3 Voltage regulator electrical characteristics............................. 13 6.4.2.3 TxD........................................................ 50 4.4 Voltage monitor electrical characteristics............................... 16 6.4.2.4 RxD........................................................51 4.5 Supply current characteristics................................................. 18 6.4.3 uSDHC specifications............................................... 52 4.6 Electrostatic discharge (ESD) characteristics......................... 21 6.4.4 Ethernet switching specifications.............................. 53 4.7 Electromagnetic Compatibility (EMC) specifications............ 22 6.4.5 MediaLB (MLB) electrical specifications.................55 I/O parameters....................................................................................22 6.4.5.1 MLB 3-pin interface DC characteristics55 5.1 AC specifications @ 3.3 V Range...........................................22 6.4.5.2 MLB 3-pin interface electrical 5.2 DC electrical specifications @ 3.3V Range............................23 5.3 AC specifications @ 5 V Range..............................................24 5.4 DC electrical specifications @ 5 V Range..............................25 6.4.6.1 USB electrical specifications................. 57 5.5 Reset pad electrical characteristics..........................................26 6.4.6.2 ULPI timing specifications.................... 57 5.6 PORST electrical specifications..............................................28 specifications......................................... 55 6.4.6 6.4.7 Peripheral operating requirements and behaviours............................ 28 6.1 6.2 SAI electrical specifications ..................................... 58 Debug specifications............................................................... 60 Analog..................................................................................... 28 6.5.1 JTAG interface timing .............................................. 60 6.1.1 ADC electrical specifications.................................... 28 6.5.2 Nexus timing............................................................. 62 6.1.2 Analog Comparator (CMP) electrical specifications 33 6.5.3 WKPU/NMI timing................................................... 64 Clocks and PLL interfaces modules........................................34 6.5.4 External interrupt timing (IRQ pin)...........................65 6.2.1 Main oscillator electrical characteristics................... 34 6.2.2 32 kHz Oscillator electrical specifications ............... 36 6.2.3 16 MHz RC Oscillator electrical specifications........ 36 6.2.4 128 KHz Internal RC oscillator Electrical specifications ............................................................ 37 6.2.5 6.3 6.5 USB electrical specifications.....................................57 PLL electrical specifications .................................... 37 Memory interfaces...................................................................38 7 Thermal attributes.............................................................................. 65 7.1 8 Dimensions.........................................................................................67 8.1 9 Thermal attributes................................................................... 65 Obtaining package dimensions ...............................................67 Pinouts................................................................................................68 9.1 Package pinouts and signal descriptions................................. 68 10 Reset sequence................................................................................... 68 6.3.1 Flash memory program and erase specifications.......38 10.1 Reset sequence duration.......................................................... 68 6.3.2 Flash memory Array Integrity and Margin Read 10.2 BAF execution duration.......................................................... 68 specifications............................................................. 39 10.3 Reset sequence description......................................................69 6.3.3 Flash memory module life specifications..................40 11 Revision History.................................................................................71 6.3.4 Data retention vs program/erase cycles..................... 40 MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 3 Block diagram 1 Block diagram System bus masters 80 MHz e200z2 uSDHC MLB150 160 MHz e200z4 64-bit AHB HSM 8 KB i-cache 4 KB d-cache E2 E-ECC Ethernet(ENET) Ethernet Switch eDMA Flexray WKPU 3 x STM HS_USBSPH HS_USBOTG BAF PMC FMPLL 16 MHz FIRC RTC/API DEBUG/ JTAG 160 MHz e200z4 SPFP-APU Nexus 3+ E2 E-ECC 64-bit AHB Nexus 3+ 64-bit data System E2 E-ECC SMPU 4 x SWTs FCCU 3 x DSMC 2 x DSMC 16 x SEMA4 PASS 16 x PIT-RTI SSCM 32 KHz SXOSC MC_CGM, MC_PCU, MC_ME, MC_RGM 128 KHz SIRC SIUL 8-40 MHz FXOSC STCU (MBIST/ LBIST) 2 x MEMU CMU Padkeeper support TDM Flash 3xRAM E2 E-ECC E2 E-ECC 3 x SA-PF buffers 64-bit wide RAM Triple ported 256 KB array 6 MB array (inc EEE) 256 KB array Peripheral bridge E2 E-ECC Low power unit interface 256 KB array Peripheral clusters 80 ch 10-bit ADC0 64 ch 12-bit ADC1 1 x FlexCAN(PN) (mix int and ext) (mix int and ext) 7 x FlexCAN 1x 18 LinFlex 4 x I2C 3 x analog comparator (CMP) 4 x DSPI 6 x SPI 3 x SAI 3 x FCD 3 x eMIOS + BCTU 3-core INTC DMA and 2 x chmux 1 x CRC Register protection LPU_CTL *All FlexCANs optionally support CAN FD Figure 1. MPC5748G block diagram 2 Family comparison The following table provides a summary of the different members of the MPC5748G family and their proposed features. This information is intended to provide an understanding of the range of functionality offered by this family. For full details of all of the family derivatives please contact your marketing representative. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 4 NXP Semiconductors Family comparison NOTE All optional features (Flash memory, RAM, Peripherals) start with lowest peripheral number (for example: STM_0) or memory address and end at the highest available peripheral number or memory address (for example: MPC574xC have 2 STM, ending with STM_1). Table 1. MPC5748G Family Comparison1 Feature MPC5747C MPC5748C MPC5746G MPC5747G MPC5748G CPUs e200z4 e200z4 e200z4 e200z4 e200z4 e200z2 e200z2 e200z4 e200z4 e200z4 e200z2 e200z2 e200z2 e200z4 e200z4 e200z4 e200z4 e200z4 e200z4 FPU e200z4 Maximum Operating Frequency2 Flash memory EEPROM support RAM e200z4 160MHz (z4) 160MHz (z4) 160MHz (z4) 160MHz (z4) 160MHz (z4) 80MHz (z2) 80MHz (z2) 160MHz (z4) 160MHz (z4) 160MHz (z4) 80MHz (z2) 80MHz (z2) 80MHz (z2) 4 MB 6 MB 4 MB 6 MB 3 MB 32 KB to 128 KB emulated 32 KB to 192 KB emulated 512 KB 768 KB ECC End to End SMPU 24 entry 32 entry DMA 32 channels 10-bit ADC 48 Standard channels 32 External channels 12-bit ADC 16 Precision channels 16 Standard channels 32 External channels AnalogComparator 3 BCTU 1 SWT 2 STM 2 43 3 PIT-RTI 16 channels PIT 1 channels RTI RTC/API Total Timer Yes I/O4 96 channels 16-bits LINFlexD 1 M/S, 15 M 1 M/S, 17 M FlexCAN 8 with optional CAN FD support DSPI/SPI 4 x DSPI 6 x SPI Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 5 Family comparison Table 1. MPC5748G Family Comparison1 (continued) Feature MPC5747C MPC5748C MPC5746G I2C 4 SAI/I2S 3 FXOSC 8 - 40 MHz SXOSC 32 KHz FIRC 16 MHz SIRC 128 KHz FMPLL Yes LPU Yes FlexRay 2.1 (dual channel) Yes, 128 MB MPC5747G MLB150 0 1 USB 2.0 SPH 0 1 USB 2.0 OTG 0 1 SDHC 1 Ethernet (RMII, MII + 1588, Muti queue AVB support) Up to 2 3 Port L2 Ethernet Switch Optional CRC 1 MEMU 2 STCU 1 HSM-v2 (security) Optional Censorship Yes FCCU 1 Safety level Specific functions ASIL-B certifiable User MBIST Yes User LBIST Yes I/O Retention in Standby Yes GPIO5 Up to 264 GPI and up to 246 GPIO Debug JTAGC, MPC5748G cJTAG Nexus Z4 N3+ Z2 N3+ Packages 176 LQFP-EP 256 BGA, 324 BGA 1. Feature set dependent on selected peripheral multiplexing, table shows example. Peripheral availability is package dependent. 2. Based on 125C ambient operating temperature and subject to full device characterisation. 3. Additional SWT included when HSM option selected 4. Refer device datasheet and reference manual for information on to timer channel configuration and functions. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 6 NXP Semiconductors Family comparison 5. Estimated I/O count for largest proposed packages based on multiplexing with peripherals. Table 2. MPC5748G Family Comparison - NVM Memory Map 1 Start Address End Address Flash block RWW MPC5746 MPC5747 MPC5748 0x01000000 0x0103FFFF 256 KB code Flash block 0 6 available available available 0x01040000 0x0107FFFF 256 KB code Flash block 1 6 available available available 0x01080000 0x010BFFFF 256 KB code Flash block 2 6 available available available 0x010C0000 0x010FFFFF 256 KB code Flash block3 6 available available available 0x01100000 0x0113FFFF 256 KB code Flash block 4 6 available available available 0x01140000 0x0117FFFF 256 KB code Flash block 5 6 available available available 0x01180000 0x011BFFFF 256 KB code Flash block 6 6 available available available 0x011C0000 0x011FFFFF 256 KB code Flash block 7 6 available available available 0x01200000 0x0123FFFF 256 KB code Flash block 8 7 available available available 0x01240000 0x0127FFFF 256 KB code Flash block 9 7 available available available 0x01280000 0x012BFFFF 256 KB code Flash block 10 7 not available available available 0x012C0000 0x012FFFFF 256 KB code flash block 11 7 not available available available 0x01300000 0x0133FFFF 256 KB code flash block 12 7 not available available available 0x01340000 0x0137FFFF 256 KB code flash block 13 7 not available available available 0x01380000 0x013BFFFF 256 KB code flash block 14 7 not available not available available 0x013C0000 0x013FFFFF 256 KB code flash block 15 7 not available not available available 0x01400000 0x0143FFFF 256 KB code flash block 16 8 not available not available available 0x01440000 0x0147FFFF 256 KB code flash block 17 8 not available not available available 0x01480000 0x014BFFFF 256 KB code flash block 18 8 not available not available available 0x14C0000 0x014FFFFF 256 KB code flash block 19 9 not available not available available 0x01500000 0x0153FFFF 256 KB code flash block 20 9 not available not available available 0x01540000 0x0157FFFF 256 KB code flash block 21 9 not available not available available MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 7 Ordering parts Table 3. MPC5748G Family Comparison - NVM Memory Map 2 Start Address End Address Flash block RWW MPC5747C MPC5746G MPC5748C MPC5747G MPC5748G 0x00F90000 0x00F93FFF 16 KB data Flash 2 available available 0x00F94000 0x00F97FFF 16 KB data Flash 2 available available 0x00F98000 0x00F9BFFF 16 KB data Flash 2 available available 0x00F9C000 0x00F9FFFF 16 KB data Flash 2 available available 0x00FA0000 0x00FA3FFF 16 KB data Flash 3 available available 0x00FA4000 0x00FA7FFF 16 KB data Flash 3 available available 0x00FA8000 0x00FABFFF 16 KB data Flash 3 available available 0x00FAC000 0x00FAFFFF 16 KB data Flash 3 available available 0x00FB0000 0x00FB7FFF 32 KB data Flash 2 not available available 0x00FB8000 0x00FBFFFF 32 KB data flash 3 not available available Table 4. MPC5748G Family Comparison - RAM Memory Map Start Address End Address Allocated size [KB] MPC5747C MPC5748C MPC5746G MPC5747G MPC5748G 0x40000000 0x40001FFF 8 available available 0x40002000 0x4000FFFF 56 available available 0x40010000 0x4001FFFF 64 available available 0x40020000 0x4003FFFF 128 available available 0x40040000 0x4007FFFF 256 available available 0x40080000 0x400BFFFF 256 not available available 3 Ordering parts 3.1 Determining valid orderable parts To determine the orderable part numbers for this device, go to www.nxp.com and perform a part number search for the following device number: MPC5748G . MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 8 NXP Semiconductors General 3.2 Ordering Information P Example Code PC 57 4 8 G S K0 M MJ 6 R Qualification Status Power Architecture Automotive Platform Core Version Flash Size (core dependent) Product Optional fields Fab and mask indicator Temperature spec. Package Code CPU Frequency R = Tape & Reel (blank if Tray) Qualification Status P = Engineering samples S = Automotive qualified Product Version C = Body Control Feature Set G = Gateway Feature Set PC = Power Architecture Optional fields Blank = Feature not available S = HSM (Security Module) F = CAN FD B = Both HSM and CAN FD Automotive Platform 57 = Power Architecture in 55nm Core Version 4 = e200z4 Core Version (highest core version in the case of multiple cores) Flash Memory Size 6 = 3 MB 7 = 4 MB 8 = 6 MB T = HSM and 2nd Ethernet G = CAN FD and 2nd Ethernet H = HSM, CAN FD, and 2nd Eternet Fab and mask version indicator K=TSMC Fab #=Version of maskset 0=0N65H 1=1N81M 0A=0N78S Package Code KU = 176 LQFP EP MJ = 256 MAPBGA MN = 324 MAPBGA CPU Frequency 2 = Each z4 operates up to 120 MHz 6 = Each z4 operates up to 160 MHz Shipping Method R = Tape and reel Blank = Tray Temperature spec. C = -40.C to +85.C Ta V = -40.C to +105.C Ta M = -40.C to +125.C Ta , Note: Not all part number combinations are available as production product 4 General 4.1 Absolute maximum ratings NOTE Functional operating conditions appear in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maximum values is not guaranteed. See footnotes in Table 5 for specific conditions MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 9 General Stress beyond the listed maximum values may affect device reliability or cause permanent damage to the device. Table 5. Absolute maximum ratings Symbol VDD_HV_A, VDD_HV_B, VDD_HV_C2 VDD_HV_FLA3, 4 VDD_LP_DEC5 7 VDD_HV_ADC1_REF VDD_HV_ADC0 Conditions1 Min Max Unit 3.3 V - 5. 5V input/output supply voltage -- -0.3 6.0 V 3.3 V flash supply voltage (when supplying from an external source in bypass mode) -- -0.3 3.63 V Decoupling pin for low power regulators6 -- -0.3 1.32 V 3.3 V / 5.0 V ADC1 high reference voltage -- -0.3 6 V 3.3 V to 5.5V ADC supply voltage -- -0.3 6.0 V 3.3V to 5.5V ADC supply ground -- -0.1 0.1 V Parameter VDD_HV_ADC1 VSS_HV_ADC0 VSS_HV_ADC1 VDD_LV Core logic supply voltage -- -0.3 1.32 V VINA Voltage on analog pin with respect to ground (VSS_HV) -- -0.3 Min (VDD_HV_x, VDD_HV_ADCx, VDD_ADCx_REF) +0.3 V VIN Voltage on any digital pin with respect to ground (VSS_HV) Relative to VDD_HV_A, VDD_HV_B, VDD_HV_C -0.3 VDD_HV_x + 0.3 V Always -5 5 mA IINJPAD Injected input current on any pin during overload condition IINJSUM Absolute sum of all injected input currents during overload condition -- -50 50 mA Tramp 1. 2. 3. 4. 5. 6. 7. 8. Supply ramp rate -- 0.5 V / min 100V/ms -- TA8 Ambient temperature -- -40 125 C TSTG Storage temperature -- -55 165 C All voltages are referred to VSS_HV unless otherwise specified VDD_HV_B and VDD_HV_C are common together on the 176 LQFP-EP package. VDD_HV_FLA must be connected to VDD_HV_A when VDD_HV_A = 3.3V VDD_HV_FLA must be disconnected from ANY power sources when VDD_HV_A = 5V This pin should be decoupled with low ESR 1 F capacitor. Not available for input voltage, only for decoupling internal regulators 10-bit ADC does not have dedicated reference and its reference is double bonded to 10-bit ADC supply(VDD_HV_ADC0). TJ=150C. Assumes TA=125C * Assumes maximum JA. SeeThermal attributes MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 10 NXP Semiconductors General 4.2 Recommended operating conditions The following table describes the operating conditions for the device, and for which all specifications in the data sheet are valid, except where explicitly noted. The device operating conditions must not be exceeded in order to guarantee proper operation and reliability. The ranges in this table are design targets and actual data may vary in the given range. NOTE * For normal device operations, all supplies must be within operating range corresponding to the range mentioned in following tables. This is required even if some of the features are not used. * If VDD_HV_A is in 3.3V range, VDD_HV_FLA should be externally supplied using a 3.3V source. If VDD_HV_A is in 3.3V range, VDD_HV_FLA should be shorted to VDD_HV_A. * VDD_HV_A, VDD_HV_B and VDD_HV_C are all independent supplies and can each be set to 3.3V or 5V. The following tables: 'Recommended operating conditions (VDD_HV_x = 3.3 V)' and table 'Recommended operating conditions (VDD_HV_x = 5 V)' specify their ranges when configured in 3.3V or 5V respectively. Table 6. Recommended operating conditions (VDD_HV_x = 3.3 V) Symbol VDD_HV_A Conditions1 Min2 Max Unit HV IO supply voltage -- 3.15 3.6 V HV flash supply voltage -- 3.15 3.6 V HV ADC1 high reference voltage -- 3.0 5.5 V HV ADC supply voltage -- max(VDD_H V_A,VDD_H V_B,VDD_H V_C) - 0.05 3.6 V HV ADC supply ground -- -0.1 0.1 V Core supply voltage -- 1.2 1.32 V Analog Comparator DAC reference voltage -- 3.15 3.6 V Injected input current on any pin during overload condition -- -3.0 3.0 mA Parameter VDD_HV_B VDD_HV_C VDD_HV_FLA3 VDD_HV_ADC1_REF VDD_HV_ADC0 VDD_HV_ADC1 VSS_HV_ADC0 VSS_HV_ADC1 VDD_LV4 VIN1_CMP_REF5, 6 IINJPAD Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 11 General Table 6. Recommended operating conditions (VDD_HV_x = 3.3 V) (continued) Symbol Parameter Conditions1 Min2 Max Unit TA Ambient temperature under bias fCPU 160 MHz -40 125 C TJ Junction temperature under bias -- -40 150 C 1. All voltages are referred to VSS_HV unless otherwise specified 2. Device will be functional down (and electrical specifications as per various datasheet parameters will be guaranteed) to the point where one of the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset. 3. VDD_HV_FLA must be connected to VDD_HV_A when VDD_HV_A = 3.3V 4. VDD_LV supply pins should never be grounded (through a small impedance). If these are not driven, they should only be left floating. 5. VIN1_CMP_REF VDD_HV_A 6. This supply is shorted VDD_HV_A on lower packages. NOTE If VDD_HV_A is in 5V range, it is necessary to use internal Flash supply 3.3V regulator. VDD_HV_FLA should not be supplied externally and should only have decoupling capacitor. Table 7. Recommended operating conditions (VDD_HV_x = 5 V) Symbol VDD_HV_A Conditions 1 Min2 Max Unit HV IO supply voltage -- 4.5 5.5 V HV flash supply voltage -- 3.15 3.6 V HV ADC1 high reference voltage -- 3.15 5.5 V HV ADC supply voltage -- max(VDD_H V_A,VDD_H V_B,VDD_H V_C) - 0.05 5.5 V HV ADC supply ground -- -0.1 0.1 V Core supply voltage -- 1.2 1.32 V Analog Comparator DAC reference voltage -- 3.15 5.5 V Injected input current on any pin during overload condition -- -3.0 3.0 mA Parameter VDD_HV_B VDD_HV_C VDD_HV_FLA3 VDD_HV_ADC1_REF VDD_HV_ADC0 VDD_HV_ADC1 VSS_HV_ADC0 VSS_HV_ADC1 VDD_LV4 VIN1_CMP_REF5 IINJPAD TA Ambient temperature under bias fCPU 160 MHz -40 125 C TJ Junction temperature under bias -- -40 150 C 1. All voltages are referred to VSS_HV unless otherwise specified 2. Device will be functional down (and electrical specifications as per various datasheet parameters will be guaranteed) to the point where one of the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset. 3. When VDD_HV is in 5 V range, VDD_HV_FLA cannot be supplied externally.This pin is decoupled with Cflash_reg. 4. VDD_LV supply pins should never be grounded (through a small impedance). If these are not driven, they should only be left floating 5. This supply is shorted VDD_HV_A on lower packages. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 12 NXP Semiconductors General 4.3 Voltage regulator electrical characteristics The voltage regulator is composed of the following blocks: * Choice of generating supply voltage for the core area. * Control of external NPN ballast transistor * Connecting an external 1.25 V (nominal) supply directly without the NPN ballast * Internal generation of the 3.3 V flash supply when device connected in 5V applications * External bypass of the 3.3 V flash regulator when device connected in 3.3V applications * Low voltage detector - low threshold (LVD_IO_A_LO) for VDD_HV_IO_A supply * Low voltage detector - high threshold (LVD_IO_A_Hi) for VDD_HV_IO_A supply * Various low voltage detectors (LVD_LV_x) * High voltage detector (HVD_LV_cold) for 1.2 V digital core supply (VDD_LV) * Power on Reset (POR_LV) for 1.25 V digital core supply (VDD_LV) * Power on Reset (POR_HV) for 3.3 V to 5 V supply (VDD_HV_A) The following bipolar transistors1 are supported, depending on the device performance requirements. As a minimum the following must be considered when determining the most appropriate solution to maintain the device under its maximum power dissipation capability: current, ambient temperature, mounting pad area, duty cycle and frequency for Idd, collector voltage, etc 1. BCP56, MCP68 and MJD31are guaranteed ballasts. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 13 General LPPREG VDD_LP_DEC VDD_HV_BALLAST ULPPREG CLP/ULPREG VRC_CTRL V SS_HV FPREG CBE_FPREG Flash voltage regulator V DD_LV VDD_HV_FLA CFLASH_REG CFP_REG VSS_HV VSS_HV DEVICE Figure 2. Voltage regulator capacitance connection Table 8. Voltage regulator electrical specifications Symbol Cfp_reg 1 Clp/ulp_reg Cbe_fpreg3 Cflash_reg4 Parameter Conditions Min Typ Max Unit 1.32 2.22 3 F -- 0.03 Ohm 1 1.4 F -- 0.1 Ohm External decoupling / stability capacitor Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. Combined ESR of external capacitor -- External decoupling / stability capacitor for internal low power regulators Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. Combined ESR of external capacitor -- Capacitor in parallel to baseemitter BCP68 and BCP56 3.3 MJD31 4.7 External decoupling / stability capacitor for internal Flash regulators Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. Combined ESR of external capacitor -- 0.001 0.8 0.001 1.32 0.001 nF 2.2 3 F -- 0.03 Ohm Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 14 NXP Semiconductors General Table 8. Voltage regulator electrical specifications (continued) Symbol Parameter Conditions Min Typ Max Unit CHV_VDD_A VDD_HV_A supply capacitor Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 1 -- -- F CHV_VDD_B VDD_HV_B supply capacitor5 Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 1 -- -- F CHV_VDD_C VDD_HV_C supply capacitor5 Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 1 -- -- F CHV_ADC0 HV ADC supply decoupling capacitances Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 1 -- -- F HV ADC SAR reference supply decoupling capacitances Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 0.47 -- -- F VDD_HV_BALL FPREG Ballast collector supply 7 voltage AST When collector of NPN ballast is directly supplied by an on board supply source (not shared with VDD_HV_A supply pin) without any series resistance, that is, RC_BALLAST less than 0.01 Ohm. 2.25 -- 5.5 V RC_BALLAST Series resistor on collector of FPREG ballast When VDD_HV_BALLAST is shorted to VDD_HV_A on the board -- -- 0.1 Ohm Start-up time after main supply stabilization Cfp_reg = 3 F -- 74 -- s Load current transient Iload from 15% to 55% CHV_ADC1 CHV_ADR6 tSU tramp 1.0 s Cfp_reg = 3 F 1. Split capacitance on each pair VDD_LV pin should sum up to a total value of Cfp_reg 2. Typical values will vary over temperature, voltage, tolerance, drift, but total variation must not exceed minimum and maximum values. 3. Ceramic X7R or X5R type with capacitance-temperature characteristics +/-15% of -55 degC to +125degC is recommended. The tolerance +/-20% is acceptable. 4. It is required to minimize the board parasitic inductance from decoupling capacitor to VDD_HV_FLA pin and the routing inductance should be less than 1nH. 5. 1. For VDD_HV_A, VDD_HV_B, and VDD_HV_C, 1f on each side of the chip a. 0.1 f close to each VDD/VSS pin pair. b. 10 f near for each power supply source c. For VDD_LV, 0.1uf close to each VDD/VSS pin pair is required. Depending on the the selected regulation mode, this amount of capacitance will need to be subtracted from the total capacitance required by the regulator for e.g., as specified by CFP_REG parameter. 2. For VDD_LV, 0.1uf close to each VDD/VSS pin pair is required. Depending on the the selected regulation mode, this amount of capacitance will need to be subtracted from the total capacitance required by the regulator for e.g., as specified by CFP_REG parameter 6. Only applicable to ADC1 MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 15 General 7. In external ballast configuration the following must be ensured during power-up and power-down (Note: If VDD_HV_BALLAST is supplied from the same source as VDD_HV_A this condition is implicitly met): * During power-up, VDD_HV_BALLAST must have met the min spec of 2.25V before VDD_HV_A reaches the POR_HV_RISE min of 2.75V. * During power-down, VDD_HV_BALLAST must not drop below the min spec of 2.25V until VDD_HV_A is below POR_HV_FALL min of 2.7V. NOTE For a typical configuration using an external ballast transistor with separate supply for VDD_HV_A and the ballast collector, a bulk storage capacitor (as defined in Table 8) is required on VDD_HV_A close to the device pins to ensure a stable supply voltage. Extra care must be taken if the VDD_HV_A supply is also being used to power the external ballast transistor or the device is running in internal regulation mode. In these modes, the inrush current on device Power Up or on exit from Low Power Modes is significant and may case the VDD_HV_A voltage to drop resulting in an LVD reset event. To avoid this, the board layout should be optimized to reduce common trace resistance or additional capacitance at the ballast transistor collector (or VDD_HV_A pins in the case of internal regulation mode) is required. NXP recommends that customers simulate the external voltage supply circuitry. In all circumstances, the voltage on VDD_HV_A must be maintained within the specified operating range (see Recommended operating conditions) to prevent LVD events. 4.4 Voltage monitor electrical characteristics Table 9. Voltage monitor electrical characteristics Symbol Parameter State Conditions Configuration Powe Mas r Up 1 k Opt VPOR_LV LV supply Fall power on reset detector Rise Untrimmed Yes No Threshold Reset Type Powerup Min Typ Unit Max V 0.930 0.979 1.028 V Trimmed 0.959 0.979 0.999 V Untrimmed 0.980 1.029 1.078 V Trimmed 1.009 1.029 1.049 V Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 16 NXP Semiconductors General Table 9. Voltage monitor electrical characteristics (continued) Symbol Parameter State Conditions Configuration Powe Mas r Up 1 k Opt VHVD_LV_cold VLVD_LV_PD2_hot VLVD_LV_PD1_hot VLVD_LV_PD0_hot VPOR_HV VLVD_IO_A_LO, 2 VLVD_IO_A_HI2 VLVD_LV_PD2_cold LV supply high Fall voltage monitoring, Rise detecting at the device pin Untrimmed Yes Reset Type Functional Min V Disabled at Start Untrimmed Disabled at Start Trimmed 1.345 1.365 1.395 V LV supply low Fall voltage monitoring, Rise detecting in the PD1 core (hot) area Untrimmed LV supply low Fall voltage monitoring, Rise detecting in the PD0 core (hot) area Untrimmed HV supply Fall power on Rise reset detector Untrimmed HV IO_A supply low voltage monitoring low range Fall Untrimmed HV IO_A supply low voltage monitoring high range Fall Yes V 1.120 1.160 V 1.125 1.143 1.160 V Untrimmed 1.100 1.140 1.180 V Trimmed 1.145 1.163 1.180 V 1.080 1.120 1.160 V Trimmed 1.114 1.137 1.160 V Untrimmed 1.100 1.140 1.180 V Trimmed 1.134 1.157 1.180 V 1.080 1.120 1.160 V Trimmed 1.114 1.137 1.160 V Untrimmed 1.100 1.140 1.180 V Trimmed 1.134 1.157 1.180 V 2.700 2.850 3.000 V 2.750 2.900 3.050 V 2.750 2.923 3.095 V Trimmed 2.978 3.039 3.100 V Untrimmed 2.780 2.953 3.125 V Trimmed 3.008 3.069 3.130 V Yes Yes No No No Powerup 1.375 1.080 Yes No 1.345 Trimmed Powerup Powerup Powerup Untrimmed Trimmed Yes No No Yes Powerup Functional Disabled at Start 4.060 LV supply low Fall voltage monitoring, Rise detecting at the device pin Max 1.325 Untrimmed Rise Typ Unit Trimmed LV supply low Fall voltage monitoring, Rise detecting in the PD2 core (hot) area Rise No Threshold Trimmed 4.240 V Disabled at Start 4.115 Untrimmed 4.151 No Yes Functional 4.201 4.3 V Disabled at Start Trimmed 1.14 1.158 Untrimmed Disabled at Start Trimmed 1.16 1.178 1.175 1.195 V V 1. All monitors that are active at power-up will gate the power up recovery and prevent exit from POWERUP phase until the minimum level is crossed. These monitors can in some cases be masked during normal device operation, but when active will always generate a destructive reset. 2. There is no voltage monitoring on the VDD_HV_ADC0, VDD_HV_ADC1, VDD_HV_B and VDD_HV_C I/O segments. For applications requiring monitoring of these segments, either connect these to VDD_HV_A at the PCB level or monitor externally. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 17 General 4.5 Supply current characteristics Current consumption data is given in the following table. These specifications are design targets and are subject to change per device characterization. NOTE The ballast must be chosen in accordance with the ballast transistor supplier operating conditions and recommendations. Table 10. Current consumption characteristics Symbol IDD_FULL 2, 3 Conditions1 Parameter RUN Full Mode LV supply + HV supply + HV Flash supply + Operating current 2 x HV ADC supplies Min Typ Max Unit -- 219 292 mA Ta = 85C VDD_LV = 1.25 V VDD_HV_A = 5.5V SYS_CLK = 160MHz IDD_GWY 5, 6 RUN Gateway Mode Operating current Ta = 105C -- 230 328 mA Ta = 125 C -- 249 400 mA 260 mA LV supply + HV supply + HV Flash supply + 2 x HV ADC supplies -- 183 Ta = 85C VDD_LV = 1.25 V VDD_HV_A = 5.5V SYS_CLK = 160MHz Ta = 105C Ta = IDD_BODY_1 7, 8 RUN Body Mode Profile Operating current 125C4 LV supply + HV supply + HV Flash supply + 2 x HV ADC supplies -- 196 294 mA -- 215 348 mA 223 mA -- 149 Ta = 85 C VDD_LV = 1.25 V VDD_HV_A = 5.5V SYS_CLK = 120MHz IDD_BODY_29, 10 RUN Body Mode Profile Operating current Ta = 105 C -- 158 270 mA Ta = 125C 4 -- 175 310 mA 174 mA LV supply + HV supply + HV Flash supply + 2 x HV ADC supplies -- 105 Ta = 85 C VDD_LV = 1.25 V VDD_HV_A = 5.5V SYS_CLK = 80MHz Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 18 NXP Semiconductors General Table 10. Current consumption characteristics (continued) Symbol Conditions1 Parameter IDD_STOP Min Typ Max Unit Ta = 105 C -- 114 206 mA Ta = 125 C 4 -- 131 277 mA -- mA STOP mode Ta = 25 C Operating current VDD_LV = 1.25 V Ta = 85 C -- -- 11 19.8 105 29 145 45 160 VDD_LV = 1.25 V Ta = 105 C VDD_LV = 1.25 V Ta = 125 C 4 -- VDD_LV = 1.25 V IDD_HV_ADC_REF 11, 12 ADC REF Ta = 25 C Operating current 2 ADCs operating at 80 MHz -- 200 400 A VDD_HV_ADC_REF = 3.6 V Ta = 125 C 4 -- 200 400 2 ADCs operating at 80 MHz VDD_HV_ADC_REF = 5.5 V IDD_HV_ADCx12 ADC HV Ta = 25 C Operating current ADC operating at 80 MHz -- 1 2 1.2 2 mA VDD_HV_ADC = 3.6 V Ta = 125 C 4 -- ADC operating at 80 MHz VDD_HV_ADC = 5.5 V IDD_HV_FLASH Flash Operating current during read access Ta = 125 C 4 -- 40 45 mA 3.3 V supplies x MHz frequency 1. The content of the Conditions column identifies the components that draw the specific current. 2. ALL Modules enabled at maximum frequency: 2 x e200Z4 @160 MHz, e200Z2 at 80 MHz, Platform @160MHz, DMA (SRAM to SRAM), all SRAMs accessed in parallel, Flash access(prefetch is disabled while buffers are enabled), HSM reading from flash at regular intervals (500 pll clock cycles), ENET0 transmitting, MLB transmitting, FlexRay transmitting, USB-SPH transmitting (USB-OTG only clocked), 2 x I2C transmitting (rest clocked), 1 x SAI transmitting (rest clocked), ADC0 converting using BCTU triggers triggered through PIT (other ADC clocked), RTC running, 3 x STM running, 2 x DSPI transmitting (rest clocked), 2 x SPI transmitting (rest clocked), 4 x CAN state machines working(rest clocked), 9 x LINFlexD transmitting (rest clocked), 1 x eMIOS clocked (used OPWFMB mode) (Others clock gated), SDHC,3 x CMP only clocked, FIRC, SIRC, FXOSC, SXOSC, PLL running. All others modules clock gated if not specifically mentioned. I/O supply current excluded. 3. Recommended Transistors:MJD31 @ 85C, 105C and 125C. 4. Tj=150C. Assumes Ta=125C * Assumes maximum JA. SeeThermal attributes 5. Enabled Modules in Gateway mode: 2 x e200Z4 @160 MHz (Instruction and Data cache enabled), Platform @160MHz, e200Z2 at 80 MHz(Instruction cache enabled), all SRAMs accessed in parallel, Flash access(prefetch is disabled while buffers are enabled), HSM reading from flash at regular intervals(500 pll clock cycles), ENET0 transmitting, MLB transmitting, FlexRay transmitting, USB-SPH Transmitting, USB-OTG clocked, 2 x I2C transmitting, (2 x I2C clock gated), 1 x SAI transmitting (2 x SAI clock gated), ADC0 converting in continuous mode (ADC1 clock gated), PIT clocked, RTC clocked, 3 x STM clocked, 2 x DSPI transmitting(Other DSPS clock gated), 2 x SPI transmitting(Other SPIs clock gated), 4 MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 19 General x FlexCAN state machines clocked(other FLEXCAN clock gated), 4 x LINFlexD transmitting (Other clock gated), 1x eMIOS clocked(used OPWFMB mode) (Others clock gated), FIRC, SIRC, FXOSC, SXOSC, PLL running, BCTU, DMAMUX, ACMP clock gated. All others modules clock gated if not specifically mentioned. I/O supply current excluded 6. Recommended Transistors:MJD31@85C, 105C and 125C. 7. Enabled Modules in Body mode enabled at maximum frequency: 2 x e200Z4 @120Mhz(Instruction and Data cache enabled),Platform@120MHz, SRAMs accessed in parallel, Flash access(prefetch is disabled while buffers are enabled), HSM reading from flash at regular intervals(500 pll clock cycles), DMA (SRAM to SRAM), ADC0 converting using BCTU triggers which are triggered through PIT(ADC1 clocked), RTC clocked, 3 x STM clocked, 2 x DSPI transmitting(others DSPIs clocked), 2 x SPI transmitting(others clocked), 4 x FlexCAN state machines working(others clocked), 9xLINFlexD transmitting (others clocked), 1xeMIOS operational (used OPWFMB mode) (others clocked), FIRC, SIRC, FXOSC, SXOSC, PLL running, MEMU, FCCU, SIUL, SDHC,CMP clocked, e200Z2, ENET, MLB, SAI, I2C, FlexRay, USB clock gated. All others modules clock gated if not specifically mentioned I/O supply current excluded 8. Recommended Transistors:BCP56, BCP68 or MJD31@85C, BCP56, BCP68 or MJD31@105C and MJD31@125C. 9. Enabled Modules in Body mode enabled at maximum frequency:2 x e200Z4 @80Mhz(Instruction and Data cache enabled),Platform@80MHz, SRAMs accessed in parallel, Flash access(prefetch is disabled while buffers are enabled), HSM reading from flash at regular intervals(500 pll clock cycles), DMA (SRAM to SRAM), ADC0 converting using BCTU triggers which are triggered through PIT(ADC1 clocked), RTC clocked, 3 x STM clocked, 2 x DSPI transmitting(others DSPIs clocked), 2 x SPI transmitting(others clocked), 4 x FlexCAN state machines working(others clocked), 9xLINFlexD transmitting (others clocked), 1xeMIOS operational (used OPWFMB mode) (others clocked), FIRC, SIRC, FXOSC, SXOSC, PLL running, MEMU, FCCU, SIUL, SDHC,CMP clocked, e200Z2, ENET, MLB, SAI, I2C, FlexRay, USB clock gated. All others modules clock gated if not specifically mentioned I/O supply current excluded 10. Recommended Transistors:BCP56, BCP68 or MJD31@85C, 105C and 125C 11. Internal structures hold the input voltage less than VDD_HV_ADC_REF + 1.0 V on all pads powered by VDDA supplies, if the maximum injection current specification is met (3 mA for all pins) and VDDA is within the operating voltage specifications. 12. This value is the total current for two ADCs.Each ADC might consume upto 2mA at max. Table 11. Low Power Unit (LPU) Current consumption characteristics Symbol LPU_RUN Conditions1 Parameter with 256K RAM, Ta = 25 C but only one RAM SYS_CLK = 16MHz being accessed ADC0 = OFF, SPI0 = OFF, LIN0 = OFF, CAN0 = OFF Min Typ -- 8.9 Ta = 25 C Max Unit mA 10.2 SYS_CLK = 16MHz ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON Ta = 85 C Ta = 105 C Ta = 125 C ,2 -- 12.5 22 -- 14.5 24 -- 16 26 SYS_CLK = 16MHz ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON LPU_STOP with 256K RAM Ta = 25 C -- 0.535 mA Ta = 85 C -- 0.72 6 Ta = 105 C -- 1 8 Ta = 125 C 2 -- 1.6 10.6 1. The content of the Conditions column identifies the components that draw the specific current. 2. Assuming Ta=Tj, as the device is in static (fully clock gated) mode. Assumes maximum JA of 2s2p board. SeeThermal attributes MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 20 NXP Semiconductors General Table 12. STANDBY Current consumption characteristics Symbol Parameter Conditions1 Min Typ Max Unit STANDBY0 STANDBY with 8K RAM Ta = 25 C -- 71 -- A Ta = 85 C -- 175 800 Ta = 105 C -- 338 1725 Ta = 125 C -- 750 2775 Ta = 25 C -- 72 -- Ta = 85 C -- 176 815 Ta = 105 C -- 350 1775 Ta = 125 C -- 825 3000 Ta = 25 C -- 75 -- Ta = 85 C -- 182 830 Ta = 105 C -- 366 1825 Ta = 150 C -- 900 3250 Ta = 25 C -- 80 -- Ta = 85 C -- 197 860 Ta = 105 C -- 400 1875 Ta = 125 C -- 975 3500 Ta = 25 C -- 500 -- STANDBY1 STANDBY with 64K RAM STANDBY2 STANDBY with 128K RAM STANDBY3 STANDBY with 256K RAM STANDBY3 FIRC ON A A A A 1. The content of the Conditions column identifies the components that draw the specific current. 4.6 Electrostatic discharge (ESD) characteristics Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n + 1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. NOTE A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 13. ESD ratings Symbol VESD(HBM) Conditions1 Parameter Electrostatic discharge TA = 25 C Class Max value2 Unit H1C 2000 V (Human Body Model) Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 21 I/O parameters Table 13. ESD ratings (continued) Symbol Conditions1 Parameter Class Max value2 Unit C3A 500 V conforming to AECQ100-002 VESD(CDM) Electrostatic discharge TA = 25 C (Charged Device Model) conforming to AECQ100-011 750 (corners) 1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2. Data based on characterization results, not tested in production. 4.7 Electromagnetic Compatibility (EMC) specifications EMC measurements to IC-level IEC standards are available from NXP on request. 5 I/O parameters 5.1 AC specifications @ 3.3 V Range Table 14. Functional Pad AC Specifications @ 3.3 V Range Symbol Prop. Delay (ns)1 Rise/Fall Edge (ns) L>H/H>L Min Max pad_sr_hv (output) pad_i_hv/ pad_sr_hv Min 6/6 2.5/2.5 8.25/7.5 0.8/0.6 Drive Load (pF) Max MSB,LSB 1.9/1.5 25 3.25/3 50 6.4/5 19.5/19.5 3.5/2.5 12/12 200 2.2/2.5 8/8 0.55/0.5 3.9/3.5 25 0.090 1.1 0.035 1.1 asymmetry2 2.9/3.5 12.5/11 1/1 7/6 50 11/8 35/31 7.7/5 25/21 200 8.3/9.6 45/45 4/3.5 25/25 50 13.5/15 65/65 6.3/6.2 30/30 200 13/13 75/75 6.8/6 40/40 50 21/22 100/100 11/11 51/51 200 0.5/0.5 0.5 2/2 SIUL2_MSCRn[SRC 1:0] 11 10 01 003 NA (input)4 1. As measured from 50% of core side input to Voh/Vol of the output 2. This row specifies the min and max asymmetry between both the prop delay and the edge rates for a given PVT and 25pF load. Required for the Flexray spec. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 22 NXP Semiconductors I/O parameters 3. Slew rate control modes 4. Input slope = 2ns NOTE The specification given above is based on simulation data into an ideal lumped capacitor. Customer should use IBIS models for their specific board/loading conditions to simulate the expected signal integrity and edge rates of their system. NOTE The specification given above is measured between 20% / 80%. 5.2 DC electrical specifications @ 3.3V Range Table 15. DC electrical specifications @ 3.3V Range Symbol VDD VDD_HV_x1 Parameter Value Unit Min Max LV (core) Supply Voltage 1.08 1.32 V I/O Supply Voltage 3.15 3.63 V Vih (pad_i_hv) pad_i_hv Input Buffer High Voltage 0.72*VDD_HV_ x VDD_HV_x + 0.3 V Vil (pad_i_hv) pad_i_hv Input Buffer Low Voltage VSS_LV - 0.3 0.45*VDD_HV_ x V Vhys (pad_i_hv) pad_i_hv Input Buffer Hysteresis 0.11*VDD_HV_ x Vih_hys CMOS Input Buffer High Voltage (with hysteresis enabled) 0.67*VDD_HV_ x VDD_HV_x + 0.3 V Vil_hys CMOS Input Buffer Low Voltage (with hysteresis enabled) VSS_LV - 0.3 0.35*VDD_HV_ x V Vih CMOS Input Buffer High Voltage (with hysteresis disabled) 0.57 * VDD_HV_x VDD_HV_x + 0.3 V Vil CMOS Input Buffer Low Voltage (with hysteresis disabled) VSS_LV - 0.3 0.4 * VDD_HV_x V Vhys CMOS Input Buffer Hysteresis 0.09 * VDD_HV_x Pull_IIH (pad_i_hv) Weak Pullup Current Low Pull_Ioh Weak Pullup High Current5 Weak Pulldown Iinact_d Digital Pad Input Leakage Current (weak pull inactive) Voh Vol 28 Current4 Pull_Iol A 55 Pull_IIL (pad_i_hv) Weak Pulldown Current3 Low Pull_IIL (pad_i_hv) Weak Pulldown V 15 Pull_IIH (pad_i_hv) Weak Pullup Current High Current2 V A A 85 A 15 50 A 15 50 A -2.5 2.5 A Output High Voltage6 0.8 *VDD_HV_x -- V Output Low Voltage7 -- 0.2 *VDD_HV_x V Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 23 I/O parameters Table 15. DC electrical specifications @ 3.3V Range (continued) Symbol Parameter Value Min Output Low Full drive Full drive Iol9 Ioh_h Half drive Ioh9 Iol_h Half drive Iol9 (SIUL2_MSCRn[SRC 1:0]= 10) Iol_f Max 0.1 *VDD_HV_x Ioh9 Ioh_f 1. 2. 3. 4. 5. 6. 7. 8. 9. Voltage8 Unit (SIUL2_MSCRn[SRC 1:0]= 11) 18 70 mA 21 120 mA 9 35 mA 10.5 60 mA (SIUL2_MSCRn[SRC 1:0]= 11) (SIUL2_MSCRn[SRC 1:0]= 10) Max power supply ramp rate is 500 V / ms Measured when pad=0.69*VDD_HV_x Measured when pad=0.49*VDD_HV_x Measured when pad = 0 V Measured when pad = VDD_HV_x Measured when pad is sourcing 2 mA Measured when pad is sinking 2 mA Measured when pad is sinking 1.5 mA Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test. 5.3 AC specifications @ 5 V Range Table 16. Functional Pad AC Specifications @ 5 V Range Symbol Prop. Delay (ns)1 Rise/Fall Edge (ns) Drive Load (pF) SIUL2_MSCRn[SRC 1:0] L>H/H>L Min pad_sr_hv (output) pad_i_hv/ pad_sr_hv Max Min Max MSB,LSB 4.5/4.5 1.3/1.2 25 6/6 2.5/2 50 13/13 9/9 200 5.25/5.25 3/2 25 9/8 5/4 50 22/22 18/16 200 27/27 13/13 50 40/40 24/24 200 40/40 24/24 50 65/65 40/40 200 1.5/1.5 0.5/0.5 0.5 11 10 012 002 NA (input) 1. As measured from 50% of core side input to Voh/Vol of the output 2. Slew rate control modes MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 24 NXP Semiconductors I/O parameters NOTE The above specification is based on simulation data into an ideal lumped capacitor. Customer should use IBIS models for their specific board/loading conditions to simulate the expected signal integrity and edge rates of their system. NOTE The above specification is measured between 20% / 80%. 5.4 DC electrical specifications @ 5 V Range Table 17. DC electrical specifications @ 5 V Range Symbol VDD_LV VDD_HV_x1 Parameter Value Unit Min Max LV (core) Supply Voltage 1.08 1.32 V I/O Supply Voltage 4.5 5.5 V Vih (pad_i_hv) pad_i_hv Input Buffer High Voltage 0.7*VDD_HV_x VDD_HV_x + 0.3 V Vil (pad_i_hv) pad_i_hv Input Buffer Low Voltage VSS_LV- 0.3 0.45*VDD_HV_ x V Vhys (pad_i_hv) pad_i_hv Input Buffer Hysteresis 0.09*VDD_HV_ x V Vih CMOS Input Buffer High Voltage (with hysteresis disabled) 0.55 * VDD_HV_x VDD_HV_x + 0.3 V Vil CMOS Input Buffer Low Voltage (with hysteresis disabled) VSS_LV - 0.3 0.4 * VDD_HV_x V Vhys CMOS Input Buffer Hysteresis 0.09 * VDD_HV_x Vih_hys CMOS Input Buffer High Voltage (with hysteresis enabled) 0.65* VDD_HV_x VDD_HV_x + 0.3 V Vil_hys CMOS Input Buffer Low Voltage (with hysteresis enabled) VSS_LV - 0.3 0.35*VDD_HV_ x V Pull_IIH (pad_i_hv) Weak Pullup Current Low 23 Pull_IIH (pad_i_hv) Weak Pullup Current High Pull_IIL (pad_i_hv) Weak Pulldown Current3 Low Pull_IIL (pad_i_hv) Weak Pulldown Pull_Ioh Weak Pullup Current2 Current5 Pull_Iol Weak Pulldown Iinact_d Digital Pad Input Leakage Current (weak pull inactive) Voltage6 Voh Output High Vol Output Low Voltage7 A 82 40 High Current4 V A A 130 A 30 80 A 30 80 A -2.5 2.5 A 0.8 * VDD_HV_x -- V -- 0.2 * VDD_HV_x V Output Low Voltage8 0.1*VDD_HV_x Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 25 I/O parameters Table 17. DC electrical specifications @ 5 V Range (continued) Symbol Value Unit Min Max Ioh_f Full drive Ioh9 (SIUL2_MSCRn[SRC 1:0]= 11) 38 132 mA Iol_f Full drive Iol9 (SIUL2_MSCRn[SRC 1:0]= 11) 48 220 mA 19 66 mA 24 110 mA Ioh_h Iol_h 1. 2. 3. 4. 5. 6. 7. 8. 9. Parameter Half drive Ioh9 Half drive Iol9 (SIUL2_MSCRn[SRC 1:0]= 10) (SIUL2_MSCRn[SRC 1:0]= 10) Max power supply ramp rate is 500 V / ms Measured when pad=0.69*VDD_HV_x Measured when pad=0.49*VDD_HV_x Measured when pad = 0 V Measured when pad = VDD_HV_x Measured when pad is sourcing 2 mA Measured when pad is sinking 2 mA Measured when pad is sinking 1.5 mA Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test. 5.5 Reset pad electrical characteristics The device implements a dedicated bidirectional RESET pin. AA A VDD_HV_IOx A VDDMIN PORST VIH VIL device reset forced by PORST device start-up phase Figure 3. Start-up reset requirements MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 26 NXP Semiconductors I/O parameters VPORST hw_rst VDD_HV_IO A `1' VIH VIL `0' filtered by hysteresis filtered by lowpass filter filtered by lowpass filter WFRST unknown reset state device under hardware reset WFRST WNFRST Figure 4. Noise filtering on reset signal Table 18. Functional reset pad electrical specifications Symbol Parameter Conditions Value Min Typ Max Unit VIH Input high level TTL (Schmitt Trigger) -- 2.0 -- VDD_HV_A +0.4 V VIL Input low level TTL (Schmitt Trigger) -- -0.4 -- 0.8 V VHYS Input hysteresis TTL (Schmitt Trigger) -- 300 -- -- mV VDD_POR Minimum supply for strong pull-down activation -- -- -- 1.2 V IOL_R Strong pull-down current 1 Device under power-on reset 0.2 -- -- mA 11 -- -- mA VDD_HV_A= V DD_POR VOL = 0.35*VDD_HV_A Device under power-on reset VDD_HV_A= V DD_POR VOL = 0.35*VDD_HV_IO WFRST RESET input filtered pulse -- -- -- 500 ns WNFRST RESET input not filtered pulse -- 2000 -- -- ns |IWPU| Weak pull-up current absolute value RESET pin VIN = VDD 23 -- 82 A 1. Strong pull-down is active on PHASE0, PHASE1, PHASE2, and the beginning of PHASE3 for RESET. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 27 Peripheral operating requirements and behaviours 5.6 PORST electrical specifications Table 19. PORST electrical specifications Symbol Parameter Value Min WFPORST PORST input filtered pulse WNFPORST PORST input not filtered pulse VIH Input high level VIL Input low level -- Unit Typ Max -- 200 ns 1000 -- -- ns -- 0.65 x VDD_HV_A -- V -- 0.35 x VDD_HV_A -- V 6 Peripheral operating requirements and behaviours 6.1 Analog 6.1.1 ADC electrical specifications The device provides a 12-bit Successive Approximation Register (SAR) Analog-toDigital Converter. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 28 NXP Semiconductors Analog Offset Error OSE Gain Error GE 4095 4094 4093 4092 4091 4090 ( 2) 1 LSB ideal =(VrefH-VrefL)/ 4096 = 3.3V/ 4096 = 0.806 mV Total Unadjusted Error TUE = +/- 6 LSB = +/- 4.84mV code out 7 ( 1) 6 5 (5) 4 (4) 3 (3) 2 1 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve 1 LSB (ideal) 0 1 2 3 Offset Error OSE 4 5 6 7 4089 4090 4091 4092 4093 4094 4095 Vin(A) (LSBideal) Figure 5. ADC characteristics and error definitions MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 29 Analog 6.1.1.1 Input equivalent circuit and ADC conversion characteristics EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD_IO Source Filter RS Current Limiter RF Sampling RSW1 RAD RL CF VA Channel Selection CP1 CP2 CS RS Source Impedance RF Filter Resistance CF Filter Capacitance RL Current Limiter Resistance RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance Figure 6. Input equivalent circuit NOTE The ADC performance specifications are not guaranteed if two ADCs simultaneously sample the same shared channel. Table 20. ADC conversion characteristics (for 12-bit) Min Typ1 Max Unit 15.2 80 80 MHz -- -- 1.00 MHz 80 MHz@ 100 ohm source impedance 250 -- -- ns Conversion time4 80 MHz 700 -- -- ns Total Conversion time tsample + tconv (for standard and extended channels) 80 MHz 1.55 -- -- s 1 -- -- Symbol fCK fs Parameter Conditions ADC Clock frequency (depends on -- ADC configuration) (The duty cycle depends on AD_CK2 frequency) Sampling frequency tsample tconv ttotal_conv Sample 80 MHz time3 Total Conversion time tsample + tconv (for precision channels) CS ADC input sampling capacitance -- -- 3 5 pF 6 ADC input pin capacitance 1 -- -- -- 5 pF CP2 6 ADC input pin capacitance 2 -- -- -- 0.8 pF RSW16 Internal resistance of analog source VREF range = 4.5 to 5.5 V -- -- 0.3 k VREF range = 3.15 to 3.6 V -- -- 875 CP1 Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 30 NXP Semiconductors Analog Table 20. ADC conversion characteristics (for 12-bit) (continued) Symbol Parameter Conditions Min Typ1 Max Unit RAD6 Internal resistance of analog source -- -- -- 825 INL Integral non-linearity (precise channel) -- -2 -- 2 LSB INL Integral non-linearity (standard channel) -- -3 -- 3 LSB DNL Differential non-linearity -- -1 -- 1 LSB OFS Offset error -- -6 -- 6 LSB GNE Gain error -- -4 -- 4 LSB Max leakage (precision channel) 150 C -- -- 250 nA Max leakage (standard channel) 150 C -- -- 2500 nA Max leakage (standard channel) 105 C TA -- 5 250 nA ADC Analog Pad (pad going to one ADC) -5 -- 5 mA TUEprecision channels Total unadjusted error for precision Without current injection channels With current injection Max positive/negative injection -6 +/-4 6 LSB TUEstandard/extended Total unadjusted error for standard/ Without current injection extended channels channels With current injection7 -8 trecovery +/-5 +/-6 LSB 8 +/-8 STOP mode to Run mode recovery time LSB LSB <1 s 1. Active ADC input, VinA < [min(ADC_VrefH, ADC_ADV, VDD_HV_IOx)]. VDD_HV_IOx refers to I/O segment supply voltage. Violation of this condition would lead to degradation of ADC performance. Please refer to Table: 'Absolute maximum ratings' to avoid damage. Refer to Table: 'Recommended operating conditions (VDD_HV_x = 3.3 V)' for required relation between IO_supply_A,B,C and ADC_Supply. 2. The internally generated clock (known as AD_clk or ADCK) could be same as the peripheral clock or half of the peripheral clock based on register configuration in the ADC. 3. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tsample depend on programming. 4. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to load the result register with the conversion result. 5. Apart from tsample and tconv, few cycles are used up in ADC digital interface and hence the overall throughput from the ADC is lower. 6. See Figure 2. 7. Current injection condition for ADC channels is defined for an inactive ADC channel (on which conversion is NOT being performed), and this occurs when voltage on the ADC pin exceeds the I/O supply or ground. However, absolute maximum voltage spec on pad input (VINA, see Table: Absolute maximum ratings) must be honored to meet TUE spec quoted here Table 21. ADC conversion characteristics (for 10-bit) Symbol fCK fs tsample Parameter Conditions ADC Clock frequency (depends on -- ADC configuration) (The duty cycle depends on AD_CK2 frequency.) Sampling frequency Sample time3 -- 80 MHz@ 100 ohm source impedance Min Typ1 Max Unit 15.2 80 80 MHz -- -- 1.00 MHz 275 -- -- ns Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 31 Analog Table 21. ADC conversion characteristics (for 10-bit) (continued) Symbol Parameter tconv ttotal_conv Conditions Typ1 Max Unit Conversion time4 80 MHz 550 -- -- ns Total Conversion time tsample + tconv (for standard channels) 80 MHz 1 -- -- s Total Conversion time tsample + tconv (for extended channels) CS Min 1.5 -- -- ADC input sampling capacitance -- -- 3 5 pF CP15 ADC input pin capacitance 1 -- -- -- 5 pF CP25 ADC input pin capacitance 2 -- -- -- 0.8 pF RSW15 Internal resistance of analog source VREF range = 4.5 to 5.5 V -- -- 0.3 k 875 Internal resistance of analog source -- -- -- 825 5 RAD VREF range = 3.15 to 3.6 V -- -- INL Integral non-linearity -- -2 -- 2 LSB DNL Differential non-linearity -- -1 -- 1 LSB OFS Offset error -- -4 -- 4 LSB GNE Gain error -- -4 -- 4 LSB Max leakage (standard channel) 150 C -- -- 2500 nA Max leakage (standard channel) 105 C TA 5 250 nA -5 -- 5 mA -4 +/-3 4 LSB ADC Analog Pad (pad going to one ADC) Max positive/negative injection TUEstandard/extended Total unadjusted error for standard Without current injection channels channels With current injection6 trecovery -- STOP mode to Run mode recovery time +/-4 LSB <1 s 1. Active ADC Input, VinA < [min(ADC_ADV, IO_Supply_A,B,C)]. Violation of this condition would lead to degradation of ADC performance. Please refer to Table: 'Absolute maximum ratings' to avoid damage. Refer to Table: 'Recommended operating conditions' for required relation between IO_supply_A, B, C and ADC_Supply. 2. The internally generated clock (known as AD_clk or ADCK) could be same as the peripheral clock or half of the peripheral clock based on register configuration in the ADC. 3. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tsample depend on programming. 4. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to load the result register with the conversion result. 5. See Figure 2 6. Current injection condition for ADC channels is defined for an inactive ADC channel (on which conversion is NOT being performed), and this occurs when voltage on the ADC pin exceeds the I/O supply or ground. However, absolute maximum voltage spec on pad input (VINA, see Table: 'Absolute maximum ratings') must be honored to meet TUE spec quoted here NOTE The ADC input pins sit across all three I/O segments, VDD_HV_A, VDD_HV_B and VDD_HV_C. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 32 NXP Semiconductors Analog 6.1.2 Analog Comparator (CMP) electrical specifications Table 22. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit IDDHS Supply current, High-speed mode (EN=1, PMODE=1) -- -- 250 A IDDLS Supply current, low-speed mode (EN=1, PMODE=0) -- 5 11 A VAIN Analog input voltage VSS -- VIN1_CMP_RE V F VAIO VH Analog input offset voltage 1 -42 -- 42 mV -- 1 25 mV -- 20 50 mV -- 40 70 mV -- 60 105 mV -- -- 250 ns -- 5 14 s Analog comparator initialization delay, High speed mode4 -- 4 s Analog comparator initialization delay, Low speed mode 4 -- 100 s 3.3V Reference Voltage -- 6 9 A 5V Reference Voltage -- 10 16 A Analog comparator hysteresis 2 * CR0[HYSTCTR] = 00 * CR0[HYSTCTR] = 01 * CR0[HYSTCTR] = 10 * CR0[HYSTCTR] = 11 tDHS tDLS IDAC6b Propagation Delay, High Speed Mode (Full Swing) 1, 3 Propagation Delay, Low power Mode (Full Swing) 1, 3 6-bit DAC current adder (when enabled) INL 6-bit DAC integral non-linearity -0.5 -- 0.5 LSB5 DNL 6-bit DAC differential non-linearity -0.8 -- 0.8 LSB 1. 2. 3. 4. Measured with hysteresis mode of 00 Typical hysteresis is measured with input voltage range limited to 0.6 to VDD_HV_A-0.6V Full swing = VIH, VIL Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 5. 1 LSB = Vreference/64 MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 33 Clocks and PLL interfaces modules 6.2 Clocks and PLL interfaces modules 6.2.1 Main oscillator electrical characteristics This device provides a driver for oscillator in pierce configuration with amplitude control. Controlling the amplitude allows a more sinusoidal oscillation, reducing in this way the EMI. Other benefits arises by reducing the power consumption. This Loop Controlled Pierce (LCP mode) requires good practices to reduce the stray capacitance of traces between crystal and MCU. An operation in Full Swing Pierce (FSP mode), implemented by an inverter is also available in case of parasitic capacitances and cannot be reduced by using crystal with high equivalent series resistance. For this mode, a special care needs to be taken regarding the serial resistance used to avoid the crystal overdrive. Other two modes called External (EXT Wave) and disable (OFF mode) are provided. For EXT Wave, the drive is disabled and an external source of clock within CMOS level based in analog oscillator supply can be used. When OFF, EXTAL is pulled down by 240 Kohms resistor and the feedback resistor remains active connecting XTAL through EXTAL by 1M resistor. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 34 NXP Semiconductors Clocks and PLL interfaces modules Figure 7. Oscillator connections scheme Table 23. Main oscillator electrical characteristics Symbol Parameter Mode fXOSCHS Oscillator frequency gmXOSCHS Driver LCP Transconduct FSP ance VXOSCHS TXOSCHSSU Oscillation Amplitude Startup time Conditions FSP/LCP LCP FSP/LCP Oscillator FSP Analog Circuit supply current Min Typ 8 Max 40 23 Unit MHz mA/V 33 8 MHz 1.0 16 MHz 1.0 40 MHz 0.8 8 MHz 2 16 MHz 1 40 MHz 0.5 8 MHz 2.2 16 MHz 2.2 40 MHz 3.2 VPP ms mA Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 35 Clocks and PLL interfaces modules Table 23. Main oscillator electrical characteristics (continued) Symbol Parameter Mode LCP Conditions Min Typ 8 MHz 141 16 MHz 252 40 MHz 518 VIH Input High EXT Wave level CMOS Schmitt trigger Oscillator supply=3.3 VIL Input low level EXT Wave CMOS Schmitt trigger Oscillator supply=3.3 Max Unit uA 1.95 V 1.25 V 6.2.2 32 kHz Oscillator electrical specifications Table 24. 32 kHz oscillator electrical specifications Symbol Parameter fosc_lo Oscillator crystal or resonator frequency tcst Crystal Start-up Time1, 2 Condition Min Typ 32 Max Unit 40 KHz 2 s 1. This parameter is characterized before qualification rather than 100% tested. 2. Proper PC board layout procedures must be followed to achieve specifications. 6.2.3 16 MHz RC Oscillator electrical specifications Table 25. 16 MHz RC Oscillator electrical specifications Symbol FTarget Parameter Conditions Value Unit Min Typ Max IRC target frequency -- -- 16 -- MHz IRC frequency variation after trimming -- -5 -- 5 % Tstartup Startup time -- -- 1.5 us TSTJIT Cycle to cycle jitter -- -- 1.5 % TLTJIT Long term jitter -- -- 0.2 % PTA NOTE The above start up time of 1 us is equivalent to 16 cycles of 16 MHz. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 36 NXP Semiconductors Clocks and PLL interfaces modules 6.2.4 128 KHz Internal RC oscillator Electrical specifications Table 26. 128 KHz Internal RC oscillator electrical specifications Symbol Foscu1 Parameter Oscillator frequency Condition Calibrated Min Typ 128 Unit 136.5 KHz Temperature dependence 600 ppm/C Supply dependence 18 %/V Clock running 2.75 A Clock stopped 200 nA Supply current 119 Max 1. Vdd=1.2 V, 1.32V, Ta=-40 C, 125 C 6.2.5 PLL electrical specifications Table 27. PLL electrical specifications Parameter Min Typ Max Unit Input Frequency 8 40 MHz VCO Frequency Range 600 1280 MHz Duty Cycle at pllclkout 48% 52% Period Jitter See Table 28 TIE See Table 28 Modulation Depth (Center Spread) +/- 0.25% Comments This specification is guaranteed at PLL IP boundary ps NON SSCG mode at 960 M Integrated over 1MHz offset not valid in SSCG mode +/- 3.0% Modulation Frequency 32 KHz Lock Time 60 s Calibration mode Table 28. Jitter calculation Type of jitter Jitter due to Supply Noise (ps) JSN1 Jitter due to Fractional Mode (ps) JSDM2 Jitter due to Fractional Mode JSSCG (ps) 3 1 Sigma Random Jitter JRJ (ps) 4 Total Period Jitter (ps) 0.1% of pllclkout1,2 +/-(JSN+JSDM+JSSCG+N[4] xJRJ) Long Term Jitter (Integer Mode) 40 +/-(N x JRJ) Long Term jitter (Fractional Mode) 100 +/-(N x JRJ) Period Jitter 60 ps 3% of pllclkout1,2 Modulation depth 1. This jitter component is due to self noise generated due to bond wire inductances on different PLL supplies. The jitter value is valid for inductor value of 5nH or less each on VDD_LV and VSS_LV. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 37 Memory interfaces 2. This jitter component is added when the PLL is working in the fractional mode. 3. This jitter component is added when the PLL is working in the Spread Spectrum Mode. Else it is 0. 4. The value of N is dependent on the accuracy requirement of the application. See Percentage of sample exceeding specified value of jitter table Table 29. Percentage of sample exceeding specified value of jitter N Percentage of samples exceeding specified value of jitter (%) 1 31.73 2 4.55 3 0.27 4 6.30 x 1e-03 5 5.63 x 1e-05 6 2.00 x 1e-07 7 2.82 x 1e-10 6.3 Memory interfaces 6.3.1 Flash memory program and erase specifications NOTE All timing, voltage, and current numbers specified in this section are defined for a single embedded flash memory within an SoC, and represent average currents for given supplies and operations. Table 30 shows the estimated Program/Erase times. Table 30. Flash memory program and erase specifications Symbol Characteristic1 Typ2 Factory Programming3, 4 Field Update Initial Max Initial Max, Full Temp Typical End of Life5 20C TA 30C -40C TJ 150C -40C TJ 150C Unit Lifetime Max6 1,000 cycles 250,000 cycles tdwpgm Doubleword (64 bits) program time 43 100 150 55 500 s tppgm Page (256 bits) program time 73 200 300 108 500 s tqppgm Quad-page (1024 bits) program time 268 800 1,200 396 2,000 s t16kers 16 KB Block erase time 168 290 320 250 1,000 ms t16kpgm 16 KB Block program time 34 45 50 40 1,000 ms Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 38 NXP Semiconductors Memory interfaces Table 30. Flash memory program and erase specifications (continued) Characteristic1 Symbol Typ2 Factory Programming3, 4 Field Update Initial Max Initial Max, Full Temp Typical End of Life5 20C TA 30C -40C TJ 150C -40C TJ 150C Unit Lifetime Max6 1,000 cycles 250,000 cycles t32kers 32 KB Block erase time 217 360 390 310 1,200 ms t32kpgm 32 KB Block program time 69 100 110 90 1,200 ms t64kers 64 KB Block erase time 315 490 590 420 1,600 ms t64kpgm 64 KB Block program time 138 180 210 170 1,600 ms t256kers 256 KB Block erase time 884 1,520 2,030 1,080 4,000 -- ms t256kpgm 256 KB Block program time 552 720 880 650 4,000 -- ms 1. Program times are actual hardware programming times and do not include software overhead. Block program times assume quad-page programming. 2. Typical program and erase times represent the median performance and assume nominal supply values and operation at 25 C. Typical program and erase times may be used for throughput calculations. 3. Conditions: 150 cycles, nominal voltage. 4. Plant Programing times provide guidance for timeout limits used in the factory. 5. Typical End of Life program and erase times represent the median performance and assume nominal supply values. Typical End of Life program and erase values may be used for throughput calculations. 6. Conditions: -40C TJ 150C, full spec voltage. 6.3.2 Flash memory Array Integrity and Margin Read specifications Table 31. Flash memory Array Integrity and Margin Read specifications Symbol Characteristic Min Typical Max Units tai16kseq Array Integrity time for sequential sequence on 16 KB block. -- -- 512 x Tperiod x Nread -- tai32kseq Array Integrity time for sequential sequence on 32 KB block. -- -- 1024 x Tperiod x Nread -- tai64kseq Array Integrity time for sequential sequence on 64 KB block. -- -- 2048 x Tperiod x Nread -- tai256kseq Array Integrity time for sequential sequence on 256 KB block. -- -- 8192 x Tperiod x Nread -- tmr16kseq Margin Read time for sequential sequence on 16 KB block. 73.81 -- 110.7 s tmr32kseq Margin Read time for sequential sequence on 32 KB block. 128.43 -- 192.6 s tmr64kseq Margin Read time for sequential sequence on 64 KB block. 237.65 -- 356.5 s tmr256kseq Margin Read time for sequential sequence on 256 KB block. 893.01 -- 1,339.5 s MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 39 Memory interfaces 6.3.3 Flash memory module life specifications Table 32. Flash memory module life specifications Symbol Array P/E cycles Data retention Characteristic Conditions Min Typical Units Number of program/erase cycles per block for 16 KB, 32 KB and 64 KB blocks. -- 250,000 -- P/E cycles Number of program/erase cycles per block for 256 KB blocks. -- 1,000 250,000 P/E cycles Minimum data retention. Blocks with 0 - 1,000 P/E cycles. 50 -- Years Blocks with 100,000 P/E cycles. 20 -- Years Blocks with 250,000 P/E cycles. 10 -- Years 6.3.4 Data retention vs program/erase cycles Graphically, Data Retention versus Program/Erase Cycles can be represented by the following figure. The spec window represents qualified limits. The extrapolated dotted line demonstrates technology capability, however is beyond the qualification limits. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 40 NXP Semiconductors Memory interfaces 6.3.5 Flash memory AC timing specifications Table 33. Flash memory AC timing specifications Symbol Characteristic Min Typical Max Units Time from setting the MCR-PSUS bit until MCR-DONE bit is set to a 1. -- 9.4 11.5 s plus four system clock periods plus four system clock periods Time from setting the MCR-ESUS bit until MCR-DONE bit is set to a 1. -- 16 20.8 plus four system clock periods plus four system clock periods Time from clearing the MCR-ESUS or PSUS bit with EHV = 1 until DONE goes low. -- -- 100 ns tdone Time from 0 to 1 transition on the MCR-EHV bit initiating a program/erase until the MCR-DONE bit is cleared. -- -- 5 ns tdones Time from 1 to 0 transition on the MCR-EHV bit aborting a program/erase until the MCR-DONE bit is set to a 1. -- 16 20.8 s plus four system clock periods plus four system clock periods Time to recover once exiting low power mode. 16 -- 45 tpsus tesus tres tdrcv plus seven system clock periods. s s plus seven system clock periods taistart Time from 0 to 1 transition of UT0-AIE initiating a Margin Read or Array Integrity until the UT0-AID bit is cleared. This time also applies to the resuming from a suspend or breakpoint by clearing AISUS or clearing NAIBP -- -- 5 ns taistop Time from 1 to 0 transition of UT0-AIE initiating an Array Integrity abort until the UT0-AID bit is set. This time also applies to the UT0-AISUS to UT0-AID setting in the event of a Array Integrity suspend request. -- -- 80 ns Time from 1 to 0 transition of UT0-AIE initiating a Margin Read abort until the UT0-AID bit is set. This time also applies to the UT0-AISUS to UT0-AID setting in the event of a Margin Read suspend request. 10.36 tmrstop plus fifteen system clock periods plus four system clock periods -- 20.42 s plus four system clock periods MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 41 Communication interfaces 6.3.6 Flash read wait state and address pipeline control settings The following table describes the recommended RWSC and APC settings at various operating frequencies based on specified intrinsic flash access times of the flash module controller array at 125 C. Table 34. Flash Read Wait State and Address Pipeline Control Combinations Flash frequency RWSC setting APC setting 0 MHz < fFlash <= 33 MHz 0 0 33 MHz < fFlash <= 100 MHz 2 1 100 MHz < fFlash <= 133 MHz 3 1 133 MHz < fFlash <= 160 MHz 4 1 6.4 Communication interfaces 6.4.1 DSPI timing Table 35. DSPI electrical specifications No 1 Symbol tSCK Parameter Conditions High Speed Mode low Speed mode Min Min Max Unit Max DSPI cycle time Master (MTFE = 0) 25 -- 50 -- Slave (MTFE = 0) 40 -- 60 -- ns 2 tCSC PCS to SCK delay -- 16 -- -- -- ns 3 tASC After SCK delay -- 16 -- -- -- ns 4 tSDC SCK duty cycle -- tSCK/2 - 10 tSCK/2 + 10 -- -- ns 5 tA Slave access time SS active to SOUT valid -- 40 -- -- ns 6 tDIS Slave SOUT disable time SS inactive to SOUT High-Z or invalid -- 10 -- -- ns 7 tPCSC PCSx to PCSS time -- 13 -- -- -- ns 8 tPASC PCSS to PCSx time -- 13 -- -- -- ns 9 tSUI Data setup time for inputs Master (MTFE = 0) NA -- 20 -- ns Slave 2 -- 2 -- Master (MTFE = 1, CPHA = 0) 15 -- 81 -- Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 42 NXP Semiconductors Communication interfaces Table 35. DSPI electrical specifications (continued) No 10 11 12 Symbol Parameter tHI Data hold time for inputs tSUO Data valid (after SCK edge) tHO Data hold time for outputs Conditions High Speed Mode low Speed mode Min Max Min Max Master (MTFE = 1, CPHA = 1) 15 -- 20 -- Master (MTFE = 0) NA -- -5 -- Slave 4 -- 4 -- -- Master (MTFE = 1, CPHA = 0) 0 -- 111 Master (MTFE = 1, CPHA = 1) 0 -- -5 -- Master (MTFE = 0) -- NA -- 4 Slave -- 15 -- 23 Master (MTFE = 1, CPHA = 0) -- 4 -- 161 Master (MTFE = 1, CPHA = 1) -- 4 -- 4 Master (MTFE = 0) NA -- -2 -- Slave 4 -- 6 -- Master (MTFE = 1, CPHA = 0) -2 -- 101 -- Master (MTFE = 1, CPHA = 1) -2 -- -2 -- Unit ns ns ns 1. SMPL_PTR should be set to 1 NOTE Restriction For High Speed modes * DSPI2, DSPI3, SPI1 and SPI2 will support 40MHz Master mode SCK * DSPI2, DSPI3, SPI1 and SPI2 will support 25MHz Slave SCK frequency * Only one {SIN,SOUT and SCK} group per DSPI/SPI will support high frequency mode * For Master mode MTFE will be 1 for high speed mode * For high speed slaves, their master have to be in MTFE=1 mode or should be able to support 15ns tSUO delay NOTE For numbers shown in the following figures, see Table 35 MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 43 Communication interfaces Table 36. Continuous SCK timing Spec Characteristics Pad Drive/Load Value Min Max tSCK SCK cycle timing strong/50 pF 100 ns - - PCS valid after SCK strong/50 pF - 15 ns - PCS valid after SCK strong/50 pF -4 ns - Table 37. DSPI high speed mode I/Os DSPI High speed SCK High speed SIN High speed SOUT DSPI2 GPIO[78] GPIO[76] GPIO[77] DSPI3 GPIO[100] GPIO[101] GPIO[98] SPI1 GPIO[173] GPIO[175] GPIO[176] SPI2 GPIO[79] GPIO[110] GPIO[111] 2 3 PCSx 1 4 SCK Output (CPOL=0) 4 SCK Output (CPOL=1) 9 SIN 10 First Data Data 12 SOUT First Data Last Data 11 Data Last Data Figure 8. DSPI classic SPI timing -- master, CPHA = 0 MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 44 NXP Semiconductors Communication interfaces PCSx SCK Output (CPOL=0) 10 SCK Output (CPOL=1) 9 Data First Data SIN Last Data 12 SOUT First Data 11 Data Last Data Figure 9. DSPI classic SPI timing -- master, CPHA = 1 3 2 SS 1 4 SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN 12 11 Data Last Data Data Last Data 6 10 First Data Figure 10. DSPI classic SPI timing -- slave, CPHA = 0 MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 45 Communication interfaces SS SCK Input (CPOL=0) SCK Input (CPOL=1) 11 5 6 12 SOUT First Data 9 SIN Data Last Data Data Last Data 10 First Data Figure 11. DSPI classic SPI timing -- slave, CPHA = 1 3 PCSx 4 1 2 SCK Output (CPOL=0) 4 SCK Output (CPOL=1) 9 SIN First Data 10 12 SOUT First Data Last Data Data 11 Data Last Data Figure 12. DSPI modified transfer format timing -- master, CPHA = 0 MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 46 NXP Semiconductors Communication interfaces PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) 10 9 SIN First Data Last Data Data 12 First Data SOUT 11 Last Data Data Figure 13. DSPI modified transfer format timing -- master, CPHA = 1 3 2 SS 1 SCK Input (CPOL=0) 4 4 SCK Input (CPOL=1) SOUT First Data Data First Data 6 Last Data 10 9 SIN 12 11 5 Data Last Data Figure 14. DSPI modified transfer format timing - slave, CPHA = 0 MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 47 FlexRay electrical specifications SS SCK Input (CPOL=0) SCK Input (CPOL=1) 11 5 6 12 First Data SOUT 9 Last Data Data Last Data 10 First Data SIN Data Figure 15. DSPI modified transfer format timing -- slave, CPHA = 1 7 8 PCSS PCSx Figure 16. DSPI PCS strobe (PCSS) timing 6.4.2 FlexRay electrical specifications 6.4.2.1 FlexRay timing This section provides the FlexRay Interface timing characteristics for the input and output signals. It should be noted that these are recommended numbers as per the FlexRay EPL v3.0 specification, and subject to change per the final timing analysis of the device. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 48 NXP Semiconductors FlexRay electrical specifications 6.4.2.2 TxEN TxEN 80 % 20 % dCCTxENFALL dCCTxENRISE Figure 17. TxEN signal Table 38. TxEN output characteristics1 Name Description Min Max Unit dCCTxENRISE25 Rise time of TxEN signal at CC -- 9 ns dCCTxENFALL25 Fall time of TxEN signal at CC -- 9 ns dCCTxEN01 Sum of delay between Clk to Q of the last FF and the final output buffer, rising edge -- 25 ns dCCTxEN10 Sum of delay between Clk to Q of the last FF and the final output buffer, falling edge -- 25 ns 1. All parameters specified for VDD_HV_IOx = 3.3 V -5%, +10%, TJ = -40 C / 150 C, TxEN pin load maximum 25 pF MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 49 FlexRay electrical specifications PE_Clk TxEN dCCTxEN10 dCCTxEN01 Figure 18. TxEN signal propagation delays 6.4.2.3 TxD TxD dCCTxD50% 80 % 50 % 20 % dCCTxDRISE dCCTxDFALL Figure 19. TxD Signal Table 39. TxD output characteristics Name Description1 Min Max Unit dCCTxAsym Asymmetry of sending CC @ 25 pF load (=dCCTxD50% - 100 ns) -2.45 2.45 ns -- 92 ns dCCTxDRISE25+dCCTx Sum of Rise and Fall time of TxD signal at the output DFALL25 Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 50 NXP Semiconductors FlexRay electrical specifications Table 39. TxD output characteristics (continued) Description1 Name Min Max Unit dCCTxD01 Sum of delay between Clk to Q of the last FF and the final output buffer, rising edge -- 25 ns dCCTxD10 Sum of delay between Clk to Q of the last FF and the final output buffer, falling edge -- 25 ns 1. All parameters specified for VDD_HV_IOx = 3.3 V -5%, +10%, TJ = -40 C / 150 C, TxD pin load maximum 25 pF. 2. For 3.3 V 10% operation, this specification is 10 ns. PE_Clk* TxD dCCTxD10 dCCTxD01 *FlexRay Protocol Engine Clock Figure 20. TxD Signal propagation delays 6.4.2.4 RxD Table 40. RxD input characteristic Name Description1 Min Max Unit C_CCRxD Input capacitance on RxD pin -- 7 pF uCCLogic_1 Threshold for detecting logic high 35 70 % uCCLogic_0 Threshold for detecting logic low 30 65 % dCCRxD01 Sum of delay from actual input to the D input of the first FF, rising edge -- 10 ns dCCRxD10 Sum of delay from actual input to the D input of the first FF, falling edge -- 10 ns MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 51 FlexRay electrical specifications 1. All parameters specified for VDD_HV_IOx = 3.3 V -5%, +10%, TJ = -40 oC / 150 oC. 6.4.3 uSDHC specifications Table 41. uSDHC switching specifications Num Symbol Description Min. Max. Unit Card input clock SD1 fpp Clock frequency (Identification mode) 0 400 kHz fpp Clock frequency (SD\SDIO full speed) 0 25 MHz fpp Clock frequency (SD\SDIO high speed) 0 40 MHz fpp Clock frequency (MMC full speed) 0 20 MHz fOD Clock frequency (MMC full speed) 0 40 MHz SD2 tWL Clock low time 7 -- ns SD3 tWH Clock high time 7 -- ns SD4 tTLH Clock rise time -- 3 ns SD5 tTHL Clock fall time -- 3 ns SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD6 tOD SDHC output delay (output valid) -5 6.5 ns SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD7 tISU SDHC input setup time 5 -- ns SD8 tIH SDHC input hold time 0 -- ns SD3 SD2 SD1 SDHC_CLK SD6 Output SDHC_CMD Output SDHC_DAT[3:0] SD7 SD8 Input SDHC_CMD Input SDHC_DAT[3:0] Figure 21. uSDHC timing MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 52 NXP Semiconductors FlexRay electrical specifications 6.4.4 Ethernet switching specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 6.4.4.1 MII signal switching specifications The following timing specs meet the requirements for MII style interfaces for a range of transceiver devices. NOTE ENET0 supports the following xMII interfaces: MII, MII_Lite and RMII. ENET1 supports the following xMII interfaces: MII_Lite. NOTE It is only possible to use ENET0 and ENET1 simultaneously when both are configured for MII_Lite. NOTE In certain pinout configurations ENET1 MII-Lite signals can be across multiple VDD_HV_A/B/C domains. If these configuration are used, VDD_HV IO domains need to be at the same voltage (for example: 3.3V) Table 42. MII signal switching specifications Symbol -- MII1 Description RXCLK frequency RXCLK pulse width high Min. Max. Unit -- 25 MHz 35% 65% RXCLK period MII2 RXCLK pulse width low 35% 65% RXCLK period MII3 RXD[3:0], RXDV, RXER to RXCLK setup 5 -- ns MII4 RXCLK to RXD[3:0], RXDV, RXER hold 5 -- ns TXCLK frequency -- 25 MHz 35% 65% TXCLK -- MII5 TXCLK pulse width high period MII6 TXCLK pulse width low 35% 65% TXCLK period MII7 TXCLK to TXD[3:0], TXEN, TXER invalid 2 -- ns MII8 TXCLK to TXD[3:0], TXEN, TXER valid -- 25 ns MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 53 FlexRay electrical specifications MII6 MII5 TXCLK (input) MII8 MII7 TXD[n:0] Valid data TXEN Valid data TXER Valid data Figure 22. RMII/MII transmit signal timing diagram MII2 MII1 MII3 MII4 RXCLK (input) RXD[n:0] Valid data RXDV Valid data RXER Valid data Figure 23. RMII/MII receive signal timing diagram 6.4.4.2 RMII signal switching specifications The following timing specs meet the requirements for RMII style interfaces for a range of transceiver devices. Table 43. RMII signal switching specifications Num -- Description EXTAL frequency (RMII input clock RMII_CLK) Min. Max. Unit -- 50 MHz RMII1 RMII_CLK pulse width high 35% 65% RMII_CLK period RMII2 RMII_CLK pulse width low 35% 65% RMII_CLK period RMII3 RXD[1:0], CRS_DV, RXER to RMII_CLK setup 4 -- ns RMII4 RMII_CLK to RXD[1:0], CRS_DV, RXER hold 2 -- ns RMII7 RMII_CLK to TXD[1:0], TXEN invalid 4 -- ns RMII8 RMII_CLK to TXD[1:0], TXEN valid -- 15 ns MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 54 NXP Semiconductors MediaLB (MLB) electrical specifications 6.4.5 MediaLB (MLB) electrical specifications 6.4.5.1 MLB 3-pin interface DC characteristics The section lists the MLB 3-pin interface electrical characteristics. Table 44. MediaLB 3-Pin Interface Electrical DC Specifications Parameter Symbol Test Conditions Min Max Unit Maximum input voltage -- -- -- 3.6 V Low level input threshold VIL -- -- 0.7 V High level input threshold VIH See Note1 1.8 -- V Low level output threshold VOL IOL = -6 mA -- 0.4 V High level output threshold VOH IOH = -6 mA 2.0 -- V Input leakage current IL 0 < Vin < VDD -- 10 A 1. Higher VIH thresholds can be used; however, the risks associated with less noise margin in the system must be evaluated and assumed by the customer. 6.4.5.2 MLB 3-pin interface electrical specifications This section describes the timing electrical information of the MLB module. Figure 24. MediaLB 3-Pin Timing MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 55 MediaLB (MLB) electrical specifications Ground = 0.0 V; Load Capacitance = 60 pF, input transition= 1 ns ; MediaLB speed = 256/512 Fs; Fs = 48 kHz; all timing parameters specified from the valid voltage threshold as listed below; unless otherwise noted. Table 45. MLB 3-Pin 256/512 Fs Timing Parameters Parameter Symbol MLBCLK operating frequency fmck MLBCLK rise time MLBCLK fall time MLBCLK low time1 Min 11.264 Max Unit 25.6 MHz 256xFs at 44.0 kHz, 512xFs at 50.0 kHz tmckr 3 ns VIL to VIH tmckf 3 ns VIH to VIL -- ns 256xFs tmckl 30 14 MLBCLK high time Comment tmckh 512xFs 30 -- ns 14 256xFs 512xFs MLBSIG/MLBDAT receiver input setup to MLBCLK falling tdsmcf 1 -- ns -- MLBSIG/MLBDAT receiver input hold from MLBCLK low tdhmcf tmcfdz -- ns -- MLBSIG/MLBDAT output valid from MLBCLK low tmcfdz 0 tmckl ns 2 Bus output hold from MLBCLK low tmdzh 4 -- ns 2 1. MLBCLK low/high time includes the pluse width variation. 2. The MediaLB driver can release the MLBDAT/MLBSIG line as soon as MLBCLK is low; however, the logic state of the final driven bit on the line must remain on the bus for tmdzh. Therefore, coupling must be minimized while meeting the maximum load capacitance listed. Ground = 0.0 V; Load Capacitance = 40 pF, input transition= 1 ns; MediaLB speed = 1024 Fs; Fs = 48 kHz; all timing parameters specified from the valid voltage threshold as listed below; unless otherwise noted. Table 46. MLB 3-Pin 1024 Fs Timing Parameters Parameter MLBCLK Operating Symbol Frequency1 fmck Min Max Unit Comment 45.056 - MHz 1024 x fs at 44.0 kHz - 51.2 MHz 1024 x fs at 50.0 kHz MLBCLK rise time fmckr 1 ns VIL to VIH MLBCLK fall time fmckf 1 ns VIH to VIL MLBCLK low time tmckl 6.1 -- ns 2 MLBCLK high time tmckh 9.3 -- ns 2 MLBSIG/MLBDAT receiver input setup to MLBCLK falling tdsmcf 1 -- ns MLBSIG/MLBDAT receiver input hold tdhmcf from MLBCLK low tmcfdz -- ns MLBSIG/MLBDAT output valid from MLBCLK low tmcfdz 0 tmckl ns 3 Bus Hold from MLBCLK low tmdzh 2 -- ns 3 MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 56 NXP Semiconductors USB electrical specifications 1. The controller can shut off MLBCLK to place MediaLB in a low-power state. Depending on the time the clock is shut off, a runt pulse can occur on MLBCLK. 2. MLBCLK low/high time includes the pluse width variation. 3. The MediaLB driver can release the MLBDAT/MLBSIG line as soon as MLBCLK is low; however, the logic state of the final driven bit on the line must remain on the bus for tmdzh. Therefore, coupling must be minimized while meeting the maximum load capacitance listed. 6.4.6 USB electrical specifications 6.4.6.1 USB electrical specifications The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org. 6.4.6.2 ULPI timing specifications The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin Interface. Control and data timing requirements for the ULPI pins are given in the following table. These timings apply to synchronous mode only. All timings are measured with respect to the clock as seen at the USB_CLKIN pin. Table 47. ULPI timing specifications Num Description Min. Typ. Max. Unit USB_CLKIN operating frequency -- 60 -- MHz USB_CLKIN duty cycle -- 50 -- % U1 USB_CLKIN clock period -- 16.67 -- ns U2 Input setup (control and data) 5 -- -- ns U3 Input hold (control and data) 1 -- -- ns U4 Output valid (control and data) -- -- 9.5 ns U5 Output hold (control and data) 1 -- -- ns MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 57 USB electrical specifications U1 USB_CLKIN U2 U3 ULPI_DIR/ULPI_NXT (control input) ULPI_DATAn (input) U5 U4 ULPI_STP (control output) ULPI_DATAn (output) Figure 25. ULPI timing diagram 6.4.7 SAI electrical specifications All timing requirements are specified relative to the clock period or to the minimum allowed clock period of a device Table 48. Master mode SAI Timing no Parameter Value Unit Min Max Operating Voltage 2.7 3.6 V S1 SAI_MCLK cycle time 40 - ns S2 SAI_MCLK pulse width high/low 45% 55% MCLK period S3 SAI_BCLK cycle time 80 - BCLK period S4 SAI_BCLK pulse width high/low 45% 55% ns S5 SAI_BCLK to SAI_FS output valid - 15 ns S6 SAI_BCLK to SAI_FS output invalid 0 - ns S7 SAI_BCLK to SAI_TXD valid - 15 ns S8 SAI_BCLK to SAI_TXD invalid 0 - ns S9 SAI_RXD/SAI_FS input setup before SAI_BCLK 28 - ns S10 SAI_RXD/SAI_FS input hold after SAI_BCLK 0 - ns MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 58 NXP Semiconductors USB electrical specifications Figure 26. Master mode SAI Timing Table 49. Slave mode SAI Timing No Parameter Value Unit Min Max Operating Voltage 2.7 3.6 V S11 SAI_BCLK cycle time (input) 80 - ns S12 SAI_BCLK pulse width high/low (input) 45% 55% BCLK period S13 SAI_FS input setup before SAI_BCLK 10 - ns S14 SAI_FS input hold after SAI_BCLK 2 - ns S15 SAI_BCLK to SAI_TXD/SAI_FS output valid - 28 ns S16 SAI_BCLK to SAI_TXD/SAI_FS output invalid 0 - ns S17 SAI_RXD setup before SAI_BCLK 10 - ns S18 SAI_RXD hold after SAI_BCLK 2 - ns MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 59 Debug specifications Figure 27. Slave mode SAI Timing 6.5 Debug specifications 6.5.1 JTAG interface timing Table 50. JTAG pin AC electrical characteristics 1 # Symbol Characteristic Min Max Unit 1 tJCYC TCK Cycle Time 2 62.5 -- ns 2 tJDC TCK Clock Pulse Width 40 60 % 3 tTCKRISE TCK Rise and Fall Times (40% - 70%) -- 3 ns 4 tTMSS, tTDIS TMS, TDI Data Setup Time 5 -- ns 5 tTMSH, tTDIH TMS, TDI Data Hold Time 5 -- ns -- 203 ns 6 tTDOV TCK Low to TDO Data Valid 7 tTDOI TCK Low to TDO Data Invalid 0 -- ns 8 tTDOHZ TCK Low to TDO High Impedance -- 15 ns 11 tBSDV TCK Falling Edge to Output Valid -- 6004 ns 12 tBSDVZ TCK Falling Edge to Output Valid out of High Impedance -- 600 ns 13 tBSDHZ TCK Falling Edge to Output High Impedance -- 600 ns 14 tBSDST Boundary Scan Input Valid to TCK Rising Edge 15 -- ns 15 tBSDHT TCK Rising Edge to Boundary Scan Input Invalid 15 -- ns 1. These specifications apply to JTAG boundary scan only. 2. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions. Refer to pad specification for allowed transition frequency 3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay. 4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 60 NXP Semiconductors Debug specifications TCK 2 3 2 3 1 Figure 28. JTAG test clock input timing TCK 4 5 TMS, TDI 6 7 8 TDO Figure 29. JTAG test access port timing MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 61 Debug specifications TCK 11 13 Output Signals 12 Output Signals 14 15 Input Signals Figure 30. JTAG boundary scan timing 6.5.2 Nexus timing Table 51. Nexus debug port timing 1 No. Symbol Parameter 1 tMCYC MCKO Cycle Time 2 tMDC MCKO Duty Cycle MCKO Low to MDO, MSEO, EVTO Data Valid2 Condition s Min Max Unit -- 15.6 -- ns -- 40 60 % -- -0.1 0.25 tMCYC 3 tMDOV 4 tEVTIPW EVTI Pulse Width -- 4 -- tTCYC 5 tEVTOPW EVTO Pulse Width -- 1 -- tMCYC -- 62.5 -- ns Time3 6 tTCYC TCK Cycle 7 tTDC TCK Duty Cycle -- 40 60 % 8 tNTDIS, tNTMSS TDI, TMS Data Setup Time -- 8 -- ns Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 62 NXP Semiconductors Debug specifications Table 51. Nexus debug port timing 1 (continued) No. Symbol Parameter Condition s Min Max Unit 9 tNTDIH, tNTMSH TDI, TMS Data Hold Time -- 5 -- ns 10 tJOV TCK Low to TDO/RDY Data Valid -- 0 25 ns 1. JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. 2. For all Nexus modes except DDR mode, MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 3. The system clock frequency needs to be four times faster than the TCK frequency. 1 2 MCKO 3 MDO MSEO EVTO Output Data Valid 5 Figure 31. Nexus output timing EVTI 4 Figure 32. Nexus EVTI Input Pulse Width MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 63 Debug specifications 6 7 TCK 8 9 TMS, TDI 10 TDO/RDY Figure 33. Nexus TDI, TMS, TDO timing 6.5.3 WKPU/NMI timing Table 52. WKPU/NMI glitch filter No. Symbol Parameter Min Typ Max Unit 1 WFNMI NMI pulse width that is rejected -- -- 20 ns 2 WNFNMID NMI pulse width that is passed 400 -- -- ns MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 64 NXP Semiconductors Thermal attributes 6.5.4 External interrupt timing (IRQ pin) Table 53. External interrupt timing specifications No. Symbol Parameter Conditions Min Max Unit 1 tIPWL IRQ pulse width low -- 3 -- tCYC 2 tIPWH IRQ pulse width high -- 3 -- tCYC 3 tICYC IRQ edge to edge time -- 6 -- tCYC These values applies when IRQ pins are configured for rising edge or falling edge events, but not both. IRQ 1 2 3 Figure 34. External interrupt timing 7 Thermal attributes 7.1 Thermal attributes Board type Symbol Description 176LQFP Unit Notes Single-layer RJA (1s) Thermal resistance, junction to ambient (natural convection) 45.5 C/W 1, 2 Four-layer (2s2p) Thermal resistance, junction to ambient (natural convection) 23.1 C/W 1, 2, 3 Single-layer RJMA (1s) Thermal resistance, junction to ambient (200 ft./min. air speed) 34.8 C/W 1,3 Four-layer (2s2p) RJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 16 C/W 1,3 -- RJB Thermal resistance, junction to board 9.4 C/W 4 -- RJCtop Thermal resistance, junction to case top 9.5 C/W 5 -- RJCbotttom Thermal resistance, junction to case bottom 0.2 C/W 6 RJA Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 65 Thermal attributes Board type -- Symbol JT Description Thermal characterization parameter, junction to package top 176LQFP 0.2 Unit C/W Notes 7 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any interface resistance. 7. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. Board type Symbol Description 324 MAPBGA Unit Notes Singlelayer (1s) RJA Thermal resistance, junction to ambient (natural convection) 25.5 C/W 1, 2 Four-layer (2s2p) RJA Thermal resistance, junction to ambient (natural convection) 19.0 C/W 1,23 Singlelayer (1s) RJMA Thermal resistance, junction to ambient (200 ft./ min. air speed) 18.1 C/W 1, 3 Four-layer (2s2p) RJMA Thermal resistance, junction to ambient (200 ft./ min. air speed) 14.8 C/W 1,3 -- RJB Thermal resistance, junction to board 10.4 C/W 4 -- RJC Thermal resistance, junction to case 8.4 C/W 5 -- JT Thermal characterization parameter, junction to package top natural convection) 0.45 C/W 6 -- JB Thermal characterization parameter, junction to package top natural convection) 2.65 C/W 7 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance., 2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 3. Per JEDEC JESD51-6 with the board horizontal 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 66 NXP Semiconductors Dimensions Board type Symbol Description 256 MAPBGA Unit Notes Singlelayer (1s) RJA Thermal resistance, junction to ambient (natural convection) 39.5 C/W 1, 2 Four-layer (2s2p) RJA Thermal resistance, junction to ambient (natural convection) 22.9 C/W 1,23 Singlelayer (1s) RJMA Thermal resistance, junction to ambient (200 ft./ min. air speed) 28.5 C/W 1,3 Four-layer (2s2p) RJMA Thermal resistance, junction to ambient (200 ft./ min. air speed) 18.3 C/W 1,3 -- RJB Thermal resistance, junction to board 9.5 C/W 4 -- RJC Thermal resistance, junction to case 5.8 C/W 5 -- JT Thermal characterization parameter, junction to package top outside center (natural convection) 0.2 C/W 6 -- JB Thermal characterization parameter, junction to package bottom outside center (natural convection) 6.4 C/W 7 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance., 2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 3. Per JEDEC JESD51-6 with the board horizontal 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB. 8 Dimensions 8.1 Obtaining package dimensions Package dimensions are provided in package drawing. To find a package drawing, go to www.nxp.com and perform a keyword search for the drawing's document number: Package NXP Document Number 176-pin LQFP-EP 98ASA00673D 256 MAPBGA 98ASA00346D 324 MAPBGA 98ASA10582D MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 67 Pinouts 9 Pinouts 9.1 Package pinouts and signal descriptions For package pinouts and signal descriptions, refer to the Reference Manual. 10 Reset sequence This section describes different reset sequences and details the duration for which the device remains in reset condition in each of those conditions. 10.1 Reset sequence duration Table 54 specifies the minimum and the maximum reset sequence duration for the five different reset sequences described in Reset sequence description. Table 54. RESET sequences No. Symbol Parameter TReset Min Typ 1 Unit Max 1 TDRB Destructive Reset Sequence, BIST enabled 5.730 7.796 ms 2 TDR Destructive Reset Sequence, BIST disabled 0.111 0.182 ms 3 TERLB External Reset Sequence Long, Unsecure Boot 5.729 7.793 ms 4 TFRL Functional Reset Sequence Long, Unsecure Boot 0.110 0.179 ms 5 TFRS Functional Reset Sequence Short, Unsecure Boot 0.007 0.009 ms 1. The Typ value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET_B by an external reset generator. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 68 NXP Semiconductors Reset sequence 10.2 BAF execution duration Following table specifies the typical BAF execution time in case BAF boot header is present at first location (Typical) and last location (worst case). Total Boot time is the sum of reset sequence duration and BAF execution time. Table 55. BAF execution duration BAF execution duration Min Typ Max Unit BAF execution time (boot header at first location) - 200 - s BAF execution time (boot header at last location) - 320 - s 10.3 Reset sequence description The figures in this section show the internal states of the device during the five different reset sequences. The dotted lines in the figures indicate the starting point and the end point for which the duration is specified in Table 54. With the beginning of DRUN mode, the first instruction is fetched and executed. At this point, application execution starts and the internal reset sequence is finished. The following figures show the internal states of the device during the execution of the reset sequence and the possible states of the RESET_B signal pin. NOTE RESET_B is a bidirectional pin. The voltage level on this pin can either be driven low by an external reset generator or by the device internal reset circuitry. A high level on this pin can only be generated by an external pullup resistor which is strong enough to overdrive the weak internal pulldown resistor. The rising edge on RESET_B in the following figures indicates the time when the device stops driving it low. The reset sequence durations given in Table 54 are applicable only if the internal reset sequence is not prolonged by an external reset generator keeping RESET_B asserted low beyond the last Phase3. MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 69 Reset sequence Reset Sequence Trigger Reset Sequence Start Condition RESET_B PHASE0 PHASE1,2 Establish IRC and PWR PHASE3 Flash Init BIST Device Config Self Test MBIST Setup PHASE1,2 Flash Init LBIST PHASE3 DRUN BAF+ Application Ex ecut ion Device Config TDRB, min < TRESET < TDRB, max Figure 35. Destructive reset sequence, BIST enabled Reset Sequence Trigger Reset Sequence Start Condition RESET_B PHASE0 PHASE1,2 Establish IRC and PWR Flash Init PHASE3 DRUN BAF+ Application Execution Device Config TDR, min < TRESET < TDR, max Figure 36. Destructive reset sequence, BIST disabled Reset Sequence Trigger Reset Sequence Start Condition RESET_B PHASE1,2 Flash Init PHASE3 Device Config BIST Self Test MBIST Setup PHASE1,2 PHASE3 Flash Init LBIST Device Config DRUN BAF+ Application Ex ecut ion TERLB, min < TRESET < TERLB, max Figure 37. External reset sequence long, BIST enabled Reset Sequence Trigger Reset Sequence Start Condition RESET_B PHASE1,2 Flash Init PHASE3 Device Config DRUN BAF+ Application Ex ecut ion TFRL, min < TRESET < TFRL, max Figure 38. Functional reset sequence long MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 70 NXP Semiconductors Revision History Reset Sequence Trigger Reset Sequence Start Condition RESET_B PHASE3 DRUN BAF+ Application Execution TFRS, min < TRESET < TFRS, max Figure 39. Functional reset sequence short The reset sequences shown in Figure 38 and Figure 39 are triggered by functional reset events. RESET_B is driven low during these two reset sequences only if the corresponding functional reset source (which triggered the reset sequence) was enabled to drive RESET_B low for the duration of the internal reset sequence. See the RGM_FBRE register in the device reference manual for more information. 11 Revision History The following table provides a revision history for this document. Table 56. Revision History Rev. No. Date Substantial Changes 1 14 March 2013 Initial Release 1.1 16 May 2013 Updated Pinouts section 2 22 May 2014 * * * * * Removed Category (SR, CC, P, T, D, B) column from all the table of the Datasheet Revised the feature list. Revised Introduction section to remove classification information. Updated optional information in the ordering information figure. Revised Absolute maximum rating section: * Removed category column from table * Added footnote at Ta * Revised Recommended operating conditions section * Added notes * Updated table: Recommended operating conditions (VDD_HV_x = 3.3 V) * Updated table: Recommended operating conditions (VDD_HV_x = 5 V) * Revised Voltage regulator electrical characteristics * Updated text describing bipolar transistors * Updated figure: Voltage regulator capacitance connection * Updated table: Voltage regulator electrical specifications * Removed Brownout information * Revised Voltage monitor electrical characteristics table * Revised Supply current characteristics section * Updated table: Current consumption characteristics * Updated table: Low Power Unit (LPU) Current consumption characteristics * STANDBY Current consumption characteristics Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 71 Revision History Table 56. Revision History (continued) Rev. No. Date Substantial Changes * * * * * * * * * * * * * Revised Electromagnetic Interference (EMI) characteristics section Revised DC electrical specifications @ 3.3V Range table for naming convections. Revised DC electrical specifications @ 5 V Range table for naming conventions Deleted MLB 6-pin Electrical Specifications Removed PORST characteristics from Functional reset pad electrical characteristics table Added section PORST electrical characteristics Revised Input impedance and ADC accuracy section to remove SNR, THD, SINAD, ENOB, Revised 32 kHz oscillator electrical specifications table to remove 'Vpp' row. Updated 16 MHz RC Oscillator electrical specifications table for statuptime, cycle to cycle jitter, and lonf term jitter Updated 128 KHz Internal RC oscillator electrical specifications table. Updated PLL electrical specifications table Added Jitter Calculation table Added Percentage of Sample exceeding specified value of jitter table * Revised Memory interfaces section * Revised Communication interfaces section * Updated note * Added Continuous SCK timing table * Added DSPI high speed mode I/Os table * Updated input transition value in section MLB 3-pin interface electrical specifications * Deleted MLB 6-pin interface DC characteristics section * Deleted MLB 6-pin interface AC characteristics section * Updated JTAG pin AC electrical characteristics table * Revised table under Thermal attributes section * Updated Obtaining package dimensions section for Freescale Document numbers 3 12 May 2015 * Editorial updates throughout the sections * Renamed '176 LQFP' package to '176 LQFP-EP' * Added following sections: * Block diagram * Family comparison * Ordering Information * In table: Absolute maximum ratings as follows: * Removed row for symbol: 'VSS_HV' * Added symbol: 'VDD_LV' * Updated 'Max' column for symbol 'VINA' * Added footnote to 'Conditions' column * Removed footnote from 'Max' column * In section: Recommended operating conditions * Added opening text: ''The following table describes the operating conditions ... " * Added note: "VDD_HV_A, VDD_HV_B and VDD_HV_C are all ... " * In table: Recommended operating conditions (VDD_HV_x = 3.3 V) * Added footnote to 'Conditions' cloumn * Updated footnote for 'Min' column * Removed footnote from symbols 'VDD_HV_A', 'VDD_HV_B', and 'VDD_HV_C' * Removed row for symbol: 'VSS_HV' * Updated 'Parameter' column for symbol 'VDD_HV_FLA', 'VDD_HV_ADC1_REF', 'VDD_LV' * Updated 'Min' column for symbol 'VDD_HV_ADC0' and 'VDD_HV_ADC1' * Updated 'Parameter' 'Min' 'Max' column for symbol 'VSS_HV_ADC0' and 'VSS_HV_ADC1' * Added footnote to symbol 'VDD_LV ' * Removed footnote from symbol 'VIN1_CMP_REF' Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 72 NXP Semiconductors Revision History Table 56. Revision History (continued) Rev. No. Date Substantial Changes * Removed row for symbol 'VSS_LV' * Removed footnote from 'Max' column of symbols 'VDD_HV_ADC0' and 'VDD_HV_ADC1' * In section: Recommended operating conditions * In table: Recommended operating conditions (VDD_HV_x = 5 V) * Added footnote to 'Conditions' cloumn * Updated footnote for 'Min' column * Removed footnote from symbols 'VDD_HV_A', 'VDD_HV_B', and 'VDD_HV_C' * Removed row for symbol: 'VSS_HV' * Updated 'Parameter' column for symbol 'VDD_HV_ADC1_REF' 'VDD_HV_ADC1_REF', 'VDD_LV' * Updated 'Min' columnn of symbol 'VDD_HV_ADC0' and 'VDD_HV_ADC1' * Updated 'Parameter', 'Min' 'Max' column for symbol 'VSS_HV_ADC0' and 'VSS_HV_ADC1' * Added footnote to symbol 'VDD_LV' * Removed row for symbol 'VSS_LV' * Added row for symbol 'VIN1_CMP_REF' and corresponding footnotes to the symbol * In section: Voltage regulator electrical characteristics * In table: Voltage regulator electrical specifications * Added note to symbol 'Cbe_fpreg' * In section: Voltage monitor electrical characteristics * In table: Voltage monitor electrical characteristics * Updated column 'Parameter', 'Min' and 'Max' (of fall/rise trimmed condition) for symbol 'VHVD_LV_cold' and 'VLVD_IO_A_HI' * Updated column 'Parameter', 'Min' and 'Typ' (of fall/rise trimmed condition) for symbol) 'VLVD_LV_PD2_hot', 'VLVD_LV_PD2_cold LV' * Updated column 'Parameter' for symbol 'VLVD_LV_PD0_hot' * Updated column 'Typ' and 'Max' (of fall/rise trimmed condition) for symbol) 'VLVD_FLASH' * Updated footnote on symbol 'VLVD_IO_A_LO' and 'VLVD_IO_A_HI' * In section: Supply current characteristics * In table: Current consumption characteristics * Updated column 'Typ' for symbol 'IDD_FULL' for temperature 85, 105, 125 * Updated column 'Typ' for symbol 'IDD_GWY' for temperature 85, 105, 125 and column 'Max' for temperature 105 * Updated column 'Typ' for symbol 'IDD_BODY1' for temperature 85, 105, 125 * Updated column 'Typ' for symbol 'IDD_BODY2' for temperature 85, 105, 125 and 'Max' for temperature 125 * Added 'Typ' value for temperature 25 for symbol 'IDD_STOP' * Updated column 'Typ' and 'Max' for symbol 'IDD_STOP' for temperature 85, 105, 125 * In table: Low Power Unit (LPU) Current consumption characteristics * Updated column 'Typ' for symbol 'LPU_RUN' for tempeature 25 and 125 * Added 'Typ' and 'Max' value for temperature 85 and 105 for symbol 'LPU_RUN' * Updated column 'Typ' for symbol 'LPU_STOP' for tempeature 25 and 125 * Added 'Typ' and 'Max' value for temperature 85 and 105 for symbol 'LPU_STOP' * In table: STANDBY Current consumption characteristics * Updated to have one STANDBY * In section: I/O parameters Table continues on the next page... MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 73 Revision History Table 56. Revision History (continued) Rev. No. Date Substantial Changes * In table: Functional Pad AC Specifications @ 3.3 V Range * Updated values for symbol 'pad_sr_hv (output)' * In table: DC electrical specifications @ 3.3V Range * Updtaed values for VDD_HV_x, Vih, Vhys * Added Vih (pad_i_hv), Vil (pad_i_hv), Vhys (pad_i_hv), Vih_hys, Vil_hys * In table: Functional Pad AC Specifications @ 5 V Range * Updated values for symbol 'pad_sr_hv (output)' * In table DC electrical specifications @ 5 V Range * Added Vih (pad_i_hv), Vil (pad_i_hv), Vhys (pad_i_hv), Vih_hys, Vil_hys * In section: PORST electrical specifications * In table: PORST electrical specifications * Updated 'Min' value for WNFPORST * Corrected 'Unit' for VIH and VIL * In section: Peripheral operating requirements and behaviours * Revised table: ADC conversion characteristics (for 12-bit) and ADC conversion characteristics (for 10-bit) * In section: Analogue Comparator (CMP) electrical specifications * In table: Comparator and 6-bit DAC electrical specifications * Updated 'Max' value of IDDLS * Updated 'Min' and 'Max' for VAIO and DNL * Updated 'Descripton' 'Min' 'Max' od VH * Updated row for tDHS * Added row for tDLS * Removed row for VCMPOh and VCMPOl * In section: Clocks and PLL interfaces modules * Revised table: Main oscillator electrical characteristics * In table: 16 MHz RC Oscillator electrical specifications * Updated 'Max' of Tstartup * In table: 128 KHz Internal RC oscillator electrical specifications * Removed Uncaliberated 'Condition' for Fosc * Updated 'Min' and 'Max' of Caliberated Fosc * Updated 'Temperature dependence' and 'Supply dependence' * In table: PLL electrical specifications * Removed Input Clock Low Level, Input Clock High Level, Power consumption, Regulator Maximum Output Current, Analog Supply, Digital Supply (VDD_LV), Modulation Depth (Down Spread), PLL reset assertion time, and Power Consumption * Removed 'Typ' value of Duty Cycle at pllclkout * Removed 'Min' from calibration mode of Lock Time * In table: Jitter calculation * Added 1 Sigma Random Jitter value for Long term jitter * In section Flash read wait state and address pipeline control settings * Revised table: Flash Read Wait State and Address Pipeline Control * Removed section: On-chip peripherals * Added section: 'Reset sequence' Rev4 Feb 10 2017 * Added VDD_HV_BALLAST footnote in Voltage regulator electrical characteristics * Added Note to clarify In-Rush current and pin capacitance in Voltage regulator electrical characteristics * Updated SIUL2_MSCRn[SRC 1:0]=11@25pF max value; SIUL2_MSCRn[SRC 1:0]=11@50pF min value; SIUL2_MSCRn[SRC 1:0]=10@25pF min and max values in AC specifications @ 3.3 V Range MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 74 NXP Semiconductors Revision History Table 56. Revision History Rev. No. Date Substantial Changes * Updated VIH min and VIL max values in Main oscillator electrical characteristics * Replaced ipp_sre[1:0] by SIUL2_MSCRn[SRC 1:0] in AC specifications @ 3.3 V Range, DC electrical specifications @ 3.3V Range * Functional reset sequence short, unsecure boot corrected Reset sequence duration * Added NVM memory map and RAM memory map Family comparison * Added BAF execution duration section BAF execution duration * Supply names (VDD_LV, VSS_LV replace dvss, avss, dvdd, avdd) corrected in Jitter calculation table PLL electrical specifications * Updated Ordering information: Fab and Mask version indicator * Updated tpsus typical and max values Flash memory AC timing specifications * Added Notes on IBIS models use in AC specifications @3.3 V Range AC specifications @ 3.3 V Range * Updated Vol value in DC electrical specifications @ 3.3V Range DC electrical specifications @ 3.3V Range * Added Notes on IBIS models in Functional Pad AC Specifications @ 5 V Range AC specifications @ 5 V Range * Updated Vol values in DC electrical specifications @5V Range DC electrical specifications @ 5 V Range * Updated IDD Current values Supply current characteristics * Updated STANDBY current consumption with FIRC ON Supply current characteristics * Thermal numbers update for 256MAPBGA Thermal attributes * POR_HV Trim values removed Voltage monitor electrical characteristics * ADC analog pad leakage for 105 C added ADC electrical specifications * IDD STANDBY0, 1, 2 and 3 added Supply current characteristics MPC5748G Microcontroller Data Sheet, Rev. 4, 02/2017 NXP Semiconductors 75 How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. 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