74HC373DTR2G - ON Semiconductor

March, 2007 − Rev. 0

1Publication Order Number:

74HC373/D

74HC373

Octal 3−State Non−Inverting

Transparent Latch

High−Performance Silicon−Gate CMOS

The 74HC373 is identical in pinout to the LS373. The device inputs

are compatible with standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

These latches appear transparent to data (i.e., the outputs change

asynchronously) when Latch Enable is high. When Latch Enable goes

low, data meeting the setup and hold time becomes latched.

The Output Enable input does not affect the state of the latches, but

when Output Enable is high, all device outputs are forced to the

high−impedance state. Thus, data may be latched even when the

outputs are not enabled.

The HC373A is identical in function to the HC573A which has the

data inputs on the opposite side of the package from the outputs to

facilitate PC board layout.

The HC373A is the non−inverting version of the HC533A.

Features

•Output Drive Capability: 15 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 mA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the JEDEC Standard No. 7.0 A Requirements

•ESD Performance: HBM > 2000 V; Machine Model > 200 V

•Chip Complexity: 186 FETs or 46.5 Equivalent Gates

•This is a Pb−Free Device

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MARKING

DIAGRAM

HC373 = Specific Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

See detailed ordering and shipping information in the package

dimensions section on page 3 of this data sheet.

ORDERING INFORMATION

373

ALYW G

TSSOP−20

DT SUFFIX

CASE 948E

(Note: Microdot may be in either location)

74HC373

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DATA

INPUTS

D7 18

OUTPUT ENABLE

PIN 20 = VCC

PIN 10 = GND

NONINVERTING

OUTPUTS

LATCH ENABLE

FUNCTION TABLE

Inputs Output

Output Latch

Enable Enable D Q

LHHH

LHLL

L L X No Change

HXXZ

X = Don’t Care

Z = High Impedance

OUTPUT

ENABLE

GND

Q1 5

VCC

LATCH

ENABLE

LOGIC DIAGRAM PIN ASSIGNMENT

Design Criteria Value Units

Internal Gate Count* 46.5 ea

Internal Gate Propagation Delay 1.5 ns

Internal Gate Power Dissipation 5.0 mW

Speed Power Product 0.0075 pJ

*Equivalent to a two−input NAND gate.

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MAXIMUM RATINGS

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V

Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V

Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V

Iin DC Input Current, per Pin ±20 mA

Iout DC Output Current, per Pin ±35 mA

ICC DC Supply Current, VCC and GND Pins ±75 mA

PDPower Dissipation in Still Air, TSSOP Package† 450 mW

Tstg Storage Temperature – 65 to + 150 _C

TLLead Temperature, 1 mm from Case for 10 Seconds

(TSSOP Package) 260

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

†Derating — TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

TAOperating Temperature, All Package Types – 55 + 125 _C

tr, tfInput Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

1000

500

400

ORDERING INFORMATION

Device Package Shipping†

74HC373DTR2G TSSOP−20* 2500 Units / Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

74HC373

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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol Parameter Test Conditions

VCC

(V) – 55 to 25_Cv 85_Cv 125_CUnit

VIH Minimum High−Level Input

Voltage

Vout = VCC – 0.1 V

|Iout| v 20 mA

2.0

3.0

4.5

6.0

1.5

2.1

3.15

4.2

1.5

2.1

3.15

4.2

1.5

2.1

3.15

4.2

VIL Maximum Low−Level Input

Voltage

Vout = 0.1 V

|Iout| v 20 mA

2.0

3.0

4.5

6.0

0.5

0.9

1.35

1.8

0.5

0.9

1.35

1.8

0.5

0.9

1.35

1.8

VOH Minimum High−Level Output

Voltage

Vin = VIH

|Iout| v 20 mA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin = VIH |Iout| v 2.4 mA

|Iout| v 6.0 mA

|Iout| v 7.8 mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.2

3.7

5.2

VOL Maximum Low−Level Output

Voltage

Vin = VIL

|Iout| v 20 mA

2.0

4.5

6.0

0.1

Vin = VIL |Iout| v 2.4 mA

|Iout| v 6.0 mA

|Iout| v 7.8 mA

3.0

4.5

6.0

0.26

0.33

0.4

Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA

IOZ Maximum Three−State

Leakage Current

Output in High−Impedance State

Vin = VIL or VIH

Vout = VCC or GND

6.0 ±0.5 ±5.0 ±10 mA

ICC Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0 mA

6.0 4.0 40 40 mA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

Symbol Parameter

VCC

(V)

Guaranteed Limit

Unit

– 55 to 25_Cv 85_Cv 125_C

tPLH

tPHL

Maximum Propagation Delay, Input D to Q

(Figures 1 and 5)

2.0

3.0

4.5

6.0

125

155

110

190

130

tPLH

tPHL

Maximum Propagation Delay, Latch Enable to Q

(Figures 2 and 5)

2.0

3.0

4.5

6.0

140

175

120

210

140

tPLZ

tPHZ

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

2.0

3.0

4.5

6.0

150

100

190

125

225

150

tPZL

tPZH

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

2.0

3.0

4.5

6.0

150

100

190

125

225

150

tTLH

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 5)

2.0

3.0

4.5

6.0

Cin Maximum Input Capacitance 10 10 10 pF

Cout Maximum Three−State Output Capacitance

(Output in High−Impedance State)

15 15 15 pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High−Speed CMOS Data Book (DL129/D).

CPD Power Dissipation Capacitance (Per Enabled Output)*

Typical @ 25°C, VCC = 5.0 V

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High−Speed CMOS Data Book (DL129/D).

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TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)

Symbol Parameter Figure

VCC

(V)

Guaranteed Limit

Unit

– 55 to 25_Cv 85_Cv 125_C

Min Max Min Max Min Max

tsu Minimum Setup Time, Input D to Latch Enable 4 2.0

3.0

4.5

6.0

5.0

6.0

8.0

7.0

thMinimum Hold Time, Latch Enable to Input D 4 2.0

3.0

4.5

6.0

5.0

5 0

5.0

twMinimum Pulse Width, Latch Enable 2 2.0

3.0

4.5

6.0

tr, tfMaximum Input Rise and Fall Times 1 2.0

3.0

4.5

6.0

1000

800

500

400

1000

800

500

400

1000

800

500

400

SWITCHING WAVEFORMS

VCC

GND

INPUT D

10%

50%

90%

10%

50%

90%

tTLH

tPLH tPHL

tTHL

VCC

GND

50%

LATCH ENABLE

tPLH tPHL

50%

Figure 1. Figure 2.

Figure 3. Figure 4.

50%

1.3 V

tPZL tPLZ

tPZH tPHZ

10%

90%

VCC

GND

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

OUTPUT

ENABLE

50%

INPUT D

LATCH ENABLE

VCC

GND

VALID

tsu

50%

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TEST CIRCUITS

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 5. Figure 6.

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ AND tPZH.

1 kW

Figure 7. EXPANDED LOGIC DIAGRAM

74HC373

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PACKAGE DIMENSIONS

TSSOP−20

CASE 948E−02

ISSUE C

DIM

MIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B4.30 4.50 0.169 0.177

C1.20 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.27 0.37 0.011 0.015

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION:

MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE

MOLD FLASH, PROTRUSIONS OR GATE

BURRS. MOLD FLASH OR GATE BURRS

SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION

SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

ÍÍÍÍ

110

1120

PIN 1

IDENT

−T−

0.100 (0.004)

DGH

SECTION N−N

JJ1

−W−

SEATING

PLANE

−V−

−U−

0.10 (0.004) V S

20X REFK

L/2

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40 0.252

−−− −−−

U0.15 (0.006) T

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

74HC373

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ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

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Phone: 81−3−5773−3850

74HC373/D

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