CY25402/CY25422/CY25482
Two PLL Programmable Clock Generator
with Spread Spectrum
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-12565 Rev . *E Revised December 14, 2010
Features
■Two fully integrated phase locked loops (PLLs)
■Input frequency range
❐External crystal: 8 to 48 MHz
❐External reference: 8 to 166 MHz clock
■Reference clock input voltage range
❐2.5 V, 3.0 V, and 3.3 V for CY25482
❐1.8 V for CY25402 and CY25422
■Wide operating output frequency range
❐3 to 166 MHz
■Programmable spread spectrum with center and down spread
option and lexmark and linear modulation pro fi les
■VDD supply voltage options:
❐2.5 V, 3.0 V, and 3.3 V for CY25402 and CY25482
❐1.8 V for CY25422
■Selectable output clock voltages independent of VDD:
❐2.5 V, 3.0 V, and 3.3 V for CY25402 and CY25482
❐1.8 V for CY25422
■Frequency select feature with option to select four different
frequencies
■Power-down, Output Enable, and SS ON/OFF controls
■Low jitter, high accuracy outputs
■Ability to synthesize nonstandard frequencies with Fractional-N
capability
■Three clock outputs with programmable drive strength
■Glitch-free outputs while frequency switching
■8-pin small outline integrated circuit (SOIC) package
■Commercial and Industrial temperature ranges
Benefits
■Multiple high performance PLLs allow synthesis of unrelated
frequencies
■Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
■Application specific programmable EMI reduction using spread
spectrum for clocks
■Programmable PLLs for system frequency margin tests
■Meets critical timing requirements in complex system designs
■Suitability for PC, consumer, portable, and networking
applications
■Capable of zero parts per million (PPM) frequency synthesis
error
■Uninterrupted system operation during clock frequency switch
■Application compatibility in standard and low power systems
Block Diagram
OSC
CLK2
REFOUT
CLK1
Crossbar
Switch
FS1
SSON
XOUT
XIN/
EXCLKIN
PD#/OE
PLL 2
(SS)
FS0
MUX
and
Control
Logic
PLL 1
(SS)
Output
Dividers
and
Drive
Strength
Control
[+] Feedback
CY25402/CY25422/CY25482
Document #: 001-12565 Rev. *E Page 2 of 14
Contents
Pin Description .................................................................3
General Description .........................................................5
2 Configurable PLLs . ... ... .............................................5
Input Reference Clocks ...............................................5
VDD Power Supply Options ........................................5
Output Source Selection .............................................5
Spread Spectrum Control ............................................5
Frequency Select ........................................................5
Glitch-Free Frequency Switch .....................................5
PD#/OE Mode ................... .. .............. ..........................5
Output Drive Strength ..................................................5
Generic Configuration and Custom Frequency ...........5
Absolute Maximum Conditions .......................................6
Recommended Operating Conditions ............................6
DC Electrical Specificati on s .................. ..........................7
AC Electrical Specificati on s .................. ..........................8
Recommended Crystal Specification for SMD Packag e 8
Test and Measurement Setup ..........................................9
Voltage and Timing Definiti ons .................... ... ................9
Recommended Crystal Specification for
Thru-Hole Package ......... ..................................................9
Possible Configurations ........... ..................................10
Ordering Code Definitions .........................................11
Package Drawing and Dimensions ...............................11
Acronyms ........................................................................ 12
Document Conventions .................. ... ............................12
Units of Measure ............. ... ... ....................................12
Document History Page .......... .......................................13
Sales, Solutions, and Legal Information ......................14
Worldwide Sales and Design Support .......................14
Products ....................................................................14
PSoC® Solutions .......................................................14
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CY25402/CY25422/CY25482
Document #: 001-12565 Rev. *E Page 3 of 14
Table 1. Device Selector Guide
Pin Description
Figure 1. Pin Diagram - CY25402 8-LD SOIC
Table 2. Pin Definition - CY25402 (2.5 V, 3.0 V, or 3.3 V Supply)
Device Crystal Input EXCKLKIN Input VDD
CY25402 Yes 1.8 V LVCMOS 2.5 V, 3.0 V, 3.3 V
CY25482 No 2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V
CY25422 Yes 1.8 V LVCMOS 1.8 V
Pin Number Name IO Description
1 XIN/EXCLKIN Input Crystal input or 1.8 V External clock input
2V
DD Power Power supply: 2.5 V, 3.0 V, or 3.3 V
3 CLK1 Output Programmable clock output with spread spectrum
4 REFOUT/FS0 Output/input Multifunction programmable pi n: Reference clock output or frequency select pin
5 PD#/OE/FS1 Input Multifunction programmable pin: Power-down, output enable or Frequency select
pin
6 CLK2/SSON Output/input Multifunction programmable pin: Programmable clock output with spread spectrum
or Spread spectrum ON/OFF control pin
7 GND Power Power supply ground
8 XOUT Output Crystal output
VDD CY25402
1
2
3
4
8
7
6
5
XOUT
GND
CLK2/SSON
PD#/OE/FS1
XIN/
EXCLKIN
CLK1
REFOUT/
FS0
[+] Feedback
CY25402/CY25422/CY25482
Document #: 001-12565 Rev. *E Page 4 of 14
Figure 2. Pin Diagram - CY25482 8-LD SOIC
Table 3. Pin Definition - CY25482 (2.5 V, 3.0 V, or 3.3 V Supply)
Figure 3. Pin Diagram - CY25422 8-LD SOIC
Table 4. Pin Definition - CY25422 (1.8 V Supply)
Pin Number Name IO Description
1 EXCLKIN Input 2.5 V, 3.0 V, or 3.3 V external clock input
2V
DD Power Power Supply: 2.5 V, 3.0 V, or 3.3 V
3 CLK1 Output Programmable clock output with spread spectrum
4 REFOUT/FS0 Output/input Multifunction programmable pin: Reference clock output or frequency select pin
5 PD#/OE/FS1 Input Multifunction programmable pin: Power-down, output enable or fre quency select
pin
6 CLK2/SSON Output/input Multifunction Programmable pin: Programmable clock output with spread spectrum
or spread spectrum ON/OFF control pin
7 GND Power Power supply ground
8 DNU Output Do not use this pin
Pin Number Name IO Description
1 XIN/EXCLKIN Input Crystal input or 1.8 V external clock input
2V
DD Power Power supply: 1.8 V
3 CLK1 Output Programmable clock output with spread spectrum
4 REFOUT/FS0 Output/input Multifunction programmable pin: reference clock output or frequency select pin
5 PD#/OE/FS1 Input Multifunction programmable pin: power-down, output enable or frequency se lect
pin
6 CLK2/SSON Output/input Multifunction programmable pin: programmable clock output with spread spectrum
or spread spectrum ON/OFF control pin
7 GND Power Power supply ground
8 XOUT Output Crystal output
VDD CY25482
1
2
3
4
8
7
6
5
DNU
GND
PD#/OE/FS1
EXCLKIN
CLK1
REFOUT/
FS0
CLK2/SSON
CY25422
1
2
3
4
8
7
6
5
XOUT
GND
PD#/OE/FS1
XIN/
EXCLKIN
VDD
CLK1
REFOUT/
FS0
CLK2/SSON
[+] Feedback
CY25402/CY25422/CY25482
Document #: 001-12565 Rev. *E Page 5 of 14
General Description
2 Configurable PLLs
The CY25402, CY25422, and CY25482 have two programmable
PLLs that can be used to generate output frequencies ranging
from 3 to 166 MHz. The advantage of having two PLLs is tha t a
single device generates two independent frequencies from a
single crystal.
Input Reference Clocks
The input reference clock can be either a crystal or a clock signal,
for CY25402 and CY25422 while just a clock signal for CY25482.
The input frequency range for crystal (XIN) is 8 MHz to 48 MHz
and that for external reference clock (EXCLKIN) is 8 MHz to 166
MHz. The voltage range of the reference clock input for CY25482
is 2.5 V/3.0 V/3.3 V while that for CY25402 and CY25422 is
1.8 V. Thi s gives user an option for this devi ce to be compatible
for different input clock voltage levels in the system.
VDD Power Supply Options
These devices have programmable power supply options. The
CY25402/CY25482 is a high voltage part that can be
programmed to operate at any voltage 2.5 V , 3.0 V, or 3.3 V while
CY25422 is a low voltage part that can operate at 1.8 V.
Output Source Selection
These devices have programmable input sources for each of its
clock outputs. There are three available clock sources and these
clock sources are: XIN/EXCLKIN, PLL1, and PLL2. Output clock
source selection is done by using three out of three crossbar
switch. Thus, any one of these three available clock sources can
be arbitrarily selected for the clock outputs. This gives user a
flexibility to have two indepen dent clock outputs.
Spread Spectrum Control
Both PLLs (PLL1 and PLL2) have spread spectrum capability for
EMI reduction in the system. The device uses a Cypress
proprietary PLL and spread spectrum clock (SSC) technology to
synthesize and modulate the frequency of th e PLL. The spread
spectrum feature can be turned on or off using a multifunction
control pin (CLK2/SSON). It can be programmed to either center
spread range from ±0.125% to ±2.50% or down spread range
from –0.25% to –5.0% with lexmark or linear profile.
Frequency Select
Each PLL can be programmed for up to four different
frequencies. There are two multifunction programmable pins,
REFOUT/FS0 and PD#/OE/FS1 which if programmed as
frequency select inputs, can be used to select among these
arbitrarily programmed frequency settings. Each output has
programmable output divider options.
Glitch-Free Frequency Switch
When the frequency select pin, FS(1:0) is used to switch
frequency, the outputs are glitch-free provided frequency is
switched using output dividers. This feature enables
uninterrupted system operation while clock frequency is being
switched.
PD#/OE Mode
Multifunction pin PD#/OE/FS1 (Pin 5) can be programmed to
operate as either frequency se lect (FS1), power down (PD#) or
output enable (OE) mode. PD# is a low-true input. If activated it
shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal high brings the
device in the operational mode with default register settings.
When this pin is programmed as Output Enable (OE), clock
outputs can be enabled or disabled using OE (pin 5). Indivi dual
clock outputs can be programmed to be sensitive to this OE pin.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values. Table 4 on page 4 shows the
typical rise and fall times for different drive strength settings.
Generic Configuration and Custom Frequency
There is a generic set of output frequencies available from the
factory that can be used for the device evaluation purposes. The
devices, CY25402, CY25422, and CY25482 can be custom
programmed to any desired frequencies and listed features. For
customer specific programming, please contact local Cypress
field application engineer (FAE) or sales representative.
Table 5. Output Drive Strength
Output Drive Strength Rise/Fall Time (ns)
(Typical Value)
Low 6.8
Mid Low 3.4
Mid High 2.0
High 1.0
[+] Feedback
CY25402/CY25422/CY25482
Document #: 001-12565 Rev. *E Page 6 of 14
Absolute Maximum Conditions
Parameter Description Condition Min Max Unit
VDD Supply voltage for CY25402/CY25482 – –0.5 4.5 V
VDD Supply voltage for CY25422 – –0.5 2.6 V
VIN Input voltage for CY25402/CY25482 Relative to VSS –0.5 VDD+0.5 V
VIN Input voltage for CY25422 Relative to VSS –0.5 2.2 V
TSTemperature, Storage Non Functional –65 +150 °C
ESDHBM ESD protection (human body model) JEDEC EIA/JESD22-A114-E 2000 – V
UL-94 Flammability rating V-0 at1/8 in. – 10 ppm
MSL Moisture sensitivity level SOIC package 3
Recommended Operating Conditions
Parameter Description Min Typ Max Unit
VDD VDD Operating voltage for CY25402/CY25482 2.25 – 3.60 V
VDD VDD Operating voltage for CY25422 1.65 1.8 1.95 V
TAC Commercial ambient temperature 0 – +70 °C
TAI In du strial ambient temperature –40 -- +85 °C
CLOAD Maximum load capacitance – – 15 pF
tPU Power-up time for all VDD to reach minimum specified voltage
(power ramps must be monotonic) 0.05 – 500 ms
[+] Feedback
CY25402/CY25422/CY25482
Document #: 001-12565 Rev. *E Page 7 of 14
DC Electrical Specifications
Parameter Description Conditions Min Typ Max Unit
VOL Output low voltage IOL = 2 mA, drive strength = [00] – – 0.4 V
IOL = 3 mA, drive strength = [01]
IOL = 7 mA, drive strength = [10]
IOL = 12 mA, drive strength = [11]
VOH Output high voltage IOH = –2 mA, drive strength = [00] VDD – 0.4 – – V
IOH = –3 mA, drive strength = [01]
IOH = –7 mA, drive strength = [10]
IOH = –12 mA, drive strength = [11]
VIL1 Input low voltage of PD#/OE, FS0, FS1
and SSON –––0.2*V
DD V
VIL2 Input low voltage of EXCLKIN – – – 0.18 V
VIH1 Input High Voltage of PD#/OE, FS0,
FS1 and SSON –0.8*V
DD ––V
VIH2 Input high voltage of EXCLKIN for
CY25402/CY25422 –1.62–2.2V
VIH3 Input high voltage of EXCLKIN for
CY25482 –0.8*V
DD ––V
IIL Input low current, PD#/OE/FS1 VIN = 0V – – 10 µA
IIH Input high current, PD#/OE/FS1 VIN = VDD ––10µA
IILDN Input low current, SSON and FS0 pins VIN = 0V (Internal pull down resistor
= 160k typ.) ––10µA
IIHDN Input high current, SSON and FS0 pins VIN = VDD (Internal pull down
resistor = 160k typ.) 14 – 36 µA
RDN Pull-down resistor of CLK1,
REFOUT/FS0 and CLK2/SSON pins Output clocks in off state by setting
PD# = Low 100 160 250 k
IDD[1,2] Supply current for CY25422 PD# = High, No load –12–mA
Supply current for CY25402/CY25482 PD# = High, No load –14–mA
IDDS[1] Standby curre nt PD# = Low –3–µA
CIN[2] Input capacitance SSON, PD#/OE/FS1 and FS 0 pins ––7pF
Notes
1. Guaranteed by design but not 100% tested
2. Configuration dependent.
[+] Feedback
CY25402/CY25422/CY25482
Document #: 001-12565 Rev. *E Page 8 of 14
AC Electrical Specifications
Parameter Description Conditions Min Typ Max Unit
FIN (crystal) Crystal Frequency, XIN 8 –48 MHz
FIN (clock) Input Clock Frequency
(EXCLKIN) 8–166 MHz
FCLK Output Clock Frequency 3 –166 MHz
DC Output Duty Cycle, All
Clocks except Ref Out Duty Cycle is defined in Figure 5 on page 9; t1/t2,
measured at 50% of VDD 45 50 55 %
DC Ref Out Duty Cycle Ref In Min 45%, Max 55% 40 – 60 %
TRF1[3] Output Rise /Fall Time Measured from 20% to 80% of VDD, as shown in
Figure 6 on page 9, CLOAD = 15 pF, drive strength [00] –6.8–ns
TRF2[3] Output Rise /Fall Time Measured from 20% to 80% of VDD, as shown in
Figure 6 on page 9, CLOAD = 15 pF, drive strength [01] –3.4–ns
TRF3[3] Output Rise /Fall Time Measured from 20% to 80% of VDD, as shown in
Figure 6 on page 9, CLOAD = 15 pF, drive strength [10] –2.0–ns
TRF4[3] Output Rise /Fall Time Measured from 20% to 80% of VDD, as shown in
Figure 6 on page 9, CLOAD = 15 pF, drive strength [1 1] –1.0–ns
TCCJ[3,4] Cycle-to-cycle Jitter
(peak) Configuration dependent. See Table 5 – 100–ps
TLOCK[4] PLL Lock Time Measured from 90% of the applied power supply level – 1 3 ms
Table 6. Configuration Exam ple for C-C Jitter
Ref. Frequency
(MHz) CLK1 Output CLK2 Output
Freq. (MHz) C-C Jitter Typ (ps) Freq. (MHz) C-C Jitter Typ (ps)
14.3181 8.0 134 48 92
19.2 74.25 99 8 91
27 48 67 166 103
48 48 93 166 137
Recommended Crystal Specification for SMD Package
Parameter Description Range 1 Range 2 Range 3 Unit
Fmin Minimum frequency 8 14 28 MHz
Fmax Maximum frequency 14 28 48 MHz
R1 Motional resistance (ESR) 135 50 30
C0 Shunt capacitance 4 4 2 pF
CL Parallel load capacitance 18 14 12 pF
DL(max) Maximum crystal drive level 300 300 300 µW
Notes
3. Guaranteed by design but not 100% tested
4. Configuration dependent.
[+] Feedback
CY25402/CY25422/CY25482
Document #: 001-12565 Rev. *E Page 9 of 14
Test and Measurement Setup
Figure 4. Test and Measurement Setup
Voltage and Timing Definitions
Figure 5. Duty Cycle Definition
Figure 6. Rise Time = TRF, Fall Time = TRF
Recommended Crystal Specification for Thru-Hole Package
Parameter Description Range 1 Range 2 Range 3 Unit
Fmin Minimum frequency 8 14 24 MHz
Fmax Maximum frequency 14 24 32 MHz
R1 Motional resistance (ESR) 90 50 30
C0 Shunt capacitance 7 7 7 pF
CL Parallel load capacitance 18 12 12 pF
DL(max) Maximum crystal drive level 1000 1000 1000 µW
0.1 F
VDD Outputs
CLOAD
GND
DUT
Clock
Output
V
DD
50% of V
DD
0V
t
1
t
2
Clock
Output
T
RF TRF
V DD
80% of V
DD
20% of V
DD
0V
[+] Feedback
CY25402/CY25422/CY25482
Document #: 001-12565 Rev. *E Page 10 of 14
Possible Configurations
Some product offerings are factory programmed customer specific devices with customized part numbers.The Possible Configurations
table shows the available device types, but not complete part numbers. Contact your local Cypress FAE of Sales Representative for
more information.
Ordering Information
Part Number Type Package Supply Voltage Production Flow
Pb-free
CY25402SXC Field Programmable 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
CY25402SXCT Field Programmable 8-pin SOIC -Tape and reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
CY25422SXC Field Programmable 8-pin SOIC 1.8 V Commercial, 0 °C to 70 °C
CY25422SXCT Field Programmable 8-pin SOIC -Tape and reel 1.8 V Commercial, 0 °C to 70 °C
CY25482SXC Field Programmable 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
CY25482SXCT Field Programmable 8-pin SOIC -Tape and reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
CY25402SXI Field Programmable 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Industrial, -40 °C to +85 °C
CY25402SXIT Field Programmable 8-pin SOIC -Tape and reel 2.5 V, 3.0 V, or 3.3 V Industrial, -40 °C to +85 °C
CY25422SXI Field Programmable 8-pin SOIC 1.8 V Industrial, -40 °C to +85 °C
CY25422SXIT Field Programmable 8-pin SOIC -Tape and reel 1.8 V Industrial, -40 °C to +85 °C
CY25482SXI Field Programmable 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Industrial, -40 °C to +85 °C
CY25482SXIT Field Programmable 8-pin SOIC -Tape and reel 2.5 V, 3.0 V, or 3.3 V Industrial, -40 °C to +85 °C
Programmer
CY3675-CLKMAKER1 Programming kit
CY3675-SOIC8A Socket Adapter Board, for programming CY25402, CY25403, CY25422,
CY25423, CY25482 and CY25483
Part Number[5] Type Package Supply Voltage Production Flow
Pb-free
CY25402SXC-xxx Factory Programmed 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
CY25402SXC-xxxT Factory Programmed 8-pin SOIC -Tape and reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
CY25422SXC-xxx Factory Programmed 8-pin SOIC 1.8 V Commercial, 0 °C to 70 °C
CY25422SXC-xxxT Factory Programmed 8-pin SOIC -Tape and reel 1.8 V Commercial, 0 °C to 70 °C
CY25482SXC-xxx Factory Programmed 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
CY25482SXC-xxxT Factory Programmed 8-pin SOIC -Tape and reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
CY25402SXI-xxx Factory Programmed 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Industrial, -40 °C to +85 °C
CY25402SXI-xxxT Factory Programmed 8-pin SOIC -Tape and reel 2.5 V, 3.0 V, or 3.3 V Industrial, -40 °C to +85 °C
CY25422SXI-xxx Factory Programmed 8-pin SOIC 1.8 V Industrial, -40 °C to +85 °C
CY25422SXI-xxxT Factory Programmed 8-pin SOIC -Tape and reel 1.8 V Industrial, -40 °C to +85 °C
CY25482SXI-xxx Factory Programmed 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Industrial, -40 °C to +85 °C
CY25482SXI-xxxT Factory Programmed 8-pin SOIC -Tape and reel 2.5 V, 3.0 V, or 3.3 V Industrial, -40 °C to +85 °C
Note
5. xxx indicates Factor y Programmable and are fact ory programmed configurati ons. For more details, contact your local Cypress FAE or Cypre ss Sales Representa tive
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CY25402/CY25422/CY25482
Document #: 001-12565 Rev. *E Page 11 of 14
Ordering Code Definitions
Package Drawing and Dimensions
Figure 7. 8-Pin (150-Mil ) SOIC S8
Package Ty pe: (T = Tape and Reel)
Customer specific identification code
Temperature code (C=Comme rcial or I=Industrial)
8-Pin SOIC package
Marketing Code: CY25402/22/82 = Device Number
SX C/I - xxx T
CY254x2
51-85066 *D
[+] Feedback
CY25402/CY25422/CY25482
Document #: 001-12565 Rev. *E Page 12 of 14
Acronyms
Document Conventions
Units of Measure
Acronym Description
DL drive level
DNU do not use
DUT device under test
EMI electromagnetic in terference
ESD electro static discharge
FAE field application engineer
FS frequency select
JEDEC EIA joint electron devices
engineering council electronic
industries alliance
LVCMOS low voltage complemetary
metal oxide semiconductor
OE output enabl e
OSC oscillator
PD power down
PLL phase locked loop
PPM parts per million
SS spread spectrum
SSC spread spectrum cloc k
SSON spread spectrum on
Symbol Unit of Measure
°C degrees Celsius
fF femtofarads
mA milliampere
MHz megahertz
smicroseconds
ms millisecond
Wmicrowatts
ns nanoseconds
pF picofarads
ppm parts per million
ps picoseconds
Vvolts
ohms
Wwatts
[+] Feedback
CY25402/CY25422/CY25482
Document #: 001-12565 Rev. *E Page 13 of 14
Document History Page
Document Title: CY25402/CY25422/CY25482 Two PLL Programmable Clock Generator with Spread Spectrum
Document Number: 00 1-12565
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 690296 See ECN RGL New Data Sheet
*A 815788 See ECN RGL Minor Change: To post on web
*B 1428744 See ECN RGL/AESA Changed data sheet format to match generic part, CY2544/46
Added new device and specification for high ref. input voltage part, CY25482
Removed Preliminary from Title page
Replaced CLK2 with REFOUT
*C 2748211 08/10/09 TSAI Posting to external web.
*D 2898568 06/02/10 KVM Updated the Ordering Information table and package diagram.
Moved ‘xxx’ parts to Possible Configurations t able.
Updated template.
*E 3110175 12/14/2010 BASH Updated as per new tem pl a te
Added Units of Measure table
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Document #: 001-12565 Rev. *E Revised December 14, 2010 Page 14 of 14
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY25402/CY25422/CY25482
© Cypress Semicondu ctor Corpor ation, 2009-2010. The informatio n cont ained herei n is subject to chan ge without no tice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress produc ts are n ot warranted no r int end ed to be us ed fo r
medical, life supp or t, lif e savi n g, critical control o r saf ety ap pli cations, unless pur suan t to a n express written agre em en t w it h Cy press. Fu rth er mor e, Cypre ss does not auth ori ze i t s pr o ducts for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress pr oducts in life-su pport systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (Unit ed States and fore ign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s t o license e a pers onal, no n-excl usive , non-tr ansferab le license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product t o be used only in conju nction with a Cypress
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials describ ed herein. Cyp ress does not
assume any liabil ity arisi ng ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts for use as critical compon ent s in life-suppo rt systems where
a malfuncti on or failure may reasonab ly be expected to resu lt in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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