CD4099BCN - Fairchild Semiconductor

October 1987

Revised April 2002

CD4099BC 8-Bit Addressable Latch

CD4099BC

8-Bit Addressable Latch

General Description

The CD4099BC is an 8-bit addressable latch with three

address inputs (A0–A2), an active low enable input (E),

active high clear input (CL), a data input (D), and eight out-

puts (Q0–Q7).

Data is entered into a particular bit in the latch when that bit

is addressed by the address inputs and the enable (E) is

LOW. Data entry is inhibited when enable (E) is HIGH.

When cle ar (CL) and enable ( E) are HIGH, all outputs are

LOW. When clear (CL) is HIGH and enable (E) is LOW, the

channel demultiplexing occurs. The bit that is addressed

has an active output which follows the data input while all

unaddressed bits are held LOW. When operating in the

addressable latch mode (E = CL = LOW), changing more

than one bit of the addres s coul d impos e a transient w rong

address. Therefore, this should only be done while in the

memory mode (E = HIGH, CL = LOW).

Features

■Wide supply voltage rang e: 3.0V to 15V

■High noise immunity: 0.45 VDD (typ.)

■Low power TTL: fan out of 2 driving 74L

compatibility: or 1 driving 74LS

■Serial to parallel capability

■Storage register capability

■Random (addressable) data entry

■Active high demultiplexing capability

■Common active high clear

Ordering Code:

Connection Diagram

Top View

Truth Table

Order Number Package Number Package Description

CD4099BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Mode Selection

ECL Addressed Unaddressed Mode

Latch Latch

L L Follows Data Holds Previous Data Addressable Latch

H L Holds Previous Data Holds Previous Data Memory

L H Follows Data Reset to “0” Demultiplexer

H H Reset to “0” Reset to “0” Clear

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CD4099BC

Logic Diagram

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CD4099BC

Absolute Maximum Ratings(Note 1)

(Note 2) Recommended Operating

Conditions (Note 2)

Note 1: “Absolute Maximum Ratings” are those va lues beyond which the

safety of th e device ca nnot be guaranteed; th ey are not meant to imply th at

the devices should be operated at these limits. The tables of “Recom-

mended Operating Conditions” and “Electrical Charac t eristics” pro v ide con-

ditions f or actual device o peration.

Note 2: VSS = 0V unles s ot herwise s pecified .

DC Electrical Characteristics (Note 2)

Note 3: IOH and IOL are tes t ed one ou tp ut at a ti m e.

DC Supply Voltage (VDD)−0.5 to +18 VDC

Input Voltage (VIN)−0.5 to VDD +0.5 VDC

Storage Temperature

Range (TS)−65°C to +150°C

Power Dissipation (PD)

Dual-In-Line 700 mW

Small Outline 500 mW

Lead Temperature (TL)

(Soldering, 10 seconds) 260°C

DC Supply Voltage (VDD) 3.0 to 15 VDC

Input Voltage (VIN) 0 to VDD VDC

Operating Temperature Range (TA)−55°C to +125°C

Symbol Parameter Conditions −55°C+25°C+125°CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device VDD = 5V, VIN = VDD or VSS 5.0 0.02 5.0 150 µACurrent VDD = 10V, VIN = VDD or VSS 10 0.02 10 300

VDD = 15V, VIN = VDD or VSS 20 0.02 20 600

VOL LOW Level |IO| ≤ 1µA

Output Voltage VDD = 5V 0.05 0 0.05 0.05 VVDD = 10V 0.05 0 0.05 0.05

VDD = 15V 0.05 0 0.05 0.05

VOH HIGH Level |IO| ≤ 1 µA

Output Voltage VDD = 5V 4.95 4.95 5 4.95 VVDD = 10V 9.95 9.95 10 9.95

VDD = 15V 14.95 14.95 15 14.95

VIL LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 VInput Voltage VDD = 10V, VO = 1.0V or 9.0V 3.0 4.5 3.0 3.0

VDD = 15V, VO = 1.5V or 13.5V 4.0 6.75 4.0 4.0

VIH HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 2.75 3.5 VInput Voltage VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 5.5 7.0

VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 8.25 11.0

IOL LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 mACurrent (Note 3) VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9

VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4

IOH HIG H Level Output VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 mACurrent (Note 3) VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9

VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4

IIN Input Current VDD = 15V, VIN = 0V −0.1 −10−5−0.1 −1.0 µA

VDD = 15V, VIN = 15V 0.1 10−50.1 1.0

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CD4099BC

AC Electrical Characteristics (Note 4)

TA = 25°C, CL = 50 pF, RL = 200k, Input tr = tf = 20 ns, unless otherwise noted

Note 4: AC Parameters are guara nt eed by DC c orrelat ed testing.

Note 5: Dynamic power dissipation (PD) is given by: PD = (CPD + CL) VCC2f + PQ; where CL = load capacitance; f = frequency of o peration; for f urther de t ails,

see ap plication note AN -90, “54C/74C Family Characteristics”.

Symbol Parameter Conditions Min Typ Max Units

tPHL, tPLH Propagation Delay VDD = 5V 200 400 nsData to Output VDD = 10V 75 150

VDD = 15V 50 100

tPLH, tPHL Propagation Delay VDD = 5V 200 400 nsE nable to Output VDD = 10V 80 160

VDD = 15V 60 120

tPHL Propagation Delay VDD = 5V 175 350 nsClear to Output VDD = 10V 80 160

VDD = 15V 65 130

tTLH, tTHL Propagation Delay VDD = 5V 225 450 nsAddress to Output VDD = 10V 100 200

VDD = 15V 75 150

tTHL, tTLH Transition Time VDD = 5V 100 200 ns(Any Output) VDD = 10V 50 100

VDD = 15V 40 80

TWH, TWL Minimum Data VDD = 5V 100 200 nsPulse Width VDD = 10V 50 100

VDD = 15V 40 80

tWH, tWL Minimum Address VDD = 5V 200 400 nsPulse Width VDD = 10V 100 200

VDD = 15V 65 125

tWH Minimum Clear VDD = 5V 75 150 nsPulse Width VDD = 10V 40 75

VDD = 15V 25 50

tSU Minimum Set-Up Time VDD = 5V 40 80 nsData to E VDD = 10V 20 40

VDD = 15V 15 30

tHMinimum Hold Time VDD = 5V 60 120 nsData to E VDD = 10V 30 60

VDD = 15V 25 50

tSU Minimum Set-Up Time VDD = 5V −15 50 nsAddress to E VDD = 10V 0 30

VDD = 15V 0 20

tHMinimum Hold Time VDD = 5V −50 15 nsAddress to E VDD = 10V −20 10

VDD = 15V −15 5

CPD Power Dissipation Capacitance Per Package (Note 5) 100 pF

CIN Input Capacitance Any Input 5.0 7.5 pF

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CD4099BC

Switching Time Waveforms

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CD4099BC 8-Bit Addressable Latch

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N16E

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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