The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2000-2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2012.5
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-chip 1.2 GHz Prescaler
MB15E03SL
■DESCRIPTION
The Fujitsu Semiconductor MB15E03SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with
a 1.2 GHz prescaler. The 1.2 GHz prescaler has a dual modulus division ratio of 64/65 or 128/129 enabling
pulse swallowing operation.
The supply voltage range is between 2.4 V and 3.6 V. The MB15E03SL uses the latest BiCMOS process, as
a result, the supply current is typically 2.0 mA at 2.7 V. A refined charge pump supplies a well balanced output
currents of 1.5 mA or 6 mA. The charge pump current is selectable by serial data.
■FEATURES
• High frequency operation: 1.2 GHz max
• Low power supply voltage: VCC = 2.4 V to 3.6 V
• Ultra Low power supply current:ICC = 2.0 mA typ. (VCC = Vp = 2.7 V, Ta = +25°C, in locking state)
ICC = 2.5 mA typ. (VCC = Vp = 3 V, Ta = +25°C, in locking state)
• Direct power saving function:Power supply current in power saving mode
Typ. 0.1 μA (VCC = Vp = 3 V, Ta = +25°C), Max. 10 μA (VCC = Vp = 3 V)
• Dual modulus prescaler: 64/65 or 128/129
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
• Selectable charge pump current
• On-chip phase control for phase comparator
• Operating temperature: Ta = –40 to +85°C
DS04–21359–6E
MB15E03SL
2DS04–21359–6E
■PIN ASSIGNMENTS
OSCIN
OSCOUT
VP
VCC
DO
GND
Xfin
fin
φR
φP
LD/fout
ZC
PS
LE
Data
Clock
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
TOP
VIEW
LD/fout
ZC
PS
LE
VP
VCC
DO
GND
Xfin fin Clock Data
OSCOUTOSCIN RP
3
2
1
4
5678
9
10
11
12
16 15 14 13
(FPT-16P-M05)
16-pin SSOP
(LCC-16P-M69)
16-pin QFN
MB15E03SL
DS04–21359–6E 3
■PIN DESCRIPTION
Pin No. Pin
Name I/O Descriptions
SSOP QFN
115OSC
IN IProgrammable reference divider input.
Oscillator input connection to a TCXO.
216OSC
OUT O Oscillator output.
31V
P— Power supply voltage input for the charge pump.
42V
CC — Power supply voltage input.
53D
OOCharge pump output.
Phase of the charge pump can be selected via programming of the FC bit.
6 4 GND — Ground.
7 5 Xfin I Prescaler complementary input which should be grounded via a capacitor.
86fin I
Prescaler input.
Connection to an external VCO should be done via AC coupling.
97ClockI
Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock.
(Open is prohibited.)
10 8 Data I Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)
11 9 LE I Load enable signal input. (Open is prohibited.)
When LE is set high, the data in the shift register is transferred to a latch
according to the control bit in the serial data.
12 10 PS I Power saving mode control. This pin must be set at “L” at Power-ON.
(Open is prohibited.)
PS = “H”; Normal mode
PS = “L”; Power saving mode
13 11 ZC I Forced high-impedance control for the charge pump (with internal pull up
resistor.)
ZC = “H”; Normal Do output.
ZC = “L”; Do becomes high impedance.
14 12 LD/fout O Lock detect signal output (LD)/phase comparator monitoring output (fout).
The output signal is selected via programming of the LDS bit.
LDS = “H”; outputs fout (fr/fp monitoring output)
LDS = “L”; outputs LD (“H” at locking, “L” at unlocking.)
15 13 φPO
Phase comparator N-channel open drain output for an external charge
pump. Phase can be selected via programming of the FC bit.
16 14 φRO
Phase comparator CMOS output for an e xternal charge pump. Phase can
be selected via programming of the FC bit.
MB15E03SL
4DS04–21359–6E
■BLOCK DIAGRAM
Clock
Data
fin
LE
OSCOUT
OSCIN Reference
oscillator
circuit
Phase
comparator
Lock
detector
LD/fr/fp
selector
Binary 14-bit
reference
counter
Binary 7-bit
swallow
counter
Binary 11-bit
programmable
counter
14-bit latch 4-bit latch
19-bit shift register
Intermittent mode
control
(power save)
1-bit
cotrol
latch
Prescaler
64 / 65,
128 / 129
7-bit latch
Charge pump
Current switch
11-bit latch
PS
DO
VP
R
LD/fout
P
Xfin
GND
VCC
MD
ZC
C
N
T
SW FC CS
LDS
fr
fp
16
15
14
13
12
11
10
98
7
6
5
4
3
2
1
(15)
(16)
(1)
(2)
(3)
(4)
(5)
(6) (7)
(8)
(9)
(10)
(11)
(12)
(14)
(13)
: SSOP
( ) : QFN
MB15E03SL
DS04–21359–6E 5
■ABSOLUTE MAXIMUM RATINGS
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■RECOMMENDED OPERATING CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Parameter Symbol Condition Rating Unit Remark
Min. Max.
Power supply voltage VCC —–0.54.0 V
VP—VCC 6.0 V
Input voltage VI—–0.5VCC +0.5 V
Output voltage VOExcept Do GND VCC V
VODo GND VPV
Storage temperature Tstg — –55 +125 °C
Parameter Symbol Value Unit Remark
Min. Typ. Max.
Power supply voltage VCC 2.4 3.0 3.6 V
VPVCC —5.5V
Input v oltage VIGND — VCC V
Operating temperature Ta –40 — +85 °C
MB15E03SL
6DS04–21359–6E
■ELECTRICAL CHARACTERISTICS (VCC = 2.4 to 3.6 V, Ta = –40 to +85°C)
(Continued)
Parameter Symbol Condition Value Unit
Min. Typ. Max.
Power supply current*1ICC VCC = VP = 2.7 V
(VCC = VP = 3.0 V) —2.0
(2.5) —mA
Power saving current IPS ZC = “H” or open — 0.1*2 10 μA
Operating frequency fin fin — 100 — 1200 MHz
OSCIN fOSC —3—40MHz
Input sensitivity fin*3 Pfin 50 Ω system
(Refer to the Measurment
circuit.) –15 — +2 dBm
OSCIN*3 VOSC —0.5—VCC Vp-p
“H” level input voltage Data,
Clock,
LE, PS,
ZC
VIH —VCC × 0.7 — — V
“L” level input voltage VIL ———VCC × 0.3
“H” level input current Data,
Clock,
LE, PS
IIH*4 —–1.0—+1.0
μA
“L” level input current IIL*4 —–1.0—+1.0
“H” level input current OSCIN IIH — 0 — +100 μA
“L” level input current IIL*4 —–100—0
“H” level input current ZC IIH*4 —–1.0—+1.0
μA
“L” level input current IIL*4 Pull up input –100 — 0
“L” level output voltage φPV
OL Open drain output — — 0.4 V
“H” level output voltage φR,
LD/fout VOH VCC = VP = 3 V, IOH = –1 mA VCC – 0.4 — — V
“L” level output voltage VOL VCC = VP = 3 V, IOL = 1 mA — — 0.4
“H” level output voltage Do VDOH VCC = VP = 3 V, IDOH = –0.5 mA VP – 0.4 — — V
“L” level output voltage VDOL VCC = VP = 3 V, IDOL = 0.5 mA — — 0.4
High impedance cutoff
current Do IOFF VCC = VP = 3 V,
VOFF = 0.5 V to VP – 0.5 V ——2.5nA
“L” level output current φPI
OL Open drain output 1.0 — — mA
“H” level output current φR,
LD/fout IOH ———–1.0
mA
“L” level output current IOL —1.0——
“H” level output current Do IDOH*4 VCC = 3 V,
VP = 3 V,
VDO = VP/2
Ta = +25°C
CS bit = “H” — –6.0 —
mA
CS bit = “L” — –1.5 —
“L” level output current IDOL CS bit = “H” — 6.0 —
CS bit = “L” — 1.5 —
Charge pump current
rate
IDOL/IDOH IDOMT*5 VDD = VP/2 — 3 — %
vs VDO IDOVD*6 0.5 V ≤ VDO ≤ VP – 0.5 V — 10 — %
vs Ta IDOTA*7 – 40°C ≤ Ta ≤ +85°C—10—%
MB15E03SL
DS04–21359–6E 7
(Continued)
*1: Conditions; fin = 1200 MHz, fosc = 12 MHz, Ta = +25°C, in loc king state.
*2: VCC = VP = 3.0 V, fosc = 12.8 MHz, Ta = +25°C, in power saving mode
*3: AC coupling. 1000 pF capacitor is connected under the condition of min. operating frequency.
*4: The symbol “–” (minus) means direction of current flow.
*5: VCC = VP = 3.0 V, Ta = +25°C (|I3| – |I4|) / [(|I3| + |I4|) /2] × 100(%)
*6: VCC = VP = 3.0 V, Ta = +25°C [(|I2| – |I1|) /2] / [(|I1| + |I2|) /2] × 100(%) (Applied to each IDOL, IDOH)
*7: VCC = VP = 3.0 V, VDO = VP/2 (|IDO(+85°C) – IDO(–40°C)| /2) / (|IDO(+85°C) + IDO(–40°C)| /2) × 100(%) (Applied to each
IDOL, IDOH)
I1
I1
I3I2
I2I4
IDOL
IDOH
0.5 VP/2
Charge Pump Output Voltage (V)
VP
VP − 0.5
MB15E03SL
8DS04–21359–6E
■FUNCTIONAL DESCRIPTION
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(M × N) + A] × fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Output frequency of the reference frequency oscillator
R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
M : Preset divide ratio of the dual modulus prescaler (64 or 128)
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmab le reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE pin is taken high,
stored data is latched according to the control bit data as follows:
Table 1. Control Bit
(1) Shift Register Configuration
Control Bit (CNT) Destination of Serial Data
H For the programmable reference divider
L For the programmable divider
12345678910111213141516171819
CNTR1R2R3R4R5R6R7R8R9R10R11R12R13R14SWFC
LDS CS
Programmable Reference Counter
MSB
Data Flow
CNT : Control bit [Table 1]
R1 to R14 : Divide ratio setting bit for the programmable reference counter (3 to 16,383) [Table 2]
SW : Divide ratio setting bit for the prescaler (64/65 or 128/129) [Table 5]
FC : Phase control bit for the phase comparator [Table 8]
LDS : LD/fout signal select bit [Table 7]
CS : Charge pump current select bit [Table 6]
Note: Start data input with MSB first.
LSB
MB15E03SL
DS04–21359–6E 9
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Note: Divide ratio less than 3 is prohibited.
Table 3. Binary 11-bit Programmable Counter Data Setting
Note: Divide ratio less than 3 is prohibited.
Table 4. Binary 7-bit Swallow Counter Data Setting
Divide ratio
(R) R14R13R12R11R10R9R8R7R6R5R4R3R2R1
3 0 0 0 0 0000000011
4 0 0 0 0 0000000100
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅⋅⋅⋅⋅⋅⋅⋅⋅
16383 1 1 1 1 1 111111111
Divide ratio
(N) N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1
3 00000000011
4 00000000100
⋅ ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅
2047 1 1 1 1 1 1 1 1 1 1 1
Divide ratio
(A) A7 A6 A5 A4 A3 A2 A1
0 0000000
1 0000001
⋅ ⋅⋅⋅⋅⋅⋅⋅
127 1111111
12345678910111213141516171819
CNTA1A2A3A4A5A6A7N1N2N3N4N5N6N7N8N9N10N11
Programmable Counter
LSB MSB
Data Flow
CNT : Control bit [Table 1]
N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047) [Table 3]
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127) [Table 4]
Note: Start data input with MSB first.
MB15E03SL
10 DS04–21359–6E
Table 5. Prescaler Data Setting
Table 6. Charge Pump Current Setting
Table 7. LD/fout Output Select Data Setting
(2) Relation between the FC Input and Phase Characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output
le vel (DO) and the phase comparator output (φR, φP) are re versed according to the FC bit. Also , the monitor pin
(fout) output is controlled by the FC bit. The relationship between the FC bit and each of DO, φR, and φP is
shown below.
Table 8. FC Bit Data Setting (LDS = “H”)
* : High impedance
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
SW Prescaler Divide Ratio
H 64/65
L 128/129
CS Current Value
H±6.0 mA
L±1.5 mA
LDS LD/fOUT Output Signal
H fout signal
L LD signal
FC = High FC = Low
DOφRφP LD/fout DOφRφPLD/fout
fr > fp H L L
fout = fr
LHZ*
fout = fpfr < fp L H Z* H L L
fr = fp Z* L Z* Z* L Z*
(1)
VCO
Output
Frequency
LPF Output Voltage
(2)
MB15E03SL
DS04–21359–6E 11
3. Do Output Control
Table 9. ZC Pin Setting
ZC pin Do output
H Normal output
L High impedance
MB15E03SL
12 DS04–21359–6E
4. Power Saving Mode (Intermittent Mode Control Circuit)
Table 10. PS Pin Setting
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption.
See the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the signal PLL, the lock detector, LD, remains high, indicating a locked condition.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because
of the unknown relationship between the comparison frequency (fp) and the ref erence frequency (fr) which can
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in loc kup
time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
Notes: •When pow er (VCC) is first applied, the device must be in standb y mode , PS = Lo w, f or at least 1 μs.
•PS pin must be set “L” for Power-ON.
PS pin Status
HNormal mode
L Power saving mode
ONOFF
VCC
Clock
Data
LE
PS
(1) (2) (3)
tV ≥ 1 μs
tPS ≥ 100 ns
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1 μs later after power supply remains stable (VCC > 2.2 V).
(3) Release power saving mode (PS: “L” → “H”) 100 ns later after setting serial data.
MB15E03SL
DS04–21359–6E 13
■SERIAL DATA INPUT TIMING
Data
Clock
LE
MSB LSB
Control bit Invalid data
2nd data1st data
t1t2t3
t6
t5t4
t7
∼
∼
∼
∼
Note: LE should be “L” when the data is transferred into the shift register.
Parameter Min. Typ. Max. Unit
t1 20 — — ns
t2 20 — — ns
t3 30 — — ns
t4 30 — — ns
Parameter Min. Typ. Max. Unit
t5 100 — — ns
t6 20 — — ns
t7 100 — — ns
On the rising edge of the clock, one bit of data is transferred into the shift register .
MB15E03SL
14 DS04–21359–6E
■PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
LD
DO
H
L
L
H
DO
tWU tWL
Z
Z
Notes:•Phase error detection range: –2π to +2π
•Pulses on Do output signal during locked state are output to prevent dead zone.
•LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL
or less and continues to be so for three cycles or more.
•tWU and tWL depend on OSCIN input frequency.
tWU > 2/fosc (s) (e. g. tWU > 156.3 ns, fosc = 12.8 MHz)
tWU < 4/fosc (s) (e. g. tWL < 312.5 ns, fosc = 12.8 MHz)
•LD becomes high during the power saving mode (PS = “L”).
[FC = “H”]
[FC = “L”]
MB15E03SL
DS04–21359–6E 15
■MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
S.G.
50
1000 pF S.G.
50
1000 pF
0.1 F
0.1 F
86431
9101112 14
75 2
13 15 16
1000 pF
VCC
fin Xfin GND DOVCC VPOSCOUT OSCIN
Clock
Controller
(setting divide ratio) Oscilloscope
Data LE PS ZC LD/fout PR
Note : SSOP-16
MB15E03SL
16 DS04–21359–6E
■TYPICAL CHARACTERISTICS
1. fin input sensitivity
2. OSCIN input sensitivity
10
0
0 500 1000 1500 2000
-10
-20
-30
-40
-50
Ta = +25 °C
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
Input sensitivity - Input frequency (Prescaler 64/65)
Input frequency fin (MHz)
Input sensitivity Pfin (dBm)
SPEC
V
CC
= 2.4 V
V
CC
= 3.0 V
V
CC
= 3.6 V
0 50 100
Ta = +25 °C
Input sensitivity - Input frequency
Input frequency f
OSC
(MHz)
10
0
-10
-20
-30
-40
-50
-60
Input sensitivity V
OSC
(dBm)
SPEC
MB15E03SL
DS04–21359–6E 17
3. Do output current
10.00
I
OH
I
OL
2.000
/div
0
0 4.800
.6000/div
− 10.00
VDO
− IDO
Charge pump output voltage VDO
(V)
Charge pump output current I
DO
(mA)
Ta = +25 °C
V
CC
= 3.0 V
V
P
= 3.0 V
4.800
− 10.00
VDO
− IDO
Charge pump output voltage VDO
(V)
Charge pump output current I
DO
(mA)
10.00
I
OH
I
OL
2.000
/div
0
0.6000/div
Ta = +25 °C
V
CC
= 3.0 V
VP = 3.0 V
1.5 mA mode
6.0 mA mode
MB15E03SL
18 DS04–21359–6E
4. fin input impedance
5. OSCIN input impedance
297.63 Ω
−656.53 Ω
100 MHz
24.523 Ω
−185.55 Ω
400 MHz
9.3789 Ω
−77.168 Ω
800 MHz
10.188 Ω
−33.143 Ω
1.2 GHz
1 :
2 :
3 :
4 :
4
3
2
START 100.000 000 MHz STOP 1 200.000 000 MHz
1
9.063 kΩ
−3.113 kΩ
3 MHz
3.8225 Ω
−4.6557 kΩ
10 MHz
1.5735 Ω
−3.2154 kΩ
20 MHz
405.69 Ω
−1.8251 kΩ
40 MHz
1 :
2 :
3 :
4 :
3
1
START 3.000 000 MHz STOP 40.000 000 MHz
4
3
MB15E03SL
DS04–21359–6E 19
■REFERENCE INFORMATION
(Continued)
S.G. OSC
IN
fin
VCO
D
O
LPF
Spectrum
Analyzer
f
VCO
= 810.425 MHz
K
V
= 17 MHz/V
fr = 25 kHz
f
OSC
= 14.4 MHz
exp current: 6.0 mA
4.2 kΩ
47000 pF
9.1 kΩ
4700 pF 1500 pF
VCODo
•LPF
MB15E03SL
20 DS04–21359–6E
(Continued)
ATTEN
CENTER SPAN 20.00 kHz810.42500 MHz
RBW 100 Hz ** SWPVBW 100 Hz 3.00 s
ΔMKR − 53.00 dB10 dB
RL 2.23 kHz− 5.0 dBm
73.0 dBc/Hz
ATTEN
CENTER SPAN 200.0 kHz810.42500 MHz
RBW 1.0 kHz SWPVBW 1.0 kHz 1.00 s
ΔMKR − 79.83 dB10 dB
RL 25.0 kHz− 5.0 dBm
79.8 dBc
**
Ta = +25°C
• PLL Reference Leakage
• PLL Phase Noise
Ta = +25°C
MB15E03SL
DS04–21359–6E 21
(Continued)
830.00500
MHz
2.00
KHz/div
829.99500
MHz
5.0000000 ms
830.00500
MHz
2.00
KHz/div
829.99500
MHz
5.0000000 ms
850.00500
MHz
10.00000
Hz/div
810.00000
MHz
5.0000000 ms
860.00000
MHz
10.00000
Hz/div
810.00000
MHz
5.0000000 ms
PLL Lock Up Time
810.425 MHz → 826.425±1 kHz
Lch → Hch 1.40 ms
PLL Lock Up Time
826.425 MHz → 810.425±1 kHz
Hch → Lch 1.52 ms
MB15E03SL
22 DS04–21359–6E
■ APPLICATION EXAMPLE
■USAGE PRECAUTIONS
To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting device into or removing device from a socket.
-Protect leads with a conductive sheet when transporting a board-mounted device.
10 kΩ
0.1 μF
1000 pF
Output
V
P
12 kΩ
12 kΩ
10 kΩ
LPF VCO
16 15 13 12 11 10 9
123 4 56 78
0.1 μF1000 pF
Lock detect.
MB15E03SL
From
a controller
φRφPLD/fout ZC Clock
PS LE Data
OSC
IN
OSC
OUT
V
P
V
CC
D
O
GND Xfin fin
TCXO
1000 pF
14
VP: 5.5 V Max
Notes: • In case of using a crystal resonator , it is necessary to optimize matching between the crystal and
this LSI, and perf orm detailed system e valuation. It is recommended to consult with a supplier of
the crystal resonator. (Reference oscillator circuit provides its own bias, feedback resistor is
100 kΩ (typ).)
• SSOP-16
MB15E03SL
DS04–21359–6E 23
■ORDERING INFORMATION
Part number Package Remarks
MB15E03SLPFV1 16-pin, Plastic SSOP
(FPT-16P-M05)
MB15E03SLWQN 16-pin, Plastic QFN
(LCC-16P-M69)
MB15E03SL
24 DS04–21359–6E
■PACKAGE DIMENSIONS
16-pin plastic SSOP Lead pitch 0.65 mm
Package width
×
package length
4.40 × 5.00 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.45mm MAX
Weight 0.07g
Code
(Reference) P-SSOP16-4.4×5.0-0.65
16-pin plastic SSOP
(FPT-16P-M05)
(FPT-16P-M05)
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F16013S-c-4-8
5.00±0.10(.197±.004)
4.40±0.10 6.40±0.20
(.252±.008)(.173±.004)
.049–.004
+.008
–0.10
+0.20
1.25 (Mounting height)
0.10(.004)
0.65(.026) 0.24±0.08
(.009±.003)
1 8
16 9
"A"
0.10±0.10 (Stand off)
0.17±0.03
(.007±.001)
M
0.13(.005)
(.004±.004)
Details of "A" part
0~8°
(.024±.006)
0.60±0.15
(.020±.008)
0.50±0.20
0.25(.010)
LEAD No.
INDEX
*1
*2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
MB15E03SL
DS04–21359–6E 25
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
16-pin plastic QFN Lead pitch 0.50 mm
Package width ×
package length 4.00 mm × 4.00 mm
Sealing method Plastic mold
Mounting height 0.80 mm MAX
Weight 0.04 g
16-pin plastic QFN
(LCC-16P-M69)
(LCC-16P-M69)
+0.03
–0.02
–.001
+.001
0.02
(.001 )
C
2010 FUJITSU SEMICONDUCTOR LIMITED HMbC16-69Sc-1-1
INDEX AREA
(.157±.004)
4.00±0.10
4.00±0.10
(.157±.004)
2.60±0.10
0.50(.020)
TYP
(.016±.002)
0.40±0.05
1PIN CORNER
(C0.35 (C.014))
0.25±0.05
(.010±.002)
(.030±.002)
0.75±0.05
(0.20(.008))
(.102±.004)
2.60±0.10
(.102±.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB15E03SL
26 DS04–21359–6E
MEMO
MB15E03SL
DS04–21359–6E 27
MEMO
MB15E03SL
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://sg.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District,
Shanghai 201204, China
Tel : +86-21-6146-3688 Fax : +86-21-6146-3660
http://cn.fujitsu.com/fss/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre , 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris-
ing in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-
current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
Mouser Electronics
Authorized Distributor
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