LTC4419 18V Dual Input Micropower PowerPath Prioritizer FEATURES DESCRIPTION Selects Highest Priority Valid Supply from Two Inputs nn Wide 1.8V to 18V Operating Range nn Internal Dual 2, 0.5A Switches nn Low 3.6A Operating Current nn Low 320nA V2 Current When V1 Connected to OUT nn Blocks Reverse and Cross Conduction Currents nn Reverse Supply Protection to -15V nn V2 Freshness Seal/Ship Mode nn 1.5% Accurate Adjustable Switchover Threshold nn Two Auxiliary 2.3% Accurate Voltage Comparators nn Overcurrent and Thermal Protection nn Thermally Enhanced 10-Pin 3mm x 3mm DFN and 12-Lead Exposed Pad MSOP Packages The LTC(R)4419 is a dual input monolithic PowerPathTM prioritizer with low operating current, that provides backup switchover for keeping critical circuitry alive during brown out and power loss conditions. Unlike diode-OR products, little current is drawn from the inactive supply even if its voltage is greater than the active supply. nn APPLICATIONS Low Power Battery Backup Portable Equipment nn Point-of-Sale (POS) Equipment nn Internal 2, current limited PMOS switches provide power path selection from a primary input (V1) or a backup input (V2) to the output. An adjustable voltage monitor set via an external resistive divider provides flexibility in setting the V1 to V2 switchover threshold. When primary input V1 drops, the ADJ monitor input causes OUT to be switched to V2. Fast non-overlap switchover circuitry prevents both reverse and cross conduction while minimizing output droop. The LTC4419 has two auxiliary comparators with opendrain outputs that provide flexible voltage monitoring. The V2ON output indicates if V2 is powering OUT. Freshness seal mode prevents V2 battery discharge during storage or shipment. nn L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PowerPath and ThinSOT are trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Typical Switchover Waveforms 5V WALL ADAPTER C1 10F V1 OUT 1M OUT 1M 1M ADJ CMPOUT1 V1UV CMP1 CMPOUT2 V2UV 237k 121k + 7.4V Li-Ion LTC4419 V2 V2ON V2ON SWITCHOVER THRESHOLD: V1 < 4V (V1 FALLING) V1UV THRESHOLD: V1 < 4.4V (V1 FALLING) V2UV THRESHOLD: V2 < 6V (V2 FALLING) 4.02M CMP2 280k V2 2V/DIV V1 2V/DIV GND OUT COUT = 10F ILOAD = 100mA SWITCHOVER THRESHOLD 50s/DIV 4419 TA01b 4419 TA01a 4419fa For more information www.linear.com/LTC4419 1 LTC4419 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Input Supply Voltage V1, V2.......................................................-15V to 24V OUT........................................................ -0.3V to 24V OUT - V2..................................................-24V to 39V OUT - V1..................................................-24V to 39V Input Voltages ADJ, CMP1, CMP2 (Note 3) ................... -0.3V to 24V Output Voltages CMPOUT1, CMPOUT2, V2ON (Note 3) ... -0.3V to 24V Pin Currents (Note 2) ADJ, CMP1, CMP2, CMPOUT1, CMPOUT2, V2ON..................................................................-1mA Operating Ambient Temperature Range LTC4419C................................................. 0C to 70C LTC4419I..............................................-40C to 85C Junction Temperature (Notes 4, 5)......................... 125C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec) MSOP Package.................................................. 300C PIN CONFIGURATION TOP VIEW TOP VIEW V1 1 10 V2 CMP1 2 9 CMP2 ADJ 3 GND 4 CMPOUT1 5 11 GND 8 OUT 7 V2ON 6 CMPOUT2 1 2 3 4 5 6 13 GND 12 11 10 9 8 7 V2 NC CMP2 OUT V2ON CMPOUT2 MSE PACKAGE 12-LEAD PLASTIC MSOP DD PACKAGE 10-LEAD (3mm x 3mm) PLASTIC DFN TJMAX = 125C, JA = 43C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION V1 NC CMP1 ADJ GND CMPOUT1 TJMAX = 125C, JA = 40C/W EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB http://www.linear.com/product/LTC4419#orderinfo LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4419CDD#PBF LTC4419CDD#TRPBF LGMS 10-Lead (3mm x 3mm) Plastic DFN 0C to 70C LTC4419IDD#PBF LTC4419IDD#TRPBF LGMS 10-Lead (3mm x 3mm) Plastic DFN -40C to 85C LTC4419CMSE#PBF LTC4419CMSE#TRPBF 4419 12-Lead Plastic Exposed Pad MSOP 0C to 70C LTC4419IMSE#PBF LTC4419IMSE#TRPBF 4419 12-Lead Plastic Exposed Pad MSOP -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 4419fa For more information www.linear.com/LTC4419 LTC4419 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V1 = 3.6V, V2 = 3.6V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Voltage and Currents 18 V 3.6 500 6.3 800 A nA 3.3 320 120 6 650 220 A nA nA 1 2 5 l 34 64 94 ms 1.032 1.047 1.062 V1, V2 Operating Voltage Range IV1 V1 Current, V1 Powering OUT V1 Current, V2 Powering OUT IOUT = 0, V1 = 8.4V, V2 = 3.6V V1 = 8.4V, V2 = 3.6V l l IV2 V2 Current, V2 Powering OUT V2 Current, V1 Powering OUT V2 Current in Freshness Seal Mode IOUT = 0, V1 = 3.6V, V2 = 8.4V V1 = 3.6V, V2 = 8.4V V1 = GND, V2 = 5V l l l RON Switch Resistance V1 = V2 = 5V, IOUT = -100mA l tVALID(V1) Input Qualification Time V1 Rising, ADJ Rising l 1.8 Input Comparators VTHA ADJ Threshold ADJ Falling l V VHYSTA ADJ Comparator Hysteresis ADJ Rising l 30 50 70 VTHC CMP1, CMP2 Threshold CMP1, CMP2 Falling l 0.378 0.387 0.396 V VHYSTC CMP1, CMP2 Hysteresis CMP1, CMP2 Rising l 7.5 10 12.5 mV tPDA ADJ Comparator Falling Response Time 10% Overdrive l 4 7.3 12 s tPDC CMP1, CMP2 Comparator Response Times 20% Overdrive l 30 65 s mV Power Path Function ILIM Output Current Limit V1, V2 = 8.4V l 0.5 1.1 1.6 A VREV Reverse Comparator Threshold (V1, V2) - VOUT for Power Path Turn-On l 25 50 75 mV tSWITCH Break-Before-Make Switchover Time V1 = V2 = 5V, IOUT = -100mA l 1 2.5 5 s 15 120 50 250 mV mV 1.65 2.3 V 50 150 nA I/O Specifications VOL Output Voltage Low, CMPOUT1, CMPOUT2 and V2ON I = 100A I = 1mA l l VOH V2ON Output High Voltage I = -1A, V2 = 5V l IOH CMPOUT1, CMPOUT2 and V2ON, Output High Leakage CMPOUT1, CMPOUT2, V2ON = 18V l IPU(V2ON) V2ON Pull-Up Current V2 = 5V, ADJ = 0V, V2ON = 0V l ILEAK ADJ, CMP1, CMP2 Leakage Current ADJ, CMP1, CMP2 = 0V, 1.5V l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive; all voltages are referenced to GND unless otherwise noted. Note 3: These pins can be tied to voltages down to -5V through a resistor that limits the current to less than -1mA. 1.05 -2.7 -5 -8 A 1 5 nA Note 4: The LTC4419 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: The LTC4419 is tested under pulsed load conditions such that TJ TA. The junction temperature (TJ in C) is calculated from the ambient temperature (TA in C) and power dissipation (PD in Watts) according to the formula: TJ = TA + (PD * JA) 4419fa For more information www.linear.com/LTC4419 3 LTC4419 TYPICAL PERFORMANCE CHARACTERISTICS 4.5 V1 Current, V1 Powers OUT (IOUT = 0) 4.0 V1 = 1.8V V1 = 3.6V V1 6V (TA = 25C, V1 = V2 = 3.6V unless otherwise indicated). V2 Current, V2 Powers OUT (IOUT = 0) V2 Current, V1 Powers OUT 450 V2 = 1.8V V2 = 3.6V V2 6V V1 = V2 400 3.5 350 V2 CURRENT (nA) 3.5 V2 CURRENT (A) V1 CURRENT (A) 4.0 3.0 300 250 3.0 -40C 25C 85C 200 2.5 -50 -25 0 25 50 75 TEMPERATURE (C) 100 2.5 -50 125 -25 0 25 50 75 TEMPERATURE (C) 4419 G01 200 450 150 350 300 5 10 15 V2 VOLTAGE (V) Open-Drain (CMPOUT1, CMPOUT2, V2ON) VOL vs Pull-Down Current 5 10 15 V2 VOLTAGE (V) 20 1.010 1.000 0.995 50 0 0.0 20 Normalized CMP1 and CMP2 Falling Thresholds vs Temperature 1.005 100 -40C 25C 85C 0 0 4419 G03 NORMALIZED VTHC 500 VOL (mV) V1 CURRENT (nA) 250 V1 = V2 400 150 125 4419 G02 V1 Current, V2 Powers OUT 550 100 0.5 1.0 1.5 PULL-DOWN CURRENT (mA) 4419 G04 2 0.990 -50 -25 0 25 50 75 TEMPERATURE (C) 100 4419 G05 Normalized Falling ADJ Threshold vs Temperature 4419 G06 ADJ Hysteresis vs Temperature 1.010 125 ADJ Leakage vs Temperature 70 3.0 VADJ = 0V, 1.5V 1.000 0.995 0.990 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 4419 G07 4 60 ADJ LEAKAGE (nA) ADJ HYSTERESIS (mV) NORMALIZED VTHA 1.005 2.5 50 40 30 -50 2.0 1.5 1.0 -25 0 25 50 75 TEMPERATURE (C) 100 125 4419 G08 0.5 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 4419 G09 4419fa For more information www.linear.com/LTC4419 LTC4419 TYPICAL PERFORMANCE CHARACTERISTICS Output Current Limit vs Temperature Output Current IOUT Response for Different Shorting Impedances IOUT vs VOUT for Different Input Supply Voltages 3.0 2.5 1.20 2.0 IOUT (A) 1.30 1.10 1.2 1.2 2.2 3.3 3.9 5.0 1.5 1.0 0.4 0.90 0.5 0.2 0 0 0 25 50 75 TEMPERATURE (C) 100 125 250 5V 3.6V 2V 1.8V 3.6V 5V 6V V2 CURRENT (nA) 200 3 5 4419 G12 V1 = 0V 100 50 -25 0 25 50 75 TEMPERATURE (C) 100 0 -50 125 -25 0 25 50 TEMPERATURE (C) 75 4419 G13 Switchover from a Higher to a Lower Voltage OUT 2V/DIV 4 150 2 V2 100 4419 G14 Output Voltage and Current Waveforms During Switchover COUT = 10F IOUT = 200mA V1 2 3 VOUT (V) Freshness Seal Current vs V2 Voltage and Temperature 5 RON () 1 4419 G11 Switch RON vs Temperature 1 -50 0 40s/DIV 4419 G10 4 OHMIC 0.6 1.0 -25 CURRENT LIMIT 0.8 1.00 0.80 -50 VIN = 1.8V VIN = 3.6V VIN = 5V FOLDBACK IOUT (A) 1.40 CURRENT LIMIT (A) (TA = 25C, V1 = V2 = 3.6V unless otherwise indicated). V1 Reverse Voltage Blocking with V2 Powering OUT V2 5V/DIV 10V 6V 10V DISCONNECT FROM V1 V2 6V OUT COUT = 10F C1 = C2 = 10F ILOAD = 50mA IOUT 0.5A/DIV CONNECT TO V2 3ms/DIV V1 2V/DIV 4419 G15 10s/DIV 4419 G16 V1 10V/DIV -10V IOUT 0.5A/DIV ILOAD = 50mA 20ms/DIV 4419 G17 4419fa For more information www.linear.com/LTC4419 5 LTC4419 PIN FUNCTIONS ADJ: Adjustable V1 Switchover Threshold Input. ADJ is the noninverting input to the switchover threshold comparator. If V1 1.55V and ADJ 1.097V for at least 64ms, OUT is switched internally to the primary V1 input. When the ADJ input voltage is lower than 1.047V, OUT is switched internally to V2, if V2 1.55V. Otherwise, OUT stays unpowered. Tie ADJ via a resistive divider to V1 to set the V1 to V2 switchover voltage. Do not leave open. CMP1: Auxiliary Comparator 1 Monitor Input. CMP1 is the noninverting input to an auxiliary comparator. The inverting input is internally connected to a 0.387V reference. Connect CMP1 to GND when it is not used. CMP2: Auxiliary Comparator 2 Monitor Input. CMP2 is the noninverting input to a second auxiliary comparator. The inverting input is internally connected to a 0.387V reference. Connect CMP2 to GND when it is not used. CMPOUT1: Auxiliary Comparator 1 Output. This open-drain comparator output is pulled low when CMP1 is below 0.387V and during power-up, otherwise it is released. Once released, connecting a resistor between CMPOUT1 and a desired supply voltage up to 18V causes this pin to be pulled high. Leave open if unused. CMPOUT2: Auxiliary Comparator 2 Output. This open-drain comparator output is pulled low when CMP2 is below 0.387V and during power-up, otherwise it is released. Once released, connecting a resistor between CMPOUT1 and a desired supply voltage up to 18V causes this pin to be pulled high. Leave open if unused. 6 Exposed Pad: The exposed pad is ground and must be soldered to the PCB ground plane. GND: Device Ground. NC: No Connection. Not internally connected. OUT: Output Voltage Supply. OUT is a prioritized voltage output that is either connected to V1, V2 or is unpowered as indicated in Table 1 of the Applications Information section. Additionally, OUT must be at least 50mV below the input supply for a connection to that supply to be activated. Bypass with a capacitor of 1F or greater. See Applications Information section for bypass capacitor recommendations. V1: Primary Power Supply. OUT is internally switched to V1 if V1 1.55V and ADJ 1.097V. When in freshness seal mode, applying V1 1.55V and ADJ 1.097V for 32ms disables freshness seal. Bypass with 1F or greater. Tie to GND if unused. V2: Backup Power Supply. V2 is valid if its voltage is 1.55V. OUT is internally switched to V2 if ADJ < 1.047V or V1 < 1.55V, provided V2 is valid. Refer to Table 1 of the Applications Information section. Bypass with 1F or greater. Tie to GND if unused. V2ON: V2 Connected Status. V2ON is an output that is driven high with a 5A pull-up when the V2 to OUT power path is active. Otherwise it is driven low. Connect a resistor between OUT or V2 and this pin to provide additional pull-up. As this pin is used to enable freshness seal, do not force low or connect a pull-down resistor to this pin. Leave open if unused. 4419fa For more information www.linear.com/LTC4419 LTC4419 FUNCTIONAL DIAGRAM CMPOUT1 + - CP1 CMP1 0.397V/ 0.387V + - CP2 CMP2 0.397V/ 0.387V CMPOUT2 V1 OUT V2 EN1 OUT +- - + EN2 CREV1 50mV - + 50mV +- OUT 1.55V/ 1.52V - + 2.5V CUV1 - + CUV2 CREV2 CONTROL LOGIC 1.55V/ 1.52V FRESHNESS SEAL ADJ 1.097V/ 1.047V 5A V2ON GND - + CADJ 64ms 7.3s 4419 FD 4419fa For more information www.linear.com/LTC4419 7 LTC4419 OPERATION The Functional Diagram shows the major blocks of the LTC4419. The LTC4419 is a PowerPath prioritizer that switches output OUT between primary (V1) and backup (V2) sources depending on their validity and priority with V1 having the highest priority. If neither supply is valid, OUT stays unpowered. A resistive divider between V1, ADJ and GND and comparators CUV1 and CADJ are used to monitor V1's voltage to establish validity. V1 is valid if V1 1.55V and ADJ 1.097V for 64ms after V1 rises above 1.55V. Otherwise V1 is invalid. V2 is valid if its voltage as monitored by comparator CUV2 is 1.55V. Otherwise, it is invalid. Switchover threshold is independent of relative V1 and V2 voltages, permitting V1 to be lower or higher than V2 when V1 powers OUT and vice versa. Power connection to the output is made by enhancing backto-back internal P-channel MOSFETs. Current passed by the MOSFETs is limited to typically 1.1A if OUT is greater than 1V. Otherwise it is limited to 250mA. When switching from V1 to V2, the V1 to OUT power path is first disabled and comparator CREV2 is enabled. After the OUT voltage drops 50mV below V2, as detected by CREV2, OUT is then connected to V2. V2ON pulls high after switchover. 8 This break-before-make strategy prevents OUT from backfeeding V2. Switchover back to V1 occurs in a similar manner once V1 has been revalidated. V2ON pulls low if the V2 power path is disabled and during initial power-up when V1 or V2 is first applied. The LTC4419 blocks reverse voltages up to -15V when a reverse condition occurs on an inactive channel. The LTC4419 also disables a channel if the corresponding input supply falls below 1.52V. A small ~3A current is drawn from either the prioritized input supply or the highest input supply if both input supplies are below 1.55V. Very little current (~320nA) is drawn from the unused supply. The LTC4419 provides two additional comparators, CP1 and CP2, whose open-drain outputs pull low when CMP1 and CMP2 pin voltages fall below 0.387V and during initial power-up. These comparators can be used to monitor supplies to provide early power failure warning and other useful information. The LTC4419 can be put into a V2 freshness seal mode to prevent battery discharge during storage or shipment. The Applications Information section lists the steps to engage and disengage V2 freshness seal. 4419fa For more information www.linear.com/LTC4419 LTC4419 APPLICATIONS INFORMATION The LTC4419 is a low quiescent current 2-channel prioritizer that powers both its internal circuitry and its output OUT from a prioritized valid input supply. Unlike an ideal diode-OR, the LTC4419 does not draw current from the highest supply as long as any one supply is greater than 1.8V. Table 1 lists the input supply from which the LTC4419 draws its internal quiescent current ICC and the supply to which OUT is connected after input supplies have been qualified. Table 1. OUT and LTC4419 ICC Power Table INPUT VOLTAGES V1 > 1.55V OUT ADJ > 1.097V V2 > 1.55V CONNECTION ICC SOURCE Y Y X N Y V2 V2 Y N N Hi-Z V1 N X Y V2 V2 N X N Hi-Z VMAX* X V1 V1 Note: X = Don't Care. *VMAX = Higher of V1 and V2. For 64ms. A typical battery backup application is shown in Figure 1. V1 is powered by a 2-cell Li-ion battery pack whose safe discharge limit is between 5.6V and 6V. V2 is powered by a 9V alkaline hold-up battery which is completely discharged when its voltage drops to 6V. In order to protect the 2-cell Li-ion battery on V1, switchover threshold is set to ~5.6V. After switchover to V2, the Li-ion battery primarily supplies only divider R1-R3's current, as the LTC4419 draws only a small standby current from V1. Monitor inputs CMP1 and CMP2 are configured to provide V1 and V2 undervoltage + 2-CELL 7.4V Li-Ion C1 4.7F R3 1M R2 150k R1 78.7k + 9V ALKALINE C2 4.7F R5 4.02M R4 280k V1 OUT ADJ OUT R6 1M COUT 10F R7 1M CMPOUT2 V2UV CMP1 CMPOUT1 LTC4419 V1UV SWITCHOVER THRESHOLD: V1< 5.6V (V1 FALLING) V1UV: V1 < 6V (V1 FALLING) V2UV: V2 < 6V (V2 FALLING) V2 CMP2 GND 4419 F01 warnings. Outputs V1UV and V2UV are driven low when V1 and V2 voltages fall below 6V. Relevant equations used to calculate these component values are discussed in the following subsections. Setting the Switchover Threshold Several factors affect switchover voltage and should be taken into account when calculating resistor values. These include resistor tolerance, 1.5% ADJ comparator threshold error, divider impedance and worst-case ADJ pin leakage. These factors also apply to resistive dividers connected to monitor inputs CMP1 and CMP2. Referring to Figure 1 and the Electrical Characteristics table, the typical V1 switchover threshold is: VSW1 = VTHA * (R1+R2+R3) R1+R2 (1) Typical V1 undervoltage threshold is: VV1UV = VTHC * (R1+R2+R3) R1 (2) and typical V2 undervoltage threshold is: VV2UV = VTHC * (R4+R5) R4 (3) Equations 1-3 assume ADJ and CMP pin leakages are negligible. To account for pin leakage, equations 1-3 must be modified by an ILEAK * REQ term, where equivalent resistance, REQ, must be calculated on a case-by-case basis. Worst-case component values and reference voltage tolerances must be used to calculate the maximum and minimum threshold voltages. For example, to calculate minimum falling switchover threshold voltage, VSW1(MIN), use VTHA(MIN), (R2 + R1)(MAX), and R3(MIN) in equation 1. Selecting Output Capacitor, COUT COUT can be selected to control either output voltage droop during switchover or output rising slew rate during initial power-up or when switching to a higher supply. In general, output droop, VOUT, can be calculated by: Figure 1. The LTC4419 Protecting a 2-Cell Li-Ion Battery Pack on V1 from Discharge Below Its Safe Minimum Voltage VOUT = tNOV *IOUT COUT (4) 4419fa For more information www.linear.com/LTC4419 9 LTC4419 APPLICATIONS INFORMATION t *I COUT NOV OUT VOUT (5) limits output droop to less than VOUT. In order to estimate tNOV and IOUT, first consider a scenario where power supplies are present on both V1 and V2, and their voltages are changing slowly compared to the ADJ comparator propagation delay tPDA. In such cases, IOUT is ILOAD and tNOV is tSWITCH. COUT can be sized according to equation 5 with IOUT = ILOAD(MAX) and tNOV = tSWITCH(MAX) to limit maximum output droop when switching to a higher supply. When switching to a lower supply, switchover is initiated only after OUT falls VREV below the supply that is being switched in. In such cases, total output droop is VOUT + VREV. Next consider a scenario where the input power source powering OUT is unplugged. OUT back-feeds circuitry connected to the input supply pin. Both input and output droop at the same rate. Referring to Figure 1, assume the battery on V1 is unplugged when OUT is connected to V1. IOUT is the sum of ILOAD and the reverse current IBACK, which in this example is IR3. As OUT and V1, since the two are connected, droop below the ADJ threshold, switchover occurs to V2 with a dead time: tNOV = tPDA + tSWITCH (6) where tPDA is an overdrive dependent ADJ comparator delay. As an approximation, use tPDA from the Electrical Characteristics table to estimate tNOV. Use this tNOV and: IOUT = (IBACK + ILOAD) (7) in equation 5 to size COUT: COUT ( tPDA + tSWITCH ) *IOUT VOUT (8) Refer to Figure 2 for a more accurate estimate of tPDA versus dVOUT/dt. If ADJ is filtered with capacitor, its discharge time via divider R1-R3 increases tPDA. This results in a higher output droop than estimated by equation 8. 10 In order to limit output rising slew rate dVOUT/dt, size: COUT ILIM dVOUT dt (9) as the LTC4419 limits OUT charging current to ILIM until OUT approaches the input supply to within ILIM * RON, where RON is the channel switch resistance. Refer to the Thermal Protection and Maximum COUT section to determine maximum allowed COUT. 125 100 t PDA (s) where IOUT is the current supplied by COUT during nonoverlap or "dead" time tNOV. Choosing: 75 50 25 0 10 100 1k dVADJ/dt (V/s) 10k 100k 4419 F02 Figure 2. ADJ Comparator Propagation Delay as a Function of Slew Rate; tPDA vs dVADJ/dt Inductive Effects Parasitic inductance and resistance can impact circuit performance by causing overshoot and undershoot of input and output voltages depending on the scenario. Parasitic inductance in the power path causes positive-going overshoot on the input and a negative-going undershoot on the output when the LTC4419 turns off. Another cause of positive input overshoot is R-L-C tank ringing during hot plug of an input supply. Input overshoot is most pronounced when the total resistance of the input tank is low. Care must be taken to ensure overvoltage transients do not exceed the absolute maximum ratings of the LTC4419. Additionally, parasitic resistance and inductance can cause input undershoot during power path turn-on. If severe enough, undershoot can temporarily invalidate a supply and cause repeated power up cycles ("motorboating") or unwanted switchover between sources. 4419fa For more information www.linear.com/LTC4419 LTC4419 APPLICATIONS INFORMATION V1 LTC4419 LPAR1 V1 RSN1 0.5 LPAR2 OUT OPTIONAL CSN1 5F OUT RSN2 1 COUT2 10F OPTIONAL D1 1N5818 COUT1 1F 4419 F03 Figure 3. Recommended Inductive Transient Suppression Circuitry The first step to avoid these issues is to minimize parasitic inductance and resistance in the power path. Guidelines are given in the layout section for minimizing parasitic inductance on the printed circuit board (PCB). External to the PCB, twist the power and ground wires together to minimize inductance. damp R-L-C ringing if required. Size COUT2 to obtain the required total output capacitance. Also add a diode between OUT and ground close to the LTC4419 to clamp negative ringing if the OUT pin rings below -0.3V. Second, use a bypass capacitor at the input to limit input voltage overshoot during LTC4419 power path turn off. A few micro farads is sufficient for most applications. When hot plugging supplies with large parasitic inductances, it is possible for the R-L-C tank to ring to more than twice the nominal supply voltage. Wall adapters and batteries typically have enough loss (i.e. series resistance) to prevent ringing of this magnitude. However, if this is a problem, snub input capacitor CSN1 with resistor RSN1, typically 0.5. Place this network close to the supply pin. In some applications, built-in CMP1 hysteresis may be insufficient. In such cases, CMP1 hysteresis can be increased as shown in Figure 4. Hysteresis at the monitored input VMON with R8 present and assuming R9 << R8 is given by: Third, if an input capacitor is not permissible, use a TVS (such as SMAJ16CA) in applications when supply pin transients can exceed 24V. Use a bidirectional TVS in applications requiring reverse input protection. Note that a TVS does not address droop and motor boating, which are solved only by input bypassing. During normal operation, the LTC4419 limits power path current to < 1.6A and internal circuitry prevents OUT from ringing below ground during power path turn off. This is also true for output shorts when the short is close to the LTC4419's OUT pin. However, if the output is shorted through a long wire, current in the wire inductance (LPAR2 in Figure 3) builds up due to the discharge of COUT1 and can be much higher than 1.6A. This current causes the OUT pin to ring below its -0.3V absolute maximum rating once COUT1 has been fully discharged. For this special case, split the output capacitor between COUT1 and COUT2 and make COUT1 small. Snub COUT1 with resistor RSN2 to Increasing CMP1 and CMP2 Hysteresis VHYST = VHYSTC * R3 R3 + VPU * R1||R3||R8 R8 (10) where VHYSTC and VTHC are found in the Electrical Characteristics table and are typically 10mV and 0.387V respectively. Account for supply VPU and resistor R8 when calculating rising and falling thresholds of monitored input VMON. Supply Impedance and ADJ Comparator Hysteresis VMON R3 VPU CMP1 R1 LTC4419 R9 CMPOUT1 R8 4419 F04 Figure 4. Increasing CMP1 Hysteresis In some applications, V1 could be supplied by a battery pack with high ESR or through a long cable with appreciable series resistance. Load current, IOUT, flowing through this resistance reduces the monitored V1 voltage by: V1 = IOUT * RESR (11) 4419fa For more information www.linear.com/LTC4419 11 LTC4419 APPLICATIONS INFORMATION The drop can be as high as: V1 = ILIM * RESR (12) when COUT is initially being charged. Voltage droop at the V1 pin can result in repeated switchover between V1 and V2 if built-in V1 (ADJ) hysteresis is insufficient. In such cases, CMP1 can be used to set V1 hysteresis as shown in Figure 5. When V1 falls, ADJ and CMP2 are pulled low when CMP1 falls below VTHC and output CMPOUT2 activates hysteresis resistor R8. When switching from V1 to V2, current supplied by V1 will go to zero, resulting in a voltage increase on V1. Switchover back to V1 is prevented due to increased V1 hysteresis as determined by equation 10. V1 droop is higher during the initial charging of COUT. Referring to Figure 5, to prevent repeated switchover when COUT is initially being charged, add input capacitor C1. Ideally, if V1 is greater than switchover threshold VSW1 by V, size: V VSW1 *COUT * 1- 2 *ILIM *RESR C1 V (13) A filter capacitor CADJ can also be added to ADJ to ride through the initial output charge up time. CADJ should be minimized as it slows ADJ response, resulting in a larger ESR + V1 R2 C1 + R8 R1 V1 V2 V2 Input Shorts and Supply Brown-Out The LTC4419 temporarily turns off its active power path during input shorts or brown-out conditions if the input supply falls below OUT by 0.7V. If the primary input supply becomes invalid, switchover to the backup supply occurs. The power path is reactivated when the input recovers to within 0.7V of the output. Figure 6 shows the response of the LTC4419 to a brownout and recovery on V1 where switchover to V2 does not occur as V1 stays above 1.8V. When V1 falls, OUT gets disconnected from V1 and is slowly discharged by load resistance ROUT. When V1 recovers, the power path is reactivated and OUT tracks V1. In Figure 7, when V1 falls, OUT gets disconnected from V1 as V1 drops below the V1 5V/DIV to ensure no switchover occurs when COUT is initially being charged. If the resulting C1 value causes large inrush current, is physically too big or requires a large snubber resistor when V1 is plugged in (refer to the Typical Applications section), select C1 to be as high a value as the application can tolerate. R3 output droop when the input supply powering V1 is either unplugged or drops quickly. OUT OUT COUT V2 5V/DIV OUT 5V/DIV 100s/DIV 4419 F06 Figure 6. Voltage Waveforms During a Brown-Out on V1 that Does Not Result in a Switchover to V2. Switchover Threshold = 1.8V V1 5V/DIV V2 5V/DIV LTC4419 OUT 5V/DIV CMP1 CMPOUT2 COUT = 10F ROUT = 100 CMPOUT1 100s/DIV ADJ CMP2 4419 F05 Figure 5. Increasing Supply Hysteresis in High ESR Applications 12 COUT = 10F ROUT = 100 4419 F07 Figure 7. Voltage Waveforms When a Brown-Out on V1 Results in Switchover to V2. Switchover Threshold = 3V 4419fa For more information www.linear.com/LTC4419 LTC4419 APPLICATIONS INFORMATION switch-over threshold. When V1 recovers, it needs to be qualified for 64ms before it is reconnected to OUT. OUT gets discharged by ROUT and is connected to V2 once its voltage is 50mV less than V2. 5V INPUT Reverse Voltage Blocking The LTC4419 blocks reverse voltages on supply pins V1 and V2 up to -15V relative to GND and up to -39V relative to OUT. Transient voltage suppressors (TVS) connected to V1 and V2 must be bidirectional and capacitors connected to these pins must be rated to handle reverse voltages. A reverse voltage on V2 does not disrupt V1 operation and vice versa. Freshness Seal Freshness seal mode prevents V2 battery discharge by keeping V2 disconnected from OUT even if V1 is absent or invalid. Very little current is drawn from V2--typically just 120nA. The following sequence (refer to Figure 8) puts the LTC4419 in freshness seal mode: 1. Power up V2 while holding V1 low and wait for at least 10ms. 2. Drive V2ON below 50mV. 3. Power up V1 and ADJ for at least 94ms. Freshness seal is enabled. 1 V2 2 3 1.8V DRIVEN LOW EXTERNALLY V2ON ADJ 1.8V 1.116V RSN1 0.5 C1 2.2F R3 365k R2 88.7k R1 44.2k C2 2.2F + 2-CELL Li-Ion 7.4V R5 1.37M R4 95.3k V1 ADJ OUT R6 1M CMPOUT1 R7 1M OUT COUT 15F PFV1 LTC4419 CMP1 CMPOUT2 V2UV V2 CMP2 GND 4419 F09 Figure 9. Design Example Design Example In Figure 9, the LTC4419 prioritizes between a 5V supply connected to V1 and a 7.4V 2-cell Li-Ion battery connected to V2. The system is designed to switch OUT to V2 when V1 drops below 4V, provide early power failure warning when V1 drops below 4.5V and low battery warning when the backup battery voltage drops below 6V. Maximum anticipated load current is 100mA and maximum allowed output droop is 100mV. Output rising slew rate is limited to <0.1V/s and V1 and V2 input capacitors are limited to 10F to avoid large inrush current. 1% tolerance resistors are used. ADJ and CMP pin leakages are ignored as their design impact is small. First choose total resistive divider current to be ~10A for V1 and ~5A for V2. For the 5V supply, this results in: 10ms V1 next time V1 is revalidated. Limit V2ON pin capacitance to less than 10nF in order to prevent freshness seal mode from accidentally being engaged. FSEAL ENABLED 94ms R1+R2+R3 = 4419 F08 Figure 8. Freshness Seal Engage Procedure Engage this mode if V2 is a backup battery either during storage or during shipment. Once freshness seal has been engaged, if V1 is disconnected, V2 stays disconnected from OUT. Freshness seal is automatically disabled the 5V = 500k 10A (14) Since desired switchover threshold, VSW1, and the total divider impedance are known, use equation 1 to first calculate R3. Using R3 and equation 2, calculate R1 and R2. Rewriting equation 1 results in: (R1+R2) = VTHA * (R1+R2+R3) VSW1 (15) 4419fa For more information www.linear.com/LTC4419 13 LTC4419 APPLICATIONS INFORMATION Using (R1 + R2 + R3) = 500k from equation 14, results in: (R1+R2) = 1.047V * 500k =130.9k 4V R3 ~ (500k - 130.9k) = 369.1k (16) (17) Using the nearest 1% resistor value yields R3 = 365k. Rearranging equation 2 results in COUT affects both OUT droop during switchover as determined by equation 4 and OUT rising slew rate as determined by equation 9. Calculate minimum COUT required to meet desired output droop and slew rate specifications using equations 8 and 9 and size COUT to be the larger of the two values. COUT required to limit OUT droop to < 100mV is given by equation 8: R1= VTHC * (R2+R2+R3) VPFV1 (18) COUT R1= 0.387V * (500k) 4.5V (19) COUT ( tPDA + tSWITCH ) *ILOAD 100mV (7.3s+2.5s) * 0.1A = 9.8F 100mV (23) (24) Solving equations 16 and 19 results in R1 = 43.3k and R2 = 87.6k. Using the nearest 1% resistors results in R2 = 88.7k. Recalculating equation 1 using calculated R2 and R3 values and using standard 1% resistor values close to 43.3k for R1 results in R1 = 44.2k. COUT required to limit OUT slew rate to < 0.1V/s is given by equation 9: A similar procedure is used to calculate R4 and R5 using equation 3 and total divider current. The design equations are shown below: Choose a COUT capacitor whose minimum value is 11F accounting for voltage and temperature coefficients. Do this for other capacitors as well. Assuming correct PCB layout, choose C1 to be 2.2F, which is ~ 1/5th of COUT to suppress inductive transients. Also snub C1 with a 0.5 resistor to prevent ringing. R4+R5 = 7.4V =1.48M 5A (20) as desired current in the divider is 5A. Rewriting equation 3 neglecting pin leakage and assuming R5 >> R4 results in: R4 = VTHC * (R4+R5) VV2UV (21) R4 = 0.387V *1.48M 6V (22) Solving 20 and 22 results in R4 = 96.2k and R5 = 1.38M. Choosing the nearest 1% resistor results in R4 = 95.3k and R5 = 1.37M. 14 COUT ILIM =11F 0.1V/s (25) Layout Consideration Make power and ground traces as wide as possible. Place bypass capacitors, snubbers and TVS devices as close to the pin as possible to reduce power path resistance and parasitic inductance. These result in smaller overvoltage transients and improved overvoltage protection. Place resistive dividers close to the pins to improve noise immunity. Use a 4-layer board if possible with layer 2 as dedicated GND and solder the exposed pad to a large PCB GND trace for better heat dissipation. A partial layout for a 2-Layer PCB is shown in Figure 10. 4419fa For more information www.linear.com/LTC4419 LTC4419 APPLICATIONS INFORMATION GND GND C1 V1 C2 V2 LTC4419 OUT COUT GND 4419 F10 Figure 10. Recommended 12-Lead MSE Layout for a 2-Layer PCB Depending on the difference between input and output voltages, the LTC4419's internal power dissipation can be high when operating in current limit mode. This usually occurs when a large COUT is being charged either during initial power up or when OUT switches over to a higher supply. The situation is made worse if a DC load is present on OUT, as this reduces the current available to charge COUT. In such cases, self heating can cause power path turn-off due to activation of the thermal protection circuitry. The power path is reactivated when die temperature drops to a safe value. This process can repeat indefinitely if COUT is discharged fully by load current IOUT in the interval when the power path is off. Maximum allowed COUT to prevent activation of the thermal protection circuit depends on several factors such as input supply and output voltages, starting ambient temperature, heat dissipation in the PCB and DC output current. Choose COUT < 500F if possible. If a larger COUT is necessary, use Figure 11 to choose COUT.. Follow PCB layout guidelines to improve heat dissipation. 60k ILOAD = 0 10k COUT (F) Thermal Protection and Maximum COUT 1k 100 -40C 25C 85C 5 10 15 VIN (V) 20 4419 F11 Figure 11. Maximum Allowed COUT vs Input Voltage for Different TA 4419fa For more information www.linear.com/LTC4419 15 LTC4419 TYPICAL APPLICATIONS Battery Backup with Interface to Low Voltage Logic 5V TO 18V WALL ADAPTER V1 RSN1 0.5 C1 10F OUT R3 365k ADJ C3 10F R6 1M V2 R9 1M SYSTEM V2UV CMPOUT2 V2ON V2ON R5 1M R7 1M V1UV CMPOUT1 R1 44.2k RSN2 0.5 C2 10F 3.3V LTC4419 R2 88.7k CMP1 3.6V TO 18V BACKUP COUT 10F IN OUT LTC1763-3.3V SHDN GND SWITCHOVER THRESHOLD: V1 < 4V (V1 FALLING) V1UV THRESHOLD: V1 < 4.5V (V1 FALLING) V2UV THRESHOLD: V2 < 3V (V2 FALLING) CMP2 R4 150k 4419 TA02 GND SuperCap Backup with SuperCap Charging L1 3.3H C1 10F 1.7V TO 5.5V INPUT R8 1M C2 120pF R12 12.1k R13 127k SW1 RSENP RSENS SW2 VOUT MID LTC3128 IN PROG MAXV C2: MURATA DMF3Z5R5H474M3DTA0 GND FB RUN 4.2V C2 940mF 940mF R3 1M R5 1.87M R4A 61.9k R4B 237k M1 2N4351 R2 237k R1 121k V1 V2 OUT LTC4419 COUT 10F R6 1M R7 1M OUT ADJ CMPOUT1 V1UV CMP1 CMPOUT2 V2UV CMP2 V2ON GND 4419 TA03 SWITCHOVER THRESHOLD: V1 < 4V (V1 FALLING) V1UV THRESHOLD: V1 < 4.4V (V1 FALLING) V2UV THRESHOLD: V2 < 3.5V (V2 FALLING) 16 4419fa For more information www.linear.com/LTC4419 LTC4419 TYPICAL APPLICATIONS Triple Supply Monitor with Primary Battery Pack Protection + 4-CELL 14.8V Li-Ion V1 10F OUT R3 2M ADJ R1 191k + 9V ALKALINE CMP2 LTC4419 V2 10F R11 5.36M R7 1M R6 1M COUT 10F R4 113k CMPOUT1 V2UV CMPOUT2 OUTUV V2ON CMP1 R10 316k OUT R5 2M GND 4419 TA04 V2ON SWITCHOVER THRESHOLD: V1 < 12V (V1 FALLING) V2UV THRESHOLD: V2 < 7V (V2 FALLING) OUTUV THRESHOLD: OUT < 7.5V (OUT FALLING) 4419fa For more information www.linear.com/LTC4419 17 LTC4419 TYPICAL APPLICATIONS Early Power Failure Warning with Low Battery Indication L1, 10H C4 0.1F 5V TO 15V INPUT C8 10F SW1 SW2 C5 0.1F BST1 BST2 LTC3111 VIN VOUT COMP R13 1M R14 137k C7 1nF R12 44.2k C6 39pF RUN SNSGND FB VCC PWM TO OTHER CIRCUITS 12V R8 20k C9 18pF R10 2.21M 4-CELL + 14.8V Li-Ion C1 22F V1 OUT COUT 10F OUT R6 1M R7 1M ADJ R2 75k R11 158k C3 1F R3 1M LTC4419 CMP1 R1 41.2k CMPOUT1 PFV1 CMPOUT2 V2UV V2ON V2ON V2 C2 10F R5 5.23M CMP2 PFV1: V1 POWER FAILURE THRESHOLD: V1 < 10.6V (V1 FALLING) SWITCHOVER THRESHOLD: V1 < 10V (V1 FALLING) V2UV THRESHOLD: V2 < 12V (V2 FALLING) 18 R4 174k GND 4419 TA05 4419fa For more information www.linear.com/LTC4419 LTC4419 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC4419#packaging for the most recent package drawings. DD Package 10-Lead Plastic DFN (3mm x 3mm) (Reference LTC DWG # 05-08-1699 Rev C) 0.70 0.05 3.55 0.05 1.65 0.05 2.15 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 0.10 (4 SIDES) R = 0.125 TYP 6 0.40 0.10 10 1.65 0.10 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.35 x 45 CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 0.75 0.05 0.00 - 0.05 5 1 (DD) DFN REV C 0310 0.25 0.05 0.50 BSC 2.38 0.10 (2 SIDES) BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4419fa For more information www.linear.com/LTC4419 19 LTC4419 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC4419#packaging for the most recent package drawings. MSE Package 12-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1666 Rev G) BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 0.102 (.112 .004) 5.10 (.201) MIN 2.845 0.102 (.112 .004) 0.889 0.127 (.035 .005) 6 1 1.651 0.102 (.065 .004) 1.651 0.102 3.20 - 3.45 (.065 .004) (.126 - .136) 12 0.65 0.42 0.038 (.0256) (.0165 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 0.35 REF 4.039 0.102 (.159 .004) (NOTE 3) 0.12 REF DETAIL "B" CORNER TAIL IS PART OF DETAIL "B" THE LEADFRAME FEATURE. FOR REFERENCE ONLY 7 NO MEASUREMENT PURPOSE 0.406 0.076 (.016 .003) REF 12 11 10 9 8 7 DETAIL "A" 0 - 6 TYP 3.00 0.102 (.118 .004) (NOTE 4) 4.90 0.152 (.193 .006) GAUGE PLANE 0.53 0.152 (.021 .006) DETAIL "A" 1.10 (.043) MAX 0.18 (.007) SEATING PLANE 0.22 - 0.38 (.009 - .015) TYP 1 2 3 4 5 6 0.650 (.0256) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 20 0.86 (.034) REF 0.1016 0.0508 (.004 .002) MSOP (MSE12) 0213 REV G 4419fa For more information www.linear.com/LTC4419 LTC4419 REVISION HISTORY REV DATE DESCRIPTION A 09/17 Updated tSWITCH test condition Updated pin function for Exposed Pad PAGE NUMBER 3 6 4419fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC4419 21 LTC4419 TYPICAL APPLICATION High Efficiency Backup 5V WALL ADAPTER RSN1 0.5 C1 10F R3 1M R2 237k R1 121k C2 10F + 2-CELL 7.4V Li-Ion R5 4.02M R4 280k V1 OUT ADJ COUT 10F R13 1.1M R12 1.05M LTC4419 CMP1 C3 2.2F V2 CMPOUT1 CMPOUT2 CMP2 V2ON L1 3.3H BST1 SW1 VIN RUN C5 22nF SW2 BST2 OUT RUN LTC3129-1 MPPC VS2 VS1 VCC PWM GND PGND VS3 5V C4 10F R7 1M R6 1M SYSTEM C4 22nF V1UV V2UV V2_ON SWITCHOVER THRESHOLD: V1< 4V (V1 FALLING) V1UV THRESHOLD: V1 < 4.4V (V1 FALLING) V2UV THRESHOLD: V2 < 6V (V2 FALLING) GND 4419 TA06 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1763 500mA, Low Noise Micropower LDO Regulators VIN: 1.8V to 20V, 12-DFN, SO-8 Packages LTC2952 Pushbutton PowerPath Controller with Supervisor VIN: 2.7V to 28V, On/Off Timers, 8kV HBM ESD, TSSOP-20 and QFN-20 Packages LTC3103 15V, 300mA Synchronous Step-Down DC/DC Converter VIN: 2.5V-15V, DFN-10 and MSE-10 Packages LTC3129/LTC3129-1 15V, 200mA Synchronous Buck-Boost DC/DC Converter with 1.3A Quiescent Current VIN: 1.92V to 15V, QFN-16 and MSE-16 Packages LTC3388-1/LTC3388-3 20V, 50mA High Efficiency Nanopower Step-Down Regulator VIN: 2.7V to 20V, DFN-10 and MSE-10 Packages LTC4411 2.6A Low Loss Ideal Diode in ThinSOTTM Internal 2.6A P-channel, 2.6V to 5.5V, IQ = 40A, SOT-23 Package LTC4412 36V Low Loss PowerPath Controller in ThinSOT 2.5V to 36V, P-channel, IQ = 11A, SOT-23 Package LTC4415 Dual 4A Ideal Diodes with Adjustable Current Limit Dual Internal P-channel, 1.7V to 5.5V, MSOP-16 and DFN-16 Packages LTC4416 36V Low Loss Dual PowerPath Controller for Large PFETs 3.6V to 36V, 35A per IQ Supply, MSOP-10 Package LTC4417 3-Channel Prioritized PowerPath Controller Triple P-Channel Controller, 2.5V to 36V, SSOP-24 and QFN-24 Packages LTC4355 Positive High Voltage Ideal Diode-OR with Supply and Fuse Monitors Dual N-channel, 9V to 80V, SO-16, MSOP-16 and DFN-14 Packages LTC4359 Ideal Diode Controller with Reverse Input Protection N-channel, 4V to 80V, MSOP-8 and DFN-6 Packages 22 4419fa LT 0917 REV A * PRINTED IN USA For more information www.linear.com/LTC4419 www.linear.com/LTC4419 LINEAR TECHNOLOGY CORPORATION 2015