LM139AQML
LM139AQML LM139QML Low Power Low Offset Voltage Quad Comparators
Literature Number: SNOSAH8F
LM139AQML
LM139QML
October 15, 2010
Low Power Low Offset Voltage Quad Comparators
General Description
The LM139 series consists of four independent precision volt-
age comparators with an offset voltage specification as low
as 2 mV max for all four comparators. These were designed
specifically to operate from a single power supply over a wide
range of voltages. Operation from split power supplies is also
possible and the low power supply current drain is indepen-
dent of the magnitude of the power supply voltage. These
comparators also have a unique characteristic in that the input
common-mode voltage range includes ground, even though
operated from a single power supply voltage.
Application areas include limit comparators, simple analog to
digital converters; pulse, squarewave and time delay gener-
ators; wide range VCO; MOS clock timers; multivibrators and
high voltage digital logic gates. The LM139 series was de-
signed to directly interface with TTL and CMOS. When oper-
ated from both plus and minus power supplies, they will
directly interface with MOS logic— where the low power drain
of the LM139/LM139A is a distinct advantage over standard
comparators.
Features
■Available with Radiation Guarantee
—Total Ionizing Dose 100 krad(Si)
—ELDRS Free 100 krad(Si)
■Wide supply voltage range
■LM139/139A Series 2 to 36 VDC or ±1 to ±18 VDC
■Very low supply current drain (0.8 mA) — independent of
supply voltage
■Low input biasing current: 25 nA
■Low input offset current: ±5 nA
■Offset voltage: ±1 mV
■Input common-mode voltage range includes GND
■Differential input voltage range equal to the power supply
voltage
■Low output saturation voltage: 250 mV at 4 mA
■Output voltage compatible with TTL, DTL, ECL, MOS and
CMOS logic systems
Advantages
■High precision comparators
■Reduced VOS drift over temperature
■Eliminates need for dual supplies
■Allows sensing near GND
■Compatible with all forms of logic
■Power drain suitable for battery operation
Ordering Information
NS Part Number SMD Part Number NS Package Number Package Description
LM139E/883 E20A 20 terminal Leadless Chip Carrier
LM139J/883 J14A 14LD CERDIP
LM139AW-SMD 5962–8773901DA W14B 14LD CERPACK
LM139AWG-SMD 5962–8773901XA WG14A 14LD Ceramic SOIC
LM139AE/883 E20A 20 terminal Leadless Chip Carrier
LM139AJ/883 J14A 14LD CERDIP
LM139AJRQMLV (Note 11)5962R9673801VCA
100 krad(Si) J14A 14LD CERDIP
LM139AJRLQMLV (Note 15)
ELDRS Free
5962R9673802VCA
100 krad(Si) J14A 14LD CERDIP
LM139AW-QMLV 5962–9673801VDA W14B 14LD CERPACK
LM139AW/883 W14B 14LD CERPACK
LM139AWG-QMLV 5962–9673801VXA WG14A 14LD Ceramic SOIC
LM139AWG/883 WG14A 14LD Ceramic SOIC
LM139AWGRQMLV (Note 11)5962R9673801VXA
100 krad(Si) WG14A 14LD Ceramic SOIC
LM139AWGRLQMLV (Note 15)
ELDRS Free
5962R9673802VXA
100 krad(Si) WG14A 14LD Ceramic SOIC
LM139AWRQMLV (Note 11)5962R9673801VDA
100 krad(Si) W14B 14LD CERPACK
© 2011 National Semiconductor Corporation 201221 www.national.com
LM139AQML/LM139QML Low Power Low Offset Voltage Quad Comparators
NS Part Number SMD Part Number NS Package Number Package Description
LM139AWRLQMLV (Note 15)
ELDRS Free
5962R9673802VDA
100 krad(Si) W14B 14LD CERPACK
LM139 MDE (Note 15)
ELDRS Free
5962R9673802V9A
100 krad(Si) (Note 1) Bare Die
LM139 MDR (Note 11)5962R9673801V9A
100 krad(Si) (Note 1) Bare Die
Note 1: FOR ADDITIONAL DIE INFORMATION, PLEASE VISIT THE HI REL WEB SITE AT: www.national.com/analog/space/level_die
Connection Diagrams
Dual-In-Line Package
20122102
See NS Package NumberJ14A
20122127
See NS Package Number W14B, WG14A
20122144
See NS Package Number E20A
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LM139AQML/LM139QML
Absolute Maximum Ratings (Note 2)
LM139 / LM139A
Supply Voltage, V+36 VDC or ±18 VDC
Differential Input Voltage (Note 8) 36 VDC
Input Voltage −0.3 VDC to +36 VDC
Input Current (VIN < −0.3 VDC) (Note 4) 50 mA
Power Dissipation (Note 5, Note 14)
LCC 1250 mW
CERDIP 1200 mW
CERPACK 680 mW
SOIC 680 mW
Sink Current (approx) (Note 12) 20mA
Output Short-Circuit to GND, (Note 3) Continuous
Storage Temperature Range -65°C ≤ TA ≤ +150°C
Maximum Junction Temperature (TJ) +150°C
Lead Temperature (Soldering, 10 seconds) 300°C
Operating Temperature Range -55°C ≤ TA ≤ +125°C
Thermal Resistance
θJA
LCC (Still Air) 100°C/W
LCC (500LF / Min Air flow) 73°C/W
CERDIP (Still Air) 103°C/W
CERDIP (500LF / Min Air flow) 65°C/W
CERPACK (Still Air) 183°C/W
CERPACK (500LF / Min Air flow) 120°C/W
SOIC (Still Air) 183°C/W
SOIC (500LF / Min Air flow) 120°C/W
θJC
LCC 28°C/W
CERDIP 23°C/W
CERPACK 23°C/W
SOIC 23°C/W
Package Weight (typical)
LCC 470mg
CERDIP 2,190mg
CERPACK 460mg
SOIC 410mg
ESD rating (Note 13) 600V
Recommended Operating Conditions
Supply Voltage 5.0 VDC to +30 VDC
Ambient Operating Temperature Range −55°C ≤ TA ≤ +125°C
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LM139AQML/LM139QML
Quality Conformance Inspection
Mil-Std-883, Method 5005 — Group A
Subgroup Description Temp (°C)
1 Static tests at +25
2 Static tests at +125
3 Static tests at -55
4 Dynamic tests at +25
5 Dynamic tests at +125
6 Dynamic tests at -55
7 Functional tests at +25
8A Functional tests at +125
8B Functional tests at -55
9 Switching tests at +25
10 Switching tests at +125
11 Switching tests at -55
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LM139AQML/LM139QML
LM139 883 Electrical Characteristics
DC Parameters
The following conditions apply, unless otherwise specified. +V = 5V, VCM = 0V
Symbol Parameters Conditions Notes Min Max Unit Sub-
groups
ICC Supply Current RL = Infinity 2.0 mA 1, 2, 3
Supply Current +V = 30V, RL = Infinity 2.0 mA 1, 2, 3
VIO Input Offset Voltage +V = 30V -5.0 5.0 mV 1
-9.0 9.0 mV 2, 3
+V = 30V, VCM = 28.5V -5.0 5.0 mV 1
+V = 30V, VCM = 28.0V -9.0 9.0 mV 2, 3
-5.0 5.0 mV 1
-9.0 9.0 mV 2, 3
CMRR Common Mode Rejection Ratio +V = 30V, VCM = 0V to 28.5V 60 dB 1
PSRR Power Supply Rejection Ratio +V = 5V to 30V 60 dB 1
± IBias Input Bias Current VO = 1.5V (Note 6) -100 -1.0 nA 1
(Note 6) -300 -1.0 nA 2, 3
IIO Input Offset Current VO = 1.5V -25 25 nA 1
-100 100 nA 2, 3
ICEX Output Leakage Current +V = 30V, VO = 30V 1.0 µA 1, 2, 3
ISink Output Sink Current VO = 1.5V 6.0 mA 1
VSat Saturation Voltage ISink = 4mA 400 mV 1
700 mV 2, 3
AVVoltage Gain +V = 15V, RL ≥ 15ΩK, VI = 1V to
11V 50 V/mV 1
VCM Common Mode Voltage Range +V = 30V (Note 9) 0 V+ -
(1.5) V 1
(Note 9) 0 V+ -
(2.0) V 2, 3
VDiff Differential Input Voltage +V = 30V, -V = 0V, +VI = 36V, -VI
= 0V (Note 10) 500 nA 1, 2, 3
+V = 30V, -V = 0V, +VI = 0V, -VI =
36V (Note 10) 500 nA 1, 2, 3
AC Parameters
The following conditions apply, unless otherwise specified. +V = 5V
Symbol Parameters Conditions Notes Min Max Unit Sub-
groups
tRLH Response Time VOD = 5mV 5.0 µS 9
VOD = 50mV 0.8 µS 9
tRHL Response Time VOD = 5mV 2.5 µS 9
VOD = 50mV 0.8 µS 9
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LM139AQML/LM139QML
LM139A SMD 5962–8773901 Electrical Characteristics
DC Parameters
The following conditions apply, unless otherwise specified. +V = 5V, VCM = 0V
Symbol Parameter Conditions Notes Min Max Unit Sub-
groups
ICC Supply Current +V = 30V, RL = Infinity 3.0 mA 1, 2, 3
RL = Infinity 3.0 mA 1, 2, 3
ICEX Output Leakage Current +V = 30V, -VI = 0V, +VI ≥ 1V, VO
= 30V
0.5 µA 1
1.0 µA 2, 3
VSat Saturation Voltage ISink ≤ 4mA, -VI = 1V, +VI = 0V 400 mV 1
700 mV 2, 3
ISink Output Sink Current VO ≥ 1.5V, -VI = 1V, +VI = 0V 6.0 mA 1
VIO Input Offset Voltage RS = 0Ω -2.0 2.0 mV 1
-4.0 4.0 mV 2, 3
+V = 30V, RS = 0Ω -2.0 2.0 mV 1
-4.0 4.0 mV 2, 3
+V = 30V, VCM = 28V, VO = 1.4V,
RS = 0Ω
-2.0 2.0 mV 1
-4.0 4.0 mV 2, 3
±IIB Input Bias Current VO = 1.5V (Note 6) -100 -1.0 nA 1
(Note 6) -300 -1.0 nA 2, 3
IIO Input Offset Current VO = 1.5V -25 25 nA 1
-100 100 nA 2, 3
PSRR Power Supply Rejection Ratio +V = 5V to 30V 70 dB 1, 2, 3
CMRR Common Mode Rejection Ratio +V = 30V, VCM = 0V to 28V, RL
≥ 15KΩ 70 dB 1, 2, 3
AVVoltage Gain +V = 15V, RL ≥ 15KΩ, VO = 1V to
11V
50 V/mV 4
25 V/mV 5, 6
VCM Common Mode Voltage Range +V = 30V (Note 9) 0 V+ -
(2.0) V 1, 2, 3
+V = 5V (Note 9) 0 V+ -
(2.0) V 1, 2, 3
AC Parameters
The following conditions apply, unless otherwise specified. +V = 5V
Symbol Parameters Conditions Notes Min Max Unit Sub-
groups
tRLH Response Time VOD = 5mV, RL = 5.1KΩ 5.0 µS 9
tRHL Response Time VOD = 5mV, RL = 5.1KΩ 2.5 µS 9
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LM139AQML/LM139QML
LM139A 883, QMLV & RH, SMD 5962–9673801 Electrical Characteristics
DC Parameters (Note 11, Note 15)
The following conditions apply, unless otherwise specified. +V = 5V, VCM = 0V
Symbol Parameters Conditions Notes Min Max Unit Sub-
groups
ICC Supply Current RL = Infinity 2.0 mA 1, 2, 3
+V = 30V, RL = Infinity 2.0 mA 1, 2, 3
ICEX Output Leakage Current +V = 30V, VO = 30V 1.0 µA 1, 2, 3
VSat Saturation Voltage ISink = 4mA 400 mV 1
700 mV 2, 3
ISink Output Sink Current VO = 1.5V 6.0 mA 1
VIO Input Offset Voltage -2.0 2.0 mV 1
-4.0 4.0 mV 2, 3
+V = 30V -2.0 2.0 mV 1
-4.0 4.0 mV 2, 3
+V = 30V, VCM = 28.5V,
VO = 1.5V -2.0 2.0 mV 1
+V = 30V, VCM = 28.0V,
VO = 1.5V -4.0 4.0 mV 2, 3
± IBias Input Bias Current VO = 1.5V (Note 6) -100 -1.0 nA 1
(Note 6) -300 -1.0 nA 2, 3
IIO Input Offset Current VO = 1.5V -25 25 nA 1
-100 100 nA 2, 3
PSRR Power Supply Rejection Ratio +V = 5V to 30V 60 dB 1
CMRR Common Mode Rejection Ratio +V = 30V, VCM = 0V to 28.5V 60 dB 1
AVVoltage Gain +V = 15V, RL ≥ 15KΩ, VO = 1V to
11V 50 V/mV 1
VCM Common Mode Voltage Range +V = 30V (Note 7,
Note 9)0V+ -
(1.5) V 1
(Note 7,
Note 9)0V+ -
(2.0) V 2, 3
VDiff Differential Input Voltage +V = 30V, -V =0V, +VI = 36V, -VI
= 0V (Note 10) 500 nA 1, 2, 3
+V = 30V, -V = 0V, +VI = 0V, -VI =
36V (Note 10) 500 nA 1, 2, 3
AC Parameters (Note 11, Note 15)
The following conditions apply, unless otherwise specified. +V = 5V
Symbol Parameters Conditions Notes Min Max Unit Sub-
groups
tRLH Response Time VOD = 5mV 5.0 µS 4
VOD = 50mV 0.8 µS 4
tRHL Response Time VOD = 5mV 2.5 µS 4
VOD = 50mV 0.8 µS 4
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LM139AQML/LM139QML
DC Parameters Delta Values
The following conditions apply, unless otherwise specified. +V = 5V, VCM = 0V
Deltas required for S-Level, MLS (as specified on Internal Processing instructions (IPI)), and QMLV product at Group B, Subgroup
5.
Symbol Parameters Conditions Notes Min Max Unit Sub-
groups
VIO Input Offset Voltage -1.0 1.0 mV 1
± IBias Input Bias Current VO = 1.5V (Note 6) -15 15 nA 1
IIO Input Offset Current VO = 1.5V -10 +10 nA 1
DC/AC Parameters 50K Post Rad Limits +25°C (Note 11)
The following conditions apply, unless otherwise specified.
DC: +V = 5V, VCM = 0V
AC: +V = 5V
Symbol Parameters Conditions Notes Min Max Unit Sub-
groups
VIO Input Offset Voltage +V = 5V, VCM = 0 -2.5 2.5 mV 1
+V = 30V, VCM = 0 -2.5 2.5 mV 1
+V = 30V, VCM = 28.5V,
VO = 1.5V -2.5 2.5 mV 1
± IBias Input Bias Current VO = 1.5V (Note 6) -110 -1.0 nA 1
tRLH Response Time VOD (Overdrive) = 50mV 0.9 µS 4
DC/AC Parameters 100K Post Rad Limits +25°C (Note 11, Note 15)
The following conditions apply, unless otherwise specified.
DC: +V = 5V, VCM = 0V
AC: +V = 5V
Symbol Parameters Conditions Notes Min Max Unit Sub-
groups
VIO Input Offset Voltage +V = 5V, VCM = 0 -4.0 4.0 mV 1
+V = 30V, VCM = 0 -4.0 4.0 mV 1
+V = 30V, VCM = 28.5V,
VO = 1.5V -4.0 4.0 mV 1
± IBias Input Bias Current VO = 1.5V (Note 6) -110 -1.0 nA 1
tRLH Response Time VOD (Overdrive) = 50mV 1.0 µS 4
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LM139AQML/LM139QML
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guaranteed specific performance limits. For guaranteed specifications and test conditions, see, the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 3: Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground, the maximum output
current is approximately 20 mA independent of the magnitude of V+.
Note 4: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP
transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action
on the IC chip. This transistor action can cause the output voltages of the comparators to go to the V+ voltage level (or to ground for a large overdrive) for the
time duration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which was negative, again
returns to a value greater than −0.3 VDC (at 25°)C.
Note 5: The low bias dissipation and the ON-OFF characteristics of the outputs keeps the chip dissipation very small (PD ≤ 100mW), provided the output transistors
are allowed to saturate.
Note 6: The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of the output
so no loading change exists on the reference or input lines.
Note 7: The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end of the common-
mode voltage range is V+ −1.5V for Subgroup 1, or V+ −2.0V for Subgroup 2 & 3. Either or both inputs can go to +30 VDC without damage, independent of the
magnitude of V+.
Note 8: Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, the
comparator will provide a proper output state. The low input voltage state must not be less than −0.3 VDC (or 0.3 VDCbelow the magnitude of the negative power
supply, if used) (at 25°C).
Note 9: Parameter guaranteed by VIO tests
Note 10: The value for VDiff is not data logged during Read and Record.
Note 11: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the “Post Radiation Limits” table.
These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters
are guaranteed only for the conditions as specified in Mil-Std-883, Method 1019, Condition A.
Note 12: SMD 5962–8773901 only
Note 13: Human Body model, 1.5 KΩ in series with 100 pF
Note 14: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (Package
junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax — TA) /
θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
Note 15: Low dose rate testing has been performed on a wafer-by-wafer basis, per test method 1019, condition D, MIL-STD-883, with no enhanced low dose
rate sensitivity (ELDRS) effect. Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics, except as listed in the “Post
Radiation Limits” table. Radiation end point limits for the noted parameters are guaranteed for only the conditions as specified in MIL-STD-883, Method 1019,
condition D.
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LM139AQML/LM139QML
Typical Performance Characteristics LM139, LM139A
Supply Current
20122134
Input Current
20122135
Output Saturation Voltage
20122136
Response Time for Various Input Overdrives
—Negative Transition
20122137
Response Time for Various Input Overdrives
—Positive Transition
20122138
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LM139AQML/LM139QML
Application Hints
The LM139 series are high gain, wide bandwidth devices
which, like most comparators, can easily oscillate if the output
lead is inadvertently allowed to capacitively couple to the in-
puts via stray capacitance. This shows up only during the
output voltage transition intervals as the comparator changes
states. Power supply bypassing is not required to solve this
problem. Standard PC board layout is helpful as it reduces
stray input-output coupling. Reducing this input resistors to <
10 kΩ reduces the feedback signal levels and finally, adding
even a small amount (1 to 10 mV) of positive feedback (hys-
teresis) causes such a rapid transition that oscillations due to
stray feedback are not possible. Simply socketing the IC and
attaching resistors to the pins will cause input-output oscilla-
tions during the small transition intervals unless hysteresis is
used. If the input signal is a pulse waveform, with relatively
fast rise and fall times, hysteresis is not required.
All pins of any unused comparators should be tied to the neg-
ative supply.
The bias network of the LM139 series establishes a drain
current which is independent of the magnitude of the power
supply voltage over the range of from 2 VDC to 30 VDC.
It is usually unnecessary to use a bypass capacitor across the
power supply line.
The differential input voltage may be larger than V+ without
damaging the device. Protection should be provided to pre-
vent the input voltages from going negative more than −0.3
VDC (at 25°C). An input clamp diode can be used as shown
in the applications section.
The output of the LM139 series is the uncommitted collector
of a grounded-emitter NPN output transistor. Many collectors
can be tied together to provide an output OR'ing function. An
output pull-up resistor can be connected to any available
power supply voltage within the permitted supply voltage
range and there is no restriction on this voltage due to the
magnitude of the voltage which is applied to the V+ terminal
of the LM139A package. The output can also be used as a
simple SPST switch to ground (when a pull-up resistor is not
used). The amount of current which the output device can sink
is limited by the drive available (which is independent of V+)
and the β of this device. When the maximum current limit is
reached (approximately 16 mA), the output transistor will
come out of saturation and the output voltage will rise very
rapidly. The output saturation voltage is limited by the ap-
proximately 60Ω RSAT of the output transistor. The low offset
voltage of the output transistor (1 mV) allows the output to
clamp essentially to ground level for small load currents.
Typical Applications
(V+ = 5.0 VDC)
Basic Comparator
20122103
Driving CMOS
20122104
Driving TTL
20122105
AND Gate
20122108
OR Gate
20122109
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LM139AQML/LM139QML
Typical Applications
(V+= 15 VDC)
One-Shot Multivibrator
20122110
Bi-Stable Multivibrator
20122111
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LM139AQML/LM139QML
One-Shot Multivibrator with Input Lock Out
20122112
Pulse Generator
20122117
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LM139AQML/LM139QML
Large Fan-In AND Gate
20122113
ORing the Outputs
20122115
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LM139AQML/LM139QML
Time Delay Generator
20122114
Non-Inverting Comparator with Hysteresis
20122118
Inverting Comparator with Hysteresis
20122119
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LM139AQML/LM139QML
Squarewave Oscillator
20122116
Basic Comparator
20122121
Limit Comparator
20122124
Comparing Input Voltages
of Opposite Polarity
20122120
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LM139AQML/LM139QML
Output Strobing
20122122
* Or open-collector logic gate without pull-up resistor
Crystal Controlled Oscillator
20122125
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LM139AQML/LM139QML
Two-Decade High-Frequency VCO
20122123
V+ = +30 VDC
250 mVDC ≤ VC ≤ +50 VDC
700 Hz ≤ fO ≤ 100 kHz
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LM139AQML/LM139QML
Transducer Amplifier
20122128
Zero Crossing Detector (Single Power Supply)
20122130
Split-Supply Applications
(V+ = +15 VDC and V− = −15 VDC)
MOS Clock Driver
20122131
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LM139AQML/LM139QML
Zero Crossing Detector
20122132
Comparator With a Negative Reference
20122133
Schematic Diagram
20122101
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LM139AQML/LM139QML
Revision History
Date Released Revision Section Changes
02/08/05 A New Release to corporate format 3 MDS datasheets converted into one Corp.
datasheet format. MNLM139A-X-RH rev 4B0,
MDLM139A-X rev 0C1, MNLM139–X rev 1A1.
MDS datasheets will be archived.
06/28/06 B Features, Ordering Information Table, Rad
Hard Electrical Section and Notes
Added Available with Radiation Guarantee, Low
Dose NSID's to table 5962R9673802VCA
LM139AJRLQMLV, 5962R9673802VDA
LM139AWRLQMLV, 5962R9673802VXA
LM139AWGRLQMLV, and reference to Note 11
and 16. Note 16 to Rad Hard Electrical Heading.
Note 16 to Notes. Archive Revision A.
02/13/08 C Features, Ordering Table, LM139A 883,
QMLV & RH, SMD 5962–9673801
Electrical Characteristics, Notes
Added TID & Eldrs reference, Note 11 - Condition
A. Changed VCM parameter - pg 8, Title from Drift
Values to Delta Values - pg 9 & Note 16. Revision
B will be Archive .
10/15/2010 D Data Sheet Title, Ordering Table, Changed the data sheet title from LM139A/
LM139QML to LM139AQML/LM139QML,
removed EOL NSID's. Added Bare Die NSID's.
Revision C will be Archived
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LM139AQML/LM139QML
Physical Dimensions inches (millimeters) unless otherwise noted
Leadless Chip Carrier (E))
NS Package Number E20A
Ceramic Dual-In-Line Package (J)
NS Package Number J14A
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LM139AQML/LM139QML
Ceramic Flat Package (W)
NS Package Number W14B
Ceramic SOIC (WG)
NS Package Number WG14A
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LM139AQML/LM139QML
Notes
LM139AQML/LM139QML Low Power Low Offset Voltage Quad Comparators
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