ac XRK4991 PRELIMINARY 3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER FEBRUARY 2004 REV. P1.0.0 FUNCTIONAL DESCRIPTION The XRK4991 3.3/2.5V High-Speed Low-Voltage Programmable Skew Clock Buffer offers user selectable control over system clock functions. Eight individual drivers, arranged as four pairs of usercontrollable outputs, can each drive terminated transmission lines with impedances as low as 50 while delivering minimal and specified output skews and full-swing logic levels (LVTTL). Each output can be hardwired to one of nine delay or function configurations. Delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs able to skew up to 6 time units from their nominal "zero" skew position. The completely integrated PLL allows external load and transmission line delay effects to be canceled. When this "zero delay" capability is combined with the selectable output skew functions, the user can create output-tooutput delays of up to 12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions allow distribution of a lowfrequency clock that can be multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility. FEATURES * All output pair skew <100 ps typical (250 max.) * 3.75- to 100-MHz output operation * User-selectable output functions -Selectable skew to 18 ns -Inverted and non-inverted -Operation at 1/2 and 1/4 input frequency -Operation at 2x and 4x input frequency (input as low as 3.75 MHz) * Zero input-to-output delay * 50% duty-cycle outputs * LVTTL outputs drive 50 terminated lines * Operates from a single 3.3/2.5V supply * Low operating current * 32-pin PLCC package * Jitter < 200 ps peak-to-peak (< 25 ps RMS) * Green packaging FIGURE 1. BLOCK DIAGRAM OF THE XRK4991 TEST FB PHASE FREQ DET REF FILTER VCO AND TIME UNIT GENERATOR FS 4Q0 4F0 4F1 4Q1 Select Inputs 3F0 SKEW 3Q0 3F1 SELECT 3Q1 2Q0 2F0 MATRIX 2F1 2Q1 1F0 1Q0 1F1 1Q1 Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com ac PRELIMINARY XRK4991 3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER REV. P1.0.0 PRODUCT ORDERING INFORMATION PRODUCT NUMBER ACCURACY OPERATING TEMPERATURE RANGE XRK4991CJ-2 250 ps 0C to +70C XRK4991IJ-5 500 ps -40C to +85C XRK4991CJ-5 500 ps 0C to +70C XRK4991CJ-7 750 ps 0C to +70C 3F0 FS VCCQ REF GND TEST 2F1 FIGURE 2. PIN OUT OF THE XRK4991 4 3 2 1 32 31 30 3F1 5 29 2F0 4F0 6 28 GND 4F1 7 27 1F1 VCCQ 8 26 1F0 VCCN 9 25 VCCN 4Q1 10 24 1Q0 4Q0 11 23 1Q1 GND 12 22 GND GND 13 21 GND VCCN 18 19 20 2Q0 3Q0 17 2Q1 16 VCCN 15 FB 14 3Q1 XRK4991 2 ac PRELIMINARY 3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER XRK4991 REV. P1.0.0 PIN DESCRIPTIONS PIN NAME TYPE DESCRIPTION REF I Reference frequency input. This input supplies the frequency and timing against which all functional variation is measured. FB I PLL feedback input (typically connected to one of the eight outputs). FS I Three-level frequency range select. Set Table 1. 1F0, 1F1 I Three-level function selects inputs for output pair 1 (1Q0, 1Q1). See Table 2. 2F0, 2F1 I Three-level function selects inputs for output pair 2 (2Q0, 2Q1). See Table 2. 3F0, 3F1 I Three-level function selects inputs for output pair 3 (3Q0, 3Q1). See Table 2. 4F0, 4F1 I Three-level function selects inputs for output pair 4 (4Q0, 4Q1). See Table 2. TEST I Three-level select. See test mode section under the block diagram descriptions. 1Q0, 1Q1 O Output pair 1. See Table 2. 2Q0, 2Q1 O Output pair 2. See Table 2. 3Q0, 3Q1 O Output pair 3. See Table 2. 4Q0, 4Q1 O Output pair 4. See Table 2. VCCN PWR Power supply for output drivers. VCCQ PWR Power supply for internal circuitry. GND PWR Ground. 3 ac PRELIMINARY XRK4991 3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER REV. P1.0.0 TABLE 1: FREQUENCY RANGE SELECT AND tU CALCULATION [1] fNOM (MHZ) tU = 1 / fNOM X N APPROXIMATE FREQUENCY (MHZ) AT FS[2,3] MIN MAX LOW 15 30 44 22.7 MID 25 50 26 38.5 HIGH 40 100 16 62.5 WHERE N= WHICH tU = 1.0ns SKEW SELECT MATRIX The skew select matrix is comprised of four independent sections. Each section has two low-skew, high-fanout drivers (xQ0, xQ1), and two corresponding three-level function select (xF0, xF1) inputs. Table 2 below shows the nine possible output functions for each section as determined by the function select inputs. All times are measured with respect to the REF input assuming that the output connected to the FB input has 0tU selected. TABLE 2: PROGRAMMABLE SKEW CONFIGURATIONS [1] FUNCTION SELECTS OUTPUT FUNCTIONS 1F1, 2F1, 3F1, 4F1 1F0, 2F0, 3F0, 4F0 1Q0, 1Q1, 2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1 LOW LOW -4tU Divide by 2 Divide by 2 LOW MID -3tU -6tU -6tU LOW HIGH -2tU -4tU -4tU MID LOW -1tU -2tU -2tU MID MID 0tU 0tU 0tU MID HIGH +1tU +2tU +2tU HIGH LOW +2tU +4tU +4tU HIGH MID +3tU +6tU +6tU HIGH HIGH +4tU Divide by 4 Inverted NOTES: 1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 2. The level to be set on FS is determined by the "normal" operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency (fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs will be fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication by using a divided output as the FB input. 3. When the FS pin is selected HIGH, the REF input must not transition upon power-up until VCC has reached 2.8V. 4 ac PRELIMINARY XRK4991 3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER REV. P1.0.0 t0+6tU t0+5tU t0+4tU t0+3tU t0+2tU t0+1tU t0 t0-1tU t0-2tU t0-3tU t0-4tU t0-5tU t0-6tU FIGURE 3. TYPICAL OUTPUTS WITH FB CONNECTED TO A ZERO-SKEW OUTPUT [4] FBInput 1Fx 2Fx (N/A) LL LM LH ML MM MH HL HM HH (N/A) (N/A) 3Fx 4Fx LM LH (N/A) ML (N/A) MM (N/A) MH (N/A) HL HM LL/HH REFInput (N/A) HH INVERT -6tU -4tU -3tU -2tU -1tU 0tU +1tU +2tU +3tU +4tU +6tU DIVIDED NOTES: 4. FB connected to an output selected for "zero" skew (i.e. xF1 = xF0 = MID). TEST MODE The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the XRK4991 to operate as explained briefly above (for testing purposes, any of the three-level inputs can have a removable jumper to ground, or be tied LOW through a 100 resistor. This will allow an external tester to change the state of these pins.) If the TEST input is forced to its MID or HIGH state, the device will operate with its internal phase locked loop disconnected, and input levels supplied to REF will directly control all outputs. Relative output to output functions are the same as in normal mode. In contrast with normal operation (TEST tied LOW). All outputs will function based only on the connection of their own function select inputs (xF0 and xF1) and the waveform characteristics. 5 ac PRELIMINARY XRK4991 3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER REV. P1.0.0 MAXIMUM RATINGS ABOVE WHICH THE USEFUL LIFE MAY BE IMPAIRED. FOR USER GUIDELINES, NOT TESTED. Storage Temperature -65C to +150C Ambient Temperature with Power Applied -55C to +125C Supply Voltage to Ground Potential .-0.5V to +7.0V DC Input Voltage -0.5V to +7.0V Output Current into Outputs (LOW) 64 mA Static Discharge Voltage (per MIL-STD-883, Method 3015) >2001V Latch-Up Current. >200 mA OPERATING RANGE RANGE AMBIENT TEMPERATURE VCC Industrial -40C to +85C 2.5V + 5%/3.3 + 10% Commercial 0C to +70C 2.5V + 5%/3.3 + 10% ELECTRICAL CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE [5] SYMBOL DESCRIPTION VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage (REF and FB inputs only) VIL Input LOW Voltage (REF and FB inputs only) VIHH Three-Level Input HIGH Voltage (Test, FS, xFn) VIMM VILL 2.4 UNIT CONDITION V VCC = Min., IOH = -18mA 0.45 V VCC = Min., IOL = 35mA 2.0 VCC V -0.5 0.8 V 0.87*VCC VCC V Min. < VCC < Max. 0.47*VCC 0.53 * VCC V Min. < VCC < Max. 0.0 0.13 * VCC V Min. < VCC < Max. 20 VCC = Max., VIN = Max. VCC = Max., VIN = 0.4V 200 VIN = VCC 50 A VIN = VCC/2 [6] Three-Level Input LOW Voltage (Test, FS, xFn) MAX [6} Three-Level Input MID Voltage (Test, FS, xFn) MIN [6] IIH Input HIGH Leakage Current (REF and FB inputs only) IIL Input LOW Leakage Current (REF and FB inputs only) IIHH Input HIGH Current (Test, FS, xFn) IIMM Input MID Current (Test, FS, xFn) -20 -50 6 ac PRELIMINARY XRK4991 3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER REV. P1.0.0 ELECTRICAL CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE [5] SYMBOL DESCRIPTION MIN MAX UNIT CONDITION IILL Input LOW Current (Test, FS, xFn) -200 A VIN = GND IOS Short Circuit Current [7] -200 mA VCC = Max, VOUT = GND (25 only) ICCQ ICCN Operating Current Used by Internal Circuitry Com'l 95 Mil/Ind 100 19 Output Buffer Current per Output Pair [8] mA VCCN = VCCQ = Max., All Inputs Selects Open mA VCCN = VCCQ = Max., IOUT = 0 mA Inputs Selects Open, fMAX PD 104 Power Dissipation per Output Pair [9] mW VCCN = VCCQ = Max., IOUT = 0 mA Input Selects Open, fMAX ELECTRICAL CHARACTERISTICS OVER THE 2.5V + 5% OPERATING RANGE [5] SYMBOL DESCRIPTION VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage (REF and FB inputs only) VIL Input LOW Voltage (REF and FB inputs only) VIHH Three-Level Input HIGH Voltage (Test, FS, xFn) VIMM VILL 2.0 UNIT CONDITION V VCC = Min., IOH = TBD 0.4 V VCC = Min., IOL = TBD 1.7 VCC V -0.5 0.7 V 0.87*VCC VCC V Min. < VCC < Max. 0.47*VCC 0.53 * VCC V Min. < VCC < Max. 0.0 0.13 * VCC V Min. < VCC < Max. 20 VCC = Max., VIN = Max. VCC = Max., VIN = 0.4V 200 VIN = VCC 50 A VIN = VCC/2 [6] Three-Level Input LOW Voltage (Test, FS, xFn) MAX [6} Three-Level Input MID Voltage (Test, FS, xFn) MIN [6] IIH Input HIGH Leakage Current (REF and FB inputs only) IIL Input LOW Leakage Current (REF and FB inputs only) IIHH Input HIGH Current (Test, FS, xFn) IIMM Input MID Current (Test, FS, xFn) -20 -50 7 ac PRELIMINARY XRK4991 3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER REV. P1.0.0 ELECTRICAL CHARACTERISTICS OVER THE 2.5V + 5% OPERATING RANGE [5] SYMBOL DESCRIPTION MIN MAX UNIT CONDITION IILL Input LOW Current (Test, FS, xFn) -200 A VIN = GND IOS Short Circuit Current [7] -200 mA VCC = Max, VOUT = GND (25 only) ICCQ ICCN Operating Current Used by Internal Circuitry Com'l TBD Mil/Ind TBD TBD Output Buffer Current per Output Pair [8] mA VCCN = VCCQ = Max., All Inputs Selects Open mA VCCN = VCCQ = Max., IOUT = 0 mA Inputs Selects Open, fMAX PD TBD Power Dissipation per Output Pair [9] mW VCCN = VCCQ = Max., IOUT = 0 mA Input Selects Open, fMAX CAPACITANCE SYMBOL CIN DESCRIPTION Input Capacitance MAX. UNIT 10 pF CONDITION TA = 25C, f=1 MHz, VCC = 3.3/2.5V NOTES: 5. See the last page of this specification for Group A subgroup testing information. 6. These inputs are normally wired to VCC, GND or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an addtional tLOCK time before all data sheet limits are achieved. 7. XRK4991 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. 8. Total output current per output pair can be approximated by the following expression that includes device current plus load current: XRK4991: ICCN = [(4+0.11F) + [[((835-3F)/Z + (.0022FC)]N] x 1.1 Where: F = frequency in MHz C = capacitive load in pF Z = line impedance in ohms N = number of loaded outputs; 0, 1, or 2 FC = F < C 9. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to the load circuit: PD = [(22 + 0.61F) + [[(1550 + 2.7F)/Z) + (.0125FC)]N] x 1.1 See note 8 for variable definition. 10. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters. 8 ac PRELIMINARY XRK4991 3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER REV. P1.0.0 FIGURE 4. TTL AC TEST LOAD VCC R1 CL R1 = 100 R2 = 100 CL = 30pF (includes fixture and probe capacitance R2 FIGURE 5. TTL INPUT TEST WAVEFORM 3.0V 2.0V 2.0V Vth = 1.5V Vth = 1.5V 0.8V 0.8V 0.0V <1ns <1ns SWITCHING CHARACTERISTICS OVER THE OPERATING RANGE [2,11] SYMBOL fNOM DESCRIPTION Operating Clock Frequency in MHz MIN MAX UNIT FS = LOW [1, 2] 15 30 MHz FS = MID [1, 2] 25 50 FS = HIGH [1, 2, 3] 40 100 9 ac PRELIMINARY XRK4991 3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER REV. P1.0.0 SWITCHING CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE [2,11] XRK4991-2 SYMBOL XRK4991-5 XRK4991-7 UNIT DESCRIPTION MIN TYP MAX MIN TYP MAX MIN TYP MAX tRPWH REF Pulse Width HIGH 5 5 5 ns tRPWL REF Pulse Width LOW 5 5 5 ns tu tSKEWPR Programmable Skew Unit See Table 1 Zero Output Matched-Pair Skew (XQ0, XQ1) [13, 14] 0.05 0.2 0.1 0.25 0.1 0.25 ns tSKEW0 Zero Output Skew (All Outputs) [13, 15] 0.1 0.25 0.25 0.5 0.3 0.75 ns tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs 0.1 0.5 0.6 0.7 0.6 1 ns tSKEW2 Output Skew (Rise-Fall, NominalInverted, Divided-Divided) [13, 17] 0.5 1 0.5 1 1 1.5 ns tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs) [13, 17] 0.25 0.5 0.5 0.7 0.7 1.2 ns tSKEW4 Output Skew (Rise-Fall, NominalDivided, Divided-Inverted [13, 17] 0.5 0.9 0.5 1 1.2 1.7 ns 1.65 ns tDEV Device-to-Device Skew [12, 18] tPD Propagation Delay, REF Rise to FB Rise -0.25 0 0.25 -0.5 0 0.5 -0.7 0 0.7 ns tODCV Output Duty Cycle Variation [19] -.65 0 .65 -1 0 1 -1.2 0 1.2 ns tPWH Output HIGH Time Deviation from 50% 1.25 1.25 2 2.5 3 ns 1.5 3 3.5 ns [20] tPWL Output LOW Time Deviation from 50% [20] tORISE Output Rise Time [20, 21] 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns tOFALL Output Fall Time [20, 21] 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns tLOCK PLL Lock Time [22] tJR Cycle-to-Cycle Output Jitter 0.5 0.5 0.5 ms RMS [12] 25 25 25 ps Peak-to-Peak 200 200 200 [12] NOTES: 11. Test measurement levels for the XRK4991 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 10 ac PRELIMINARY XRK4991 3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER REV. P1.0.0 13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 30pF and terminated with 50 to VCC/2 (XRK4991). 14. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU. 15. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Ohter outputs are divided or inverted but not shifted. 16. CL = 0pF. For CL = 30pF, tSKEW0 = 0.35ns. 17. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode). 18. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.) 19. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. 20. Specified with outputs loaded with 30pF for the XRK4991-5 and -7 devices. Devices are terminated through 50 to VCC/2. tPWH is measured at 2.0V. tPWL is measured at 0.8V. 21. tORISE and tOFALL measured between 0.8V and 2.0V. 22. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits FIGURE 6. AC TIMING DIAGRAM tREF tRPWH tRPWL REF tPD tODCV tODCV FB tJR Q tSKEWPR, tSKEW0, 1 tSKEWPR, tSKEW0, 1 OTHER Q tSKEW2 tSKEW2 INVERTED Q tSKEW3, 4 tSKEW3, 4 tSKEW3, 4 REF DIVIDED BY 2 tSKEW1, 3, 4 tSKEW2, 4 REF DIVIDED BY 4 11 ac PRELIMINARY XRK4991 3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER REV. P1.0.0 SWITCHING CHARACTERISTICS OVER THE 2.5V + 5% OPERATING RANGE [2,11] SYMBOL XRK4991-2 XRK4991-5 XRK4991-7 MIN MIN MIN UNIT DESCRIPTION MAX MAX MAX tRPWH REF Pulse Width HIGH 5 5 5 ns tRPWL REF Pulse Width LOW 5 5 5 ns tu tSKEWPR Programmable Skew Unit See Table 1 Zero Output Matched-Pair Skew (XQ0, XQ1) 0.2 0.25 0.25 ns [13, 14] tSKEW0 Zero Output Skew (All Outputs) [13, 15] 0.25 0.5 0.75 ns tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs 0.5 0.7 1 ns tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided) [13, 17] 1 1 1.5 ns tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Class Outputs) [13, 17] 0.5 0.7 1.2 ns tSKEW4 Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted [13, 17] 0.9 1 1.7 ns tDEV Device-to-Device Skew [12, 18] 1.25 1.25 1.65 ns tPD Propagation Delay, REF Rise to FB Rise -0.25 0.25 -0.5 0.5 -0.7 0.7 ns tODCV Output Duty Cycle Variation [19] -.65 1 -.65 1 -1.2 1.2 ns tPWH Output HIGH Time Deviation from 50% [20] 2 2.5 3 ns tPWL Output LOW Time Deviation from 50% [20] 1.5 3 3.5 ns Different tORISE Output Rise Time [20, 21] 0.15 1.2 0.15 1.5 0.15 2.5 ns tOFALL Output Fall Time [20, 21] 0.15 1.2 0.15 1.5 0.15 2.5 ns tLOCK PLL Lock Time [22] tJR Cycle-to-Cycle Output Jitter 0.5 0.5 0.5 ms RMS [12] 25 25 25 ps Peak-to-Peak [12] 200 200 200 12 ac PRELIMINARY XRK4991 3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER REV. P1.0.0 PACKAGE DIMENSIONS 32 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) Rev. 1.00 D A1 D1 A2 30 x H1 2 1 32 45 x H2 B1 Corner Chamfer E1 E3 B E D2 e 72 deg typ. C R D3 A INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.120 0.140 3.05 3.56 A1 0.075 0.095 1.91 2.41 A2 0.020 --0.51 --B 0.013 0.021 0.33 0.53 B1 0.026 0.032 0.66 0.81 C 0.008 0.013 0.19 0.32 D 0.485 0.495 12.33 12.58 D1 0.448 0.454 11.39 11.54 D2 0.400 0.440 10.17 11.18 0.300 typ. 7.62 typ. D3 E 0.585 0.595 14.87 15.11 E1 0.545 0.557 13.85 14.15 E2 0.500 0.540 12.71 13.72 0.400 typ. 10.16 typ. E3 0.050 BSC 1.27 BSC e H1 0.023 0.029 0.58 0.74 H2 0.042 0.048 1.07 1.22 R 0.025 0.045 0.64 1.14 Note: The control dimension is in inches. 13 SEATING PLANE ac PRELIMINARY XRK4991 3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER REV. P1.0.0 REVISION HISTORY REVISION # P1.0.0 DATE DESCRIPTION February 2004 Initial release NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2004 EXAR Corporation Datasheet February 2004. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 14