XRK4991 - Exar Corporation

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www . exa r .c om

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PRELIMINARY

XRK4991

3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

FEBRUARY 2004 REV. P1.0.0

FUNCTIONAL DESCRIPTION

The XRK4991 3.3/2.5V High-Speed Low-Voltage

Programmable Skew Clock Buffer offers user

selectable control over system clock functions. Eight

individual drivers, arranged as four pairs of user-

controllable outputs, can each drive terminated

transmission lines with impedances as low as 50Ω

while delivering minimal and specified output skews

and full-swing logic levels (LVTTL).

Each ou tpu t c an be h ar dwi red to one of ni ne de lay or

function configurations. Delay increments of 0.7 to

1.5 ns are determined by the operating frequency

with outputs able to skew up to ±6 time units from

their nominal “zero” skew position. The completely

integrated PLL all ows exter nal load and transmis sion

line delay effects to be canceled. When this “zero

delay” capability is combined with the selectable

output skew functions, the user can creat e output-to-

output delays of up to ±12 time units.

Divide-by-two and divide-by-four output functions are

provided for addition al flexibi lity in de signing complex

clock systems. When combined with the internal PLL,

these divide functions allow distribution of a low-

frequency clock that can be multiplied by two or four

at the clock destination. This facility minimizes clock

distribution difficulty while allowing maximum system

clock speed and flexibility.

FEATURES

•All output pair skew <100 ps typical (250 max.)

•3.75- to 100-MHz output operation

•User-selectable output functions

-Selectable ske w to 18 ns

-Inverted and non-inverted

-Operation at 1/2 and 1/4 input frequency

-Operation at 2x and 4x input frequency (input

as low as 3.75 MHz)

•Zero input-to-output delay

•50% duty-cycle outputs

•LVTTL outputs drive 50Ω terminated lines

•Operates from a single 3.3/2.5V supply

•Low operating current

•32-pin PLCC package

•Jitter < 200 ps peak-to-peak (< 25 ps RMS)

•Gree n packaging

FIGURE 1. BLOCK DIAGRAM OF THE XRK4991

VCO AND TIME

UNIT GENERATOR

SKEW

SELECT

MATRIX

PHASE

FREQ

DET FILTER

REF

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

TEST

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

Select Inputs

XRK4991

PRELIMINARY

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REV. P1.0.0

3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

PR ODUCT OR DERING INFORMATION

PRODUCT NUMBER ACCURACY OPERATING TEMPERATURE RANGE

XRK4991CJ-2 250 ps 0°C to +70°C

XRK4991IJ-5 500 ps -40°C to +85°C

XRK4991CJ-5 500 ps 0°C to +70°C

XRK4991CJ-7 750 ps 0°C to +70°C

FIGURE 2. PIN OUT OF THE XRK4991

3Q1

3Q0

VCCN

2Q1

2Q0

XRK4991

3F0

VCCQ

REF

GND

TEST

2F1

3F1

4F0

4F1

VCCQ

VCCN

4Q1

4Q0

GND

2F0

GND

1F1

1F0

VCCN

1Q0

1Q1

GND

14 15 16 17 18 19 20

4321323130

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PRELIMINARY

XRK4991

3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

REV. P1.0.0

PIN DESCRIPTIONS

PIN NAME TYPE DESCRIPTION

REF I Reference frequency input. This input supplies the frequency and timing against

which all functional variation is measured.

FB I PLL feedback input (typically connected to one of the eight outputs).

FS I Three-level frequency range select. Set Table 1.

1F0, 1F1 I Three-level function selects inputs for output pair 1 (1Q0, 1Q1). See Table 2.

2F0, 2F1 I Three-level function selects inputs for output pair 2 (2Q0, 2Q1). See Table 2.

3F0, 3F1 I Three-level function selects inputs for output pair 3 (3Q0, 3Q1). See Table 2.

4F0, 4F1 I Three-level function selects inputs for output pair 4 (4Q0, 4Q1). See Table 2.

TES T I Three-level select. See test mode section under the block diagram descrip tions.

1Q0, 1Q1 O Out put pair 1. See Table 2.

2Q0, 2Q1 O Out put pair 2. See Table 2.

3Q0, 3Q1 O Out put pair 3. See Table 2.

4Q0, 4Q1 O Out put pair 4. See Table 2.

VCCN PWR Power supply for output drivers.

VCCQ PWR Power supply for internal circuitry.

GND PWR Ground.

XRK4991

PRELIMINARY

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REV. P1.0.0

3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

SKEW SELECT MATRIX

The skew select matrix is comprised of four independent sections. Each section has two low-skew, high-fanout

dri vers ( xQ0, xQ1), and two corres ponding three -level functi on select ( xF0, xF1) in puts. Table 2 bel ow shows

the nine possible output functions for each section as determined by the function select inputs. All times are

measured with respect to the REF input assuming that the output connected to the FB input has 0tU sele ct ed .

OTES

1. For all three-state inputs, HIGH indicates a connection to V

, LOW indicates a connection to GND, and MID

indicates an open connection. Internal termination circuitry holds an unconnected input to V

/2.

2. The level to be set on FS is determined by the “normal” operating frequency (f

NOM

) of the V

and Time Unit

Generator (see Logic Block Diagram). Nominal frequency (f

NOM

) always appears at 1Q0 and the other outputs

when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB

inp uts wi ll be f

NOM

when the output connected to FB is undivided. The frequency of the REF and FB inputs will be

NOM

/2 or f

NOM

/4 when the part is configured for a frequency multiplication by using a divided output as the FB

input.

3. When the FS p in i s s ele cte d H IG H, the REF input must not transition upo n power-up un til V

has reach ed 2. 8V.

TABLE 1: FREQUENCY RANGE SELECT AND tU CALCULATION [1]

fNOM (MHZ)tU = 1 / fNOM X N APPROXIMATE

FREQUENCY (MHZ) AT

WHICH tU = 1. 0ns

FS[2,3] MIN MAX WHERE N =

LOW15304422.7

MID25502638.5

HIGH 40 100 16 62.5

TABLE 2: PROGRAMMABLE SKEW CONFIGURATIONS [1]

FUNCTION SELECTS OUTPUT FUNCTIONS

1F1, 2F1, 3F1, 4F1 1F0, 2F0, 3F0, 4F0 1Q0, 1Q1, 2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1

LOW LOW -4tUDivide by 2 Divide by 2

LOW MID -3tU-6tU-6tU

LOW HIGH -2tU-4tU-4tU

MID LOW -1tU-2tU-2tU

MID MID 0tU0tU0tU

MID HIGH +1tU+2tU+2tU

HIGH LOW +2tU+4tU+4tU

HIGH MID +3tU+6tU+6tU

HIGH HIGH +4tUDivide by 4 Inverted

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PRELIMINARY

XRK4991

3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

REV. P1.0.0

OTES

4. FB connected to an output selected fo r "zero" skew (i.e. xF1 = xF0 = MID).

TEST MODE

The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the

XRK4991 to operate as explained bri efly above (for te sting pur pos es, any of the three-level inputs can have a

removable jumper to ground, or be tied LOW through a 100Ω resistor. This will allow an external tester to

change the state of these pins.)

If the TEST input is for ced to its MID or HIGH state, the dev ice will operate with its inte r nal phase locked loop

disconnected, and input levels supplied to REF will directly control all outputs. Relative output to output

functions are the same as in normal mode.

In contrast with nor mal operation (TEST tied LOW). All outputs will function based only on the connection of

their own function select inputs (xF0 and xF1) and the waveform characteristics.

FIGURE 3. TYPICAL OUTPUTS WITH FB CONNECTED TO A ZERO-SKEW OUTPUT [4]

(N/A) LM

LL LH

LM (N/A)

LH ML

ML (N/A)

MM MM

MH (N/A)

HL MH

HM (N/A)

HH HL

(N/A) HM

(N/A) LL/HH

(N/A) HH

-6tU

-4tU

-3tU

-2tU

-1tU

0tU

+1tU

+2tU

+3tU

+4tU

+6tU

DIVIDED

INVERT

1Fx 3Fx

2Fx 4Fx

FBInput

REFInput

t0-6tU

t0-5tU

t0-4tU

t0-3tU

t0-2tU

t0-1tU

t0+1tU

t0+2tU

t0+3tU

t0+4tU

t0+5tU

t0+6tU

XRK4991

PRELIMINARY

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REV. P1.0.0

3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

MAXIMUM RATINGS

OPERATING RANGE

ABOVE WHICH THE USEFUL LIFE MAY BE IMPAIRED. FOR USER GUIDELINES, NOT TESTED.

Storage Temperature –65°C to +150°C

Ambient Temperature with Power Applied –55°C to +125°C

Supply Voltage to Ground Potential .–0.5V to +7.0V

DC Input Voltage –0.5V to +7.0V

Output Current into Outputs (LOW) 64 mA

Static Discharge Voltage (per MIL-STD-883, Method 3015) >2001V

Latch-Up Current. >200 mA

RANGE AMBIENT TEMPERATURE VCC

Industrial -40°C to +85°C2.5V + 5%/3.3 + 10%

Commercial 0°C to +70°C2.5V + 5%/3.3 + 10%

ELECTRICAL CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE [5]

SYMBOL DESCRIPTION MIN MAX UNIT CONDITION

VOH Output HIGH Voltage 2.4 V VCC = Min., IOH = -18mA

VOL Output LOW Voltage 0.45 V VCC = Min., IOL = 35mA

VIH Input HIGH Voltage

(REF and FB inputs only) 2.0 VCC V

VIL Input LOW Voltage

(REF and FB inputs only) -0.5 0.8 V

VIHH Three-Level Input HIGH Voltage

(Test, FS, xFn) [6} 0.87*VCC VCC VMin. < VCC < Max.

VIMM Three-Level Input MID Voltage

(Test, FS, xFn) [6] 0.47*VCC 0.53 * VCC VMin. < VCC < Max.

VILL Three-Level Input LOW Voltage

(Test, FS, xFn) [6] 0.0 0.13 * VCC VMin. < VCC < Max.

IIH Input HIGH Leakage Current

(REF and FB inputs only) 20 µΑ VCC = Max., VIN = Max.

IIL Input LOW Leakage Current

(REF and FB inputs only) -20 µΑ VCC = Max., VIN = 0.4V

IIHH Input HIGH Current

(Test, FS, xFn) 200 µΑ VIN = VCC

IIMM Input MID Current

(Test, FS, xFn) -50 50 µAV

IN = VCC/2

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PRELIMINARY

XRK4991

3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

REV. P1.0.0

IILL Inpu t LOW Current

(Test, FS, xFn) -200 µAV

IN = GND

IOS Short Circuit Current [7] -200 mA VCC = Max,

VOUT = GND (25° only)

ICCQ Operating Current Used by Inter-

nal Circuitry Com’l 95 mA VCCN = VCCQ = Max.,

All Inputs Selects Open

Mil/Ind 100

ICCN Output Buffer Current per Output Pair [8] 19 mA VCCN = VCCQ = Max.,

IOUT = 0 mA

Inputs Selects Open, fMAX

PD Power Dissipation per Output Pair [9] 104 mW VCCN = VCCQ = Max.,

IOUT = 0 mA

Input Selects Open, fMAX

ELECTRICAL CHARACTERISTICS OVER THE 2.5V + 5% OPERATING RANGE [5]

SYMBOL DESCRIPTION MIN MAX UNIT CONDITION

VOH Output HIGH Voltage 2.0 V VCC = Min., IOH = TBD

VOL Output LOW Voltage 0.4 V VCC = Min., IOL = TBD

VIH Input HIGH Voltage

(REF and FB inputs only) 1.7 VCC V

VIL Input LOW Voltage

(REF and FB inputs only) -0.5 0.7 V

VIHH Three-Level Input HIGH Voltage

(Test, FS, xFn) [6} 0.87*VCC VCC VMin. < VCC < Max.

VIMM Three-Level Input MID Voltage

(Test, FS, xFn) [6] 0.47*VCC 0.53 * VCC VMin. < VCC < Max.

VILL Three-Level Input LOW Voltage

(Test, FS, xFn) [6] 0.0 0.13 * VCC VMin. < VCC < Max.

IIH Input HIGH Leakage Current

(REF and FB inputs only) 20 µΑ VCC = Max., VIN = Max.

IIL Input LOW Leakage Current

(REF and FB inputs only) -20 µΑ VCC = Max., VIN = 0 .4V

IIHH Input HIGH Current

(Test, FS, xFn) 200 µΑ VIN = VCC

IIMM Input MID Current

(Test, FS, xFn) -50 50 µAV

IN = VCC/2

ELECTRICAL CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE [5]

SYMBOL DESCRIPTION MIN MAX UNIT CONDITION

XRK4991

PRELIMINARY

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REV. P1.0.0

3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

OTES

5. See the last page of this specification for Group A subgroup testing information.

6. These in puts are normally wire d to V

, GND or lef t unc onnected (actual thres ho ld voltages vary as a percentage

of V

). Internal termination resistors hold unconnected inputs at V

/2. If these inputs are switched, the

functio n and ti ming of t he outp uts may glit ch and the PLL ma y requi re an ad dti onal t

LOCK

time before all data sheet

limits are achieved.

7. XRK4991 should be tested one output at a time, output shorted for less than one second, less than 10% duty

cycl e. Room temperature only.

8. Total output current per output pair can be approximated by the following expression that includes device current

plus load current:

XRK4991: I

CCN

= [(4+0.11F) + [[((835-3F)/Z + (.0022FC)]N] x 1.1

Where:

F = frequency in MHz

C = capacitive load in pF

Z = line impedance in ohms

N = number of loaded outputs; 0, 1, or 2

FC = F

9. Total power dissipation per output pair can be approximated by the following expression that includes device

power dissipation plus power dissipation due to the load circuit:

PD = [(22 + 0.61F) + [[(1550 + 2.7F)/Z) + (.0125FC)]N] x 1.1

See note 8 for variable definition.

10. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these

parameters.

IILL Inpu t LOW Current

(Test, FS, xFn) -200 µAV

IN = GND

IOS Short Circuit Current [7] -200 mA VCC = Max,

VOUT = GND (25° only)

ICCQ Operating Current Used by Inter-

nal Circuitr y Com’l TBD mA VCCN = VCCQ = Max.,

All Inputs Selects Open

Mil/Ind TBD

ICCN Output Buffer Current per Output Pair [8] TBD mA VCCN = VCCQ = Max.,

IOUT = 0 mA

Inputs Selects Open, fMAX

PD Power Dissipation per Output Pair [9] TBD mW VCCN = V CCQ = Max.,

IOUT = 0 mA

Input Selects Open, fMAX

CAPACITANCE

SYMBOL DESCRIPTION MAX. UNIT CONDITION

CIN Input Cap acit ance 10 pF TA = 25°C, f=1 MHz,

VCC = 3.3/2.5V

ELECTRICAL CHARACTERISTICS OVER THE 2.5V + 5% OPERATING RANGE [5]

SYMBOL DESCRIPTION MIN MAX UNIT CONDITION

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PRELIMINARY

XRK4991

3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

REV. P1.0.0

FIGURE 4. TTL AC TEST LOAD

FIGURE 5. TTL INPUT TEST WAVEFORM

SWITCHING CHARACTERISTICS OVER THE OPERATING RANGE [2,11]

SYMBOL DESCRIPTION MIN MAX UNIT

fNOM Operating Clock Frequency in MHz FS = LOW [1, 2] 15 30 MHz

FS = MID [1, 2] 25 50

FS = HIGH [1, 2, 3] 40 100

CLR2

VCC

R1 = 100

R2 = 100

CL = 30pF

(includes fixture and probe capacitance

0.0V

2.0V

Vth = 1.5V

0.8V

2.0V

Vth = 1.5V

0.8V

<1ns <1ns

3.0V

XRK4991

PRELIMINARY

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REV. P1.0.0

3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

OTES

11. Test measurement levels for the XRK4991 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition

times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise

specified.

12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect

these parameters.

SWITCHING CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE [2,11]

SYMBOL DESCRIPTION XRK4991-2 XRK4991-5 XRK4991-7 UNIT

MIN TYP MAX MIN TYP MAX MIN TYP MAX

tRPWH REF Pulse Width HIGH 5 5 5 ns

tRPWL REF Pulse Width LOW 5 5 5 ns

tuProgrammable Skew Unit See Table 1

tSKEWPR Zero Output Matched-Pair Skew

(XQ0, XQ1) [13, 14] 0.05 0.2 0.1 0.25 0.1 0.25 ns

tSKEW0 Zero Output Skew (All Outputs) [13, 15] 0.1 0.25 0.25 0.5 0.3 0.75 ns

tSKEW1 Output Skew (Rise-Rise, Fall-Fall,

Same Class Outputs 0.1 0.5 0.6 0.7 0.6 1 ns

tSKEW2 Output Skew (Rise-Fall, Nominal-

Inverted, Divided-Divided) [13, 17] 0.51 0.51 11.5ns

tSKEW3 Output Skew (Rise-Rise, Fall-Fall,

Different Class Ou tpu ts) [13, 17] 0.25 0.5 0.5 0.7 0.7 1.2 ns

tSKEW4 Output Skew (Rise-Fall, Nominal-

Divide d, Divi ded -Inverted [13, 17] 0.5 0.9 0.5 1 1.2 1.7 ns

tDEV Device-to-Device Skew [12, 18] 1.25 1.25 1.65 ns

tPD Propagation Delay, REF Rise to FB

Rise -0.25 0 0.25 -0.5 0 0.5 -0.7 0 0.7 ns

tODCV Output Duty Cycle Variation [19] -.65 0 .65 -1 0 1 -1.2 0 1.2 ns

tPWH Output HIGH Time Deviation from 50%

[20] 22.53ns

tPWL Outp ut LOW Time De v iation from 50%

[20] 1.5 3 3.5 ns

tORISE Output Rise Time [20, 21]0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns

tOFALL Output Fall Time [20, 21] 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns

tLOCK PLL Lock Time [22] 0.5 0.5 0.5 ms

tJR Cycle-to-Cycle Output

Jitter RMS [12] 25 25 25 ps

Peak-to-Peak

[12] 200 200 200

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PRELIMINARY

XRK4991

3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

REV. P1.0.0

13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the

same t

delay has been selected when all are loaded with 30pF and terminated with 50

Ω

to V

/2 (XRK4991).

14. t

SKEWPR

is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for

15. t

SKEW0

is defined as the skew between outputs when they are selected for 0t

. Ohter outputs are divided or

inverted but not shifted.

16. C

= 0pF. For C

= 30pF, t

SKEW0

= 0.35ns.

17. T he r e are th re e cl as se s o f ou t put s : No min al (mul t i pl e o f t

delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 =

HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).

18. t

DEV

is the output-to-output skew between any two devices operating under the same conditions (V

ambient

temperature, air flow, etc.)

19. t

ODCV

is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t

SKEW2

and t

SKEW4

specifications.

20. Specified with outputs loaded with 30pF for the XRK4991-5 and -7 devices. Devices are terminated through 50

Ω

to V

/2. t

PWH

is measured at 2.0V. t

PWL

is measured at 0.8V.

21. t

ORISE

and t

OFALL

measured between 0.8V and 2.0V.

22. t

LOCK

is the time that is required before synchronization is achieved. This specification is valid only after V

stable and within normal operating limits. This parameter is measured from the application of a new signal or

frequency at REF or FB until t

is within specified limits

FIGURE 6. AC TIMING DIAGRAM

REF

OTHER Q

INVERTED Q

REF DIVIDED BY 2

tREF

tRPWH tRPWL

tPD tODCV tODCV

tJR

tSKEWPR,

tSKEW0, 1

tSKEWPR,

tSKEW0, 1

tSKEW2 tSKEW2

REF DIVIDED BY 4

tSKEW3, 4 tSKEW3, 4 tSKEW3, 4

tSKEW1, 3, 4 tSKEW2, 4

XRK4991

PRELIMINARY

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REV. P1.0.0

3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

SWITCHING CHARACTERISTICS OVER THE 2.5V + 5% OPERATING RANGE [2,11]

SYMBOL DESCRIPTION XRK4991-2 XRK4991-5 XRK4991-7 UNIT

MIN MAX MIN MAX MIN MAX

tRPWH REF Pulse Width HIGH 5 5 5 ns

tRPWL REF Pulse Width LOW 5 5 5 ns

tuProgrammable Skew Unit See Ta ble 1

tSKEWPR Zero Output Matched-Pair Skew (XQ0, XQ1)

[13, 14] 0.2 0.25 0.25 ns

tSKEW0 Zero Output Skew (All Outputs) [13, 15] 0.25 0.5 0.75 ns

tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same Class

Outputs 0.5 0.7 1 ns

tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted,

Divided-Divided) [13, 17] 111.5ns

tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different

Class Outputs) [13, 17] 0.5 0.7 1.2 ns

tSKEW4 Output Skew (Rise-Fall, Nominal-Divided,

Divided-Inverted [13, 17] 0.911.7ns

tDEV Device-to-Device Skew [12, 18] 1.25 1.25 1.65 ns

tPD Propagation Delay, REF Rise to FB Rise -0.25 0.25 -0.5 0.5 -0.7 0.7 ns

tODCV Output Duty Cycle Variation [19] -.65 1 -.65 1 -1.2 1.2 ns

tPWH Output HIGH Time Deviation from 50% [20] 22.53ns

tPWL Output LOW Time Deviation from 50% [20] 1.533.5ns

tORISE Output Rise Time [20, 21 ]0.15 1.2 0.15 1.5 0.15 2.5 ns

tOFALL Output Fall Time [20, 21] 0.15 1.2 0.15 1.5 0.15 2.5 ns

tLOCK PLL Lock Time [22] 0.5 0.5 0.5 ms

tJR Cycle-to-Cycle Output Jitter RMS [12] 25 25 25 ps

Peak-to-Peak [12] 200 200 200

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PRELIMINARY

XRK4991

3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

REV. P1.0.0

PACKAGE DIMENSIONS

SEATING PLANE

Corner Chamfer

30° x H1

7°±2 deg typ.

1232

45° x H2

SYMBOL MIN MAX MIN MAX

A 0.120 0.140 3.05 3.56

A1 0.075 0.095 1.91 2.41

A2 0.020 --- 0.51 ---

B 0.013 0.021 0.33 0.53

B1 0.026 0.032 0.66 0.81

C 0.008 0.013 0.19 0.32

D 0.485 0.495 12.33 12.58

D1 0.448 0.454 11.39 11.54

D2 0.400 0.440 10.17 11.18

E 0.585 0.595 14.87 15.11

E1 0.545 0.557 13.85 14.15

E2 0.500 0.540 12.71 13.72

H1 0.023 0.029 0.58 0.74

H2 0.042 0.048 1.07 1.22

R 0.025 0.045 0.64 1.14

Not e: The control di m ens i on i s i n inches .

0. 050 B S C 1. 27 B S C

INCHES MILLIMETERS

10. 16 t yp.0. 400 t yp.

0. 300 t yp. 7. 62 t yp.

32 LEAD PLASTIC LEADED CHIP CARRIER

(PLCC)

Rev. 1.00

XRK4991

PRELIMINARY

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REV. P1.0.0

3.3/2.5V HIGH-SPEED (100 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

NOTICE

EXAR Corp o ration reserves the right to ma ke chan ges to the products contained in this publicatio n i n or der t o

improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any

circuits described herein, conveys no license under any patent or other right, and makes no representation that

the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration

pur pose s and may var y dep ending upo n a use r’s specifi c applicati on. Whil e the inform ation in th is publicatio n

has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Cor poration does not recommend the use of any of its products in life suppor t applications where the

f ailure or malfunction of the product can reasonably be expected to cause failure of the life support system or to

significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless

EXAR Corporation receives, in w riting, assuranc es to its sa tisfaction that: (a) the risk of injur y o r damage has

been m inimized; (b) t he user ass umes all suc h ris ks; (c) poten tial liabil ity of EX AR Cor poration is a dequately

protected under the circumstances.

Datasheet February 2004.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

REVISION HISTORY

REVISION #D

ATE DESCRIPTION

P1.0.0 February 2004 Initial release