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TL/F/9516

54F/74F322 Octal Serial/Parallel Register with Sign Extend

May 1995

54F/74F322

Octal Serial/Parallel Register with Sign Extend

General Description

The ’F322 is an 8-bit shift register with provision for either

serial or parallel loading and with TRI-STATEÉparallel out-

puts plus a bi-state serial output. Parallel data inputs and

parallel outputs are multiplexed to minimize pin count. State

changes are initiated by the rising edge of the clock. Four

synchronous modes of operation are possible: hold (store),

shift right with serial entry, shift right with sign extend and

parallel load. An asynchronous Master Reset (MR) input

overrides clocked operation and clears the register.

Features

YMultiplexed parallel I/O ports

YSeparate serial input and output

YSign extend function

YTRI-STATE outputs for bus applications

Commercial Military Package Package Description

Number

74F322PC N20A 20-Lead (0.300×Wide) Molded Dual-In-Line

54F322DM (Note 2) J20A 20-Lead Ceramic Dual-In-Line

74F322SJ (Note 1) M20D 20-Lead (0.300×Wide) Molded Small Outline, EIAJ

54F322FM (Note 2) W20A 20-Lead Cerpack

54F322LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C

Note 1: Devices also available in 13×reel. Use suffix eSJX.

Note 2: Military grade device with environmental and burn-in processing. Use suffix eDMQB, FMQB and LMQB.

Logic Symbols

TL/F/9516–3

IEEE/IEC

TL/F/9516–5

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Connection Diagrams

Pin Assignment

for DIP, SOIC and Flatpak

TL/F/9516–1

Pin Assignment

for LCC

TL/F/9516–2

Unit Loading/Fan Out

54F/74F

Pin Names Description U.L. Input IIH/IIL

HIGH/LOW Output IOH/IOL

RE Register Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA

S/P Serial (HIGH) or Parallel (LOW) Mode Control Input 1.0/1.0 20 mA/b0.6 mA

SE Sign Extend Input (Active LOW) 1.0/3.0 20 mA/b1.8 mA

S Serial Data Select Input 1.0/2.0 20 mA/b1.2 mA

D0,D

1Serial Data Inputs 1.0/1.0 20 mA/b0.6 mA

CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 mA/b0.6 mA

MR Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA

OE TRI-STATE Output Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA

Q0Bi-State Serial Output 50/33.3 b1 mA/b20 mA

I/O0–I/O7Multiplexed Parallel Data Inputs or 3.5/1.083 70 mA/b0.65 mA

TRI-STATE Parallel Data Outputs 150/40 (33.3) b3 mA/24 mA (20 mA)

Functional Description

The ’F322 contains eight D-type edge triggered flip-flops

and the interstage gating required to perform right shift and

the intrastage gating necessary for hold and synchronous

parallel load operations. A LOW signal on RE enables shift-

ing or parallel loading, while a HIGH signal enables the hold

mode. A HIGH signal on S/P enables shift right, while a

LOW signal disables the TRI-STATE output buffers and en-

ables parallel loading. In the shift right mode a HIGH signal

on SE enables serial entry from either D0or D1, as deter-

mined by the S input. A LOW signal on SE enables shift right

but Q7reloads its contents, thus performing the sign extend

function required for the ’F384 Twos Complement Multiplier.

A HIGH signal on OE disables the TRI-STATE output buff-

ers, regardless of the other control inputs. In this condition

the shifting and loading operations can still be performed.

Mode Select Table

Mode Inputs Outputs Q0

MR RE S/P SE SOE*CP I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0

Clear L X X X X L X L L L L L L L L L

LXXXXHXZZZZZZZZL

Parallel HL LXXXLI

Load

Shift H L H H L L LD0O7O6O5O4O3O2O1O1

Right H L H H H L LD1O7O6O5O4O3O2O1O1

Sign HLHLXLLO

Extend

Hold H H X X X L LNC NC NC NC NC NC NC NC NC

*When the OE input is HIGH all I/Onterminals are at the high impedance state; sequential operation or clearing of the register is not affected.

Note 1: I7–I0eThe level of the steady-state input at the respective I/O terminal is loaded into the flip-flop while the flip-flop outputs (except Q0) are isolated from

the I/O terminal.

Note 2: D0,D

1eThe level of the steady-state inputs to the serial multiplexer input.

Note 3: O7–O0eThe level of the respective Qnflip-flop prior to the last Clock LOW-to-HIGH transition.

HeHIGH Voltage Level

LeLOW Voltage Level

ZeHigh Impedance Output State

LeLOW-to-HIGH Transition

NC eNo Change

Logic Diagram

TL/F/9516–4

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Storage Temperature b65§Ctoa

150§C

Ambient Temperature under Bias b55§Ctoa

125§C

Junction Temperature under Bias b55§Ctoa

175§C

Plastic b55§Ctoa

150§C

VCC Pin Potential to

Ground Pin b0.5V to a7.0V

Input Voltage (Note 2) b0.5V to a7.0V

Input Current (Note 2) b30 mA to a5.0 mA

Note 1: Absolute maximum ratings are values beyond which the device may

be damaged or have its useful life impaired. Functional operation under

these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Voltage Applied to Output

in HIGH State (with VCC e0V)

Standard Output b0.5V to VCC

TRI-STATE Output b0.5V to a5.5V

Current Applied to Output

in LOW State (Max) twice the rated IOL (mA)

Recommended Operating

Conditions

Free Air Ambient Temperature

Military b55§Ctoa

125§C

Commercial 0§Ctoa

70§C

Supply Voltage

Military a4.5V to a5.5V

Commercial a4.5V to a5.5V

DC Electrical Characteristics

Symbol Parameter 54F/74F Units VCC Conditions

Min Typ Max

VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal

VCD Input Clamp Diode Voltage b1.2 V Min IIN eb

18 mA

VOH Output HIGH 54F 10% VCC 2.5 IOH eb

1mA(Q

, I/On)

Voltage 54F 10% VCC 2.4 IOH eb

3 mA (I/On)

74F 10% VCC 2.5 V Min IOH eb

1mA(Q

, I/On)

74F 10% VCC 2.4 IOH eb

3 mA (I/On)

74F 5% VCC 2.7 IOH eb

1mA(Q

, I/On)

74F 5% VCC 2.7 IOH eb

3 mA (I/On)

VOL Output LOW 54F 10% VCC 0.5 IOL e20 mA (Q0, I/On)

Voltage 74F 10% VCC 0.5 V Min IOL e20 mA (Q0)

74F 10% VCC 0.5 IOL e24 mA ( I/On)

IIH Input HIGH 54F 20.0 mA Max VIN e2.7V

Current 74F 5.0

IBVI Input HIGH Current 54F 100 mA Max VIN e7.0V (Non-I/O Inputs)

Breakdown Test 74F 7.0

IBVIT Input HIGH Current 54F 1.0 mA Max VIN e5.5V (I/On)

Breakdown Test (I/O) 74F 0.5

ICEX Output HIGH 54F 250 mA Max VOUT eVCC

Leakage Current 74F 50

VID Input Leakage 74F 4.75 V 0.0 IID e1.9 mA

Test All Other Pins Grounded

IOD Output Leakage 74F 3.75 mA 0.0 VIOD e150 mV

Circuit Current All Other Pins Grounded

IIL Input LOW Current b0.6 mA Max VIN e0.5V (RE, S/P,D

, CP, MR,OE)

1.2 mA Max VINe0.5V (S)

b1.8 mA Max VINe0.5V (SE)

IIH aOutput Leakage Current 70 mA Max VI/O e2.7V (I/On)

IOZH

IIL aOutput Leakage Current b650 mA Max VI/O e0.5V (I/On)

IOZL

IOS Output Short-Circuit Current b60 b150 mA Max VOUT e0V

IZZ Bus Drainage Test 500 mA 0.0V VOUT e5.25V

ICC Power Supply Current 60 90 mA Max

AC Electrical Characteristics

74F 54F 74F

TAea

25§CTA,V

CC eMil TA,V

CC eCom

Symbol Parameter VCC ea

5.0V CLe50 pF CLe50 pF Units

CLe50 pF

Min Typ Max Min Max Min Max

fmax Maximum Clock Frequency 70 90 50 70 MHz

tPLH Propagation Delay 3.5 7.0 7.5 3.5 9.5 3.5 8.5

tPHL CP to I/On5.0 8.5 11.0 3.5 10.0 5.0 12.0 ns

tPLH Propagation Delay 3.5 7.0 9.0 3.5 11.0 3.5 10.0

tPHL CP to Q03.5 7.0 8.0 3.5 10.0 3.5 9.0

tPHL Propagation Delay 6.0 10.0 13.0 6.0 15.0 6.0 14.0 ns

MR to I/On

tPHL Propagation Delay 5.5 7.5 12.0 5.5 14.0 5.5 13.0 ns

MR to Q0

tPZH Output Enable Time 3.0 6.5 9.0 3.0 12.5 3.0 10.0

tPZL OE to I/On4.0 8.5 11.0 4.0 14.5 4.0 12.0 ns

tPHZ Output Disable Time 2.0 4.5 6.0 2.0 8.0 2.0 7.0

tPLZ OE to I/On2.0 5.0 7.0 2.0 10.0 2.0 8.0

tPZH Output Enable Time 4.5 8.0 10.5 4.5 13.5 4.5 11.5

tPZL S/P to I/On5.5 10.0 14.0 5.5 17.0 5.5 15.0 ns

tPHZ Output Disable Time 5.0 9.0 11.5 5.0 16.5 5.0 12.5

tPLZ S/P to I/On6.0 12.0 15.5 6.0 19.5 6.0 16.5

AC Operating Requirements

74F 54F 74F

Symbol Parameter TAea

25§CTA,V

CC eMil TA,V

CC eCom Units

VCC ea

5.0V

Min Max Min Max Min Max

ts(H) Setup Time, HIGH or LOW 6.0 14.0 7.0 ns

ts(L) RE to CP 14.0 18.0 16.0

th(H) Hold Time, HIGH or LOW 0 0 0 ns

th(L) RE to CP 0 0 0

ts(H) Setup Time, HIGH or LOW 6.5 8.5 7.5 ns

ts(L) D0,D

1or I/Onto CP 6.5 8.5 7.5

th(H) Hold Time, HIGH or LOW 2.0 3.0 3.0 ns

th(L) D0,D

1or I/Onto CP 2.0 3.0 3.0

ts(H) Setup Time, HIGH or LOW 7.0 9.0 8.0 ns

ts(L) SE to CP 2.5 11.0 3.5

th(H) Hold Time, HIGH or LOW 2.0 2.0 2.0 ns

th(L) SE to CP 0.0 1.0 0.0

ts(H) Setup Time, HIGH or LOW 11.0 13.0 12.0 ns

ts(L) S/P to CP 13.5 21.0 15.5

ts(H) Setup Time, HIGH or LOW 6.5 8.5 7.5 ns

ts(L) S to CP 9.0 11.0 10.0

th(H) Hold Time, HIGH or LOW 0 1.0 0 ns

th(L) S or S/P to CP 0 0 0

tw(H) CP Pulse Width, HIGH or LOW 7.0 8.0 7.0 ns

tw(L)

tw(L) MR Pulse Width, LOW 5.5 7.5 6.5

trec Recovery Time 8.0 12.0 8.0 ns

MR to CP

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are

defined as follows:

74F 322 S C X

Temperature Range Family Special Variations

74F eCommercial QB eMilitary grade device with

54F eMilitary environmental and burn-in

processing

Device Type XeDevices shipped in 13×reel

Package Code Temperature Range

PePlastic DIP CeCommercial (0§Ctoa

70§C)

DeCeramic DIP MeMilitary (b55§Ctoa

125§C)

FeFlatpak

SJ eSmall Outline SOIC EIAJ

LeLeadless Chip Carrier (LCC)

Physical Dimensions inches (millimeters)

20-Lead Ceramic Leadless Chip Carrier (L)

NS Package Number E20A

Physical Dimensions inches (millimeters) (Continued)

20-Lead Ceramic Dual-In-Line Package (D)

NS Package Number J20A

Physical Dimensions inches (millimeters) (Continued)

20-Lead (0.300×Wide) Molded Small Outline Package, EIAJ (SJ)

NS Package Number M20D

20-Lead (0.300×Wide) Molded Dual-In-Line Package (P)

NS Package Number N20A

54F/74F322 Octal Serial/Parallel Register with Sign Extend

Physical Dimensions inches (millimeters) (Continued)

20-Lead Ceramic Flatpak (F)

NS Package Number W20A

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SEMICONDUCTOR CORPORATION. As used herein:

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systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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